From: Jakob Stoklund Olesen <stoklund@2pi.dk>
Date: Fri, 7 Sep 2012 17:34:15 +0000 (+0000)
Subject: Custom DAGCombine for and/or/xor are for all ARMs.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=a7390fadbaa8da49649d76786555c93bcb680de6;p=oota-llvm.git

Custom DAGCombine for and/or/xor are for all ARMs.

The 'select' transformations apply to all ARM architectures and don't
require hasV6T2Ops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163396 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 5f3a9c773f2..29ca8eace32 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -796,12 +796,9 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
   setTargetDAGCombine(ISD::ADD);
   setTargetDAGCombine(ISD::SUB);
   setTargetDAGCombine(ISD::MUL);
-
-  if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON()) {
-    setTargetDAGCombine(ISD::AND);
-    setTargetDAGCombine(ISD::OR);
-    setTargetDAGCombine(ISD::XOR);
-  }
+  setTargetDAGCombine(ISD::AND);
+  setTargetDAGCombine(ISD::OR);
+  setTargetDAGCombine(ISD::XOR);
 
   if (Subtarget->hasV6Ops())
     setTargetDAGCombine(ISD::SRL);