From: 黄涛 Date: Mon, 30 Jun 2014 12:21:22 +0000 (+0800) Subject: ARM: errata: Workaround for Cortex-A12 erratum 818325 X-Git-Tag: firefly_0821_release~5020 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=a7796adfa79e34640a51764b450f58327426a383;p=firefly-linux-kernel-4.4.55.git ARM: errata: Workaround for Cortex-A12 erratum 818325 On Cortex-A12 (r0p0..r0p1-00lac0-rc11), when a CPU executes a sequence of two conditional store instructions with opposite condition code and updating the same register, the system might enter a deadlock if the second conditional instruction is an UNPREDICTABLE STR or STM instruction. This workaround setting bit[12] of the Feature Register prevents the erratum. This bit disables an optimisation applied to a sequence of 2 instructions that use opposing condition codes. --- diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0a39a5f1b04d..f5c385a93ede 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1360,6 +1360,19 @@ config ARM_ERRATA_798181 which sends an IPI to the CPUs that are running the same ASID as the one being invalidated. +config ARM_ERRATA_818325 + bool "ARM errata: Execution of an UNPREDICTABLE STR or STM instruction might deadlock" + depends on CPU_V7 + help + This option enables the workaround for the 818325 Cortex-A12 + (r0p0..r0p1-00lac0-rc11) erratum. When a CPU executes a sequence of + two conditional store instructions with opposite condition code and + updating the same register, the system might enter a deadlock if the + second conditional instruction is an UNPREDICTABLE STR or STM + instruction. This workaround setting bit[12] of the Feature Register + prevents the erratum. This bit disables an optimisation applied to a + sequence of 2 instructions that use opposing condition codes. + endmenu source "arch/arm/common/Kconfig" diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 8d96e51fccf4..34862572f217 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -328,7 +328,20 @@ __v7_setup: 1: #endif -3: mov r10, #0 + /* Cortex-A12 Errata */ +3: ldr r10, =0x00000c0d @ Cortex-A12 primary part number + teq r0, r10 + bne 4f +#ifdef CONFIG_ARM_ERRATA_818325 + teq r6, #0x00 @ present in r0p0 + teqne r6, #0x01 @ present in r0p1-00lac0-rc11 + mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register + orreq r10, r10, #1 << 12 @ set bit #12 + mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register + isb +#endif + +4: mov r10, #0 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate #ifdef CONFIG_MMU mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs