From: Chris Lattner Date: Sat, 28 Feb 2004 19:45:39 +0000 (+0000) Subject: Tab completion is our friend. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=a85d46eea8f7eba8be2e9724c099abda68dbb20a;p=oota-llvm.git Tab completion is our friend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11957 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Sparc/Sparc.td b/lib/Target/Sparc/Sparc.td index 345ea4d33e7..7607dca0280 100644 --- a/lib/Target/Sparc/Sparc.td +++ b/lib/Target/Sparc/Sparc.td @@ -18,8 +18,8 @@ include "../Target.td" // Register File Description //===----------------------------------------------------------------------===// -include "SparcV8Reg.td" -include "SparcV8Instrs.td" +include "SparcV8RegisterInfo.td" +include "SparcV8InstrInfo.td" def SparcV8InstrInfo : InstrInfo { let PHIInst = PHI; diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td new file mode 100644 index 00000000000..1d7d973e411 --- /dev/null +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -0,0 +1,68 @@ +//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the SparcV8 instructions in TableGen format. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instruction format superclass +//===----------------------------------------------------------------------===// + +class InstV8 : Instruction { // SparcV8 instruction baseline + field bits<32> Inst; + + let Namespace = "V8"; + + bits<2> op; + let Inst{31-30} = op; // Top two bits are the 'op' field + + // Bit attributes specific to SparcV8 instructions + bit isPasi = 0; // Does this instruction affect an alternate addr space? + bit isPrivileged = 0; // Is this a privileged instruction? +} + +include "SparcV8InstrInfo_F2.td" +include "SparcV8InstrInfo_F3.td" + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +// Pseudo instructions. +def PHI : InstV8 { + let Name = "PHI"; +} +def ADJCALLSTACKDOWN : InstV8 { + let Name = "ADJCALLSTACKDOWN"; +} +def ADJCALLSTACKUP : InstV8 { + let Name = "ADJCALLSTACKUP"; +} + +// Section B.20: SAVE and RESTORE - p117 +def SAVEr : F3_1<2, 0b111100, "save">; // save r, r, r +def SAVEi : F3_2<2, 0b111100, "save">; // save r, i, r +def RESTOREr : F3_1<2, 0b111101, "restore">; // restore r, r, r +def RESTOREi : F3_2<2, 0b111101, "restore">; // restore r, i, r + +// Section B.24: Call and Link - p125 +// This is the only Format 1 instruction +def CALL : InstV8 { + bits<30> disp; + + let op = 1; + let Inst{29-0} = disp; + let Name = "call"; +} + +// Section B.25: Jump and Link - p126 +def JMPLr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd +def JMPLi : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd + diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td new file mode 100644 index 00000000000..f58d06adf70 --- /dev/null +++ b/lib/Target/Sparc/SparcRegisterInfo.td @@ -0,0 +1,42 @@ +//===- SparcV8Reg.td - Describe the SparcV8 Register File -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Declarations that describe the SparcV8 register file +// +//===----------------------------------------------------------------------===// + +// Ri - 32-bit integer registers +class Ri num> : Register { + field bits<5> Num = num; // Numbers are identified with a 5 bit ID +} + +let Namespace = "SparcV8" in { + def G0 : Ri< 0>; def G1 : Ri< 1>; def G2 : Ri< 2>; def G3 : Ri< 3>; + def G4 : Ri< 4>; def G5 : Ri< 5>; def G6 : Ri< 6>; def G7 : Ri< 7>; + def O0 : Ri< 8>; def O1 : Ri< 9>; def O2 : Ri<10>; def O3 : Ri<11>; + def O4 : Ri<12>; def O5 : Ri<13>; def O6 : Ri<14>; def O7 : Ri<15>; + def L0 : Ri<16>; def L1 : Ri<17>; def L2 : Ri<18>; def L3 : Ri<19>; + def L4 : Ri<20>; def L5 : Ri<21>; def L6 : Ri<22>; def L7 : Ri<23>; + def I0 : Ri<24>; def I1 : Ri<25>; def I2 : Ri<26>; def I3 : Ri<27>; + def I4 : Ri<28>; def I5 : Ri<29>; def I6 : Ri<30>; def I7 : Ri<31>; + + // Floating-point registers? + // ... +} + + +// For fun, specify a register class. +// +// FIXME: the register order should be defined in terms of the preferred +// allocation order... +// +def IntRegs : RegisterClass; diff --git a/lib/Target/Sparc/SparcV8InstrInfo_F2.td b/lib/Target/Sparc/SparcV8InstrInfo_F2.td new file mode 100644 index 00000000000..7b550bd7ddf --- /dev/null +++ b/lib/Target/Sparc/SparcV8InstrInfo_F2.td @@ -0,0 +1,44 @@ +//===- SparcV8Instrs_F2.td - Format 2 instructions: SparcV8 Target --------===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Format #2 instruction classes in the SparcV8 +// +//===----------------------------------------------------------------------===// + +class F2 : InstV8 { // Format 2 instructions + bits<3> op2; + bits<22> imm22; + let op = 0; // op = 0 + let Inst{24-22} = op2; + let Inst{21-0} = imm22; +} + +// Specific F2 classes: SparcV8 manual, page 44 +// +class F2_1 op2Val, string name> : F2 { + bits<5> rd; + bits<22> imm; + + let op2 = op2Val; + let Name = name; + + let Inst{29-25} = rd; +} + +class F2_2 condVal, bits<3> op2Val, string name> : F2 { + bits<4> cond; + bit annul = 0; // currently unused + + let cond = condVal; + let op2 = op2Val; + let Name = name; + + let Inst{29} = annul; + let Inst{28-25} = cond; +} diff --git a/lib/Target/Sparc/SparcV8InstrInfo_F3.td b/lib/Target/Sparc/SparcV8InstrInfo_F3.td new file mode 100644 index 00000000000..f1bf6a05f8f --- /dev/null +++ b/lib/Target/Sparc/SparcV8InstrInfo_F3.td @@ -0,0 +1,62 @@ +//===- SparcV8Instrs_F3.td - Format 3 Instructions: SparcV8 Target --------===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Format #3 instruction classes in the SparcV8 +// +//===----------------------------------------------------------------------===// + +class F3 : InstV8 { + bits<5> rd; + bits<6> op3; + bits<5> rs1; + let op{1} = 1; // Op = 2 or 3 + let Inst{29-25} = rd; + let Inst{24-19} = op3; + let Inst{18-14} = rs1; +} + +// Specific F3 classes: SparcV8 manual, page 44 +// +class F3_1 opVal, bits<6> op3val, string name> : F3 { + bits<8> asi; + bits<5> rs2; + + let op = opVal; + let op3 = op3val; + let Name = name; + + let Inst{13} = 0; // i field = 0 + let Inst{12-5} = asi; // address space identifier + let Inst{4-0} = rs2; +} + +class F3_2 opVal, bits<6> op3val, string name> : F3 { + bits<13> simm13; + + let op = opVal; + let op3 = op3val; + let Name = name; + + let Inst{13} = 1; // i field = 1 + let Inst{12-0} = simm13; +} + +/* +class F3_3 opVal, bits<6> op3val, bits<9> opfVal, string name> + : F3_rs1rs2 { + bits<5> rs2; + + let op = opVal; + let op3 = op3val; + let Name = name; + + let Inst{13-5} = opfVal; + let Inst{4-0} = rs2; +} +*/ \ No newline at end of file diff --git a/lib/Target/Sparc/SparcV8Instrs.td b/lib/Target/Sparc/SparcV8Instrs.td deleted file mode 100644 index 37b4d744ca1..00000000000 --- a/lib/Target/Sparc/SparcV8Instrs.td +++ /dev/null @@ -1,68 +0,0 @@ -//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// -// -// The LLVM Compiler Infrastructure -// -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes the SparcV8 instructions in TableGen format. -// -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// Instruction format superclass -//===----------------------------------------------------------------------===// - -class InstV8 : Instruction { // SparcV8 instruction baseline - field bits<32> Inst; - - let Namespace = "V8"; - - bits<2> op; - let Inst{31-30} = op; // Top two bits are the 'op' field - - // Bit attributes specific to SparcV8 instructions - bit isPasi = 0; // Does this instruction affect an alternate addr space? - bit isPrivileged = 0; // Is this a privileged instruction? -} - -include "SparcV8Instrs_F2.td" -include "SparcV8Instrs_F3.td" - -//===----------------------------------------------------------------------===// -// Instructions -//===----------------------------------------------------------------------===// - -// Pseudo instructions. -def PHI : InstV8 { - let Name = "PHI"; -} -def ADJCALLSTACKDOWN : InstV8 { - let Name = "ADJCALLSTACKDOWN"; -} -def ADJCALLSTACKUP : InstV8 { - let Name = "ADJCALLSTACKUP"; -} - -// Section B.20: SAVE and RESTORE - p117 -def SAVEr : F3_1<2, 0b111100, "save">; // save r, r, r -def SAVEi : F3_2<2, 0b111100, "save">; // save r, i, r -def RESTOREr : F3_1<2, 0b111101, "restore">; // restore r, r, r -def RESTOREi : F3_2<2, 0b111101, "restore">; // restore r, i, r - -// Section B.24: Call and Link - p125 -// This is the only Format 1 instruction -def CALL : InstV8 { - bits<30> disp; - - let op = 1; - let Inst{29-0} = disp; - let Name = "call"; -} - -// Section B.25: Jump and Link - p126 -def JMPLr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd -def JMPLi : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd - diff --git a/lib/Target/Sparc/SparcV8Instrs_F2.td b/lib/Target/Sparc/SparcV8Instrs_F2.td deleted file mode 100644 index 7b550bd7ddf..00000000000 --- a/lib/Target/Sparc/SparcV8Instrs_F2.td +++ /dev/null @@ -1,44 +0,0 @@ -//===- SparcV8Instrs_F2.td - Format 2 instructions: SparcV8 Target --------===// -// -// The LLVM Compiler Infrastructure -// -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// Format #2 instruction classes in the SparcV8 -// -//===----------------------------------------------------------------------===// - -class F2 : InstV8 { // Format 2 instructions - bits<3> op2; - bits<22> imm22; - let op = 0; // op = 0 - let Inst{24-22} = op2; - let Inst{21-0} = imm22; -} - -// Specific F2 classes: SparcV8 manual, page 44 -// -class F2_1 op2Val, string name> : F2 { - bits<5> rd; - bits<22> imm; - - let op2 = op2Val; - let Name = name; - - let Inst{29-25} = rd; -} - -class F2_2 condVal, bits<3> op2Val, string name> : F2 { - bits<4> cond; - bit annul = 0; // currently unused - - let cond = condVal; - let op2 = op2Val; - let Name = name; - - let Inst{29} = annul; - let Inst{28-25} = cond; -} diff --git a/lib/Target/Sparc/SparcV8Instrs_F3.td b/lib/Target/Sparc/SparcV8Instrs_F3.td deleted file mode 100644 index f1bf6a05f8f..00000000000 --- a/lib/Target/Sparc/SparcV8Instrs_F3.td +++ /dev/null @@ -1,62 +0,0 @@ -//===- SparcV8Instrs_F3.td - Format 3 Instructions: SparcV8 Target --------===// -// -// The LLVM Compiler Infrastructure -// -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// Format #3 instruction classes in the SparcV8 -// -//===----------------------------------------------------------------------===// - -class F3 : InstV8 { - bits<5> rd; - bits<6> op3; - bits<5> rs1; - let op{1} = 1; // Op = 2 or 3 - let Inst{29-25} = rd; - let Inst{24-19} = op3; - let Inst{18-14} = rs1; -} - -// Specific F3 classes: SparcV8 manual, page 44 -// -class F3_1 opVal, bits<6> op3val, string name> : F3 { - bits<8> asi; - bits<5> rs2; - - let op = opVal; - let op3 = op3val; - let Name = name; - - let Inst{13} = 0; // i field = 0 - let Inst{12-5} = asi; // address space identifier - let Inst{4-0} = rs2; -} - -class F3_2 opVal, bits<6> op3val, string name> : F3 { - bits<13> simm13; - - let op = opVal; - let op3 = op3val; - let Name = name; - - let Inst{13} = 1; // i field = 1 - let Inst{12-0} = simm13; -} - -/* -class F3_3 opVal, bits<6> op3val, bits<9> opfVal, string name> - : F3_rs1rs2 { - bits<5> rs2; - - let op = opVal; - let op3 = op3val; - let Name = name; - - let Inst{13-5} = opfVal; - let Inst{4-0} = rs2; -} -*/ \ No newline at end of file diff --git a/lib/Target/Sparc/SparcV8Reg.td b/lib/Target/Sparc/SparcV8Reg.td deleted file mode 100644 index f58d06adf70..00000000000 --- a/lib/Target/Sparc/SparcV8Reg.td +++ /dev/null @@ -1,42 +0,0 @@ -//===- SparcV8Reg.td - Describe the SparcV8 Register File -------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// Declarations that describe the SparcV8 register file -// -//===----------------------------------------------------------------------===// - -// Ri - 32-bit integer registers -class Ri num> : Register { - field bits<5> Num = num; // Numbers are identified with a 5 bit ID -} - -let Namespace = "SparcV8" in { - def G0 : Ri< 0>; def G1 : Ri< 1>; def G2 : Ri< 2>; def G3 : Ri< 3>; - def G4 : Ri< 4>; def G5 : Ri< 5>; def G6 : Ri< 6>; def G7 : Ri< 7>; - def O0 : Ri< 8>; def O1 : Ri< 9>; def O2 : Ri<10>; def O3 : Ri<11>; - def O4 : Ri<12>; def O5 : Ri<13>; def O6 : Ri<14>; def O7 : Ri<15>; - def L0 : Ri<16>; def L1 : Ri<17>; def L2 : Ri<18>; def L3 : Ri<19>; - def L4 : Ri<20>; def L5 : Ri<21>; def L6 : Ri<22>; def L7 : Ri<23>; - def I0 : Ri<24>; def I1 : Ri<25>; def I2 : Ri<26>; def I3 : Ri<27>; - def I4 : Ri<28>; def I5 : Ri<29>; def I6 : Ri<30>; def I7 : Ri<31>; - - // Floating-point registers? - // ... -} - - -// For fun, specify a register class. -// -// FIXME: the register order should be defined in terms of the preferred -// allocation order... -// -def IntRegs : RegisterClass; diff --git a/lib/Target/SparcV8/SparcV8.td b/lib/Target/SparcV8/SparcV8.td index 345ea4d33e7..7607dca0280 100644 --- a/lib/Target/SparcV8/SparcV8.td +++ b/lib/Target/SparcV8/SparcV8.td @@ -18,8 +18,8 @@ include "../Target.td" // Register File Description //===----------------------------------------------------------------------===// -include "SparcV8Reg.td" -include "SparcV8Instrs.td" +include "SparcV8RegisterInfo.td" +include "SparcV8InstrInfo.td" def SparcV8InstrInfo : InstrInfo { let PHIInst = PHI; diff --git a/lib/Target/SparcV8/SparcV8InstrInfo.td b/lib/Target/SparcV8/SparcV8InstrInfo.td new file mode 100644 index 00000000000..1d7d973e411 --- /dev/null +++ b/lib/Target/SparcV8/SparcV8InstrInfo.td @@ -0,0 +1,68 @@ +//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the SparcV8 instructions in TableGen format. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instruction format superclass +//===----------------------------------------------------------------------===// + +class InstV8 : Instruction { // SparcV8 instruction baseline + field bits<32> Inst; + + let Namespace = "V8"; + + bits<2> op; + let Inst{31-30} = op; // Top two bits are the 'op' field + + // Bit attributes specific to SparcV8 instructions + bit isPasi = 0; // Does this instruction affect an alternate addr space? + bit isPrivileged = 0; // Is this a privileged instruction? +} + +include "SparcV8InstrInfo_F2.td" +include "SparcV8InstrInfo_F3.td" + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +// Pseudo instructions. +def PHI : InstV8 { + let Name = "PHI"; +} +def ADJCALLSTACKDOWN : InstV8 { + let Name = "ADJCALLSTACKDOWN"; +} +def ADJCALLSTACKUP : InstV8 { + let Name = "ADJCALLSTACKUP"; +} + +// Section B.20: SAVE and RESTORE - p117 +def SAVEr : F3_1<2, 0b111100, "save">; // save r, r, r +def SAVEi : F3_2<2, 0b111100, "save">; // save r, i, r +def RESTOREr : F3_1<2, 0b111101, "restore">; // restore r, r, r +def RESTOREi : F3_2<2, 0b111101, "restore">; // restore r, i, r + +// Section B.24: Call and Link - p125 +// This is the only Format 1 instruction +def CALL : InstV8 { + bits<30> disp; + + let op = 1; + let Inst{29-0} = disp; + let Name = "call"; +} + +// Section B.25: Jump and Link - p126 +def JMPLr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd +def JMPLi : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd + diff --git a/lib/Target/SparcV8/SparcV8InstrInfo_F2.td b/lib/Target/SparcV8/SparcV8InstrInfo_F2.td new file mode 100644 index 00000000000..7b550bd7ddf --- /dev/null +++ b/lib/Target/SparcV8/SparcV8InstrInfo_F2.td @@ -0,0 +1,44 @@ +//===- SparcV8Instrs_F2.td - Format 2 instructions: SparcV8 Target --------===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Format #2 instruction classes in the SparcV8 +// +//===----------------------------------------------------------------------===// + +class F2 : InstV8 { // Format 2 instructions + bits<3> op2; + bits<22> imm22; + let op = 0; // op = 0 + let Inst{24-22} = op2; + let Inst{21-0} = imm22; +} + +// Specific F2 classes: SparcV8 manual, page 44 +// +class F2_1 op2Val, string name> : F2 { + bits<5> rd; + bits<22> imm; + + let op2 = op2Val; + let Name = name; + + let Inst{29-25} = rd; +} + +class F2_2 condVal, bits<3> op2Val, string name> : F2 { + bits<4> cond; + bit annul = 0; // currently unused + + let cond = condVal; + let op2 = op2Val; + let Name = name; + + let Inst{29} = annul; + let Inst{28-25} = cond; +} diff --git a/lib/Target/SparcV8/SparcV8InstrInfo_F3.td b/lib/Target/SparcV8/SparcV8InstrInfo_F3.td new file mode 100644 index 00000000000..f1bf6a05f8f --- /dev/null +++ b/lib/Target/SparcV8/SparcV8InstrInfo_F3.td @@ -0,0 +1,62 @@ +//===- SparcV8Instrs_F3.td - Format 3 Instructions: SparcV8 Target --------===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Format #3 instruction classes in the SparcV8 +// +//===----------------------------------------------------------------------===// + +class F3 : InstV8 { + bits<5> rd; + bits<6> op3; + bits<5> rs1; + let op{1} = 1; // Op = 2 or 3 + let Inst{29-25} = rd; + let Inst{24-19} = op3; + let Inst{18-14} = rs1; +} + +// Specific F3 classes: SparcV8 manual, page 44 +// +class F3_1 opVal, bits<6> op3val, string name> : F3 { + bits<8> asi; + bits<5> rs2; + + let op = opVal; + let op3 = op3val; + let Name = name; + + let Inst{13} = 0; // i field = 0 + let Inst{12-5} = asi; // address space identifier + let Inst{4-0} = rs2; +} + +class F3_2 opVal, bits<6> op3val, string name> : F3 { + bits<13> simm13; + + let op = opVal; + let op3 = op3val; + let Name = name; + + let Inst{13} = 1; // i field = 1 + let Inst{12-0} = simm13; +} + +/* +class F3_3 opVal, bits<6> op3val, bits<9> opfVal, string name> + : F3_rs1rs2 { + bits<5> rs2; + + let op = opVal; + let op3 = op3val; + let Name = name; + + let Inst{13-5} = opfVal; + let Inst{4-0} = rs2; +} +*/ \ No newline at end of file diff --git a/lib/Target/SparcV8/SparcV8Instrs.td b/lib/Target/SparcV8/SparcV8Instrs.td deleted file mode 100644 index 37b4d744ca1..00000000000 --- a/lib/Target/SparcV8/SparcV8Instrs.td +++ /dev/null @@ -1,68 +0,0 @@ -//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// -// -// The LLVM Compiler Infrastructure -// -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes the SparcV8 instructions in TableGen format. -// -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// Instruction format superclass -//===----------------------------------------------------------------------===// - -class InstV8 : Instruction { // SparcV8 instruction baseline - field bits<32> Inst; - - let Namespace = "V8"; - - bits<2> op; - let Inst{31-30} = op; // Top two bits are the 'op' field - - // Bit attributes specific to SparcV8 instructions - bit isPasi = 0; // Does this instruction affect an alternate addr space? - bit isPrivileged = 0; // Is this a privileged instruction? -} - -include "SparcV8Instrs_F2.td" -include "SparcV8Instrs_F3.td" - -//===----------------------------------------------------------------------===// -// Instructions -//===----------------------------------------------------------------------===// - -// Pseudo instructions. -def PHI : InstV8 { - let Name = "PHI"; -} -def ADJCALLSTACKDOWN : InstV8 { - let Name = "ADJCALLSTACKDOWN"; -} -def ADJCALLSTACKUP : InstV8 { - let Name = "ADJCALLSTACKUP"; -} - -// Section B.20: SAVE and RESTORE - p117 -def SAVEr : F3_1<2, 0b111100, "save">; // save r, r, r -def SAVEi : F3_2<2, 0b111100, "save">; // save r, i, r -def RESTOREr : F3_1<2, 0b111101, "restore">; // restore r, r, r -def RESTOREi : F3_2<2, 0b111101, "restore">; // restore r, i, r - -// Section B.24: Call and Link - p125 -// This is the only Format 1 instruction -def CALL : InstV8 { - bits<30> disp; - - let op = 1; - let Inst{29-0} = disp; - let Name = "call"; -} - -// Section B.25: Jump and Link - p126 -def JMPLr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd -def JMPLi : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd - diff --git a/lib/Target/SparcV8/SparcV8Instrs_F2.td b/lib/Target/SparcV8/SparcV8Instrs_F2.td deleted file mode 100644 index 7b550bd7ddf..00000000000 --- a/lib/Target/SparcV8/SparcV8Instrs_F2.td +++ /dev/null @@ -1,44 +0,0 @@ -//===- SparcV8Instrs_F2.td - Format 2 instructions: SparcV8 Target --------===// -// -// The LLVM Compiler Infrastructure -// -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// Format #2 instruction classes in the SparcV8 -// -//===----------------------------------------------------------------------===// - -class F2 : InstV8 { // Format 2 instructions - bits<3> op2; - bits<22> imm22; - let op = 0; // op = 0 - let Inst{24-22} = op2; - let Inst{21-0} = imm22; -} - -// Specific F2 classes: SparcV8 manual, page 44 -// -class F2_1 op2Val, string name> : F2 { - bits<5> rd; - bits<22> imm; - - let op2 = op2Val; - let Name = name; - - let Inst{29-25} = rd; -} - -class F2_2 condVal, bits<3> op2Val, string name> : F2 { - bits<4> cond; - bit annul = 0; // currently unused - - let cond = condVal; - let op2 = op2Val; - let Name = name; - - let Inst{29} = annul; - let Inst{28-25} = cond; -} diff --git a/lib/Target/SparcV8/SparcV8Instrs_F3.td b/lib/Target/SparcV8/SparcV8Instrs_F3.td deleted file mode 100644 index f1bf6a05f8f..00000000000 --- a/lib/Target/SparcV8/SparcV8Instrs_F3.td +++ /dev/null @@ -1,62 +0,0 @@ -//===- SparcV8Instrs_F3.td - Format 3 Instructions: SparcV8 Target --------===// -// -// The LLVM Compiler Infrastructure -// -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// Format #3 instruction classes in the SparcV8 -// -//===----------------------------------------------------------------------===// - -class F3 : InstV8 { - bits<5> rd; - bits<6> op3; - bits<5> rs1; - let op{1} = 1; // Op = 2 or 3 - let Inst{29-25} = rd; - let Inst{24-19} = op3; - let Inst{18-14} = rs1; -} - -// Specific F3 classes: SparcV8 manual, page 44 -// -class F3_1 opVal, bits<6> op3val, string name> : F3 { - bits<8> asi; - bits<5> rs2; - - let op = opVal; - let op3 = op3val; - let Name = name; - - let Inst{13} = 0; // i field = 0 - let Inst{12-5} = asi; // address space identifier - let Inst{4-0} = rs2; -} - -class F3_2 opVal, bits<6> op3val, string name> : F3 { - bits<13> simm13; - - let op = opVal; - let op3 = op3val; - let Name = name; - - let Inst{13} = 1; // i field = 1 - let Inst{12-0} = simm13; -} - -/* -class F3_3 opVal, bits<6> op3val, bits<9> opfVal, string name> - : F3_rs1rs2 { - bits<5> rs2; - - let op = opVal; - let op3 = op3val; - let Name = name; - - let Inst{13-5} = opfVal; - let Inst{4-0} = rs2; -} -*/ \ No newline at end of file diff --git a/lib/Target/SparcV8/SparcV8Reg.td b/lib/Target/SparcV8/SparcV8Reg.td deleted file mode 100644 index f58d06adf70..00000000000 --- a/lib/Target/SparcV8/SparcV8Reg.td +++ /dev/null @@ -1,42 +0,0 @@ -//===- SparcV8Reg.td - Describe the SparcV8 Register File -------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// Declarations that describe the SparcV8 register file -// -//===----------------------------------------------------------------------===// - -// Ri - 32-bit integer registers -class Ri num> : Register { - field bits<5> Num = num; // Numbers are identified with a 5 bit ID -} - -let Namespace = "SparcV8" in { - def G0 : Ri< 0>; def G1 : Ri< 1>; def G2 : Ri< 2>; def G3 : Ri< 3>; - def G4 : Ri< 4>; def G5 : Ri< 5>; def G6 : Ri< 6>; def G7 : Ri< 7>; - def O0 : Ri< 8>; def O1 : Ri< 9>; def O2 : Ri<10>; def O3 : Ri<11>; - def O4 : Ri<12>; def O5 : Ri<13>; def O6 : Ri<14>; def O7 : Ri<15>; - def L0 : Ri<16>; def L1 : Ri<17>; def L2 : Ri<18>; def L3 : Ri<19>; - def L4 : Ri<20>; def L5 : Ri<21>; def L6 : Ri<22>; def L7 : Ri<23>; - def I0 : Ri<24>; def I1 : Ri<25>; def I2 : Ri<26>; def I3 : Ri<27>; - def I4 : Ri<28>; def I5 : Ri<29>; def I6 : Ri<30>; def I7 : Ri<31>; - - // Floating-point registers? - // ... -} - - -// For fun, specify a register class. -// -// FIXME: the register order should be defined in terms of the preferred -// allocation order... -// -def IntRegs : RegisterClass; diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.td b/lib/Target/SparcV8/SparcV8RegisterInfo.td new file mode 100644 index 00000000000..f58d06adf70 --- /dev/null +++ b/lib/Target/SparcV8/SparcV8RegisterInfo.td @@ -0,0 +1,42 @@ +//===- SparcV8Reg.td - Describe the SparcV8 Register File -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Declarations that describe the SparcV8 register file +// +//===----------------------------------------------------------------------===// + +// Ri - 32-bit integer registers +class Ri num> : Register { + field bits<5> Num = num; // Numbers are identified with a 5 bit ID +} + +let Namespace = "SparcV8" in { + def G0 : Ri< 0>; def G1 : Ri< 1>; def G2 : Ri< 2>; def G3 : Ri< 3>; + def G4 : Ri< 4>; def G5 : Ri< 5>; def G6 : Ri< 6>; def G7 : Ri< 7>; + def O0 : Ri< 8>; def O1 : Ri< 9>; def O2 : Ri<10>; def O3 : Ri<11>; + def O4 : Ri<12>; def O5 : Ri<13>; def O6 : Ri<14>; def O7 : Ri<15>; + def L0 : Ri<16>; def L1 : Ri<17>; def L2 : Ri<18>; def L3 : Ri<19>; + def L4 : Ri<20>; def L5 : Ri<21>; def L6 : Ri<22>; def L7 : Ri<23>; + def I0 : Ri<24>; def I1 : Ri<25>; def I2 : Ri<26>; def I3 : Ri<27>; + def I4 : Ri<28>; def I5 : Ri<29>; def I6 : Ri<30>; def I7 : Ri<31>; + + // Floating-point registers? + // ... +} + + +// For fun, specify a register class. +// +// FIXME: the register order should be defined in terms of the preferred +// allocation order... +// +def IntRegs : RegisterClass;