From: zsq Date: Thu, 22 Mar 2012 06:13:03 +0000 (-0800) Subject: modify rga driver fot rga test info X-Git-Tag: firefly_0821_release~9595^2~40 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=a87df9174e83a665f28328d990142be26aa4776a;p=firefly-linux-kernel-4.4.55.git modify rga driver fot rga test info --- diff --git a/drivers/video/rockchip/rga/RGA_API.c b/drivers/video/rockchip/rga/RGA_API.c index 7c3b4be9d7b3..af89f973e9e0 100755 --- a/drivers/video/rockchip/rga/RGA_API.c +++ b/drivers/video/rockchip/rga/RGA_API.c @@ -78,176 +78,6 @@ matrix_cal(const struct rga_req *msg, TILE_INFO *tile) } - - -u32 -RGA_dst_act_addr_temp(const struct rga_req *msg) -{ - uint32_t pw; - uint32_t x_off, y_off; - uint32_t stride; - uint32_t p; - - pw = RGA_pixel_width_init(msg->dst.format); - stride = (msg->dst.vir_w * pw + 3) & (~3); - - x_off = msg->dst.x_offset; - y_off = msg->dst.y_offset; - - p = (u32)((stride * y_off) + (x_off * pw)); - - return p; -} - -void -RGA_set_cmd_info(uint8_t cmd_mode, uint32_t cmd_addr) -{ - uint32_t reg = 0; - - reg |= ((cmd_mode & 1) << 1); - rRGA_SYS_CTRL = reg; - rRGA_CMD_ADDR = cmd_addr; -} - -void -RGA_start(void) -{ - uint32_t reg = 0; - uint8_t cmd_mode; - - reg = rRGA_SYS_CTRL; - cmd_mode = (reg >> 2) & 1; - - if (cmd_mode == 0) - { - /* passive */ - reg |= (1<<1); - rRGA_SYS_CTRL = reg; - } - else - { - /* master */ - reg = rRGA_CMD_CTRL; - reg |= 1; - rRGA_CMD_CTRL = reg; - } -} - - -void -RGA_soft_reset(void) -{ - uint32_t reg = 0; - - reg = rRGA_SYS_CTRL; - reg |= 1; - rRGA_SYS_CTRL = reg; -} - - -#if 0 -/*****************************************/ -//hxx add,2011.6.24 -void rga_one_op_st_master(RGA_INFO *p_rga_info) -{ - rRGA_SYS_CTRL = 0x4; - - rRGA_INT = s_RGA_INT_ALL_CMD_DONE_INT_EN(p_rga_info->int_info.all_cmd_done_int_en)| - s_RGA_INT_MMU_INT_EN(p_rga_info->int_info.mmu_int_en)| - s_RGA_INT_ERROR_INT_EN(p_rga_info->int_info.error_int_en); - - rRGA_CMD_ADDR = (u32) p_rga_info->sys_info.p_cmd_mst; - - rRGA_CMD_CTRL = 0x3; -} - - -void rga_set_int_info(MSG *p_msg,RGA_INFO *p_rga_info) -{ - p_msg->CMD_fin_int_enable = p_rga_info->int_info.cur_cmd_done_int_en; -} - - -void rga_check_int_all_cmd_finish(RGA_INFO *p_rga_info) -{ - u8 int_flag; - - int_flag = 0; - while(!int_flag) - { - int_flag = rRGA_INT & m_RGA_INT_ALL_CMD_DONE_INT_FLAG; - } - rRGA_INT = rRGA_INT | s_RGA_INT_ALL_CMD_DONE_INT_CLEAR(0x1); - - //if(p_rga_info->sys_info.p_cmd_mst != NULL) - // free(p_rga_info->sys_info.p_cmd_mst); -} -#endif - -void rga_start_cmd_AXI(uint8_t *base, uint32_t num) -{ - rRGA_SYS_CTRL = 0x4; - rRGA_INT = s_RGA_INT_ALL_CMD_DONE_INT_EN(ENABLE)| s_RGA_INT_MMU_INT_EN(ENABLE)| s_RGA_INT_ERROR_INT_EN(ENABLE); - rRGA_CMD_ADDR = (u32)base; - rRGA_CMD_CTRL |= (num<<3); - rRGA_CMD_CTRL |= 0x3; -} - -void rga_check_cmd_finish(void) -{ - uint8_t int_flag; - uint8_t error_flag; - - int_flag = 0; - error_flag = 0; - - while(!int_flag) - { - int_flag = rRGA_INT & m_RGA_INT_ALL_CMD_DONE_INT_FLAG; - error_flag = rRGA_INT & (m_RGA_INT_ERROR_INT_FLAG); - - if(error_flag) - { - printk("~~~~~ ERROR INTTUR OCCUR ~~~~~\n"); - } - error_flag = rRGA_INT & m_RGA_INT_MMU_INT_FLAG; - if(error_flag) - { - printk("~~~~~ MMU ERROR INTTUR OCCUR ~~~~~\n"); - } - } - rRGA_INT = rRGA_INT | s_RGA_INT_ALL_CMD_DONE_INT_CLEAR(0x1); -} - - - -void rga_start_cmd_AHB(uint8_t *base) -{ - uint32_t *base_p32; - - base_p32 = (u32 *)base; - *base_p32 = (*base_p32 | (1<<29)); - - memcpy((u8 *)(RGA_BASE + 0x100), base, 28*4); - - rRGA_SYS_CTRL = 0x2; -} - - -void rga_check_cmd_AHB_finish(void) -{ - uint8_t int_flag; - - int_flag = 0; - while(!int_flag) - { - int_flag = rRGA_INT & m_RGA_INT_NOW_CMD_DONE_INT_FLAG; - } - rRGA_INT = rRGA_INT | s_RGA_INT_NOW_CMD_DONE_INT_CLEAR(0x1); -} - - - uint32_t RGA_gen_two_pro(struct rga_req *msg, struct rga_req *msg1) { @@ -264,64 +94,64 @@ uint32_t RGA_gen_two_pro(struct rga_req *msg, struct rga_req *msg1) w_ratio = (msg->src.act_w << 16) / msg->dst.act_w; h_ratio = (msg->src.act_h << 16) / msg->dst.act_h; - memcpy(&mp->src, &msg->src, sizeof(rga_img_info_t)); + memcpy(&msg1, &msg, sizeof(struct rga_req)); - mp->dst.format = msg->src.format; + msg->dst.format = msg->src.format; /*pre_scale_w cal*/ if ((w_ratio >= (2<<16)) && (w_ratio < (4<<16))) { daw = (msg->src.act_w + 1) >> 1; - if((IS_YUV_420(mp->dst.format)) && (daw & 1)) { - mp->src.act_w = (daw - 1) << 1; + if((IS_YUV_420(msg->dst.format)) && (daw & 1)) { + msg->src.act_w = (daw - 1) << 1; } } else if ((w_ratio >= (4<<16)) && (w_ratio < (8<<16))) { daw = (msg->src.act_w + 3) >> 2; - if((IS_YUV_420(mp->dst.format)) && (daw & 1)) { - mp->src.act_w = (daw - 1) << 2; + if((IS_YUV_420(msg->dst.format)) && (daw & 1)) { + msg->src.act_w = (daw - 1) << 2; } } else if ((w_ratio >= (8<<16)) && (w_ratio < (16<<16))) { daw = (msg->src.act_w + 7) >> 3; - if((IS_YUV_420(mp->dst.format)) && (daw & 1)) { - mp->src.act_w = (daw - 1) << 3; + if((IS_YUV_420(msg->dst.format)) && (daw & 1)) { + msg->src.act_w = (daw - 1) << 3; } } pl = (RGA_pixel_width_init(msg->src.format)); stride = (pl * daw + 3) & (~3); - mp->dst.act_w = daw; - mp->dst.vir_w = stride / pl; + msg->dst.act_w = daw; + msg->dst.vir_w = stride / pl; /*pre_scale_h cal*/ if ((h_ratio >= (2<<16)) && (h_ratio < (4<<16))) { dah = (msg->src.act_h + 1) >> 1; - if((IS_YUV(mp->dst.format)) && (dah & 1)) { - mp->src.act_h = (dah - 1) << 1; + if((IS_YUV(msg->dst.format)) && (dah & 1)) { + msg->src.act_h = (dah - 1) << 1; } } else if ((h_ratio >= (4<<16)) && (h_ratio < (8<<16))) { dah = (msg->src.act_h + 3) >> 2; - if((IS_YUV(mp->dst.format)) && (dah & 1)) { - mp->src.act_h = (dah - 1) << 2; + if((IS_YUV(msg->dst.format)) && (dah & 1)) { + msg->src.act_h = (dah - 1) << 2; } } else if ((h_ratio >= (8<<16)) && (h_ratio < (16<<16))) { dah = (msg->src.act_h + 7) >> 3; - if((IS_YUV(mp->dst.format)) && (dah & 1)) { - mp->src.act_h = (dah - 1) << 3; + if((IS_YUV(msg->dst.format)) && (dah & 1)) { + msg->src.act_h = (dah - 1) << 3; } } - mp->dst.act_h = dah; - mp->dst.vir_h = dah; + msg->dst.act_h = dah; + msg->dst.vir_h = dah; - mp->dst.yrgb_addr = (u32)rga_service.pre_scale_buf; - mp->dst.uv_addr = mp->dst.yrgb_addr + stride * dah; - mp->dst.v_addr = mp->dst.uv_addr + ((stride * dah) >> 1); + msg->dst.yrgb_addr = (u32)rga_service.pre_scale_buf; + msg->dst.uv_addr = msg->dst.yrgb_addr + stride * dah; + msg->dst.v_addr = msg->dst.uv_addr + ((stride * dah) >> 1); - mp->render_mode = pre_scaling_mode; + msg->render_mode = pre_scaling_mode; - memcpy(&msg->src, &mp->dst, sizeof(rga_img_info_t)); + memcpy(&msg1->src, &msg->dst, sizeof(rga_img_info_t)); return 0; } diff --git a/drivers/video/rockchip/rga/RGA_API.h b/drivers/video/rockchip/rga/RGA_API.h index 59879e25ae9d..62a8aac4e144 100755 --- a/drivers/video/rockchip/rga/RGA_API.h +++ b/drivers/video/rockchip/rga/RGA_API.h @@ -7,220 +7,6 @@ #define ENABLE 1 #define DISABLE 0 -#if 0 -int -RGA_set_src_act_info( - msg_t *msg, - unsigned int width, /* act width */ - unsigned int height, /* act height */ - unsigned int x_off, /* x_off */ - unsigned int y_off /* y_off */ - ); - -int -RGA_set_src_vir_info( - msg_t *msg, - unsigned int yrgb_addr, /* yrgb_addr */ - unsigned int uv_addr, /* uv_addr */ - unsigned int v_addr, /* v_addr */ - unsigned int vir_w, /* vir width */ - unsigned int vir_h, /* vir height */ - unsigned char format, /* format */ - unsigned char a_swap_en - ); - -int -RGA_set_dst_act_info( - msg_t *msg, - unsigned int width, /* act width */ - unsigned int height, /* act height */ - unsigned int x_off, /* x_off */ - unsigned int y_off /* y_off */ - ); - -int -RGA_set_dst_vir_info( - msg_t *msg, - unsigned int yrgb_addr, /* yrgb_addr */ - unsigned int uv_addr, /* uv_addr */ - unsigned int v_addr, /* v_addr */ - unsigned int vir_w, /* vir width */ - unsigned int vir_h, /* vir height */ - RECT clip, /* clip window*/ - unsigned char format, /* format */ - unsigned char a_swap_en ); - - - -int -RGA_set_rop_mask_info( - msg_t *msg, - u32 rop_mask_addr, - u32 rop_mask_endian_mode); - -int -RGA_set_pat_info( - msg_t *msg, - u32 width, - u32 height, - u32 x_off, - u32 y_off, - u32 pat_format); - -int -RGA_set_alpha_en_info( - msg_t *msg, - unsigned int alpha_cal_mode, - unsigned int alpha_mode, - unsigned int global_a_value, - unsigned int PD_en, - unsigned int PD_mode - ); - -int -RGA_set_rop_en_info( - msg_t *msg, - unsigned int ROP_mode, - unsigned int ROP_code, - unsigned int color_mode, - unsigned int solid_color); - -/* -int -RGA_set_MMU_info( - MSG *msg, - unsigned int base_addr, - unsigned int src_flush, - unsigned int dst_flush, - unsigned int cmd_flush, - unsigned int page_size - ); -*/ - -int -RGA_set_MMU_info( - msg_t *msg, - u8 mmu_en, - u8 src_flush, - u8 dst_flush, - u8 cmd_flush, - u32 base_addr, - u8 page_size); - - -int -RGA_set_bitblt_mode( - msg_t *msg, - unsigned char scale_mode, // 0/near 1/bilnear 2/bicubic - unsigned char rotate_mode, // 0/copy 1/rotate_scale 2/x_mirror 3/y_mirror - unsigned int angle, // rotate angle (0~359) - unsigned int dither_en, // dither en flag - unsigned int AA_en, // AA flag - unsigned int yuv2rgb_mode - ); - - -int -RGA_set_color_palette_mode( - msg_t *msg, - u8 palette_mode, /* 1bpp/2bpp/4bpp/8bpp */ - u8 endian_mode, /* src endian mode sel */ - u32 bpp1_0_color, /* BPP1 = 0 */ - u32 bpp1_1_color /* BPP1 = 1 */ - ); - - - -int -RGA_set_color_fill_mode( - msg_t *msg, - CF_GR_COLOR gr_color, /* gradient color part*/ - u8 gr_satur_mode, /* saturation mode */ - u8 cf_mode, /* patten fill or solid fill */ - u32 color, /* solid color */ - u16 pat_width, /* pat_width */ - u16 pat_height, /* pat_height */ - u8 pat_x_off, /* patten x offset */ - u8 pat_y_off, /* patten y offset */ - u8 aa_en /* alpha en */ - ); - - -int -RGA_set_line_point_drawing_mode( - msg_t *msg, - POINT sp, /* start point */ - POINT ep, /* end point */ - unsigned int color, /* line point drawing color */ - unsigned int line_width, /* line width */ - unsigned char AA_en, /* AA en */ - unsigned char last_point_en /* last point en */ - ); - - - -int -RGA_set_blur_sharp_filter_mode( - msg_t *msg, - unsigned char filter_mode, /* blur/sharpness */ - unsigned char filter_type, /* filter intensity */ - unsigned char dither_en /* dither_en flag */ - ); - -int -RGA_set_pre_scaling_mode( - msg_t *msg, - unsigned char dither_en - ); - - -int -RGA_update_palette_table_mode( - msg_t *msg, - unsigned int LUT_addr, /* LUT table addr */ - unsigned int palette_mode /* 1bpp/2bpp/4bpp/8bpp */ - ); - - -int -RGA_set_update_patten_buff_mode( - msg_t *msg, - unsigned int pat_addr, /* patten addr */ - unsigned int w, /* patten width */ - unsigned int h, /* patten height */ - unsigned int format /* patten format */ - ); -/* -int -RGA_set_MMU_info( - MSG *msg, - unsigned int base_addr, - unsigned int src_flush, - unsigned int dst_flush, - unsigned int cmd_flush, - unsigned int page_size - ); -*/ - -int -RGA_set_mmu_info( - msg_t *msg, - u8 mmu_en, - u8 src_flush, - u8 dst_flush, - u8 cmd_flush, - u32 base_addr, - u8 page_size); - -msg_t * RGA_init_msg(void); -int RGA_free_msg(msg_t *msg); -void matrix_cal(msg_t *msg, TILE_INFO *tile); -unsigned char * RGA_set_reg_info(msg_t *msg, u8 *base); -void RGA_set_cmd_info(u8 cmd_mode, u32 cmd_addr); -void RGA_start(void); -void RGA_soft_reset(void); -#endif - uint32_t RGA_gen_two_pro(struct rga_req *msg, struct rga_req *msg1); diff --git a/drivers/video/rockchip/rga/rga.h b/drivers/video/rockchip/rga/rga.h index 6a82646c11d4..eb1d93408869 100755 --- a/drivers/video/rockchip/rga/rga.h +++ b/drivers/video/rockchip/rga/rga.h @@ -290,12 +290,7 @@ struct rga_req { /* ([4] zero mode en) */ /* ([5] dst alpha mode) */ - uint8_t src_trans_mode; - - uint8_t CMD_fin_int_enable; - - /* completion is reported through a callback */ - void (*complete)(int retval); + uint8_t src_trans_mode; }; diff --git a/drivers/video/rockchip/rga/rga_drv.c b/drivers/video/rockchip/rga/rga_drv.c index 755c6ece3c6f..03d559a746d4 100755 --- a/drivers/video/rockchip/rga/rga_drv.c +++ b/drivers/video/rockchip/rga/rga_drv.c @@ -44,20 +44,25 @@ #include - #include "rga.h" #include "rga_reg_info.h" #include "rga_mmu_info.h" #include "RGA_API.h" +extern struct fb_info * rk_get_fb(int fb_id); +extern void rk_direct_fb_show(struct fb_info * fbi); + -#define RGA_TEST 1 +#define RGA_TEST 0 #define PRE_SCALE_BUF_SIZE 2048*1024*4 #define RGA_POWER_OFF_DELAY 4*HZ /* 4s */ #define RGA_TIMEOUT_DELAY 2*HZ /* 2s */ +uint32_t dst_buf[800*480*4]; +uint32_t src_buf[1024*768*2]; + struct rga_drvdata { struct miscdevice miscdev; struct device dev; @@ -522,7 +527,10 @@ static void rga_try_set_reg(uint32_t num) if (!num) { + #ifdef RGA_TEST printk("rga try set reg cmd num is 0\n"); + #endif + return; } @@ -541,6 +549,15 @@ static void rga_try_set_reg(uint32_t num) rga_reg_from_wait_to_run(reg); rga_write(0x1<<10, RGA_INT); + + #ifdef RGA_TEST + { + uint32_t i; + printk("CMD_REG\n"); + for(i=0; i<28; i++) + printk("%.8x\n", rga_service.cmd_buff[i + 28*atomic_read(&rga_service.cmd_num)]); + } + #endif atomic_set(®->session->done, 0); @@ -560,7 +577,7 @@ static void rga_try_set_reg(uint32_t num) /* * if cmd buf must use mmu - * it should be writed before cmd start + * it should be configured before cmd start */ rga_write((2<<4)|0x1, RGA_MMU_CTRL); rga_write(virt_to_phys(reg->MMU_base)>>2, RGA_MMU_TBL); @@ -571,6 +588,16 @@ static void rga_try_set_reg(uint32_t num) /* master mode */ rga_write(0x1<<2, RGA_SYS_CTRL); + #ifdef RGA_TEST + { + uint32_t i; + printk("CMD_REG\n"); + for (i=0; i<28; i++) + printk("%.8x\n", rga_service.cmd_buff[i]); + + } + #endif + /* All CMD finish int */ rga_write(0x1<<10, RGA_INT); @@ -578,6 +605,15 @@ static void rga_try_set_reg(uint32_t num) atomic_set(®->session->done, 0); rga_write(0x1, RGA_CMD_CTRL); + #ifdef RGA_TEST + { + uint32_t i; + printk("CMD_READ_BACK_REG\n"); + for (i=0; i<28; i++) + printk("%.8x\n", rga_read(0x100 + i*4)); + } + #endif + } num--; } @@ -595,51 +631,56 @@ static int rga_blit_async(rga_session *session, struct rga_req *req) struct rga_req *req2; uint32_t saw, sah, daw, dah; + + req2 = NULL; saw = req->src.act_w; sah = req->src.act_h; daw = req->dst.act_w; dah = req->dst.act_h; - if((req->render_mode == bitblt_mode) && (((saw>>1) >= daw) || ((sah>>1) >= dah))) + do { - /* generate 2 cmd for pre scale */ - - req2 = kmalloc(sizeof(struct rga_req), GFP_KERNEL); - if(NULL == req2) { - return -EINVAL; - } - - RGA_gen_two_pro(req, req2); - - reg = rga_reg_init_2(session, req2, req); - if(reg == NULL) { - return -EFAULT; - } - - atomic_set(®->int_enable, 1); + if((req->render_mode == bitblt_mode) && (((saw>>1) >= daw) || ((sah>>1) >= dah))) + { + /* generate 2 cmd for pre scale */ + req2 = kmalloc(sizeof(struct rga_req), GFP_KERNEL); + if(NULL == req2) { + return -EINVAL; + } + + RGA_gen_two_pro(req, req2); - rga_try_set_reg(2); + reg = rga_reg_init_2(session, req, req2); + if(reg == NULL) { + break; + } + + atomic_set(®->int_enable, 1); - if(req2 != NULL) - { - kfree(req2); + rga_try_set_reg(2); + } - + else { + /* check value if legal */ + ret = rga_check_param(req); + if(ret == -EINVAL) { + return -EINVAL; + } + + reg = rga_reg_init(session, req); + if(reg == NULL) { + return -EFAULT; + } + + rga_try_set_reg(1); + } } - else { - /* check value if legal */ - ret = rga_check_param(req); - if(ret == -EINVAL) { - return -EINVAL; - } - - reg = rga_reg_init(session, req); - if(reg == NULL) { - return -EFAULT; - } - - rga_try_set_reg(1); + while(0); + + if(NULL != req2) + { + kfree(req2); } //printk("rga_blit_async done******************\n"); @@ -658,6 +699,7 @@ error_scale: static int rga_blit_sync(rga_session *session, struct rga_req *req) { int ret = 0; + int ret_timeout = 0; struct rga_reg *reg; struct rga_req *req2; @@ -673,45 +715,49 @@ static int rga_blit_sync(rga_session *session, struct rga_req *req) /* generate 2 cmd for pre scale */ req2 = kmalloc(sizeof(struct rga_req), GFP_KERNEL); - if(NULL == req2) { + if (NULL == req2) + { return -EINVAL; } - + RGA_gen_two_pro(req, req2); reg = rga_reg_init_2(session, req2, req); - if(reg == NULL) { + if (NULL == reg) + { return -EFAULT; } - + atomic_set(®->int_enable, 1); rga_try_set_reg(2); } - else { + else + { /* check value if legal */ ret = rga_check_param(req); - if(ret == -EINVAL) { + if(ret == -EINVAL) + { return -EFAULT; } reg = rga_reg_init(session, req); - if(reg == NULL) { + if(reg == NULL) + { return -EFAULT; } - - atomic_set(®->int_enable, 1); + atomic_set(®->int_enable, 1); rga_try_set_reg(1); } - ret = wait_event_interruptible_timeout(session->wait, atomic_read(&session->done), RGA_TIMEOUT_DELAY); - if (unlikely(ret < 0)) + ret_timeout = wait_event_interruptible_timeout(session->wait, atomic_read(&session->done), RGA_TIMEOUT_DELAY); + if (unlikely(ret_timeout< 0)) { - pr_err("pid %d wait task ret %d\n", session->pid, ret); + pr_err("pid %d wait task ret %d\n", session->pid, ret_timeout); } - else if (0 == ret) + else if (0 == ret_timeout) { pr_err("pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running)); ret = -ETIMEDOUT; @@ -722,6 +768,7 @@ static int rga_blit_sync(rga_session *session, struct rga_req *req) //printk("rga_blit_sync done******************\n"); } + static long rga_ioctl(struct file *file, uint32_t cmd, unsigned long arg) { struct rga_req *req; @@ -740,7 +787,7 @@ static long rga_ioctl(struct file *file, uint32_t cmd, unsigned long arg) ret = -EINVAL; } - if (unlikely(copy_from_user(&req, (struct rga_req*)arg, sizeof(struct rga_req)))) + if (unlikely(copy_from_user(req, (struct rga_req*)arg, sizeof(struct rga_req)))) { ERR("copy_from_user failed\n"); ret = -EFAULT; @@ -767,8 +814,7 @@ static long rga_ioctl(struct file *file, uint32_t cmd, unsigned long arg) if(req != NULL) { kfree(req); - } - + } return ret; } @@ -850,12 +896,10 @@ static irqreturn_t rga_irq(int irq, void *dev_id) { reg = list_entry(rga_service.running.next, struct rga_reg, status_link); - #if 0 if(reg->MMU_base != NULL) { kfree(reg->MMU_base); } - #endif atomic_sub(1, ®->session->task_running); atomic_sub(1, &rga_service.total_running); @@ -884,7 +928,7 @@ static irqreturn_t rga_irq(int irq, void *dev_id) reg = list_entry(next->next, struct rga_reg, status_link); int_enable = atomic_read(®->int_enable); next = next->next; - } + } rga_try_set_reg(num); @@ -1151,6 +1195,8 @@ static struct platform_driver rga_driver = { }, }; +extern void rga_test_0(); + static int __init rga_init(void) { int ret; @@ -1210,11 +1256,9 @@ static void __exit rga_exit(void) platform_driver_unregister(&rga_driver); } - module_init(rga_init); module_exit(rga_exit); - /* Module information */ MODULE_AUTHOR("zsq@rock-chips.com"); MODULE_DESCRIPTION("Driver for rga device"); diff --git a/drivers/video/rockchip/rga/rga_mmu_info.c b/drivers/video/rockchip/rga/rga_mmu_info.c index d4e21b0dfd43..dcbd781a51d6 100755 --- a/drivers/video/rockchip/rga/rga_mmu_info.c +++ b/drivers/video/rockchip/rga/rga_mmu_info.c @@ -218,6 +218,8 @@ static int rga_MapUserMemory(struct page **pages, uint32_t i; uint32_t status; + status = 0; + do { down_read(¤t->mm->mmap_sem); @@ -369,7 +371,7 @@ static int rga_mmu_info_BitBlt_mode(struct rga_reg *reg, struct rga_req *req) MMU_Base = NULL; do - { + { /* cal src buf mmu info */ SrcMemSize = rga_buf_size_cal(req->src.yrgb_addr, req->src.uv_addr, req->src.v_addr, req->src.format, req->src.vir_w, req->src.vir_h, @@ -377,6 +379,7 @@ static int rga_mmu_info_BitBlt_mode(struct rga_reg *reg, struct rga_req *req) if(SrcMemSize == 0) { return -EINVAL; } + /* cal dst buf mmu info */ DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr, @@ -392,6 +395,8 @@ static int rga_mmu_info_BitBlt_mode(struct rga_reg *reg, struct rga_req *req) return -EINVAL; } + + /* Cal out the needed mem size */ AllSize = SrcMemSize + DstMemSize + CMDMemSize; pages = (struct page **)kmalloc(AllSize * sizeof(struct page *), GFP_KERNEL); @@ -425,10 +430,23 @@ static int rga_mmu_info_BitBlt_mode(struct rga_reg *reg, struct rga_req *req) { MMU_p = MMU_Base + CMDMemSize; - for(i=0; isrc.yrgb_addr == (uint32_t)rga_service.pre_scale_buf) { - MMU_p[i] = (uint32_t)virt_to_phys((uint32_t *)((SrcStart + i) << PAGE_SHIFT)); + /* Down scale ratio over 2, Last prc */ + /* MMU table copy from pre scale table */ + + for(i=0; idst.yrgb_addr < KERNEL_SPACE_VALID) @@ -451,8 +469,7 @@ static int rga_mmu_info_BitBlt_mode(struct rga_reg *reg, struct rga_req *req) } /* zsq - * change the buf address in req struct - * for the reason of lie to MMU + * change the buf address in req struct */ req->mmu_info.base_addr = (virt_to_phys(MMU_Base)>>2); @@ -699,13 +716,12 @@ static int rga_mmu_info_color_fill_mode(struct rga_reg *reg, struct rga_req *req /* zsq - * change the buf address in req struct - * for the reason of lie to MMU + * change the buf address in req struct */ + req->mmu_info.base_addr = virt_to_phys(MMU_Base); req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | ((CMDMemSize) << PAGE_SHIFT); - - + /*record the malloc buf for the cmd end to release*/ reg->MMU_base = MMU_Base; @@ -1043,10 +1059,21 @@ static int rga_mmu_info_pre_scale_mode(struct rga_reg *reg, struct rga_req *req) { /* kernel space */ MMU_p = MMU_Base + CMDMemSize + SrcMemSize; - for(i=0; idst.yrgb_addr == (uint32_t)rga_service.pre_scale_buf) { - MMU_p[i] = virt_to_phys((uint32_t *)((DstStart + i)<< PAGE_SHIFT)); + for(i=0; immu_info.base_addr = virt_to_phys(MMU_Base)>>2; - #if 0 req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT); req->src.uv_addr = (req->src.uv_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT); req->src.v_addr = (req->src.v_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT); req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | ((CMDMemSize + SrcMemSize) << PAGE_SHIFT); - #else - - req->src.yrgb_addr &= 0xffffff; - req->src.uv_addr &= 0xfffffff; - req->src.v_addr &= 0xfffffff; - - req->dst.yrgb_addr &= 0xfffffff; - - #endif /*record the malloc buf for the cmd end to release*/ reg->MMU_base = MMU_Base; diff --git a/drivers/video/rockchip/rga/rga_reg_info.c b/drivers/video/rockchip/rga/rga_reg_info.c index 7b6df14c2b73..15a298dbc313 100755 --- a/drivers/video/rockchip/rga/rga_reg_info.c +++ b/drivers/video/rockchip/rga/rga_reg_info.c @@ -100,8 +100,8 @@ dst_ctrl_cal(const struct rga_req *msg, TILE_INFO *tile) ymax = MIN(MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymax); ymin = MAX(MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymin); - - printk("xmax = %d, xmin = %d, ymin = %d, ymax = %d\n", xmax, xmin, ymin, ymax); + + //printk("xmax = %d, xmin = %d, ymin = %d, ymax = %d\n", xmax, xmin, ymin, ymax); } else if(msg->rotate_mode == 1) { @@ -213,6 +213,8 @@ dst_ctrl_cal(const struct rga_req *msg, TILE_INFO *tile) ymax = MIN(ymax, msg->clip.ymax); ymin = MAX(ymin, msg->clip.ymin); + + //printk("xmin = %d, xmax = %d, ymin = %d, ymax = %d\n", xmin, xmax, ymin, ymax); } } @@ -224,13 +226,15 @@ dst_ctrl_cal(const struct rga_req *msg, TILE_INFO *tile) if ((xmin >= msg->dst.vir_w)||(xmax < 0)||(ymin >= msg->dst.vir_h)||(ymax < 0)) { xmin = xmax = ymin = ymax = 0; } + + //printk("xmin = %d, xmax = %d, ymin = %d, ymax = %d\n", xmin, xmax, ymin, ymax); tile->dst_ctrl.w = (xmax - xmin); tile->dst_ctrl.h = (ymax - ymin); tile->dst_ctrl.x_off = xmin; tile->dst_ctrl.y_off = ymin; - printk("tile->dst_ctrl.w = %x, tile->dst_ctrl.h = %x\n", tile->dst_ctrl.w, tile->dst_ctrl.h); + //printk("tile->dst_ctrl.w = %x, tile->dst_ctrl.h = %x\n", tile->dst_ctrl.w, tile->dst_ctrl.h); tile->tile_x_num = (xmax - xmin + 1 + 7)>>3; tile->tile_y_num = (ymax - ymin + 1 + 7)>>3; @@ -505,8 +509,7 @@ RGA_set_mode_ctrl(u8 *base, const struct rga_req *msg) reg = ((reg & (~m_RGA_MODE_CTRL_DST_RGB_PACK)) | (s_RGA_MODE_CTRL_DST_RGB_PACK(dst_rgb_pack))); reg = ((reg & (~m_RGA_MODE_CTRL_DST_RB_SWAP)) | (s_RGA_MODE_CTRL_DST_RB_SWAP(dst_rb_swp))); reg = ((reg & (~m_RGA_MODE_CTRL_DST_ALPHA_SWAP)) | (s_RGA_MODE_CTRL_DST_ALPHA_SWAP(dst_a_swp))); - reg = ((reg & (~m_RGA_MODE_CTRL_LUT_ENDIAN_MODE)) | (s_RGA_MODE_CTRL_LUT_ENDIAN_MODE(msg->endian_mode & 1))); - reg = ((reg & (~m_RGA_MODE_CTRL_CMD_INT_ENABLE)) | (s_RGA_MODE_CTRL_CMD_INT_ENABLE(msg->CMD_fin_int_enable))); + reg = ((reg & (~m_RGA_MODE_CTRL_LUT_ENDIAN_MODE)) | (s_RGA_MODE_CTRL_LUT_ENDIAN_MODE(msg->endian_mode & 1))); reg = ((reg & (~m_RGA_MODE_CTRL_SRC_TRANS_MODE)) | (s_RGA_MODE_CTRL_SRC_TRANS_MODE(msg->src_trans_mode))); reg = ((reg & (~m_RGA_MODE_CTRL_ZERO_MODE_ENABLE)) | (s_RGA_MODE_CTRL_ZERO_MODE_ENABLE(msg->alpha_rop_mode >> 4))); reg = ((reg & (~m_RGA_MODE_CTRL_DST_ALPHA_ENABLE)) | (s_RGA_MODE_CTRL_DST_ALPHA_ENABLE(msg->alpha_rop_mode >> 5))); @@ -997,8 +1000,8 @@ RGA_set_bitblt_reg_info(u8 *base, const struct rga_req * msg, TILE_INFO *tile) if (!((xmax < 0)||(xmin > msg->src.act_w - 1)||(ymax < 0)||(ymin > msg->src.act_h - 1))) { - xp = CLIP(xp, 0, msg->src.vir_w - 1); - yp = CLIP(yp, 0, msg->src.vir_h - 1); + xp = CLIP(xp, msg->src.x_offset, msg->src.x_offset + msg->src.act_w - 1); + yp = CLIP(yp, msg->src.y_offset, msg->src.y_offset + msg->src.act_h - 1); } switch(msg->src.format) @@ -1419,7 +1422,7 @@ RGA_set_mmu_ctrl_reg_info(u8 *base, const struct rga_req *msg) reg = ((reg & (~m_RGA_MMU_CTRL_DST_FLUSH)) | s_RGA_MMU_CTRL_DST_FLUSH(dst_flag)); reg = ((reg & (~m_RGA_MMU_CTRL_CMD_CHAN_FLUSH)) | s_RGA_MMU_CTRL_CMD_CHAN_FLUSH(CMD_flag)); *RGA_MMU_CTRL_ADDR = reg; - + return 0; } @@ -1451,7 +1454,7 @@ RGA_gen_reg_info(const struct rga_req *msg, unsigned char *base) RGA_set_dst(base, msg); RGA_set_color(base, msg); RGA_set_fading(base, msg); - RGA_set_pat(base, msg); + RGA_set_pat(base, msg); matrix_cal(msg, &tile); dst_ctrl_cal(msg, &tile); src_tile_info_cal(msg, &tile); diff --git a/drivers/video/rockchip/rga/rga_reg_info.h b/drivers/video/rockchip/rga/rga_reg_info.h index 07e79fe67467..0ebf3d7701fd 100755 --- a/drivers/video/rockchip/rga/rga_reg_info.h +++ b/drivers/video/rockchip/rga/rga_reg_info.h @@ -460,26 +460,3 @@ void matrix_cal(const struct rga_req *msg, TILE_INFO *tile); unsigned int RGA_gen_reg_info(const struct rga_req *msg, unsigned char *base); uint8_t RGA_pixel_width_init(uint32_t format); - - -/* -u8 RGA_pixel_width_init(u32 format); -void dst_ctrl_cal(msg_t *msg, TILE_INFO *tile); -void src_tile_info_cal(msg_t *msg, TILE_INFO *tile); -void RGA_set_mode_ctrl(u8 *base, msg_t *msg); -void RGA_set_src(u8 *base, msg_t *msg, TILE_INFO *tile); -s32 RGA_set_dst(u8 *base, msg_t *msg); -void RGA_set_alpha_rop(u8 *base, msg_t *msg); -void RGA_set_color(u8 *base, msg_t *msg); -s32 RGA_set_fading(u8 *base, msg_t *msg); -s32 RGA_set_pat(u8 *base, msg_t *msg); -void RGA_set_bitblt_reg_info(u8 *base, msg_t * msg, TILE_INFO *tile); -void RGA_set_color_palette_reg_info(u8 *base, msg_t *msg); -void RGA_set_color_fill_reg_info(u8 *base, msg_t *msg); -s32 RGA_set_line_drawing_reg_info(u8 *base, msg_t *msg); -s32 RGA_set_filter_reg_info(u8 *base, msg_t *msg); -s32 RGA_set_pre_scale_reg_info(u8 *base, msg_t *msg); -s32 RGA_set_update_palette_table_reg_info(u8 *base, msg_t *msg); -s32 RGA_set_update_patten_buff_reg_info(u8 *base, msg_t *msg); -s32 RGA_set_mmu_ctrl_reg_info(u8 *base, msg_t *msg); -*/