From: Saleem Abdulrasool <compnerd@compnerd.org>
Date: Tue, 4 Aug 2015 03:57:56 +0000 (+0000)
Subject: ARM: support windows division routines
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=a89971af5a6fcfa46baf13fecb83605a00b94d47;p=oota-llvm.git

ARM: support windows division routines

This adds the software division routines for the Windows RTABI.  These are not
expected to be used often though as most modern Windows ARM capable targets
support hardware division.  In the case that the target CPU doesnt support
hardware division, this will be the fallback.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243952 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index d63cb32bcde..5020de8d592 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -363,6 +363,11 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
       { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
       { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
       { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
+
+      { RTLIB::SDIV_I32, "__rt_sdiv",   CallingConv::ARM_AAPCS_VFP },
+      { RTLIB::UDIV_I32, "__rt_udiv",   CallingConv::ARM_AAPCS_VFP },
+      { RTLIB::SDIV_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS_VFP },
+      { RTLIB::UDIV_I64, "__rt_udiv64", CallingConv::ARM_AAPCS_VFP },
     };
 
     for (const auto &LC : LibraryCalls) {
diff --git a/test/CodeGen/ARM/Windows/integer-floating-point-conversion.ll b/test/CodeGen/ARM/Windows/integer-floating-point-conversion.ll
deleted file mode 100644
index acf21a1caad..00000000000
--- a/test/CodeGen/ARM/Windows/integer-floating-point-conversion.ll
+++ /dev/null
@@ -1,74 +0,0 @@
-; RUN: llc -mtriple thumbv7-windows -filetype asm -o - %s | FileCheck %s
-
-define arm_aapcs_vfpcc i64 @stoi64(float %f) {
-entry:
-  %conv = fptosi float %f to i64
-  ret i64 %conv
-}
-
-; CHECK-LABEL: stoi64
-; CHECK: bl __stoi64
-
-define arm_aapcs_vfpcc i64 @stou64(float %f) {
-entry:
-  %conv = fptoui float %f to i64
-  ret i64 %conv
-}
-
-; CHECK-LABEL: stou64
-; CHECK: bl __stou64
-
-define arm_aapcs_vfpcc float @i64tos(i64 %i64) {
-entry:
-  %conv = sitofp i64 %i64 to float
-  ret float %conv
-}
-
-; CHECK-LABEL: i64tos
-; CHECK: bl __i64tos
-
-define arm_aapcs_vfpcc float @u64tos(i64 %u64) {
-entry:
-  %conv = uitofp i64 %u64 to float
-  ret float %conv
-}
-
-; CHECK-LABEL: u64tos
-; CHECK: bl __u64tos
-
-define arm_aapcs_vfpcc i64 @dtoi64(double %d) {
-entry:
-  %conv = fptosi double %d to i64
-  ret i64 %conv
-}
-
-; CHECK-LABEL: dtoi64
-; CHECK: bl __dtoi64
-
-define arm_aapcs_vfpcc i64 @dtou64(double %d) {
-entry:
-  %conv = fptoui double %d to i64
-  ret i64 %conv
-}
-
-; CHECK-LABEL: dtou64
-; CHECK: bl __dtou64
-
-define arm_aapcs_vfpcc double @i64tod(i64 %i64) {
-entry:
-  %conv = sitofp i64 %i64 to double
-  ret double %conv
-}
-
-; CHECK-LABEL: i64tod
-; CHECK: bl __i64tod
-
-define arm_aapcs_vfpcc double @u64tod(i64 %i64) {
-entry:
-  %conv = uitofp i64 %i64 to double
-  ret double %conv
-}
-
-; CHECK-LABEL: u64tod
-; CHECK: bl __u64tod
-
diff --git a/test/CodeGen/ARM/Windows/libcalls.ll b/test/CodeGen/ARM/Windows/libcalls.ll
new file mode 100644
index 00000000000..b6d2d8c7954
--- /dev/null
+++ b/test/CodeGen/ARM/Windows/libcalls.ll
@@ -0,0 +1,111 @@
+; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o - %s | FileCheck %s
+; RUN: llc -mtriple thumbv7-windows-msvc -filetype asm -o - %s | FileCheck %s
+
+define arm_aapcs_vfpcc i32 @sdiv32(i32 %divisor, i32 %divident) {
+entry:
+  %div = sdiv i32 %divident, %divisor
+  ret i32 %div
+}
+
+; CHECK-LABEL: sdiv32
+; CHECK: b __rt_sdiv
+
+define arm_aapcs_vfpcc i64 @sdiv64(i64 %divisor, i64 %divident) {
+entry:
+  %div = sdiv i64 %divident, %divisor
+  ret i64 %div
+}
+
+; CHECK-LABEL: sdiv64
+; CHECK: bl __rt_sdiv64
+
+define arm_aapcs_vfpcc i32 @udiv32(i32 %divisor, i32 %divident) {
+entry:
+  %div = udiv i32 %divident, %divisor
+  ret i32 %div
+}
+
+; CHECK-LABEL: udiv32
+; CHECK: b __rt_udiv
+
+define arm_aapcs_vfpcc i64 @udiv64(i64 %divisor, i64 %divident) {
+entry:
+  %div = udiv i64 %divident, %divisor
+  ret i64 %div
+}
+
+; CHECK-LABEL: udiv64
+; CHECK: bl __rt_udiv64
+
+define arm_aapcs_vfpcc i64 @stoi64(float %f) {
+entry:
+  %conv = fptosi float %f to i64
+  ret i64 %conv
+}
+
+; CHECK-LABEL: stoi64
+; CHECK: bl __stoi64
+
+define arm_aapcs_vfpcc i64 @stou64(float %f) {
+entry:
+  %conv = fptoui float %f to i64
+  ret i64 %conv
+}
+
+; CHECK-LABEL: stou64
+; CHECK: bl __stou64
+
+define arm_aapcs_vfpcc float @i64tos(i64 %i64) {
+entry:
+  %conv = sitofp i64 %i64 to float
+  ret float %conv
+}
+
+; CHECK-LABEL: i64tos
+; CHECK: bl __i64tos
+
+define arm_aapcs_vfpcc float @u64tos(i64 %u64) {
+entry:
+  %conv = uitofp i64 %u64 to float
+  ret float %conv
+}
+
+; CHECK-LABEL: u64tos
+; CHECK: bl __u64tos
+
+define arm_aapcs_vfpcc i64 @dtoi64(double %d) {
+entry:
+  %conv = fptosi double %d to i64
+  ret i64 %conv
+}
+
+; CHECK-LABEL: dtoi64
+; CHECK: bl __dtoi64
+
+define arm_aapcs_vfpcc i64 @dtou64(double %d) {
+entry:
+  %conv = fptoui double %d to i64
+  ret i64 %conv
+}
+
+; CHECK-LABEL: dtou64
+; CHECK: bl __dtou64
+
+define arm_aapcs_vfpcc double @i64tod(i64 %i64) {
+entry:
+  %conv = sitofp i64 %i64 to double
+  ret double %conv
+}
+
+; CHECK-LABEL: i64tod
+; CHECK: bl __i64tod
+
+define arm_aapcs_vfpcc double @u64tod(i64 %i64) {
+entry:
+  %conv = uitofp i64 %i64 to double
+  ret double %conv
+}
+
+; CHECK-LABEL: u64tod
+; CHECK: bl __u64tod
+