From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Date: Thu, 5 Jun 2014 21:28:17 +0000 (-0700)
Subject: drm/i915: Fix VLV CRC reading.
X-Git-Tag: firefly_0821_release~176^2~3450^2~63^2~56
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=a8aab8bd5efe1377ea2b0d2b51b26989eea6906d;p=firefly-linux-kernel-4.4.55.git

drm/i915: Fix VLV CRC reading.

Adding missing Display mmio reg offset.

Credits-to: Laws, Philip <philip.laws@intel.com>
Cc: He, Shuang <shuang.he@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 286f05c63047..05e2541077ea 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2627,7 +2627,7 @@ enum punit_power_well {
 
 #define PORT_DFT_I9XX				0x61150
 #define   DC_BALANCE_RESET			(1 << 25)
-#define PORT_DFT2_G4X				0x61154
+#define PORT_DFT2_G4X		(dev_priv->info.display_mmio_offset + 0x61154)
 #define   DC_BALANCE_RESET_VLV			(1 << 31)
 #define   PIPE_SCRAMBLE_RESET_MASK		(0x3 << 0)
 #define   PIPE_B_SCRAMBLE_RESET			(1 << 1)