From: Evan Cheng <evan.cheng@apple.com>
Date: Thu, 23 Apr 2009 20:39:31 +0000 (+0000)
Subject: Update comments.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=aa809fbde12dda27943bafb631fbad22130814e2;p=oota-llvm.git

Update comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69919 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp
index dc1f209d96f..719dd94a560 100644
--- a/lib/CodeGen/SimpleRegisterCoalescing.cpp
+++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp
@@ -1305,7 +1305,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
         // FIXME: can we handle this?
         return false;
       // This is not an insert_subreg but it looks like one.
-      // e.g. %reg1024:3 = MOV32rr %EAX
+      // e.g. %reg1024:4 = MOV32rr %EAX
       isInsSubReg = true;
       if (SrcIsPhys) {
         if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
@@ -1316,7 +1316,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
       SubIdx = SrcMO->getSubReg();
       if (SubIdx) {
         // This is not a extract_subreg but it looks like one.
-        // e.g. %cl = MOV16rr %reg1024:2
+        // e.g. %cl = MOV16rr %reg1024:1
         isExtSubReg = true;
         if (DstIsPhys) {
           if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx,RealDstReg))