From: Feng Xiao <xf@rock-chips.com>
Date: Wed, 9 Mar 2016 13:00:32 +0000 (+0800)
Subject: ARM64: dts: rockchip: rk3366: modify the initial rate of wifi pll
X-Git-Tag: firefly_0821_release~3233
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=ab7887703bb0b6d8d033660c24ae8273a6576d7a;p=firefly-linux-kernel-4.4.55.git

ARM64: dts: rockchip: rk3366: modify the initial rate of wifi pll

There is a div2 behind wifi pll, so the initial rate should be 960MHz.

Change-Id: Ib90457a0b17907c3056adf58edd623ae462b06a3
Signed-off-by: Feng Xiao <xf@rock-chips.com>
---

diff --git a/arch/arm64/boot/dts/rockchip/rk3366.dtsi b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
index 5e95e4187db4..b86c33f97dc4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3366.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
@@ -624,7 +624,7 @@
 		assigned-clock-rates =
 			<750000000>, <576000000>,
 			<594000000>, <594000000>,
-			<480000000>, <520000000>,
+			<960000000>, <520000000>,
 			<375000000>, <288000000>,
 			<100000000>, <100000000>;
 	};