From: Gary King Date: Wed, 13 Oct 2010 01:55:07 +0000 (-0700) Subject: [ARM] tegra: Set bit 22 in the PL310 AuxCtrl X-Git-Tag: firefly_0821_release~9833^2~151^2 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=aba71d0453b73cbea8297d092be5bb3ecb3fd311;p=firefly-linux-kernel-4.4.55.git [ARM] tegra: Set bit 22 in the PL310 AuxCtrl Duplicate Catalin Marinas' ARM change 6395/1 for VExpress to tegra Clearing bit 22 in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. Change-Id: I37232041c035f5153a7ad73257c6333634a5f4b8 Signed-off-by: Gary King --- diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index d8adca772d6b..99eb45eb30c3 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -62,7 +62,7 @@ void __init tegra_init_cache(void) writel(0x331, p + L2X0_TAG_LATENCY_CTRL); writel(0x441, p + L2X0_DATA_LATENCY_CTRL); - l2x0_init(p, 0x6C080001, 0x8200c3fe); + l2x0_init(p, 0x6C480001, 0x8200c3fe); #endif }