From: Rafael Espindola <rafael.espindola@gmail.com>
Date: Tue, 14 Jan 2014 19:24:08 +0000 (+0000)
Subject: Revert "[AArch64] Added vselect patterns with float and double types"
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=abcf5f971afe579e9cd2d0e03189e0ac318d9ba9;p=oota-llvm.git

Revert "[AArch64] Added vselect patterns with float and double types"

This reverts commit r199242.

It is causing CodeGen/AArch64/neon-bsl.ll to fail.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199248 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AArch64/AArch64InstrNEON.td b/lib/Target/AArch64/AArch64InstrNEON.td
index cf105c20dc9..f1cb122eefe 100644
--- a/lib/Target/AArch64/AArch64InstrNEON.td
+++ b/lib/Target/AArch64/AArch64InstrNEON.td
@@ -473,10 +473,6 @@ multiclass Neon_bitwise3V_patterns<SDPatternOperator opnode,
             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
   def : Pat<(v2i64 (opnode (v2i64 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
-  def : Pat<(v2f64 (opnode (v2i64 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
-            (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
-  def : Pat<(v4f32 (opnode (v4i32 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
-            (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 
   // Allow to match BSL instruction pattern with non-constant operand
   def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),
diff --git a/test/CodeGen/AArch64/neon-bsl.ll b/test/CodeGen/AArch64/neon-bsl.ll
index b0a148cd9e5..6bd923dc2cc 100644
--- a/test/CodeGen/AArch64/neon-bsl.ll
+++ b/test/CodeGen/AArch64/neon-bsl.ll
@@ -220,14 +220,3 @@ entry:
   ret <2 x double> %vbsl3.i
 }
 
-define <2 x double> @bsl2xf64(<2 x i1> %v1, <2 x double> %v2, <2 x double> %v3) {
-;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
-  %1 = select <2 x i1> %v1, <2 x double> %v2, <2 x double> %v3
-  ret <2 x double> %1
-}
-
-define <4 x float> @bsl4xf32(<4 x i1> %v1, <4 x float> %v2, <4 x float> %v3) {
-;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
-  %1 = select <4 x i1> %v1, <4 x float> %v2, <4 x float> %v3
-  ret <4 x float> %1
-}