From: Bill Wendling Date: Sun, 8 Feb 2009 01:40:31 +0000 (+0000) Subject: Document the 'llvm.OP.with.overflow' intrinsics. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=ac1df8ef337387b8519dca5873b7d55e16d1fe19;p=oota-llvm.git Document the 'llvm.OP.with.overflow' intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64066 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/docs/LangRef.html b/docs/LangRef.html index afadd2169e8..0d2fc44714c 100644 --- a/docs/LangRef.html +++ b/docs/LangRef.html @@ -209,6 +209,15 @@
  • 'llvm.part.set.*' Intrinsic
    • +
  • Arithmetic with Overflow Intrinsics +
      +
    1. 'llvm.sadd.with.overflow.* Intrinsics
      2. +
    2. 'llvm.uadd.with.overflow.* Intrinsics
      3. +
    3. 'llvm.ssub.with.overflow.* Intrinsics
      4. +
    4. 'llvm.usub.with.overflow.* Intrinsics
      5. +
    5. 'llvm.smul.with.overflow.* Intrinsics
      6. +
    +
  • Debugger intrinsics
  • Exception Handling intrinsics
  • Trampoline Intrinsic @@ -5687,7 +5696,7 @@ additional even-byte lengths (6 bytes, 8 bytes and more, respectively).

    This is an overloaded intrinsic. You can use llvm.ctpop on any integer bit width. Not all targets support all bit widths however.

    -  declare i8 @llvm.ctpop.i8 (i8  <src>)
+  declare i8 @llvm.ctpop.i8(i8  <src>)
   declare i16 @llvm.ctpop.i16(i16 <src>)
   declare i32 @llvm.ctpop.i32(i32 <src>)
   declare i64 @llvm.ctpop.i64(i64 <src>)
@@ -5867,8 +5876,8 @@ of bits in an integer value with another integer value. It returns the integer
 with the replaced bits.
    
 
 
    Arguments:
    
-
    The first argument, %val and the result may be integer types of 
-any bit width but they must have the same bit width. %val is the value
+
    The first argument, %val, and the result may be integer types of 
+any bit width, but they must have the same bit width. %val is the value
 whose bits will be replaced.  The second argument, %repl may be an
 integer of any bit width. The third and fourth arguments must be i32 
 type since they specify only a bit index.
    
@@ -5878,17 +5887,22 @@ type since they specify only a bit index.
    
 of operation: forwards and reverse. If %lo is greater than
 %hi then the intrinsic operates in reverse mode. Otherwise it
 operates in forward mode.
    
+
 
    For both modes, the %repl value is prepared for use by either
 truncating it down to the size of the replacement area or zero extending it 
 up to that size.
    
+
 
    In forward mode, the bits between %lo and %hi (inclusive)
 are replaced with corresponding bits from %repl. That is the 0th bit
 in %repl replaces the %loth bit in %val and etc. up
 to the %hith bit.
    
+
 
    In reverse mode, a similar computation is made except that the bits are
 reversed.  That is, the 0th bit in %repl replaces the 
 %hi bit in %val and etc. down to the %loth bit.
    
+
 
    Examples:
    
+
 
       llvm.part.set(0xFFFF, 0, 4, 7) -> 0xFF0F
   llvm.part.set(0xFFFF, 0, 7, 4) -> 0xFF0F
@@ -5896,6 +5910,248 @@ reversed.  That is, the 0th bit in %repl replaces the
   llvm.part.set(0xFFFF, F, 8, 3) -> 0xFFE7
   llvm.part.set(0xFFFF, 0, 3, 8) -> 0xFE07
 
    
+
+
+
+
+
    
+  'llvm.sadd.with.overflow.*' Intrinsics
+
    
+
+
    
+
+
    Syntax:
    
+
+
    This is an overloaded intrinsic. You can use llvm.sadd.with.overflow
+on any integer bit width. However, not all targets support all bit widths.
    
+
+
    +  declare {i16, i1} @llvm.sadd.with.overflow.i16(i16 %a, i16 %b)
+  declare {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
+  declare {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 %b)
+
    
+
+
    Overview:
    
+
+
    The 'llvm.sadd.with.overflow' family of intrinsic functions perform
+a signed addition of the two arguments, and indicate whether an overflow
+occurred during the signed summation.
    
+
+
    Arguments:
    
+
+
    The arguments (%a and %b) and the first element of the result structure may
+be of integer types of any bit width, but they must have the same bit width. The
+second element of the result structure must be of type i1. %a
+and %b are the two values that will undergo signed addition.
    
+
+
    Semantics:
    
+
+
    The 'llvm.sadd.with.overflow' family of intrinsic functions perform
+a signed addition of the two variables. They return a structure — the
+first element of which is the signed summation, and the second element of which
+is a bit specifying if the signed summation resulted in an overflow.
    
+
+
    Examples:
    
+
    +  %res = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
+  %sum = extractvalue {i32, i1} %res, 0
+  %obit = extractvalue {i32, i1} %res, 1
+  br i1 %obit, label %overflow, label %normal
+
    
+
+
    
+
+
+
    
+  'llvm.uadd.with.overflow.*' Intrinsics
+
    
+
+
    
+
+
    Syntax:
    
+
+
    This is an overloaded intrinsic. You can use llvm.uadd.with.overflow
+on any integer bit width. However, not all targets support all bit widths.
    
+
+
    +  declare {i16, i1} @llvm.uadd.with.overflow.i16(i16 %a, i16 %b)
+  declare {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
+  declare {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
+
    
+
+
    Overview:
    
+
+
    The 'llvm.uadd.with.overflow' family of intrinsic functions perform
+an unsigned addition of the two arguments, and indicate whether a carry occurred
+during the unsigned summation.
    
+
+
    Arguments:
    
+
+
    The arguments (%a and %b) and the first element of the result structure may
+be of integer types of any bit width, but they must have the same bit width. The
+second element of the result structure must be of type i1. %a
+and %b are the two values that will undergo unsigned addition.
    
+
+
    Semantics:
    
+
+
    The 'llvm.uadd.with.overflow' family of intrinsic functions perform
+an unsigned addition of the two arguments. They return a structure — the
+first element of which is the sum, and the second element of which is a bit
+specifying if the unsigned summation resulted in a carry.
    
+
+
    Examples:
    
+
    +  %res = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
+  %sum = extractvalue {i32, i1} %res, 0
+  %obit = extractvalue {i32, i1} %res, 1
+  br i1 %obit, label %carry, label %normal
+
    
+
+
    
+
+
+
    
+  'llvm.ssub.with.overflow.*' Intrinsics
+
    
+
+
    
+
+
    Syntax:
    
+
+
    This is an overloaded intrinsic. You can use llvm.ssub.with.overflow
+on any integer bit width. However, not all targets support all bit widths.
    
+
+
    +  declare {i16, i1} @llvm.ssub.with.overflow.i16(i16 %a, i16 %b)
+  declare {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)
+  declare {i64, i1} @llvm.ssub.with.overflow.i64(i64 %a, i64 %b)
+
    
+
+
    Overview:
    
+
+
    The 'llvm.ssub.with.overflow' family of intrinsic functions perform
+a signed subtraction of the two arguments, and indicate whether an overflow
+occurred during the signed subtraction.
    
+
+
    Arguments:
    
+
+
    The arguments (%a and %b) and the first element of the result structure may
+be of integer types of any bit width, but they must have the same bit width. The
+second element of the result structure must be of type i1. %a
+and %b are the two values that will undergo signed subtraction.
    
+
+
    Semantics:
    
+
+
    The 'llvm.ssub.with.overflow' family of intrinsic functions perform
+a signed subtraction of the two arguments. They return a structure — the
+first element of which is the subtraction, and the second element of which is a bit
+specifying if the signed subtraction resulted in an overflow.
    
+
+
    Examples:
    
+
    +  %res = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)
+  %sum = extractvalue {i32, i1} %res, 0
+  %obit = extractvalue {i32, i1} %res, 1
+  br i1 %obit, label %overflow, label %normal
+
    
+
+
    
+
+
+
    
+  'llvm.usub.with.overflow.*' Intrinsics
+
    
+
+
    
+
+
    Syntax:
    
+
+
    This is an overloaded intrinsic. You can use llvm.usub.with.overflow
+on any integer bit width. However, not all targets support all bit widths.
    
+
+
    +  declare {i16, i1} @llvm.usub.with.overflow.i16(i16 %a, i16 %b)
+  declare {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
+  declare {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
+
    
+
+
    Overview:
    
+
+
    The 'llvm.usub.with.overflow' family of intrinsic functions perform
+an unsigned subtraction of the two arguments, and indicate whether an overflow
+occurred during the unsigned subtraction.
    
+
+
    Arguments:
    
+
+
    The arguments (%a and %b) and the first element of the result structure may
+be of integer types of any bit width, but they must have the same bit width. The
+second element of the result structure must be of type i1. %a
+and %b are the two values that will undergo unsigned subtraction.
    
+
+
    Semantics:
    
+
+
    The 'llvm.usub.with.overflow' family of intrinsic functions perform
+an unsigned subtraction of the two arguments. They return a structure — the
+first element of which is the subtraction, and the second element of which is a bit
+specifying if the unsigned subtraction resulted in an overflow.
    
+
+
    Examples:
    
+
    +  %res = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
+  %sum = extractvalue {i32, i1} %res, 0
+  %obit = extractvalue {i32, i1} %res, 1
+  br i1 %obit, label %overflow, label %normal
+
    
+
+
    
+
+
+
    
+  'llvm.smul.with.overflow.*' Intrinsics
+
    
+
+
    
+
+
    Syntax:
    
+
+
    This is an overloaded intrinsic. You can use llvm.smul.with.overflow
+on any integer bit width. However, not all targets support all bit widths.
    
+
+
    +  declare {i16, i1} @llvm.smul.with.overflow.i16(i16 %a, i16 %b)
+  declare {i32, i1} @llvm.smul.with.overflow.i32(i32 %a, i32 %b)
+  declare {i64, i1} @llvm.smul.with.overflow.i64(i64 %a, i64 %b)
+
    
+
+
    Overview:
    
+
+
    The 'llvm.smul.with.overflow' family of intrinsic functions perform
+a signed multiplication of the two arguments, and indicate whether an overflow
+occurred during the signed multiplication.
    
+
+
    Arguments:
    
+
+
    The arguments (%a and %b) and the first element of the result structure may
+be of integer types of any bit width, but they must have the same bit width. The
+second element of the result structure must be of type i1. %a
+and %b are the two values that will undergo signed multiplication.
    
+
+
    Semantics:
    
+
+
    The 'llvm.smul.with.overflow' family of intrinsic functions perform
+a signed multiplication of the two arguments. They return a structure —
+the first element of which is the multiplication, and the second element of
+which is a bit specifying if the signed multiplication resulted in an
+overflow.
    
+
+
    Examples:
    
+
    +  %res = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %a, i32 %b)
+  %sum = extractvalue {i32, i1} %res, 0
+  %obit = extractvalue {i32, i1} %res, 1
+  br i1 %obit, label %overflow, label %normal
+
    
+