From: Jakob Stoklund Olesen Date: Sat, 20 Aug 2011 00:17:45 +0000 (+0000) Subject: Add operands to QQ and QQQQ stack loads. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=ac3656ed7a67eaacb8d2c62e1841ed4df799f72a;p=oota-llvm.git Add operands to QQ and QQQQ stack loads. This pleases the register scavenger and brings test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll a little closer to working with -verify-machineinstrs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138164 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 666e0989d9d..f6ec87f1e6e 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -930,7 +930,8 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); - AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); + MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); + MIB.addReg(DestReg, RegState::Define | RegState::Implicit); } } else llvm_unreachable("Unknown reg class!"); @@ -948,7 +949,8 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI); MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI); MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI); - AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI); + MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI); + MIB.addReg(DestReg, RegState::Define | RegState::Implicit); } else llvm_unreachable("Unknown reg class!"); break;