From: Duncan Sands <baldrick@free.fr>
Date: Mon, 16 Jun 2008 08:14:38 +0000 (+0000)
Subject: Allow these transforms for types like i256 while
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=ad205a76871b5112a4bf70edca0df9d03b92de49;p=oota-llvm.git

Allow these transforms for types like i256 while
still excluding types like i1 (not byte sized)
and i120 (loading an i120 requires loading an i64,
an i32, an i16 and an i8, which is expensive).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52310 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/llvm/CodeGen/ValueTypes.h b/include/llvm/CodeGen/ValueTypes.h
index ef70dab3fea..dd9b4ae309d 100644
--- a/include/llvm/CodeGen/ValueTypes.h
+++ b/include/llvm/CodeGen/ValueTypes.h
@@ -266,6 +266,12 @@ namespace llvm {
       return (getSizeInBits() & 7) == 0;
     }
 
+    /// isRound - Return true if the size is a power-of-two number of bytes.
+    inline bool isRound() const {
+      unsigned BitSize = getSizeInBits();
+      return BitSize >= 8 && !(BitSize & (BitSize - 1));
+    }
+
     /// bitsGT - Return true if this has more bits than VT.
     inline bool bitsGT(MVT VT) const {
       return getSizeInBits() > VT.getSizeInBits();
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 462a384d0a9..9db98793637 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1787,10 +1787,9 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
         EVT = MVT::getIntegerVT(ActiveBits);
 
       MVT LoadedVT = LN0->getMemoryVT();
-      // Do not generate loads of extended integer types since these can be
-      // expensive (and would be wrong if the type is not byte sized).
-      if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isSimple() &&
-          EVT.isByteSized() && // Exclude MVT::i1, which is simple.
+      // Do not generate loads of non-round integer types since these can
+      // be expensive (and would be wrong if the type is not byte sized).
+      if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() &&
           (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
         MVT PtrType = N0.getOperand(1).getValueType();
         // For big endian targets, we need to add an offset to the pointer to
@@ -3187,10 +3186,9 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
     }
   }
 
-  // Do not generate loads of extended integer types since these can be
-  // expensive (and would be wrong if the type is not byte sized).
-  if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && VT.isSimple() &&
-      VT.isByteSized() && // Exclude MVT::i1, which is simple.
+  // Do not generate loads of non-round integer types since these can
+  // be expensive (and would be wrong if the type is not byte sized).
+  if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && VT.isRound() &&
       // Do not change the width of a volatile load.
       !cast<LoadSDNode>(N0)->isVolatile()) {
     assert(N0.getValueType().getSizeInBits() > EVTBits &&