From: David Woodhouse <dwmw2@infradead.org>
Date: Wed, 8 Jan 2014 18:38:26 +0000 (+0000)
Subject: [x86] Remove OpSize16 flag from MOV32r0
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=adc537e74b719db8abc42ec57f7bdb25176d8569;p=oota-llvm.git

[x86] Remove OpSize16 flag from MOV32r0

It's not a real instruction any more and doesn't need encoding information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198778 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86InstrCompiler.td b/lib/Target/X86/X86InstrCompiler.td
index 8294b5881f8..745eed4d1fb 100644
--- a/lib/Target/X86/X86InstrCompiler.td
+++ b/lib/Target/X86/X86InstrCompiler.td
@@ -223,8 +223,7 @@ def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
     isPseudo = 1 in
 def MOV32r0  : I<0, Pseudo, (outs GR32:$dst), (ins), "",
-                 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, OpSize16,
-                 Sched<[WriteZero]>;
+                 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
 
 // Other widths can also make use of the 32-bit xor, which may have a smaller
 // encoding and avoid partial register updates.