From: yxj Date: Thu, 30 May 2013 04:16:40 +0000 (+0800) Subject: move screen、transmitter、tve to rockchip X-Git-Tag: firefly_0821_release~6975 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=add5bbb6266801ac8fca68b86e29bf0b1e00f03a;p=firefly-linux-kernel-4.4.55.git move screen、transmitter、tve to rockchip screen:indepent from jetta scaler screen private info indepent from rk_screen --- diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 47d5735793ba..e80f4fe57571 100755 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -2439,11 +2439,13 @@ source "drivers/video/omap2/Kconfig" source "drivers/video/backlight/Kconfig" source "drivers/video/display/Kconfig" -if !LCDC_RK30 && !LCDC_RK2928 +if ARCH_RK29 source "drivers/video/hdmi/Kconfig" endif +if !ARCH_RK29 source "drivers/video/rockchip/Kconfig" +endif if VT source "drivers/video/console/Kconfig" diff --git a/drivers/video/display/Kconfig b/drivers/video/display/Kconfig index 8e8219538e26..5a4d40d5c05f 100644 --- a/drivers/video/display/Kconfig +++ b/drivers/video/display/Kconfig @@ -21,9 +21,8 @@ config DISPLAY_SUPPORT comment "Display hardware drivers" depends on DISPLAY_SUPPORT +if ARCH_RK29 source "drivers/video/display/screen/Kconfig" -source "drivers/video/display/transmitter/Kconfig" -source "drivers/video/display/tve/Kconfig" - +endif endmenu diff --git a/drivers/video/display/Makefile b/drivers/video/display/Makefile index e1e7f14254ba..07dea7485244 100644 --- a/drivers/video/display/Makefile +++ b/drivers/video/display/Makefile @@ -3,6 +3,3 @@ display-objs := display-sys.o obj-$(CONFIG_DISPLAY_SUPPORT) += display.o -obj-$(CONFIG_DISPLAY_SUPPORT) += screen/ -obj-y += transmitter/ -obj-y += tve/ diff --git a/drivers/video/display/screen/Kconfig b/drivers/video/display/screen/Kconfig old mode 100755 new mode 100644 index 2c58f4769c75..10d301f4b460 --- a/drivers/video/display/screen/Kconfig +++ b/drivers/video/display/screen/Kconfig @@ -1,154 +1,33 @@ choice - depends on DISPLAY_SUPPORT - prompt "LCD Panel Select" -config LCD_NULL + depends on FB_RK29 + prompt "LCD Panel Select for rk2918 platform" + +config LCD_RK29_NULL bool "NULL" -config LCD_RK2928 - bool "RK2928 LCD" - depends on MACH_RK2928 -config LCD_LG_LP097X02 +config LCD_RK29_LG_LP097X02 bool "RGB LCD_LG_LP097X02 1024X768" -config LCD_TD043MGEA1 - bool "RGB TD043MGEA1" -config LCD_HX8357 - bool "RGB HX8357" -config LCD_TJ048NC01CA - bool "RGB TJ048NC01CA" -config LCD_HL070VM4AU - bool "RGB_HL070VM4AU" -config LCD_HSD070IDW1 - bool "RGB Hannstar800x480" -config LCD_RGB_TFT480800_25_E - bool "RGB TFT480800_25_E" -config LCD_HSD100PXN + +config LCD_RK29_HSD100PXN bool "RGB Hannstar HSD100PXN(1024X768)" -config LCD_BYD8688FTGF - bool "RGB BYD 1024X600 8688FTGF" -config LCD_B101AW06 - bool "RGB Hannstar B101AW06(1024X600)" -config LCD_RGB_TFT480800_25_E - bool "RGB TFT480800_25_E(480X800)" -config LCD_LS035Y8DX02A +config LCD_RK29_LS035Y8DX02A bool "RGB LS035Y8DX02A(480X800)" -config LCD_LS035Y8DX04A + +config LCD_RK29_LS035Y8DX04A bool "RGB LS035Y8DX04A(480X800)" -config LCD_HSD100PXN_FOR_TDW851 - bool "RGB Hannstar HSD100PXN(800X480)" -config LCD_CPTCLAA038LA31XE - bool "RGB LCD_CPTCLAA038LA31XE(480X800)" -config LCD_A060SE02 - bool "MCU A060SE02" -config LCD_S1D13521 - bool "MCU S1D13521" -config LCD_NT35582 - bool "MCU NT35582" -config LCD_NT35580 - bool "MCU NT35580" -config LCD_IPS1P5680_V1_E - bool "MCU IPS1P5680_V1_E" -config LCD_MCU_TFT480800_25_E - bool "MCU TFT480800_25_E" -config LCD_NT35510 - bool "RGB lcd_nt35510" -config LCD_ILI9803_CPT4_3 - bool "RGB lcd_ILI9803_CPT4_3" -config LCD_IPS1P5680_V1_E - bool "MCU IPS1P5680_V1_E" -config LCD_MCU_TFT480800_25_E - bool "MCU TFT480800_25_E" + +config LCD_RK29_NT35510 + bool "RGB lcd_nt35510" + config DEFAULT_OUT_HDMI bool "HDMI for default panel" depends on HDMI ---help--- if you want set HDMI for default panel, android UI size is HDMI default resolution. -config LCD_AT070TNA2 - bool "RGB AT070TNA2" -config LCD_AT070TN93 - bool "RGB AT070TN93" -config LCD_TX23D88VM - bool "HITACHI LVDS TX23D88VM (1200x800)" -config LCD_A050VL01 + +config LCD_RK29_A050VL01 bool "RGB A050VL01" -config LCD_B101EW05 - bool "RGB lcd panel B101EW05" -config LCD_RK3168M_B101EW05 - bool "RGB lcd panel LCD_RK3168M_B101EW05" -config LCD_HJ050NA_06A - bool "RGB lcd panel HJ050NA-06A" -config LCD_HDMI_1366x768 - depends on MFD_RK610 - bool "RK610 LCD_HDMI_1366X768" - ---help--- - if support RK610, this setting can support dual screen output - -config LCD_HDMI_1280x800 - depends on MFD_RK610 - bool "RGB Hannstar LCD_HDMI_1280X800" - ---help--- - if support RK610, this setting can support dual screen output -config LCD_HDMI_1024x768 - depends on MFD_RK610 - bool "RGB Hannstar LCD_HDMI_1024X768" - ---help--- - if support RK610, this setting can support dual screen output - -config LCD_HSD07PFW1 - depends on MFD_RK610 - bool "RGB Hannstar LCD_HDMI_1024X600" - -config LCD_HDMI_800x480 - depends on MFD_RK610 - bool "RGB Hannstar LCD_HDMI_800x480" - ---help--- - if support RK610, this setting can support dual screen output -config LCD_HV070WSA100 - bool "HV070WSA-100 1024X600" -config LCD_COMMON - bool "LCD COMMON" -config LCD_RK3168_AUO_A080SN03 - bool "RK3168 auo panel 800x480" - -config LCD_RK2928_A720 - bool "RK2928 A720 panel 800x480" -config LCD_RK2926_V86 - bool "RK2926 v86 panel 800x480" - -config LCD_RK3168_86V - bool "RK3168 86v panel 800x480" - -config LCD_HJ080NA - bool "HJ080NA_4J 1024X768" - -config LCD_HJ101NA - bool "HJ101NA_4J 1280X800" - -config LCD_AUTO - bool "auto select lcd" - -config LCD_HSD07PFW1 - depends on MFD_RK610 - bool "RGB lcd panel HSD07PFW1" - -config LCD_I30_800X480 - bool "lcd I30" -config LCD_TL5001_MIPI - bool "TL5001 720X1280" - -config LCD_LP097QX1 - bool "Display Port screen LP097QX1" -config LCD_DS1006H - bool "Lvds screen for ds1006h(RK3168)" -config LCD_B101UANO_1920x1200 - bool "Lvds screen B101UANO for u30gt2" -config LCD_E242868_1024X600 - bool "RK3168 86v RGB 1024*600 " -config LCD_WY_800X480 - bool "lcd for 760" -config LCD_HH070D_LVDS - bool "lcd lvds for 760" - endchoice diff --git a/drivers/video/display/screen/Makefile b/drivers/video/display/screen/Makefile old mode 100755 new mode 100644 index ad3e2ec2b856..abe7fa41937a --- a/drivers/video/display/screen/Makefile +++ b/drivers/video/display/screen/Makefile @@ -1,62 +1,12 @@ -obj-$(CONFIG_LCD_NULL) += lcd_null.o +obj-$(CONFIG_LCD_RK29_NULL) += lcd_null.o -obj-$(CONFIG_LCD_RK2928) += lcd_rk2928.o +obj-$(CONFIG_LCD_RK29_LG_LP097X02)+= lcd_LG_LP097X02.o -obj-$(CONFIG_LCD_TD043MGEA1) += lcd_td043mgea1.o -obj-$(CONFIG_LCD_HSD070IDW1) += lcd_hsd800x480.o -obj-$(CONFIG_LCD_HL070VM4AU) += lcd_hl070vm4.o -obj-$(CONFIG_LCD_BYD8688FTGF) += lcd_byd1024x600.o -obj-$(CONFIG_LCD_LG_LP097X02)+= lcd_LG_LP097X02.o -obj-$(CONFIG_LCD_TJ048NC01CA) += lcd_tj048nc01ca.o +obj-$(CONFIG_LCD_RK29_LS035Y8DX02A) += lcd_ls035y8dx02a.o +obj-$(CONFIG_LCD_RK29_LS035Y8DX04A) += lcd_ls035y8dx04a.o +obj-$(CONFIG_LCD_RK29_HSD100PXN) += lcd_hsd100pxn.o +obj-$(CONFIG_LCD_RK29_NT35510) += lcd_nt35510.o +obj-$(CONFIG_LCD_RK29_A050VL01) += lcd_A050VL01.o -obj-$(CONFIG_LCD_A060SE02) += lcd_a060se02.o -obj-$(CONFIG_LCD_S1D13521) += lcd_s1d13521.o -obj-$(CONFIG_LCD_NT35582) += lcd_nt35582.o -obj-$(CONFIG_LCD_NT35580) += lcd_nt35580.o -obj-$(CONFIG_LCD_IPS1P5680_V1_E) += lcd_ips1p5680_v1_e.o -obj-$(CONFIG_LCD_RGB_TFT480800_25_E) += lcd_rgb_tft480800_25_e.o -obj-$(CONFIG_LCD_MCU_TFT480800_25_E) += lcd_mcu_tft480800_25_e.o -obj-$(CONFIG_LCD_LS035Y8DX02A) += lcd_ls035y8dx02a.o -obj-$(CONFIG_LCD_LS035Y8DX04A) += lcd_ls035y8dx04a.o -obj-$(CONFIG_LCD_CPTCLAA038LA31XE) += lcd_CPTclaa038la31xe.o -obj-$(CONFIG_LCD_HX8357) += lcd_hx8357.o -obj-$(CONFIG_LCD_HSD100PXN) += lcd_hsd100pxn.o -obj-$(CONFIG_LCD_HDMI_1366x768) += lcd_hdmi_1366x768.o -obj-$(CONFIG_LCD_HDMI_1280x800) += lcd_hdmi_1280x800.o -obj-$(CONFIG_LCD_HDMI_1024x768) += lcd_hdmi_1024x768.o -obj-$(CONFIG_LCD_HDMI_800x480) += lcd_hdmi_800x480.o -obj-$(CONFIG_LCD_B101AW06) += lcd_B101AW06.o -obj-$(CONFIG_LCD_NT35510) += lcd_nt35510.o -obj-$(CONFIG_LCD_ILI9803_CPT4_3) += lcd_ili9803_cpt4_3.o -obj-$(CONFIG_LCD_RGB_TFT480800_25_E) += lcd_rgb_tft480800_25_e.o -obj-$(CONFIG_LCD_LS035Y8DX02A) += lcd_ls035y8dx02a.o -obj-$(CONFIG_LCD_IPS1P5680_V1_E) += lcd_ips1p5680_v1_e.o -obj-$(CONFIG_LCD_MCU_TFT480800_25_E) += lcd_mcu_tft480800_25_e.o -obj-$(CONFIG_LCD_AT070TNA2) += lcd_AT070TNA2.o -obj-$(CONFIG_LCD_TX23D88VM) += lcd_tx23d88vm.o -obj-$(CONFIG_LCD_AT070TN93) += lcd_at070tn93.o -obj-$(CONFIG_LCD_A050VL01) += lcd_A050VL01.o -obj-$(CONFIG_LCD_B101EW05) += lcd_b101ew05.o -obj-$(CONFIG_LCD_RK3168M_B101EW05) += lcd_hdmi_rk3168m_b101ew05.o -obj-$(CONFIG_LCD_HJ050NA_06A) += lcd_hj050na_06a.o -obj-$(CONFIG_LCD_HSD100PXN_FOR_TDW851) += lcd_hsd100pxn_for_tdw851.o -obj-$(CONFIG_LCD_HV070WSA100) += lcd_hv070wsa.o -obj-$(CONFIG_LCD_COMMON) += lcd_common.o -obj-$(CONFIG_LCD_RK2928_A720) += lcd_YQ70CPT9160.o -obj-$(CONFIG_LCD_RK3168_AUO_A080SN03) += lcd_AUO_A080SN03.o -obj-$(CONFIG_LCD_RK2926_V86) += lcd_YQ70CPT9160_v86.o -obj-$(CONFIG_LCD_RK3168_86V) += lcd_YQ70CPT9160_rk3168_86v.o -obj-$(CONFIG_LCD_HSD07PFW1) += lcd_hdmi_1024x600.o -obj-$(CONFIG_LCD_HJ080NA) += lcd_hj080na.o -obj-$(CONFIG_LCD_HJ101NA) += lcd_hj101na.o -obj-$(CONFIG_LCD_AUTO) += lcd_auto.o -obj-$(CONFIG_LCD_I30_800X480) += lcd_I30_800x480.o -obj-$(CONFIG_LCD_TL5001_MIPI) += lcd_tl5001_mipi.o -obj-$(CONFIG_LCD_LP097QX1) += lcd_LP097QX1.o -obj-$(CONFIG_LCD_DS1006H) += lcd_ds1006h.o -obj-$(CONFIG_LCD_B101UANO_1920x1200) += lcd_b101uano_1920x1200.o -obj-$(CONFIG_LCD_E242868_1024X600) += lcd_E242868_rk3168_86v.o -obj-$(CONFIG_LCD_WY_800X480) += lcd_wy_800x480.o -obj-$(CONFIG_LCD_HH070D_LVDS) += lcd_hh070d_lvds.o \ No newline at end of file diff --git a/drivers/video/display/screen/lcd_AT070TNA2.c b/drivers/video/display/screen/lcd_AT070TNA2.c deleted file mode 100644 index e970453a2aa2..000000000000 --- a/drivers/video/display/screen/lcd_AT070TNA2.c +++ /dev/null @@ -1,84 +0,0 @@ -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include "screen.h" - - -/* Base */ -#define OUT_TYPE SCREEN_RGB - -#if defined(CONFIG_MACH_RK29SDK)||defined(CONFIG_MACH_RK29FIH) -#define OUT_FACE OUT_D888_P666 -#else -#define OUT_FACE OUT_D888_P666 -#endif -#define OUT_CLK 58500000 // 65000000 -#define LCDC_ACLK 500000000//312000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 10 -#define H_BP 100 -#define H_VD 1024 -#define H_FP 210 - -#define V_PW 10 -#define V_BP 10 -#define V_VD 600 -#define V_FP 18 - -#define LCD_WIDTH 202 -#define LCD_HEIGHT 152 -/* Other */ -#define DCLK_POL 0 -#if defined(CONFIG_MACH_RK29SDK)||defined(CONFIG_MACH_RK29FIH) -#define SWAP_RB 0 -#else -#define SWAP_RB 0 -#endif - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; -} - - - diff --git a/drivers/video/display/screen/lcd_AUO_A080SN03.c b/drivers/video/display/screen/lcd_AUO_A080SN03.c deleted file mode 100755 index ea9d91b477fe..000000000000 --- a/drivers/video/display/screen/lcd_AUO_A080SN03.c +++ /dev/null @@ -1,89 +0,0 @@ -/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */ - -#include -#include -#include -#include -#include - - - -/* Base */ -#define OUT_TYPE SCREEN_RGB -#define OUT_FACE OUT_P888//OUT_P666 -#define OUT_CLK 40000000 -#define LCDC_ACLK 500000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 1//30//48 //10 -#define H_BP 46//10//40 //100 -#define H_VD 800 //1024 -#define H_FP 210// //210 - -#define V_PW 3// 2// 3//13//10 -#define V_BP 23// 18 // 23//10// //10 -#define V_VD 600//480 //768 -#define V_FP 2// 8// 12//22 //18 - -/* Other */ -#define DCLK_POL 1 -#define SWAP_RB 0 - -#define LCD_WIDTH 162//154 //need modify -#define LCD_HEIGHT 121//85 - -static struct rk29lcd_info *gLcd_info = NULL; - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - /*screen->init = init;*/ - screen->init = NULL; - screen->standby = NULL; - if(lcd_info) - gLcd_info = lcd_info; -} -size_t get_fb_size(void) -{ - size_t size = 0; - #if defined(CONFIG_THREE_FB_BUFFER) - size = ((H_VD)*(V_VD)<<2)* 3; //three buffer - #else - size = ((H_VD)*(V_VD)<<2)<<1; //two buffer - #endif - return ALIGN(size,SZ_1M); -} diff --git a/drivers/video/display/screen/lcd_B101AW06.c b/drivers/video/display/screen/lcd_B101AW06.c deleted file mode 100755 index e0000cacba2c..000000000000 --- a/drivers/video/display/screen/lcd_B101AW06.c +++ /dev/null @@ -1,76 +0,0 @@ -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include "screen.h" - - -/* Base */ -#define OUT_TYPE SCREEN_RGB -#define OUT_FACE OUT_D888_P666 -#define OUT_CLK 45000000 -#define LCDC_ACLK 312000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 10 -#define H_BP 80 -#define H_VD 1024 -#define H_FP 100 - -#define V_PW 10 -#define V_BP 10 -#define V_VD 600 -#define V_FP 18 - -#define LCD_WIDTH 202 -#define LCD_HEIGHT 152 -/* Other */ -#define DCLK_POL 0 -#define SWAP_RB 0 - - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; -} - - - diff --git a/drivers/video/display/screen/lcd_CPTclaa038la31xe.c b/drivers/video/display/screen/lcd_CPTclaa038la31xe.c deleted file mode 100755 index 2b896ba81746..000000000000 --- a/drivers/video/display/screen/lcd_CPTclaa038la31xe.c +++ /dev/null @@ -1,327 +0,0 @@ -/* - * Copyright (C) 2011 ROCKCHIP, Inc. - * - * author: hhb@rock-chips.com - * creat date: 2011-03-22 - * route:drivers/video/display/screen/lcd_ls035y8dx02a.c - driver for rk29 phone sdk - * declaration: This program driver have been tested in rk29_phonesdk hardware platform at 2011.03.31. - * about migration: you need just 3 interface functions,such as lcd_init(void),lcd_standby(u8 enable), - * set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include "screen.h" - -/* Base */ -#define OUT_TYPE SCREEN_RGB -#define OUT_FACE OUT_P666 -#define OUT_CLK (26*1000000) //***27 uint Hz -#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ�� - -/* Timing */ -#define H_PW 10//8 //16 -#define H_BP 10//24 -#define H_VD 480//320 -#define H_FP 10//60//16 - -#define V_PW 3 -#define V_BP 3 -#define V_VD 800//480 -#define V_FP 3 - -#define LCD_WIDTH 800 //need modify -#define LCD_HEIGHT 480 - -/* Other */ -#define DCLK_POL 0 //0 -#define SWAP_RB 0 - -static struct rk29lcd_info *gLcd_info = NULL; -int lcd_init(void); -int lcd_standby(u8 enable); - -#define RXD_PORT RK29_PIN2_PC7 -#define TXD_PORT gLcd_info->txd_pin -#define CLK_PORT gLcd_info->clk_pin -#define CS_PORT gLcd_info->cs_pin -#define RESET_PORT RK29_PIN6_PC6 - -#define CS_OUT() gpio_direction_output(CS_PORT, 1) -#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) -#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) -#define CLK_OUT() gpio_direction_output(CLK_PORT, 0) -#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) -#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) -#define TXD_OUT() gpio_direction_output(TXD_PORT, 1) -#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) -#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) -#define RXD_IN() gpio_direction_input(RXD_PORT) -#define RXD_GET() gpio_get_value(RXD_PORT) - -#define DRVDelayUs(i) udelay(i*4) -#define DRVDelayMs(i) mdelay(i*4) - -/*---------------------------------------------------------------------- -Name : Claa0381a31RegSet -Desc : IO模拟SPI对屏寄存器进行设置 -Params : Reg 寄存器地址 - Data 数据 -Return : -Notes : 设置前需要调用SetIOSpiMode(1)进入IO模式 - 设置后需要调用SetIOSpiMode(0)退出IO模式 -----------------------------------------------------------------------*/ -void Claa0381a31Cmd(u32 data) -{ - u32 i; - TXD_OUT(); - CLK_OUT(); - CS_OUT(); - DRVDelayUs(2); - - CS_SET(); - TXD_SET(); - CLK_SET(); - DRVDelayUs(2); - - if(data) - { - CS_CLR(); - DRVDelayUs(2); - - TXD_CLR(); //wr 0 - CLK_CLR(); - DRVDelayUs(2); - CLK_SET(); - DRVDelayUs(2); - - for(i = 0; i < 8; i++) //reg - { - if(data &(1<<(7-i))) - TXD_SET(); - else - TXD_CLR(); - - // 模拟CLK - CLK_CLR(); - DRVDelayUs(2); - CLK_SET(); - DRVDelayUs(2); - } - } -} - -void Claa0381a31Data(u32 data) -{ - u32 i; - - TXD_SET(); - CLK_CLR(); - DRVDelayUs(2); - CLK_SET(); - DRVDelayUs(2); - - for(i = 0; i < 8; i++) //reg - { - if(data &(1<<(7-i))) - TXD_SET(); - else - TXD_CLR(); - - // 模拟CLK - CLK_CLR(); - DRVDelayUs(2); - CLK_SET(); - DRVDelayUs(2); - } - -} - - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; /*>2*/ - screen->right_margin = H_FP; /*>2*/ - screen->hsync_len = H_PW; /*>2*/ //***all > 326, 4upper_margin = V_BP; /*>2*/ - screen->lower_margin = V_FP; /*>2*/ - screen->vsync_len = V_PW; /*>6*/ - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = lcd_init; - screen->standby = lcd_standby; - if(lcd_info) - gLcd_info = lcd_info; -} - -int lcd_init(void) -{ - volatile u32 data; - if(gLcd_info){ - gLcd_info->io_init(); - } - - /* reset lcd to start init lcd by software if there is no hardware reset circuit for the lcd */ -#ifdef RESET_PORT - gpio_request(RESET_PORT, NULL); - gpio_direction_output(RESET_PORT, 0); - mdelay(2); - gpio_set_value(RESET_PORT, 1); - mdelay(10); - gpio_free(RESET_PORT); -#endif - - printk("lcd init...\n"); - - Claa0381a31Cmd(0xb9); - Claa0381a31Data(0xff); - Claa0381a31Data(0x83); - Claa0381a31Data(0x63); - Claa0381a31Cmd(0); - - Claa0381a31Cmd(0xb1); - Claa0381a31Data(0x81); - Claa0381a31Data(0x30); - Claa0381a31Data(0x03); - Claa0381a31Data(0x34); - Claa0381a31Data(0x02); - Claa0381a31Data(0x13); - Claa0381a31Data(0x11); - Claa0381a31Data(0x00); - Claa0381a31Data(0x35); - Claa0381a31Data(0x3e); - Claa0381a31Data(0x16); - Claa0381a31Data(0x16); - Claa0381a31Cmd(0); - - Claa0381a31Cmd(0x11); - Claa0381a31Cmd(0); - - DRVDelayMs(150); - - Claa0381a31Cmd(0xb6); - Claa0381a31Data(0x42); - Claa0381a31Cmd(0); - - Claa0381a31Cmd(0xb3); - Claa0381a31Data(0x01); - Claa0381a31Cmd(0); - - Claa0381a31Cmd(0xb4); - Claa0381a31Data(0x04); - Claa0381a31Cmd(0); - - Claa0381a31Cmd(0xe0); - Claa0381a31Data(0x00); - Claa0381a31Data(0x1e); - Claa0381a31Data(0x23); - Claa0381a31Data(0x2d); - Claa0381a31Data(0x2d); - Claa0381a31Data(0x3f); - Claa0381a31Data(0x08); - Claa0381a31Data(0xcc); - Claa0381a31Data(0x8c); - Claa0381a31Data(0xcf); - Claa0381a31Data(0x51); - Claa0381a31Data(0x12); - Claa0381a31Data(0x52); - Claa0381a31Data(0x92); - Claa0381a31Data(0x1E); - Claa0381a31Data(0x00); - Claa0381a31Data(0x1e); - Claa0381a31Data(0x23); - Claa0381a31Data(0x2d); - Claa0381a31Data(0x2d); - Claa0381a31Data(0x3f); - Claa0381a31Data(0x08); - Claa0381a31Data(0xcc); - Claa0381a31Data(0x8c); - Claa0381a31Data(0xcf); - Claa0381a31Data(0x51); - Claa0381a31Data(0x12); - Claa0381a31Data(0x52); - Claa0381a31Data(0x92); - Claa0381a31Data(0x1E); - Claa0381a31Cmd(0); - - Claa0381a31Cmd(0xcc); - Claa0381a31Data(0x0b); - Claa0381a31Cmd(0); - - Claa0381a31Cmd(0x3a); - Claa0381a31Data(0x60); - Claa0381a31Cmd(0); - - DRVDelayMs(20); - - Claa0381a31Cmd(0x29); - Claa0381a31Cmd(0); - - if(gLcd_info) - gLcd_info->io_deinit(); - - return 0; -} - -int lcd_standby(u8 enable) //***enable =1 means suspend, 0 means resume -{ - - if(gLcd_info) - gLcd_info->io_init(); - printk("lcd standby\n"); - if(enable) { - printk("lcd standby...enable =1 means suspend\n"); - //spi_screenreg_set(0x10, 0xffff, 0xffff); - //mdelay(120); - //spi_screenreg_set(0x28, 0xffff, 0xffff); - } else { - printk("lcd standby...0 means resume\n"); - //spi_screenreg_set(0x29, 0xffff, 0xffff); - //spi_screenreg_set(0x11, 0xffff, 0xffff); - //mdelay(150); - } - - if(gLcd_info) - gLcd_info->io_deinit(); - return 0; -} - diff --git a/drivers/video/display/screen/lcd_E242868_rk3168_86v.c b/drivers/video/display/screen/lcd_E242868_rk3168_86v.c deleted file mode 100644 index 983365bd6bf2..000000000000 --- a/drivers/video/display/screen/lcd_E242868_rk3168_86v.c +++ /dev/null @@ -1,195 +0,0 @@ -/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */ -#include -#include -#include -#include -#include -#include -#include "screen.h" -#include -//#include "../../rk29_fb.h" -#include "../transmitter/rk610_lcd.h" - -/* Base */ -#define OUT_TYPE SCREEN_RGB -#define OUT_FACE OUT_P888 -#define OUT_CLK 50000000 -#define LCDC_ACLK 500000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 30 -#define H_BP 10 -#define H_VD 1024 -#define H_FP 210 - -#define V_PW 13 -#define V_BP 10 -#define V_VD 600 -#define V_FP 22 - -#define LCD_WIDTH 154 -#define LCD_HEIGHT 85 - -/* Other */ -#define DCLK_POL 0 -#define SWAP_RB 0 -#ifdef CONFIG_HDMI_DUAL_DISP -static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution) -{ - screen->s_clk_inv = S_DCLK_POL; - screen->s_den_inv = 0; - screen->s_hv_sync_inv = 0; - switch(hdmi_resolution){ - case HDMI_1920x1080p_60Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S_OUT_CLK; - screen->s_hsync_len = S_H_PW; - screen->s_left_margin = S_H_BP; - screen->s_right_margin = S_H_FP; - screen->s_hsync_len = S_H_PW; - screen->s_upper_margin = S_V_BP; - screen->s_lower_margin = S_V_FP; - screen->s_vsync_len = S_V_PW; - screen->s_hsync_st = S_H_ST; - screen->s_vsync_st = S_V_ST; - break; - case HDMI_1920x1080p_50Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S1_OUT_CLK; - screen->s_hsync_len = S1_H_PW; - screen->s_left_margin = S1_H_BP; - screen->s_right_margin = S1_H_FP; - screen->s_hsync_len = S1_H_PW; - screen->s_upper_margin = S1_V_BP; - screen->s_lower_margin = S1_V_FP; - screen->s_vsync_len = S1_V_PW; - screen->s_hsync_st = S1_H_ST; - screen->s_vsync_st = S1_V_ST; - break; - case HDMI_1280x720p_60Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S2_OUT_CLK; - screen->s_hsync_len = S2_H_PW; - screen->s_left_margin = S2_H_BP; - screen->s_right_margin = S2_H_FP; - screen->s_hsync_len = S2_H_PW; - screen->s_upper_margin = S2_V_BP; - screen->s_lower_margin = S2_V_FP; - screen->s_vsync_len = S2_V_PW; - screen->s_hsync_st = S2_H_ST; - screen->s_vsync_st = S2_V_ST; - break; - case HDMI_1280x720p_50Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S3_OUT_CLK; - screen->s_hsync_len = S3_H_PW; - screen->s_left_margin = S3_H_BP; - screen->s_right_margin = S3_H_FP; - screen->s_hsync_len = S3_H_PW; - screen->s_upper_margin = S3_V_BP; - screen->s_lower_margin = S3_V_FP; - screen->s_vsync_len = S3_V_PW; - screen->s_hsync_st = S3_H_ST; - screen->s_vsync_st = S3_V_ST; - break; - case HDMI_720x576p_50Hz_4x3: - case HDMI_720x576p_50Hz_16x9: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S4_OUT_CLK; - screen->s_hsync_len = S4_H_PW; - screen->s_left_margin = S4_H_BP; - screen->s_right_margin = S4_H_FP; - screen->s_hsync_len = S4_H_PW; - screen->s_upper_margin = S4_V_BP; - screen->s_lower_margin = S4_V_FP; - screen->s_vsync_len = S4_V_PW; - screen->s_hsync_st = S4_H_ST; - screen->s_vsync_st = S4_V_ST; - break; - case HDMI_720x480p_60Hz_16x9: - case HDMI_720x480p_60Hz_4x3: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S5_OUT_CLK; - screen->s_hsync_len = S5_H_PW; - screen->s_left_margin = S5_H_BP; - screen->s_right_margin = S5_H_FP; - screen->s_hsync_len = S5_H_PW; - screen->s_upper_margin = S5_V_BP; - screen->s_lower_margin = S5_V_FP; - screen->s_vsync_len = S5_V_PW; - screen->s_hsync_st = S5_H_ST; - screen->s_vsync_st = S5_V_ST; - break; - default : - printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution); - return -1; - break; - } - - return 0; -} -#else -static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution){} -#endif - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - /*screen->init = init;*/ - screen->init = NULL; - screen->standby = NULL; - screen->sscreen_get = set_scaler_info; -#ifdef CONFIG_RK610_LVDS - screen->sscreen_set = rk610_lcd_scaler_set_param; -#endif -} -size_t get_fb_size(void) -{ - size_t size = 0; - #if defined(CONFIG_THREE_FB_BUFFER) - size = ((H_VD)*(V_VD)<<2)* 3; //three buffer - #else - size = ((H_VD)*(V_VD)<<2)<<1; //two buffer - #endif - return ALIGN(size,SZ_1M); -} diff --git a/drivers/video/display/screen/lcd_I30_800x480.c b/drivers/video/display/screen/lcd_I30_800x480.c deleted file mode 100755 index ee210e126101..000000000000 --- a/drivers/video/display/screen/lcd_I30_800x480.c +++ /dev/null @@ -1,109 +0,0 @@ -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include "screen.h" - -/* Base */ -#define LCD_WIDTH 154 //need modify -#define LCD_HEIGHT 85 - -#define OUT_TYPE SCREEN_RGB -#define OUT_FACE OUT_P666 -#define OUT_CLK 30000000 -#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 48 //10 -#define H_BP 88 //100 -#define H_VD 800 -#define H_FP 40 //210 - -#define V_PW 3 //10 -#define V_BP 32 //10 -#define V_VD 480 -#define V_FP 13 //18 - -/* Other */ -#define DCLK_POL 1 -#define SWAP_RB 0 - -static struct rk29lcd_info *gLcd_info = NULL; - -static int init(void) -{ - int ret = 0; - - if(gLcd_info && gLcd_info->io_init) - gLcd_info->io_init(); - - return 0; -} - -static int standby(u8 enable) -{ - if(!enable) - { - if(gLcd_info && gLcd_info->io_enable) - gLcd_info->io_enable(); - } - else - { - if(gLcd_info && gLcd_info->io_disable) - gLcd_info->io_disable(); - } - return 0; -} - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = init; - screen->standby = standby; - if(lcd_info) - { - gLcd_info = lcd_info; - } - else - { - printk("%s lcd_info==NULL\n", __func__); - } - -} - diff --git a/drivers/video/display/screen/lcd_LG_LP097X02.c b/drivers/video/display/screen/lcd_LG_LP097X02.c old mode 100755 new mode 100644 diff --git a/drivers/video/display/screen/lcd_LP097QX1.c b/drivers/video/display/screen/lcd_LP097QX1.c deleted file mode 100644 index 3ab89e1bff68..000000000000 --- a/drivers/video/display/screen/lcd_LP097QX1.c +++ /dev/null @@ -1,131 +0,0 @@ -#include -#include -#include -#include -#include - - -/* Base */ -#define OUT_TYPE SCREEN_RGB - -#define OUT_FACE OUT_P666 - - -#define OUT_CLK 205000000 //160000000//205000000 -#define LCDC_ACLK 300000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 5 -#define H_BP 500 - -#if defined(CONFIG_ARCH_RK3066B) -#define H_VD 2047 -#else -#define H_VD 2048 -#endif - - -#define H_FP 15 - -#define V_PW 1 -#define V_BP 9 -#define V_VD 1536 -#define V_FP 3 - -#define LCD_WIDTH 216 -#define LCD_HEIGHT 135 -/* Other */ -#define DCLK_POL 1 -#define SWAP_RB 0 -#define SWAP_DUMMY 0 -#define SWAP_GB 0 -#define SWAP_RG 0 - -int dsp_lut[256] ={ - 0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707, - 0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f, - 0x00101010, 0x00111111, 0x00121212, 0x00131313, 0x00141414, 0x00151515, 0x00161616, 0x00171717, - 0x00181818, 0x00191919, 0x001a1a1a, 0x001b1b1b, 0x001c1c1c, 0x001d1d1d, 0x001e1e1e, 0x001f1f1f, - 0x00202020, 0x00212121, 0x00222222, 0x00232323, 0x00242424, 0x00252525, 0x00262626, 0x00272727, - 0x00282828, 0x00292929, 0x002a2a2a, 0x002b2b2b, 0x002c2c2c, 0x002d2d2d, 0x002e2e2e, 0x002f2f2f, - 0x00303030, 0x00313131, 0x00323232, 0x00333333, 0x00343434, 0x00353535, 0x00363636, 0x00373737, - 0x00383838, 0x00393939, 0x003a3a3a, 0x003b3b3b, 0x003c3c3c, 0x003d3d3d, 0x003e3e3e, 0x003f3f3f, - 0x00404040, 0x00414141, 0x00424242, 0x00434343, 0x00444444, 0x00454545, 0x00464646, 0x00474747, - 0x00484848, 0x00494949, 0x004a4a4a, 0x004b4b4b, 0x004c4c4c, 0x004d4d4d, 0x004e4e4e, 0x004f4f4f, - 0x00505050, 0x00515151, 0x00525252, 0x00535353, 0x00545454, 0x00555555, 0x00565656, 0x00575757, - 0x00585858, 0x00595959, 0x005a5a5a, 0x005b5b5b, 0x005c5c5c, 0x005d5d5d, 0x005e5e5e, 0x005f5f5f, - 0x00606060, 0x00616161, 0x00626262, 0x00636363, 0x00646464, 0x00656565, 0x00666666, 0x00676767, - 0x00686868, 0x00696969, 0x006a6a6a, 0x006b6b6b, 0x006c6c6c, 0x006d6d6d, 0x006e6e6e, 0x006f6f6f, - 0x00707070, 0x00717171, 0x00727272, 0x00737373, 0x00747474, 0x00757575, 0x00767676, 0x00777777, - 0x00787878, 0x00797979, 0x007a7a7a, 0x007b7b7b, 0x007c7c7c, 0x007d7d7d, 0x007e7e7e, 0x007f7f7f, - 0x00808080, 0x00818181, 0x00828282, 0x00838383, 0x00848484, 0x00858585, 0x00868686, 0x00878787, - 0x00888888, 0x00898989, 0x008a8a8a, 0x008b8b8b, 0x008c8c8c, 0x008d8d8d, 0x008e8e8e, 0x008f8f8f, - 0x00909090, 0x00919191, 0x00929292, 0x00939393, 0x00949494, 0x00959595, 0x00969696, 0x00979797, - 0x00989898, 0x00999999, 0x009a9a9a, 0x009b9b9b, 0x009c9c9c, 0x009d9d9d, 0x009e9e9e, 0x009f9f9f, - 0x00a0a0a0, 0x00a1a1a1, 0x00a2a2a2, 0x00a3a3a3, 0x00a4a4a4, 0x00a5a5a5, 0x00a6a6a6, 0x00a7a7a7, - 0x00a8a8a8, 0x00a9a9a9, 0x00aaaaaa, 0x00ababab, 0x00acacac, 0x00adadad, 0x00aeaeae, 0x00afafaf, - 0x00b0b0b0, 0x00b1b1b1, 0x00b2b2b2, 0x00b3b3b3, 0x00b4b4b4, 0x00b5b5b5, 0x00b6b6b6, 0x00b7b7b7, - 0x00b8b8b8, 0x00b9b9b9, 0x00bababa, 0x00bbbbbb, 0x00bcbcbc, 0x00bdbdbd, 0x00bebebe, 0x00bfbfbf, - 0x00c0c0c0, 0x00c1c1c1, 0x00c2c2c2, 0x00c3c3c3, 0x00c4c4c4, 0x00c5c5c5, 0x00c6c6c6, 0x00c7c7c7, - 0x00c8c8c8, 0x00c9c9c9, 0x00cacaca, 0x00cbcbcb, 0x00cccccc, 0x00cdcdcd, 0x00cecece, 0x00cfcfcf, - 0x00d0d0d0, 0x00d1d1d1, 0x00d2d2d2, 0x00d3d3d3, 0x00d4d4d4, 0x00d5d5d5, 0x00d6d6d6, 0x00d7d7d7, - 0x00d8d8d8, 0x00d9d9d9, 0x00dadada, 0x00dbdbdb, 0x00dcdcdc, 0x00dddddd, 0x00dedede, 0x00dfdfdf, - 0x00e0e0e0, 0x00e1e1e1, 0x00e2e2e2, 0x00e3e3e3, 0x00e4e4e4, 0x00e5e5e5, 0x00e6e6e6, 0x00e7e7e7, - 0x00e8e8e8, 0x00e9e9e9, 0x00eaeaea, 0x00ebebeb, 0x00ececec, 0x00ededed, 0x00eeeeee, 0x00efefef, - 0x00f0f0f0, 0x00f1f1f1, 0x00f2f2f2, 0x00f3f3f3, 0x00f4f4f4, 0x00f5f5f5, 0x00f6f6f6, 0x00f7f7f7, - 0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff, -}; - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = SWAP_RG; - screen->swap_gb = SWAP_GB; - screen->swap_delta = 0; - screen->swap_dumy = SWAP_DUMMY; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; - screen->dsp_lut = dsp_lut; -} - -size_t get_fb_size(void) -{ - size_t size = 0; - #if defined(CONFIG_THREE_FB_BUFFER) - size = ((H_VD)*(V_VD)<<2)* 3; //three buffer - #else - size = ((H_VD)*(V_VD)<<2)<<1; //two buffer - #endif - return ALIGN(size,SZ_1M); -} - diff --git a/drivers/video/display/screen/lcd_YQ70CPT9160.c b/drivers/video/display/screen/lcd_YQ70CPT9160.c deleted file mode 100644 index ee6191b0c4dc..000000000000 --- a/drivers/video/display/screen/lcd_YQ70CPT9160.c +++ /dev/null @@ -1,80 +0,0 @@ -/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */ -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include "screen.h" - - -/* Base */ -#define OUT_TYPE SCREEN_RGB -#define OUT_FACE OUT_P666 -#define OUT_CLK 33000000 -#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 30//48 //10 -#define H_BP 10//40 //100 -#define H_VD 800 //1024 -#define H_FP 210// //210 - -#define V_PW 13//10 -#define V_BP 10// //10 -#define V_VD 480 //768 -#define V_FP 22 //18 - -/* Other */ -#define DCLK_POL 1 -#define SWAP_RB 0 - -#define LCD_WIDTH 154 //need modify -#define LCD_HEIGHT 85 - -static struct rk29lcd_info *gLcd_info = NULL; - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - /*screen->init = init;*/ - screen->init = NULL; - screen->standby = NULL; - if(lcd_info) - gLcd_info = lcd_info; -} - diff --git a/drivers/video/display/screen/lcd_YQ70CPT9160_rk3168_86v.c b/drivers/video/display/screen/lcd_YQ70CPT9160_rk3168_86v.c deleted file mode 100644 index 3bcb2a1ca5b7..000000000000 --- a/drivers/video/display/screen/lcd_YQ70CPT9160_rk3168_86v.c +++ /dev/null @@ -1,195 +0,0 @@ -/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */ -#include -#include -#include -#include -#include -#include -#include "screen.h" -#include -//#include "../../rk29_fb.h" -#include "../transmitter/rk610_lcd.h" - -/* Base */ -#define OUT_TYPE SCREEN_RGB -#define OUT_FACE OUT_P888 -#define OUT_CLK 33000000 -#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 30//48 //10 -#define H_BP 10//40 //100 -#define H_VD 800 //1024 -#define H_FP 210// //210 - -#define V_PW 13//10 -#define V_BP 10// //10 -#define V_VD 480 //768 -#define V_FP 22 //18 - -#define LCD_WIDTH 154 -#define LCD_HEIGHT 85 - -/* Other */ -#define DCLK_POL 0 -#define SWAP_RB 0 -#ifdef CONFIG_HDMI_DUAL_DISP -static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution) -{ - screen->s_clk_inv = S_DCLK_POL; - screen->s_den_inv = 0; - screen->s_hv_sync_inv = 0; - switch(hdmi_resolution){ - case HDMI_1920x1080p_60Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S_OUT_CLK; - screen->s_hsync_len = S_H_PW; - screen->s_left_margin = S_H_BP; - screen->s_right_margin = S_H_FP; - screen->s_hsync_len = S_H_PW; - screen->s_upper_margin = S_V_BP; - screen->s_lower_margin = S_V_FP; - screen->s_vsync_len = S_V_PW; - screen->s_hsync_st = S_H_ST; - screen->s_vsync_st = S_V_ST; - break; - case HDMI_1920x1080p_50Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S1_OUT_CLK; - screen->s_hsync_len = S1_H_PW; - screen->s_left_margin = S1_H_BP; - screen->s_right_margin = S1_H_FP; - screen->s_hsync_len = S1_H_PW; - screen->s_upper_margin = S1_V_BP; - screen->s_lower_margin = S1_V_FP; - screen->s_vsync_len = S1_V_PW; - screen->s_hsync_st = S1_H_ST; - screen->s_vsync_st = S1_V_ST; - break; - case HDMI_1280x720p_60Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S2_OUT_CLK; - screen->s_hsync_len = S2_H_PW; - screen->s_left_margin = S2_H_BP; - screen->s_right_margin = S2_H_FP; - screen->s_hsync_len = S2_H_PW; - screen->s_upper_margin = S2_V_BP; - screen->s_lower_margin = S2_V_FP; - screen->s_vsync_len = S2_V_PW; - screen->s_hsync_st = S2_H_ST; - screen->s_vsync_st = S2_V_ST; - break; - case HDMI_1280x720p_50Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S3_OUT_CLK; - screen->s_hsync_len = S3_H_PW; - screen->s_left_margin = S3_H_BP; - screen->s_right_margin = S3_H_FP; - screen->s_hsync_len = S3_H_PW; - screen->s_upper_margin = S3_V_BP; - screen->s_lower_margin = S3_V_FP; - screen->s_vsync_len = S3_V_PW; - screen->s_hsync_st = S3_H_ST; - screen->s_vsync_st = S3_V_ST; - break; - case HDMI_720x576p_50Hz_4x3: - case HDMI_720x576p_50Hz_16x9: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S4_OUT_CLK; - screen->s_hsync_len = S4_H_PW; - screen->s_left_margin = S4_H_BP; - screen->s_right_margin = S4_H_FP; - screen->s_hsync_len = S4_H_PW; - screen->s_upper_margin = S4_V_BP; - screen->s_lower_margin = S4_V_FP; - screen->s_vsync_len = S4_V_PW; - screen->s_hsync_st = S4_H_ST; - screen->s_vsync_st = S4_V_ST; - break; - case HDMI_720x480p_60Hz_16x9: - case HDMI_720x480p_60Hz_4x3: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S5_OUT_CLK; - screen->s_hsync_len = S5_H_PW; - screen->s_left_margin = S5_H_BP; - screen->s_right_margin = S5_H_FP; - screen->s_hsync_len = S5_H_PW; - screen->s_upper_margin = S5_V_BP; - screen->s_lower_margin = S5_V_FP; - screen->s_vsync_len = S5_V_PW; - screen->s_hsync_st = S5_H_ST; - screen->s_vsync_st = S5_V_ST; - break; - default : - printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution); - return -1; - break; - } - - return 0; -} -#else -static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution){} -#endif - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - /*screen->init = init;*/ - screen->init = NULL; - screen->standby = NULL; - screen->sscreen_get = set_scaler_info; -#ifdef CONFIG_RK610_LVDS - screen->sscreen_set = rk610_lcd_scaler_set_param; -#endif -} -size_t get_fb_size(void) -{ - size_t size = 0; - #if defined(CONFIG_THREE_FB_BUFFER) - size = ((H_VD)*(V_VD)<<2)* 3; //three buffer - #else - size = ((H_VD)*(V_VD)<<2)<<1; //two buffer - #endif - return ALIGN(size,SZ_1M); -} diff --git a/drivers/video/display/screen/lcd_YQ70CPT9160_v86.c b/drivers/video/display/screen/lcd_YQ70CPT9160_v86.c deleted file mode 100644 index 1e5549dcd501..000000000000 --- a/drivers/video/display/screen/lcd_YQ70CPT9160_v86.c +++ /dev/null @@ -1,80 +0,0 @@ -/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */ -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include "screen.h" - - -/* Base */ -#define OUT_TYPE SCREEN_RGB -#define OUT_FACE OUT_P666 -#define OUT_CLK 33000000 -#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 30//48 //10 -#define H_BP 10//40 //100 -#define H_VD 800 //1024 -#define H_FP 210// //210 - -#define V_PW 13//10 -#define V_BP 10// //10 -#define V_VD 480 //768 -#define V_FP 22 //18 - -/* Other */ -#define DCLK_POL 0 -#define SWAP_RB 0 - -#define LCD_WIDTH 154 //need modify -#define LCD_HEIGHT 85 - -static struct rk29lcd_info *gLcd_info = NULL; - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - /*screen->init = init;*/ - screen->init = NULL; - screen->standby = NULL; - if(lcd_info) - gLcd_info = lcd_info; -} - diff --git a/drivers/video/display/screen/lcd_a060se02.c b/drivers/video/display/screen/lcd_a060se02.c deleted file mode 100755 index 1cb426f43550..000000000000 --- a/drivers/video/display/screen/lcd_a060se02.c +++ /dev/null @@ -1,168 +0,0 @@ -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include "screen.h" - -/* Base */ -#define OUT_TYPE SCREEN_MCU -#define OUT_FACE OUT_P16BPP4 - -#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 1 -#define H_BP 1 -#define H_VD 600 -#define H_FP 5 - -#define V_PW 1 -#define V_BP 1 -#define V_VD 800 -#define V_FP 1 - -#define P_WR 200 - -/* Other */ -#define DCLK_POL 0 -#define SWAP_RB 0 - -#define LCD_WIDTH 600 //need modify -#define LCD_HEIGHT 800 - - -int lcd_init(void) -{ - mcu_ioctl(MCU_SETBYPASS, 1); - - // init set - mcu_ioctl(MCU_WRCMD, 0x0000); - mcu_ioctl(MCU_WRDATA, 0x0001); - - // start display - mcu_ioctl(MCU_WRCMD, 0x1001); - mcu_ioctl(MCU_WRDATA, 0x0001); - mcu_ioctl(MCU_WRDATA, 0x0001); - mcu_ioctl(MCU_WRDATA, 0x0320); - mcu_ioctl(MCU_WRDATA, 0x0258); - - // ³õʼ»¯Í¼Ïó - int i=0, j=0; - while(0) - { - mcu_ioctl(MCU_WRCMD, 0x1001); - mcu_ioctl(MCU_WRDATA, 0x0001); - mcu_ioctl(MCU_WRDATA, 0x0001); - mcu_ioctl(MCU_WRDATA, 0x0320); - mcu_ioctl(MCU_WRDATA, 0x0258); - - for(i=0; i<800*100; i++) - mcu_ioctl(MCU_WRDATA, j%2 ? 0xffff : 0x0000); - for(i=0; i<800*100; i++) - mcu_ioctl(MCU_WRDATA, j%2 ? 0x0000 : 0xffff); - j++; - - mcu_ioctl(MCU_WRCMD, 0x1002); - msleep(2000); - printk(">>>>>> lcd_init : send test image! \n"); - } - - mcu_ioctl(MCU_SETBYPASS, 0); - return 0; -} - -int lcd_standby(u8 enable) -{ - return 0; -} - -int lcd_refresh(u8 arg) -{ - mcu_ioctl(MCU_SETBYPASS, 1); - - switch(arg) - { - case REFRESH_PRE: //DMA´«ËÍÇ°×¼±¸ - #if 0 - mcu_ioctl(MCU_WRCMD, 0x1001); - mcu_ioctl(MCU_WRDATA, 0x0001); - mcu_ioctl(MCU_WRDATA, 0x0001); - mcu_ioctl(MCU_WRDATA, 0x0320); - mcu_ioctl(MCU_WRDATA, 0x0258); - printk(">>>>>> lcd_refresh : REFRESH_PRE! \n"); - #else - // init set - mcu_ioctl(MCU_WRCMD, 0x0000); - mcu_ioctl(MCU_WRDATA, 0x0001); - // start display - mcu_ioctl(MCU_WRCMD, 0x1001); - mcu_ioctl(MCU_WRDATA, 0x0001); - mcu_ioctl(MCU_WRDATA, 0x0001); - mcu_ioctl(MCU_WRDATA, 0x0320); - mcu_ioctl(MCU_WRDATA, 0x0258); - printk(">>>>>> lcd_refresh : REFRESH_PRE!!! \n"); - #endif - break; - - case REFRESH_END: //DMA´«ËͽáÊøºó - mcu_ioctl(MCU_WRCMD, 0x1002); - printk(">>>>>> lcd_refresh : REFRESH_END! \n"); - break; - - default: - break; - } - - mcu_ioctl(MCU_SETBYPASS, 0); - - return 0; -} - - - -void set_lcd_info(struct rk29fb_screen *screen) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - screen->mcu_wrperiod = P_WR; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = lcd_init; - screen->standby = lcd_standby; - screen->refresh = lcd_refresh; -} - - - - diff --git a/drivers/video/display/screen/lcd_at070tn93.c b/drivers/video/display/screen/lcd_at070tn93.c deleted file mode 100644 index 614f9f79b30b..000000000000 --- a/drivers/video/display/screen/lcd_at070tn93.c +++ /dev/null @@ -1,76 +0,0 @@ -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include "screen.h" - - -/* Base */ -#define OUT_TYPE SCREEN_RGB - -#define OUT_FACE OUT_P888 -#define OUT_CLK 46800000//33300000//50000000 -#define LCDC_ACLK 500000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 10 -#define H_BP 36 -#define H_VD 800 -#define H_FP 210 - -#define V_PW 10 -#define V_BP 13 -#define V_VD 480 -#define V_FP 22 - -#define LCD_WIDTH 154 -#define LCD_HEIGHT 86 -/* Other */ -#define DCLK_POL 0 -#define SWAP_RB 0 - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; -} - - - diff --git a/drivers/video/display/screen/lcd_auto.c b/drivers/video/display/screen/lcd_auto.c deleted file mode 100755 index 7b4efd117517..000000000000 --- a/drivers/video/display/screen/lcd_auto.c +++ /dev/null @@ -1,444 +0,0 @@ -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_HAS_EARLYSUSPEND -#include -#endif -#include -#include "screen.h" - -#include - - -extern struct rk29_bl_info rk29_bl_info; - - -//FOR ID0 -/* Base */ -#define OUT_TYPE_ID0 SCREEN_RGB - -#define OUT_FACE_ID0 OUT_P888 -#define OUT_CLK_ID0 71000000 -#define LCDC_ACLK_ID0 500000000//312000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW_ID0 100 -#define H_BP_ID0 100 -#define H_VD_ID0 1024 -#define H_FP_ID0 120 - -#define V_PW_ID0 10 -#define V_BP_ID0 10 -#define V_VD_ID0 600 -#define V_FP_ID0 15 - -#define LCD_WIDTH_ID0 202 -#define LCD_HEIGHT_ID0 152 -/* Other */ -#define DCLK_POL_ID0 0 -#define SWAP_RB_ID0 0 - -//FOR ID1 -/* Base */ -#define OUT_TYPE_ID1 SCREEN_RGB -#define OUT_FACE_ID1 OUT_P888 -#define OUT_CLK_ID1 71000000 -#define LCDC_ACLK_ID1 500000000 - -/* Timing */ -#define H_PW_ID1 10 -#define H_BP_ID1 160 -#define H_VD_ID1 1024 -#define H_FP_ID1 16 - -#define V_PW_ID1 3 -#define V_BP_ID1 23 -#define V_VD_ID1 768 -#define V_FP_ID1 12 - - -/* Other */ -#define DCLK_POL_ID1 0 -#define SWAP_RB_ID1 0 - -#define LCD_WIDTH_ID1 270 -#define LCD_HEIGHT_ID1 202 - - - -//FOR ID2 -#define OUT_TYPE_ID2 SCREEN_RGB - -#define OUT_FACE_ID2 OUT_P888 -#define OUT_CLK_ID2 65000000 -#define LCDC_ACLK_ID2 500000000 - -/* Timing */ -#define H_PW_ID2 100 -#define H_BP_ID2 100 -#define H_VD_ID2 1024 -#define H_FP_ID2 120 - -#define V_PW_ID2 10 -#define V_BP_ID2 10 -#define V_VD_ID2 768 -#define V_FP_ID2 15 - -#define LCD_WIDTH_ID2 216 -#define LCD_HEIGHT_ID2 162 -/* Other */ -#define DCLK_POL_ID2 0 -#define SWAP_RB_ID2 0 - -//FOR ID3 -/* Base */ -#define OUT_TYPE_ID3 SCREEN_RGB -#define OUT_FACE_ID3 OUT_P888 -#define OUT_CLK_ID3 71000000 -#define LCDC_ACLK_ID3 500000000 - -/* Timing */ -#define H_PW_ID3 10 -#define H_BP_ID3 160 -#define H_VD_ID3 1280 -#define H_FP_ID3 16 - -#define V_PW_ID3 3 -#define V_BP_ID3 23 -#define V_VD_ID3 800 -#define V_FP_ID3 12 - - -/* Other */ -#define DCLK_POL_ID3 0 -#define SWAP_RB_ID3 0 - -#define LCD_WIDTH_ID3 270 -#define LCD_HEIGHT_ID3 202 - - -//FOR ID4 -/* Base */ -#define OUT_TYPE_ID4 SCREEN_RGB -#define OUT_FACE_ID4 OUT_P888 -#define OUT_CLK_ID4 71000000 -#define LCDC_ACLK_ID4 300000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW_ID4 10 -#define H_BP_ID4 64 -#define H_VD_ID4 800 -#define H_FP_ID4 16 - -#define V_PW_ID4 3 -#define V_BP_ID4 8 -#define V_VD_ID4 1280 -#define V_FP_ID4 10 - - -/* Other */ -#define DCLK_POL_ID4 0 -#define SWAP_RB_ID4 0 - -#define LCD_WIDTH_ID4 152 -#define LCD_HEIGHT_ID4 202 - - -#if defined(CONFIG_TS_AUTO) -extern struct ts_private_data *g_ts; -#else -static struct ts_private_data *g_ts = NULL; -#endif - -#if defined(CONFIG_RK_BOARD_ID) -extern enum rk_board_id rk_get_board_id(void); -#else -static enum rk_board_id rk_get_board_id(void) -{ - return -1; -} -#endif -static int lcd_get_id(void) -{ - int id = -1; - int ts_id = -1; - -#if defined(CONFIG_RK_BOARD_ID) - id = rk_get_board_id(); -#elif defined(CONFIG_TS_AUTO) - if(!g_ts) - return -1; - - ts_id = g_ts->ops->ts_id; - - switch(ts_id) - { - case TS_ID_FT5306: - id = BOARD_ID_C8003; - break; - case TS_ID_GT8110: - id = BOARD_ID_C1014; - break; - case TS_ID_GT828: - id = BOARD_ID_C7018; - break; - case TS_ID_GT8005: - id = BOARD_ID_C8002; - break; - case TS_ID_CT360: - id = BOARD_ID_DS763; - break; - default: - break; - } - -#endif - return id; -} - - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - int id; - id = lcd_get_id(); - - switch(id) - { - case BOARD_ID_DS763: - - /* screen type & face */ - screen->type = OUT_TYPE_ID0; - screen->face = OUT_FACE_ID0; - - /* Screen size */ - screen->x_res = H_VD_ID0; - screen->y_res = V_VD_ID0; - - screen->width = LCD_WIDTH_ID0; - screen->height = LCD_HEIGHT_ID0; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK_ID0; - screen->pixclock = OUT_CLK_ID0; - screen->left_margin = H_BP_ID0; - screen->right_margin = H_FP_ID0; - screen->hsync_len = H_PW_ID0; - screen->upper_margin = V_BP_ID0; - screen->lower_margin = V_FP_ID0; - screen->vsync_len = V_PW_ID0; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL_ID0; - - /* Swap rule */ - screen->swap_rb = SWAP_RB_ID0; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; - - break; - - case BOARD_ID_C8002: - - /* screen type & face */ - screen->type = OUT_TYPE_ID1; - screen->face = OUT_FACE_ID1; - - /* Screen size */ - screen->x_res = H_VD_ID1; - screen->y_res = V_VD_ID1; - - screen->width = LCD_WIDTH_ID1; - screen->height = LCD_HEIGHT_ID1; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK_ID1; - screen->pixclock = OUT_CLK_ID1; - screen->left_margin = H_BP_ID1; - screen->right_margin = H_FP_ID1; - screen->hsync_len = H_PW_ID1; - screen->upper_margin = V_BP_ID1; - screen->lower_margin = V_FP_ID1; - screen->vsync_len = V_PW_ID1; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL_ID1; - - /* Swap rule */ - screen->swap_rb = SWAP_RB_ID1; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; - break; - - case BOARD_ID_C8003: - - /* screen type & face */ - screen->type = OUT_TYPE_ID2; - screen->face = OUT_FACE_ID2; - - /* Screen size */ - screen->x_res = H_VD_ID2; - screen->y_res = V_VD_ID2; - - screen->width = LCD_WIDTH_ID2; - screen->height = LCD_HEIGHT_ID2; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK_ID2; - screen->pixclock = OUT_CLK_ID2; - screen->left_margin = H_BP_ID2; - screen->right_margin = H_FP_ID2; - screen->hsync_len = H_PW_ID2; - screen->upper_margin = V_BP_ID2; - screen->lower_margin = V_FP_ID2; - screen->vsync_len = V_PW_ID2; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL_ID2; - - /* Swap rule */ - screen->swap_rb = SWAP_RB_ID2; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; - - break; - - case BOARD_ID_C1014: - default: - - /* screen type & face */ - screen->type = OUT_TYPE_ID3; - screen->face = OUT_FACE_ID3; - - /* Screen size */ - screen->x_res = H_VD_ID3; - screen->y_res = V_VD_ID3; - - screen->width = LCD_WIDTH_ID3; - screen->height = LCD_HEIGHT_ID3; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK_ID3; - screen->pixclock = OUT_CLK_ID3; - screen->left_margin = H_BP_ID3; - screen->right_margin = H_FP_ID3; - screen->hsync_len = H_PW_ID3; - screen->upper_margin = V_BP_ID3; - screen->lower_margin = V_FP_ID3; - screen->vsync_len = V_PW_ID3; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL_ID3; - - /* Swap rule */ - screen->swap_rb = SWAP_RB_ID3; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; - - break; - - case BOARD_ID_C7018: - - /* screen type & face */ - screen->type = OUT_TYPE_ID4; - screen->face = OUT_FACE_ID4; - - /* Screen size */ - screen->x_res = H_VD_ID4; - screen->y_res = V_VD_ID4; - - screen->width = LCD_WIDTH_ID4; - screen->height = LCD_HEIGHT_ID4; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK_ID4; - screen->pixclock = OUT_CLK_ID4; - screen->left_margin = H_BP_ID4; - screen->right_margin = H_FP_ID4; - screen->hsync_len = H_PW_ID4; - screen->upper_margin = V_BP_ID4; - screen->lower_margin = V_FP_ID4; - screen->vsync_len = V_PW_ID4; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL_ID4; - - /* Swap rule */ - screen->swap_rb = SWAP_RB_ID4; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; - - break; - - - } - - - printk("%s:board_id=%d\n",__func__,id); - -} - - - diff --git a/drivers/video/display/screen/lcd_b101ew05.c b/drivers/video/display/screen/lcd_b101ew05.c deleted file mode 100755 index b078a95d392f..000000000000 --- a/drivers/video/display/screen/lcd_b101ew05.c +++ /dev/null @@ -1,455 +0,0 @@ - -#include -#include -#include -#include -#include -#if defined(CONFIG_RK_HDMI) -#include "../../rockchip/hdmi/rk_hdmi.h" -#endif - - -#if defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS) -#include "../transmitter/rk610_lcd.h" -#endif - - -/* Base */ -#if defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS) -#define OUT_TYPE SCREEN_LVDS -#define LVDS_FORMAT LVDS_8BIT_2 -#else -#define OUT_TYPE SCREEN_RGB -#endif - -#define OUT_FACE OUT_D888_P666 - - -#define OUT_CLK 71000000 -#define LCDC_ACLK 300000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 10 -#define H_BP 100 -#define H_VD 1280 -#define H_FP 18 - -#define V_PW 2 -#define V_BP 8 -#define V_VD 800 -#define V_FP 6 - -#define LCD_WIDTH 216 -#define LCD_HEIGHT 135 -/* Other */ -#if defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS) -#define DCLK_POL 1 -#else -#define DCLK_POL 0 -#endif -#define DEN_POL 0 -#define VSYNC_POL 0 -#define HSYNC_POL 0 - -#define SWAP_RB 0 -#define SWAP_RG 0 -#define SWAP_GB 0 - -int dsp_lut[256] ={ - 0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707, - 0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f, - 0x00101010, 0x00111111, 0x00121212, 0x00131313, 0x00141414, 0x00151515, 0x00161616, 0x00171717, - 0x00181818, 0x00191919, 0x001a1a1a, 0x001b1b1b, 0x001c1c1c, 0x001d1d1d, 0x001e1e1e, 0x001f1f1f, - 0x00202020, 0x00212121, 0x00222222, 0x00232323, 0x00242424, 0x00252525, 0x00262626, 0x00272727, - 0x00282828, 0x00292929, 0x002a2a2a, 0x002b2b2b, 0x002c2c2c, 0x002d2d2d, 0x002e2e2e, 0x002f2f2f, - 0x00303030, 0x00313131, 0x00323232, 0x00333333, 0x00343434, 0x00353535, 0x00363636, 0x00373737, - 0x00383838, 0x00393939, 0x003a3a3a, 0x003b3b3b, 0x003c3c3c, 0x003d3d3d, 0x003e3e3e, 0x003f3f3f, - 0x00404040, 0x00414141, 0x00424242, 0x00434343, 0x00444444, 0x00454545, 0x00464646, 0x00474747, - 0x00484848, 0x00494949, 0x004a4a4a, 0x004b4b4b, 0x004c4c4c, 0x004d4d4d, 0x004e4e4e, 0x004f4f4f, - 0x00505050, 0x00515151, 0x00525252, 0x00535353, 0x00545454, 0x00555555, 0x00565656, 0x00575757, - 0x00585858, 0x00595959, 0x005a5a5a, 0x005b5b5b, 0x005c5c5c, 0x005d5d5d, 0x005e5e5e, 0x005f5f5f, - 0x00606060, 0x00616161, 0x00626262, 0x00636363, 0x00646464, 0x00656565, 0x00666666, 0x00676767, - 0x00686868, 0x00696969, 0x006a6a6a, 0x006b6b6b, 0x006c6c6c, 0x006d6d6d, 0x006e6e6e, 0x006f6f6f, - 0x00707070, 0x00717171, 0x00727272, 0x00737373, 0x00747474, 0x00757575, 0x00767676, 0x00777777, - 0x00787878, 0x00797979, 0x007a7a7a, 0x007b7b7b, 0x007c7c7c, 0x007d7d7d, 0x007e7e7e, 0x007f7f7f, - 0x00808080, 0x00818181, 0x00828282, 0x00838383, 0x00848484, 0x00858585, 0x00868686, 0x00878787, - 0x00888888, 0x00898989, 0x008a8a8a, 0x008b8b8b, 0x008c8c8c, 0x008d8d8d, 0x008e8e8e, 0x008f8f8f, - 0x00909090, 0x00919191, 0x00929292, 0x00939393, 0x00949494, 0x00959595, 0x00969696, 0x00979797, - 0x00989898, 0x00999999, 0x009a9a9a, 0x009b9b9b, 0x009c9c9c, 0x009d9d9d, 0x009e9e9e, 0x009f9f9f, - 0x00a0a0a0, 0x00a1a1a1, 0x00a2a2a2, 0x00a3a3a3, 0x00a4a4a4, 0x00a5a5a5, 0x00a6a6a6, 0x00a7a7a7, - 0x00a8a8a8, 0x00a9a9a9, 0x00aaaaaa, 0x00ababab, 0x00acacac, 0x00adadad, 0x00aeaeae, 0x00afafaf, - 0x00b0b0b0, 0x00b1b1b1, 0x00b2b2b2, 0x00b3b3b3, 0x00b4b4b4, 0x00b5b5b5, 0x00b6b6b6, 0x00b7b7b7, - 0x00b8b8b8, 0x00b9b9b9, 0x00bababa, 0x00bbbbbb, 0x00bcbcbc, 0x00bdbdbd, 0x00bebebe, 0x00bfbfbf, - 0x00c0c0c0, 0x00c1c1c1, 0x00c2c2c2, 0x00c3c3c3, 0x00c4c4c4, 0x00c5c5c5, 0x00c6c6c6, 0x00c7c7c7, - 0x00c8c8c8, 0x00c9c9c9, 0x00cacaca, 0x00cbcbcb, 0x00cccccc, 0x00cdcdcd, 0x00cecece, 0x00cfcfcf, - 0x00d0d0d0, 0x00d1d1d1, 0x00d2d2d2, 0x00d3d3d3, 0x00d4d4d4, 0x00d5d5d5, 0x00d6d6d6, 0x00d7d7d7, - 0x00d8d8d8, 0x00d9d9d9, 0x00dadada, 0x00dbdbdb, 0x00dcdcdc, 0x00dddddd, 0x00dedede, 0x00dfdfdf, - 0x00e0e0e0, 0x00e1e1e1, 0x00e2e2e2, 0x00e3e3e3, 0x00e4e4e4, 0x00e5e5e5, 0x00e6e6e6, 0x00e7e7e7, - 0x00e8e8e8, 0x00e9e9e9, 0x00eaeaea, 0x00ebebeb, 0x00ececec, 0x00ededed, 0x00eeeeee, 0x00efefef, - 0x00f0f0f0, 0x00f1f1f1, 0x00f2f2f2, 0x00f3f3f3, 0x00f4f4f4, 0x00f5f5f5, 0x00f6f6f6, 0x00f7f7f7, - 0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff, -}; - -#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& ( defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS)) - -/* scaler Timing */ -//1920*1080*60 - -#define S_OUT_CLK SCALE_RATE(148500000,74250000) //m=16 n=9 no=4 -#define S_H_PW 48 -#define S_H_BP 98 -#define S_H_VD 1280 -#define S_H_FP 59 - -#define S_V_PW 6 -#define S_V_BP 25 -#define S_V_VD 800 -#define S_V_FP 2 - -#define S_H_ST 495 -#define S_V_ST 2 - -#define S_PLL_CFG_VAL 0x01842016 -#define S_FRAC 0xc16c2d -#define S_SCL_VST 0x25 -#define S_SCL_HST 0x4ba -#define S_VIF_VST 0x1 -#define S_VIF_HST 0xca - -//1920*1080*50 -#define S1_OUT_CLK SCALE_RATE(148500000,57375000) //m=17 n=11 no=4 -#define S1_H_PW 10 -#define S1_H_BP 10 -#define S1_H_VD 1280 -#define S1_H_FP 77 - -#define S1_V_PW 10 -#define S1_V_BP 10 -#define S1_V_VD 800 -#define S1_V_FP 13 - -#define S1_H_ST 459 -#define S1_V_ST 13 - -#define S1_PLL_CFG_VAL 0x01c42016 -#define S1_FRAC 0x1f9ad4 -#define S1_SCL_VST 0x25 -#define S1_SCL_HST 0x5ab -#define S1_VIF_VST 0x1 -#define S1_VIF_HST 0xca - - -//1280*720*60 -#define S2_OUT_CLK SCALE_RATE(74250000,74250000) //m=32 n=9 no=4 -#define S2_H_PW 48 -#define S2_H_BP 98 -#define S2_H_VD 1280 -#define S2_H_FP 59 - -#define S2_V_PW 6 -#define S2_V_BP 25 -#define S2_V_VD 800 -#define S2_V_FP 2 - -#define S2_H_ST 495 -#define S2_V_ST 5 - - -//bellow are for jettaB -#define S2_PLL_CFG_VAL 0x01822016 -#define S2_FRAC 0xc16c2d -#define S2_SCL_VST 0x19 -#define S2_SCL_HST 0x483 -#define S2_VIF_VST 0x1 -#define S2_VIF_HST 0xcf - - -//1280*720*50 - -#define S3_OUT_CLK SCALE_RATE(74250000,67500000) // m=34 n=11 no=4 -#define S3_H_PW 48 -#define S3_H_BP 233 -#define S3_H_VD 1280 -#define S3_H_FP 59 - -#define S3_V_PW 6 -#define S3_V_BP 25 -#define S3_V_VD 800 -#define S3_V_FP 2 - -#define S3_H_ST 540 -#define S3_V_ST 3 - -#define S3_PLL_CFG_VAL 0x01c22016 -#define S3_FRAC 0x1f9ad4 -#define S3_SCL_VST 0x19 -#define S3_SCL_HST 0x569 -#define S3_VIF_VST 0x1 -#define S3_VIF_HST 0xcf - - -//720*576*50 -#define S4_OUT_CLK SCALE_RATE(27000000,70312500) //m=75 n=4 no=8 -#define S4_H_PW 48 -#define S4_H_BP 233 -#define S4_H_VD 1280 -#define S4_H_FP 59 - -#define S4_V_PW 9 -#define S4_V_BP 57 -#define S4_V_VD 800 -#define S4_V_FP 2 - -#define S4_H_ST 90 -#define S4_V_ST 2 - -#define S4_PLL_CFG_VAL 0x01412016 -#define S4_FRAC 0xa23d09 -#define S4_SCL_VST 0x2d -#define S4_SCL_HST 0x33d -#define S4_VIF_VST 0x1 -#define S4_VIF_HST 0xc1 - - -//720*480*60 -#define S5_OUT_CLK SCALE_RATE(27000000,75000000) //m=100 n=9 no=4 -#define S5_H_PW 48 -#define S5_H_BP 86 -#define S5_H_VD 1280 -#define S5_H_FP 16 - -#define S5_V_PW 9 -#define S5_V_BP 35 -#define S5_V_VD 800 -#define S5_V_FP 30 - -#define S5_H_ST 476 -#define S5_V_ST 12 - -#define S5_PLL_CFG_VAL 0x01c11013 -#define S5_FRAC 0x25325e -#define S5_SCL_VST 0x26 -#define S5_SCL_HST 0x2ae -#define S5_VIF_VST 0x1 -#define S5_VIF_HST 0xc1 - - -#define S_DCLK_POL 1 - - -static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution) -{ - screen->s_clk_inv = S_DCLK_POL; - screen->s_den_inv = 0; - screen->s_hv_sync_inv = 0; - switch(hdmi_resolution) - { - case HDMI_1920x1080p_60Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S_OUT_CLK; - screen->s_hsync_len = S_H_PW; - screen->s_left_margin = S_H_BP; - screen->s_right_margin = S_H_FP; - screen->s_hsync_len = S_H_PW; - screen->s_upper_margin = S_V_BP; - screen->s_lower_margin = S_V_FP; - screen->s_vsync_len = S_V_PW; - screen->s_hsync_st = S_H_ST; - screen->s_vsync_st = S_V_ST; - - //bellow are for JettaB - #if defined(CONFIG_RK616_LVDS) - screen->pll_cfg_val = S_PLL_CFG_VAL; - screen->frac = S_FRAC; - screen->scl_vst = S_SCL_VST; - screen->scl_hst = S_SCL_HST; - screen->vif_vst = S_VIF_VST; - screen->vif_hst = S_VIF_HST; - #endif - break; - case HDMI_1920x1080p_50Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S1_OUT_CLK; - screen->s_hsync_len = S1_H_PW; - screen->s_left_margin = S1_H_BP; - screen->s_right_margin = S1_H_FP; - screen->s_hsync_len = S1_H_PW; - screen->s_upper_margin = S1_V_BP; - screen->s_lower_margin = S1_V_FP; - screen->s_vsync_len = S1_V_PW; - screen->s_hsync_st = S1_H_ST; - screen->s_vsync_st = S1_V_ST; - - #if defined(CONFIG_RK616_LVDS) - screen->pll_cfg_val = S1_PLL_CFG_VAL; - screen->frac = S1_FRAC; - screen->scl_vst = S1_SCL_VST; - screen->scl_hst = S1_SCL_HST; - screen->vif_vst = S1_VIF_VST; - screen->vif_hst = S1_VIF_HST; - #endif - break; - case HDMI_1280x720p_60Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S2_OUT_CLK; - screen->s_hsync_len = S2_H_PW; - screen->s_left_margin = S2_H_BP; - screen->s_right_margin = S2_H_FP; - screen->s_hsync_len = S2_H_PW; - screen->s_upper_margin = S2_V_BP; - screen->s_lower_margin = S2_V_FP; - screen->s_vsync_len = S2_V_PW; - screen->s_hsync_st = S2_H_ST; - screen->s_vsync_st = S2_V_ST; - #if defined(CONFIG_RK616_LVDS) - screen->pll_cfg_val = S2_PLL_CFG_VAL; - screen->frac = S2_FRAC; - screen->scl_vst = S2_SCL_VST; - screen->scl_hst = S2_SCL_HST; - screen->vif_vst = S2_VIF_VST; - screen->vif_hst = S2_VIF_HST; - #endif - break; - case HDMI_1280x720p_50Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S3_OUT_CLK; - screen->s_hsync_len = S3_H_PW; - screen->s_left_margin = S3_H_BP; - screen->s_right_margin = S3_H_FP; - screen->s_hsync_len = S3_H_PW; - screen->s_upper_margin = S3_V_BP; - screen->s_lower_margin = S3_V_FP; - screen->s_vsync_len = S3_V_PW; - screen->s_hsync_st = S3_H_ST; - screen->s_vsync_st = S3_V_ST; - #if defined(CONFIG_RK616_LVDS) - screen->pll_cfg_val = S3_PLL_CFG_VAL; - screen->frac = S3_FRAC; - screen->scl_vst = S3_SCL_VST; - screen->scl_hst = S3_SCL_HST; - screen->vif_vst = S3_VIF_VST; - screen->vif_hst = S3_VIF_HST; - #endif - break; - case HDMI_720x576p_50Hz_4_3: - case HDMI_720x576p_50Hz_16_9: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S4_OUT_CLK; - screen->s_hsync_len = S4_H_PW; - screen->s_left_margin = S4_H_BP; - screen->s_right_margin = S4_H_FP; - screen->s_hsync_len = S4_H_PW; - screen->s_upper_margin = S4_V_BP; - screen->s_lower_margin = S4_V_FP; - screen->s_vsync_len = S4_V_PW; - screen->s_hsync_st = S4_H_ST; - screen->s_vsync_st = S4_V_ST; - #if defined(CONFIG_RK616_LVDS) - screen->pll_cfg_val = S4_PLL_CFG_VAL; - screen->frac = S4_FRAC; - screen->scl_vst = S4_SCL_VST; - screen->scl_hst = S4_SCL_HST; - screen->vif_vst = S4_VIF_VST; - screen->vif_hst = S4_VIF_HST; - #endif - break; - - case HDMI_720x480p_60Hz_16_9: - case HDMI_720x480p_60Hz_4_3: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S5_OUT_CLK; - screen->s_hsync_len = S5_H_PW; - screen->s_left_margin = S5_H_BP; - screen->s_right_margin = S5_H_FP; - screen->s_hsync_len = S5_H_PW; - screen->s_upper_margin = S5_V_BP; - screen->s_lower_margin = S5_V_FP; - screen->s_vsync_len = S5_V_PW; - screen->s_hsync_st = S5_H_ST; - screen->s_vsync_st = S5_V_ST; - #if defined(CONFIG_RK616_LVDS) - screen->pll_cfg_val = S5_PLL_CFG_VAL; - screen->frac = S5_FRAC; - screen->scl_vst = S5_SCL_VST; - screen->scl_hst = S5_SCL_HST; - screen->vif_vst = S5_VIF_VST; - screen->vif_hst = S5_VIF_HST; - #endif - break; - default : - printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution); - return -1; - break; - } - - return 0; -} -#else -#define set_scaler_info NULL -#endif - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->face = OUT_FACE; - screen->type = OUT_TYPE; -#if defined(CONFIG_RK610_LVDS)|| defined(CONFIG_RK616_LVDS) - screen->hw_format = LVDS_FORMAT; -#endif - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = HSYNC_POL; - screen->pin_vsync = VSYNC_POL; - screen->pin_den = DEN_POL; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = SWAP_RG; - screen->swap_gb = SWAP_GB; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; - screen->dsp_lut = dsp_lut; - screen->sscreen_get = set_scaler_info; -#if defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS) - screen->sscreen_set = rk610_lcd_scaler_set_param; -#endif -} - -size_t get_fb_size(void) -{ - size_t size = 0; - #if defined(CONFIG_THREE_FB_BUFFER) - size = ((H_VD)*(V_VD)<<2)* 3; //three buffer - #else - size = ((H_VD)*(V_VD)<<2)<<1; //two buffer - #endif - return ALIGN(size,SZ_1M); -} diff --git a/drivers/video/display/screen/lcd_b101uano_1920x1200.c b/drivers/video/display/screen/lcd_b101uano_1920x1200.c deleted file mode 100755 index 026a22580536..000000000000 --- a/drivers/video/display/screen/lcd_b101uano_1920x1200.c +++ /dev/null @@ -1,401 +0,0 @@ - -#include -#include -#include -#include -#include -#if defined(CONFIG_RK_HDMI) -#include "../../rockchip/hdmi/rk_hdmi.h" -#endif - - -#if defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS) -#include "../transmitter/rk610_lcd.h" -#endif - - -/* Base */ -#if defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS) -#define OUT_TYPE SCREEN_LVDS -#define LVDS_FORMAT LVDS_8BIT_1 -#else -#define OUT_TYPE SCREEN_RGB -#endif - -#define OUT_FACE OUT_P888 - - -#define OUT_CLK 160000000 -#define LCDC_ACLK 500000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 1 -#define H_BP 90 -#define H_VD 1920 -#define H_FP 1 - -#define V_PW 1 -#define V_BP 12 -#define V_VD 1200 -#define V_FP 1 - -#define LCD_WIDTH 217 -#define LCD_HEIGHT 136 -/* Other */ -#if defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS) -#define DCLK_POL 1 -#else -#define DCLK_POL 0 -#endif -#define DEN_POL 0 -#define VSYNC_POL 0 -#define HSYNC_POL 0 - -#define SWAP_RB 0 -#define SWAP_RG 0 -#define SWAP_GB 0 - -int dsp_lut[256] ={ - 0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707, - 0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f, - 0x00101010, 0x00111111, 0x00121212, 0x00131313, 0x00141414, 0x00151515, 0x00161616, 0x00171717, - 0x00181818, 0x00191919, 0x001a1a1a, 0x001b1b1b, 0x001c1c1c, 0x001d1d1d, 0x001e1e1e, 0x001f1f1f, - 0x00202020, 0x00212121, 0x00222222, 0x00232323, 0x00242424, 0x00252525, 0x00262626, 0x00272727, - 0x00282828, 0x00292929, 0x002a2a2a, 0x002b2b2b, 0x002c2c2c, 0x002d2d2d, 0x002e2e2e, 0x002f2f2f, - 0x00303030, 0x00313131, 0x00323232, 0x00333333, 0x00343434, 0x00353535, 0x00363636, 0x00373737, - 0x00383838, 0x00393939, 0x003a3a3a, 0x003b3b3b, 0x003c3c3c, 0x003d3d3d, 0x003e3e3e, 0x003f3f3f, - 0x00404040, 0x00414141, 0x00424242, 0x00434343, 0x00444444, 0x00454545, 0x00464646, 0x00474747, - 0x00484848, 0x00494949, 0x004a4a4a, 0x004b4b4b, 0x004c4c4c, 0x004d4d4d, 0x004e4e4e, 0x004f4f4f, - 0x00505050, 0x00515151, 0x00525252, 0x00535353, 0x00545454, 0x00555555, 0x00565656, 0x00575757, - 0x00585858, 0x00595959, 0x005a5a5a, 0x005b5b5b, 0x005c5c5c, 0x005d5d5d, 0x005e5e5e, 0x005f5f5f, - 0x00606060, 0x00616161, 0x00626262, 0x00636363, 0x00646464, 0x00656565, 0x00666666, 0x00676767, - 0x00686868, 0x00696969, 0x006a6a6a, 0x006b6b6b, 0x006c6c6c, 0x006d6d6d, 0x006e6e6e, 0x006f6f6f, - 0x00707070, 0x00717171, 0x00727272, 0x00737373, 0x00747474, 0x00757575, 0x00767676, 0x00777777, - 0x00787878, 0x00797979, 0x007a7a7a, 0x007b7b7b, 0x007c7c7c, 0x007d7d7d, 0x007e7e7e, 0x007f7f7f, - 0x00808080, 0x00818181, 0x00828282, 0x00838383, 0x00848484, 0x00858585, 0x00868686, 0x00878787, - 0x00888888, 0x00898989, 0x008a8a8a, 0x008b8b8b, 0x008c8c8c, 0x008d8d8d, 0x008e8e8e, 0x008f8f8f, - 0x00909090, 0x00919191, 0x00929292, 0x00939393, 0x00949494, 0x00959595, 0x00969696, 0x00979797, - 0x00989898, 0x00999999, 0x009a9a9a, 0x009b9b9b, 0x009c9c9c, 0x009d9d9d, 0x009e9e9e, 0x009f9f9f, - 0x00a0a0a0, 0x00a1a1a1, 0x00a2a2a2, 0x00a3a3a3, 0x00a4a4a4, 0x00a5a5a5, 0x00a6a6a6, 0x00a7a7a7, - 0x00a8a8a8, 0x00a9a9a9, 0x00aaaaaa, 0x00ababab, 0x00acacac, 0x00adadad, 0x00aeaeae, 0x00afafaf, - 0x00b0b0b0, 0x00b1b1b1, 0x00b2b2b2, 0x00b3b3b3, 0x00b4b4b4, 0x00b5b5b5, 0x00b6b6b6, 0x00b7b7b7, - 0x00b8b8b8, 0x00b9b9b9, 0x00bababa, 0x00bbbbbb, 0x00bcbcbc, 0x00bdbdbd, 0x00bebebe, 0x00bfbfbf, - 0x00c0c0c0, 0x00c1c1c1, 0x00c2c2c2, 0x00c3c3c3, 0x00c4c4c4, 0x00c5c5c5, 0x00c6c6c6, 0x00c7c7c7, - 0x00c8c8c8, 0x00c9c9c9, 0x00cacaca, 0x00cbcbcb, 0x00cccccc, 0x00cdcdcd, 0x00cecece, 0x00cfcfcf, - 0x00d0d0d0, 0x00d1d1d1, 0x00d2d2d2, 0x00d3d3d3, 0x00d4d4d4, 0x00d5d5d5, 0x00d6d6d6, 0x00d7d7d7, - 0x00d8d8d8, 0x00d9d9d9, 0x00dadada, 0x00dbdbdb, 0x00dcdcdc, 0x00dddddd, 0x00dedede, 0x00dfdfdf, - 0x00e0e0e0, 0x00e1e1e1, 0x00e2e2e2, 0x00e3e3e3, 0x00e4e4e4, 0x00e5e5e5, 0x00e6e6e6, 0x00e7e7e7, - 0x00e8e8e8, 0x00e9e9e9, 0x00eaeaea, 0x00ebebeb, 0x00ececec, 0x00ededed, 0x00eeeeee, 0x00efefef, - 0x00f0f0f0, 0x00f1f1f1, 0x00f2f2f2, 0x00f3f3f3, 0x00f4f4f4, 0x00f5f5f5, 0x00f6f6f6, 0x00f7f7f7, - 0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff, -}; - -#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& ( defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS)) - -/* scaler Timing */ -//1920*1080*60 - -#define S_OUT_CLK SCALE_RATE(148500000,74250000) //m=16 n=9 no=4 -#define S_H_PW 48 -#define S_H_BP 98 -#define S_H_VD 1280 -#define S_H_FP 59 - -#define S_V_PW 6 -#define S_V_BP 25 -#define S_V_VD 800 -#define S_V_FP 2 - -#define S_H_ST 495 -#define S_V_ST 2 - -#define S_PLL_CFG_VAL 0x01842016 -#define S_FRAC 0xc16c2d -#define S_SCL_VST 0x25 -#define S_SCL_HST 0x4ba -#define S_VIF_VST 0x1 -#define S_VIF_HST 0xca - -//1920*1080*50 -#define S1_OUT_CLK SCALE_RATE(148500000,57375000) //m=17 n=11 no=4 -#define S1_H_PW 10 -#define S1_H_BP 10 -#define S1_H_VD 1280 -#define S1_H_FP 77 - -#define S1_V_PW 10 -#define S1_V_BP 10 -#define S1_V_VD 800 -#define S1_V_FP 13 - -#define S1_H_ST 459 -#define S1_V_ST 13 - -#define S1_PLL_CFG_VAL 0x01c42016 -#define S1_FRAC 0x1f9ad4 -#define S1_SCL_VST 0x25 -#define S1_SCL_HST 0x5ab -#define S1_VIF_VST 0x1 -#define S1_VIF_HST 0xca - - -//1280*720*60 -#define S2_OUT_CLK SCALE_RATE(74250000,74250000) //m=32 n=9 no=4 -#define S2_H_PW 48 -#define S2_H_BP 98 -#define S2_H_VD 1280 -#define S2_H_FP 59 - -#define S2_V_PW 6 -#define S2_V_BP 5 -#define S2_V_VD 800 -#define S2_V_FP 2 - -#define S2_H_ST 495 -#define S2_V_ST 15 - - -//bellow are for jettaB -#define S2_PLL_CFG_VAL 0x01822016 -#define S2_FRAC 0xc16c2d -#define S2_SCL_VST 0x19 -#define S2_SCL_HST 0x483 -#define S2_VIF_VST 0x1 -#define S2_VIF_HST 0xcf - - -//1280*720*50 - -#define S3_OUT_CLK SCALE_RATE(74250000,67500000) // m=34 n=11 no=4 -#define S3_H_PW 48 -#define S3_H_BP 233 -#define S3_H_VD 1280 -#define S3_H_FP 59 - -#define S3_V_PW 6 -#define S3_V_BP 5 -#define S3_V_VD 800 -#define S3_V_FP 2 - -#define S3_H_ST 540 -#define S3_V_ST 14 -#define S3_PLL_CFG_VAL 0x01c22016 -#define S3_FRAC 0x1f9ad4 -#define S3_SCL_VST 0x19 -#define S3_SCL_HST 0x569 -#define S3_VIF_VST 0x1 -#define S3_VIF_HST 0xcf - -//720*576*50 -#define S4_OUT_CLK SCALE_RATE(27000000,70312500) //m=75 n=4 no=8 -#define S4_H_PW 48 -#define S4_H_BP 233 -#define S4_H_VD 1280 -#define S4_H_FP 59 - -#define S4_V_PW 9 -#define S4_V_BP 57 -#define S4_V_VD 800 -#define S4_V_FP 2 - -#define S4_H_ST 90 -#define S4_V_ST 2 - -#define S4_PLL_CFG_VAL 0x01412016 -#define S4_FRAC 0xa23d09 -#define S4_SCL_VST 0x2d -#define S4_SCL_HST 0x33d -#define S4_VIF_VST 0x1 -#define S4_VIF_HST 0xc1 - - -//720*480*60 -#define S5_OUT_CLK SCALE_RATE(27000000,75000000) //m=100 n=9 no=4 -#define S5_H_PW 48 -#define S5_H_BP 86 -#define S5_H_VD 1280 -#define S5_H_FP 16 - -#define S5_V_PW 9 -#define S5_V_BP 35 -#define S5_V_VD 800 -#define S5_V_FP 30 - -#define S5_H_ST 476 -#define S5_V_ST 12 - -#define S5_PLL_CFG_VAL 0x01c11013 -#define S5_FRAC 0x25325e -#define S5_SCL_VST 0x26 -#define S5_SCL_HST 0x2ae -#define S5_VIF_VST 0x1 -#define S5_VIF_HST 0xc1 - - -#define S_DCLK_POL 1 - - -static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution) -{ - screen->s_clk_inv = S_DCLK_POL; - screen->s_den_inv = 0; - screen->s_hv_sync_inv = 0; - switch(hdmi_resolution){ - case HDMI_1920x1080p_60Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S_OUT_CLK; - screen->s_hsync_len = S_H_PW; - screen->s_left_margin = S_H_BP; - screen->s_right_margin = S_H_FP; - screen->s_hsync_len = S_H_PW; - screen->s_upper_margin = S_V_BP; - screen->s_lower_margin = S_V_FP; - screen->s_vsync_len = S_V_PW; - screen->s_hsync_st = S_H_ST; - screen->s_vsync_st = S_V_ST; - break; - case HDMI_1920x1080p_50Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S1_OUT_CLK; - screen->s_hsync_len = S1_H_PW; - screen->s_left_margin = S1_H_BP; - screen->s_right_margin = S1_H_FP; - screen->s_hsync_len = S1_H_PW; - screen->s_upper_margin = S1_V_BP; - screen->s_lower_margin = S1_V_FP; - screen->s_vsync_len = S1_V_PW; - screen->s_hsync_st = S1_H_ST; - screen->s_vsync_st = S1_V_ST; - break; - case HDMI_1280x720p_60Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S2_OUT_CLK; - screen->s_hsync_len = S2_H_PW; - screen->s_left_margin = S2_H_BP; - screen->s_right_margin = S2_H_FP; - screen->s_hsync_len = S2_H_PW; - screen->s_upper_margin = S2_V_BP; - screen->s_lower_margin = S2_V_FP; - screen->s_vsync_len = S2_V_PW; - screen->s_hsync_st = S2_H_ST; - screen->s_vsync_st = S2_V_ST; - break; - case HDMI_1280x720p_50Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S3_OUT_CLK; - screen->s_hsync_len = S3_H_PW; - screen->s_left_margin = S3_H_BP; - screen->s_right_margin = S3_H_FP; - screen->s_hsync_len = S3_H_PW; - screen->s_upper_margin = S3_V_BP; - screen->s_lower_margin = S3_V_FP; - screen->s_vsync_len = S3_V_PW; - screen->s_hsync_st = S3_H_ST; - screen->s_vsync_st = S3_V_ST; - break; - case HDMI_720x576p_50Hz_4_3: - case HDMI_720x576p_50Hz_16_9: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S4_OUT_CLK; - screen->s_hsync_len = S4_H_PW; - screen->s_left_margin = S4_H_BP; - screen->s_right_margin = S4_H_FP; - screen->s_hsync_len = S4_H_PW; - screen->s_upper_margin = S4_V_BP; - screen->s_lower_margin = S4_V_FP; - screen->s_vsync_len = S4_V_PW; - screen->s_hsync_st = S4_H_ST; - screen->s_vsync_st = S4_V_ST; - break; - case HDMI_720x480p_60Hz_16_9: - case HDMI_720x480p_60Hz_4_3: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S5_OUT_CLK; - screen->s_hsync_len = S5_H_PW; - screen->s_left_margin = S5_H_BP; - screen->s_right_margin = S5_H_FP; - screen->s_hsync_len = S5_H_PW; - screen->s_upper_margin = S5_V_BP; - screen->s_lower_margin = S5_V_FP; - screen->s_vsync_len = S5_V_PW; - screen->s_hsync_st = S5_H_ST; - screen->s_vsync_st = S5_V_ST; - break; - default : - printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution); - return -1; - break; - } - - return 0; -} -#else -#define set_scaler_info NULL -#endif - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->face = OUT_FACE; - screen->type = OUT_TYPE; -#if defined(CONFIG_RK610_LVDS)|| defined(CONFIG_RK616_VIF) - screen->hw_format = LVDS_FORMAT; -#endif - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = HSYNC_POL; - screen->pin_vsync = VSYNC_POL; - screen->pin_den = DEN_POL; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = SWAP_RG; - screen->swap_gb = SWAP_GB; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; - screen->dsp_lut = dsp_lut; - screen->sscreen_get = set_scaler_info; -#if defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS) - screen->sscreen_set = rk610_lcd_scaler_set_param; -#endif -} - -size_t get_fb_size(void) -{ - size_t size = 0; - #if defined(CONFIG_THREE_FB_BUFFER) - size = ((H_VD)*(V_VD)<<2)* 3; //three buffer - #else - size = ((H_VD)*(V_VD)<<2)<<1; //two buffer - #endif - return ALIGN(size,SZ_1M); -} - diff --git a/drivers/video/display/screen/lcd_byd1024x600.c b/drivers/video/display/screen/lcd_byd1024x600.c deleted file mode 100644 index d00901890d11..000000000000 --- a/drivers/video/display/screen/lcd_byd1024x600.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * This Lcd Driver is for BYD 5' LCD BM800480-8545FTGE. - * written by Michael Lin, 2010-06-18 - */ - -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include "screen.h" - - -/* Base */ -#define OUT_TYPE SCREEN_RGB -#define OUT_FACE OUT_P888 -//tcl miaozh modify -//#define OUT_CLK 50000000 -#define OUT_CLK 47000000 -//#define OUT_CLK 42000000 -#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 10 -#define H_BP 160 -#define H_VD 1024 -#define H_FP 119 - -#define V_PW 3 -#define V_BP 23 -#define V_VD 600 -#define V_FP 9 - -/* Other */ -#define DCLK_POL 0 -#define SWAP_RB 0 - -//tcl miaozh modify -//#define LCD_WIDTH 1024 //need modify -//#define LCD_HEIGHT 600 -#define LCD_WIDTH 153 //need modify -#define LCD_HEIGHT 90 - -static struct rk29lcd_info *gLcd_info = NULL; - -#define DRVDelayUs(i) udelay(i*2) - -static int init(void); -static int standby(u8 enable); - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - /*screen->init = init;*/ - screen->init = NULL; - screen->standby = standby; -} - - -static int standby(u8 enable) -{ - printk(KERN_INFO "byd1024x600 lcd standby, enable=%d\n", enable); - if (enable) - { - //rockchip_mux_api_set(LED_CON_IOMUX_PINNAME, LED_CON_IOMUX_PINDIR); - //GPIOSetPinDirection(LED_CON_IOPIN,GPIO_OUT); - //GPIOSetPinLevel(LED_CON_IOPIN,GPIO_HIGH); -// gpio_set_value(LCD_DISP_ON_IOPIN, GPIO_LOW); - } - else - { - //rockchip_mux_api_set(LED_CON_IOMUX_PINNAME, 1); -// gpio_set_value(LCD_DISP_ON_IOPIN, GPIO_HIGH); - } - return 0; -} - diff --git a/drivers/video/display/screen/lcd_common.c b/drivers/video/display/screen/lcd_common.c deleted file mode 100644 index 4d18e7b442aa..000000000000 --- a/drivers/video/display/screen/lcd_common.c +++ /dev/null @@ -1,79 +0,0 @@ -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include "screen.h" - -/* Base */ -#define OUT_TYPE SCREEN_RGB - -#define OUT_FACE OUT_D888_P666 - - -#define OUT_CLK 71000000 -#define LCDC_ACLK 300000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 10 -#define H_BP 100 -#define H_VD 1280 -#define H_FP 18 - -#define V_PW 2 -#define V_BP 8 -#define V_VD 800 -#define V_FP 6 - -#define LCD_WIDTH 216 -#define LCD_HEIGHT 135 -/* Other */ -#define DCLK_POL 0 -#define SWAP_RB 0 - - -u32 lcdpamara[]={0x4B434F52,0x64636C5F,0x61746164,SCREEN_RGB,OUT_D888_P666,71000000,300000000,10,100,1280,18,2,8,800,6,216,135,0,0}; - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = lcdpamara[3]; - screen->face = lcdpamara[4]; - - /* Screen size */ - screen->x_res = lcdpamara[9]; - screen->y_res = lcdpamara[13]; - - screen->width = lcdpamara[15]; - screen->height = lcdpamara[16]; - - /* Timing */ - screen->lcdc_aclk = lcdpamara[6]; - screen->pixclock = lcdpamara[5]; - screen->left_margin = lcdpamara[8]; - screen->right_margin = lcdpamara[10]; - screen->hsync_len = lcdpamara[7]; - screen->upper_margin = lcdpamara[12]; - screen->lower_margin = lcdpamara[14]; - screen->vsync_len = lcdpamara[11]; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = lcdpamara[17]; - - /* Swap rule */ - screen->swap_rb = lcdpamara[18]; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; - -} - diff --git a/drivers/video/display/screen/lcd_ds1006h.c b/drivers/video/display/screen/lcd_ds1006h.c deleted file mode 100755 index ddfcd5b8ab64..000000000000 --- a/drivers/video/display/screen/lcd_ds1006h.c +++ /dev/null @@ -1,347 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include "../../rockchip/hdmi/rk_hdmi.h" -#include "screen.h" - -#ifdef CONFIG_RK610_LVDS -#include "../transmitter/rk610_lcd.h" -#endif - - -/* Base */ -#ifdef CONFIG_RK610_LVDS -#define OUT_TYPE SCREEN_LVDS -#define OUT_FORMAT LVDS_8BIT_1 -#else -#define OUT_TYPE SCREEN_RGB -#endif - -#define OUT_FACE OUT_P888 - - -#define OUT_CLK 71000000 -#define LCDC_ACLK 500000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 1 -#define H_BP 1 -#define H_VD 1280 -#define H_FP 158 - -#define V_PW 1 -#define V_BP 1 -#define V_VD 800 -#define V_FP 21 - -#define LCD_WIDTH 216 -#define LCD_HEIGHT 135 -/* Other */ -#ifdef CONFIG_RK610_LVDS -#define DCLK_POL 1 -#else -#define DCLK_POL 0 -#endif - -#define SWAP_RB 0 - -int dsp_lut[256] ={ - 0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707, - 0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f, - 0x00101010, 0x00111111, 0x00121212, 0x00131313, 0x00141414, 0x00151515, 0x00161616, 0x00171717, - 0x00181818, 0x00191919, 0x001a1a1a, 0x001b1b1b, 0x001c1c1c, 0x001d1d1d, 0x001e1e1e, 0x001f1f1f, - 0x00202020, 0x00212121, 0x00222222, 0x00232323, 0x00242424, 0x00252525, 0x00262626, 0x00272727, - 0x00282828, 0x00292929, 0x002a2a2a, 0x002b2b2b, 0x002c2c2c, 0x002d2d2d, 0x002e2e2e, 0x002f2f2f, - 0x00303030, 0x00313131, 0x00323232, 0x00333333, 0x00343434, 0x00353535, 0x00363636, 0x00373737, - 0x00383838, 0x00393939, 0x003a3a3a, 0x003b3b3b, 0x003c3c3c, 0x003d3d3d, 0x003e3e3e, 0x003f3f3f, - 0x00404040, 0x00414141, 0x00424242, 0x00434343, 0x00444444, 0x00454545, 0x00464646, 0x00474747, - 0x00484848, 0x00494949, 0x004a4a4a, 0x004b4b4b, 0x004c4c4c, 0x004d4d4d, 0x004e4e4e, 0x004f4f4f, - 0x00505050, 0x00515151, 0x00525252, 0x00535353, 0x00545454, 0x00555555, 0x00565656, 0x00575757, - 0x00585858, 0x00595959, 0x005a5a5a, 0x005b5b5b, 0x005c5c5c, 0x005d5d5d, 0x005e5e5e, 0x005f5f5f, - 0x00606060, 0x00616161, 0x00626262, 0x00636363, 0x00646464, 0x00656565, 0x00666666, 0x00676767, - 0x00686868, 0x00696969, 0x006a6a6a, 0x006b6b6b, 0x006c6c6c, 0x006d6d6d, 0x006e6e6e, 0x006f6f6f, - 0x00707070, 0x00717171, 0x00727272, 0x00737373, 0x00747474, 0x00757575, 0x00767676, 0x00777777, - 0x00787878, 0x00797979, 0x007a7a7a, 0x007b7b7b, 0x007c7c7c, 0x007d7d7d, 0x007e7e7e, 0x007f7f7f, - 0x00808080, 0x00818181, 0x00828282, 0x00838383, 0x00848484, 0x00858585, 0x00868686, 0x00878787, - 0x00888888, 0x00898989, 0x008a8a8a, 0x008b8b8b, 0x008c8c8c, 0x008d8d8d, 0x008e8e8e, 0x008f8f8f, - 0x00909090, 0x00919191, 0x00929292, 0x00939393, 0x00949494, 0x00959595, 0x00969696, 0x00979797, - 0x00989898, 0x00999999, 0x009a9a9a, 0x009b9b9b, 0x009c9c9c, 0x009d9d9d, 0x009e9e9e, 0x009f9f9f, - 0x00a0a0a0, 0x00a1a1a1, 0x00a2a2a2, 0x00a3a3a3, 0x00a4a4a4, 0x00a5a5a5, 0x00a6a6a6, 0x00a7a7a7, - 0x00a8a8a8, 0x00a9a9a9, 0x00aaaaaa, 0x00ababab, 0x00acacac, 0x00adadad, 0x00aeaeae, 0x00afafaf, - 0x00b0b0b0, 0x00b1b1b1, 0x00b2b2b2, 0x00b3b3b3, 0x00b4b4b4, 0x00b5b5b5, 0x00b6b6b6, 0x00b7b7b7, - 0x00b8b8b8, 0x00b9b9b9, 0x00bababa, 0x00bbbbbb, 0x00bcbcbc, 0x00bdbdbd, 0x00bebebe, 0x00bfbfbf, - 0x00c0c0c0, 0x00c1c1c1, 0x00c2c2c2, 0x00c3c3c3, 0x00c4c4c4, 0x00c5c5c5, 0x00c6c6c6, 0x00c7c7c7, - 0x00c8c8c8, 0x00c9c9c9, 0x00cacaca, 0x00cbcbcb, 0x00cccccc, 0x00cdcdcd, 0x00cecece, 0x00cfcfcf, - 0x00d0d0d0, 0x00d1d1d1, 0x00d2d2d2, 0x00d3d3d3, 0x00d4d4d4, 0x00d5d5d5, 0x00d6d6d6, 0x00d7d7d7, - 0x00d8d8d8, 0x00d9d9d9, 0x00dadada, 0x00dbdbdb, 0x00dcdcdc, 0x00dddddd, 0x00dedede, 0x00dfdfdf, - 0x00e0e0e0, 0x00e1e1e1, 0x00e2e2e2, 0x00e3e3e3, 0x00e4e4e4, 0x00e5e5e5, 0x00e6e6e6, 0x00e7e7e7, - 0x00e8e8e8, 0x00e9e9e9, 0x00eaeaea, 0x00ebebeb, 0x00ececec, 0x00ededed, 0x00eeeeee, 0x00efefef, - 0x00f0f0f0, 0x00f1f1f1, 0x00f2f2f2, 0x00f3f3f3, 0x00f4f4f4, 0x00f5f5f5, 0x00f6f6f6, 0x00f7f7f7, - 0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff, -}; - -#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS) - -/* scaler Timing */ -//1920*1080*60 - -#define S_OUT_CLK SCALE_RATE(148500000,74250000) //m=16 n=9 no=4 -#define S_H_PW 48 -#define S_H_BP 98 -#define S_H_VD 1280 -#define S_H_FP 59 - -#define S_V_PW 6 -#define S_V_BP 25 -#define S_V_VD 800 -#define S_V_FP 2 - -#define S_H_ST 495 -#define S_V_ST 2 - -//1920*1080*50 -#define S1_OUT_CLK SCALE_RATE(148500000,57375000) //m=17 n=11 no=4 -#define S1_H_PW 10 -#define S1_H_BP 10 -#define S1_H_VD 1280 -#define S1_H_FP 77 - -#define S1_V_PW 10 -#define S1_V_BP 10 -#define S1_V_VD 800 -#define S1_V_FP 13 - -#define S1_H_ST 459 -#define S1_V_ST 13 - -//1280*720*60 -#define S2_OUT_CLK SCALE_RATE(74250000,74250000) //m=32 n=9 no=4 -#define S2_H_PW 48 -#define S2_H_BP 98 -#define S2_H_VD 1280 -#define S2_H_FP 59 - -#define S2_V_PW 6 -#define S2_V_BP 5 -#define S2_V_VD 800 -#define S2_V_FP 2 - -#define S2_H_ST 495 -#define S2_V_ST 15 - -//1280*720*50 - -#define S3_OUT_CLK SCALE_RATE(74250000,67500000) // m=34 n=11 no=4 -#define S3_H_PW 48 -#define S3_H_BP 233 -#define S3_H_VD 1280 -#define S3_H_FP 59 - -#define S3_V_PW 6 -#define S3_V_BP 5 -#define S3_V_VD 800 -#define S3_V_FP 2 - -#define S3_H_ST 540 -#define S3_V_ST 14 - -//720*576*50 -#define S4_OUT_CLK SCALE_RATE(27000000,70312500) //m=75 n=4 no=8 -#define S4_H_PW 48 -#define S4_H_BP 233 -#define S4_H_VD 1280 -#define S4_H_FP 59 - -#define S4_V_PW 9 -#define S4_V_BP 57 -#define S4_V_VD 800 -#define S4_V_FP 2 - -#define S4_H_ST 90 -#define S4_V_ST 2 - -//720*480*60 -#define S5_OUT_CLK SCALE_RATE(27000000,75000000) //m=100 n=9 no=4 -#define S5_H_PW 48 -#define S5_H_BP 86 -#define S5_H_VD 1280 -#define S5_H_FP 16 - -#define S5_V_PW 9 -#define S5_V_BP 35 -#define S5_V_VD 800 -#define S5_V_FP 30 - -#define S5_H_ST 476 -#define S5_V_ST 12 - -#define S_DCLK_POL 1 - - -static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution) -{ - screen->s_clk_inv = S_DCLK_POL; - screen->s_den_inv = 0; - screen->s_hv_sync_inv = 0; - switch(hdmi_resolution){ - case HDMI_1920x1080p_60Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S_OUT_CLK; - screen->s_hsync_len = S_H_PW; - screen->s_left_margin = S_H_BP; - screen->s_right_margin = S_H_FP; - screen->s_hsync_len = S_H_PW; - screen->s_upper_margin = S_V_BP; - screen->s_lower_margin = S_V_FP; - screen->s_vsync_len = S_V_PW; - screen->s_hsync_st = S_H_ST; - screen->s_vsync_st = S_V_ST; - break; - case HDMI_1920x1080p_50Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S1_OUT_CLK; - screen->s_hsync_len = S1_H_PW; - screen->s_left_margin = S1_H_BP; - screen->s_right_margin = S1_H_FP; - screen->s_hsync_len = S1_H_PW; - screen->s_upper_margin = S1_V_BP; - screen->s_lower_margin = S1_V_FP; - screen->s_vsync_len = S1_V_PW; - screen->s_hsync_st = S1_H_ST; - screen->s_vsync_st = S1_V_ST; - break; - case HDMI_1280x720p_60Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S2_OUT_CLK; - screen->s_hsync_len = S2_H_PW; - screen->s_left_margin = S2_H_BP; - screen->s_right_margin = S2_H_FP; - screen->s_hsync_len = S2_H_PW; - screen->s_upper_margin = S2_V_BP; - screen->s_lower_margin = S2_V_FP; - screen->s_vsync_len = S2_V_PW; - screen->s_hsync_st = S2_H_ST; - screen->s_vsync_st = S2_V_ST; - break; - case HDMI_1280x720p_50Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S3_OUT_CLK; - screen->s_hsync_len = S3_H_PW; - screen->s_left_margin = S3_H_BP; - screen->s_right_margin = S3_H_FP; - screen->s_hsync_len = S3_H_PW; - screen->s_upper_margin = S3_V_BP; - screen->s_lower_margin = S3_V_FP; - screen->s_vsync_len = S3_V_PW; - screen->s_hsync_st = S3_H_ST; - screen->s_vsync_st = S3_V_ST; - break; - case HDMI_720x576p_50Hz_4_3: - case HDMI_720x576p_50Hz_16_9: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S4_OUT_CLK; - screen->s_hsync_len = S4_H_PW; - screen->s_left_margin = S4_H_BP; - screen->s_right_margin = S4_H_FP; - screen->s_hsync_len = S4_H_PW; - screen->s_upper_margin = S4_V_BP; - screen->s_lower_margin = S4_V_FP; - screen->s_vsync_len = S4_V_PW; - screen->s_hsync_st = S4_H_ST; - screen->s_vsync_st = S4_V_ST; - break; - case HDMI_720x480p_60Hz_16_9: - case HDMI_720x480p_60Hz_4_3: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S5_OUT_CLK; - screen->s_hsync_len = S5_H_PW; - screen->s_left_margin = S5_H_BP; - screen->s_right_margin = S5_H_FP; - screen->s_hsync_len = S5_H_PW; - screen->s_upper_margin = S5_V_BP; - screen->s_lower_margin = S5_V_FP; - screen->s_vsync_len = S5_V_PW; - screen->s_hsync_st = S5_H_ST; - screen->s_vsync_st = S5_V_ST; - break; - default : - printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution); - return -1; - break; - } - - return 0; -} -#else -#define set_scaler_info NULL -#endif - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->face = OUT_FACE; - screen->type = OUT_TYPE; -#ifdef CONFIG_RK610_LVDS - screen->hw_format = OUT_FORMAT; -#endif - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; - screen->dsp_lut = dsp_lut; - screen->sscreen_get = set_scaler_info; -#ifdef CONFIG_RK610_LVDS - screen->sscreen_set = rk610_lcd_scaler_set_param; -#endif -} - -size_t get_fb_size(void) -{ - size_t size = 0; - #if defined(CONFIG_THREE_FB_BUFFER) - size = ((H_VD)*(V_VD)<<2)* 3; //three buffer - #else - size = ((H_VD)*(V_VD)<<2)<<1; //two buffer - #endif - return ALIGN(size,SZ_1M); -} - diff --git a/drivers/video/display/screen/lcd_hdmi_1024x600.c b/drivers/video/display/screen/lcd_hdmi_1024x600.c deleted file mode 100644 index 1560edc61f08..000000000000 --- a/drivers/video/display/screen/lcd_hdmi_1024x600.c +++ /dev/null @@ -1,352 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include "../../rockchip/hdmi/rk_hdmi.h" - - -#ifdef CONFIG_RK610_LVDS -#include "../transmitter/rk610_lcd.h" -#endif - - -/* Base */ -#ifdef CONFIG_RK610_LVDS -#define OUT_TYPE SCREEN_LVDS -#define LVDS_FORMAT LVDS_8BIT_1 -#else -#define OUT_TYPE SCREEN_RGB -#endif - -#define OUT_FACE OUT_P888 -//#define OUT_FACE OUT_P888 -#define OUT_CLK 50000000 // 65000000 -#define LCDC_ACLK 312000000//312000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 20 -#define H_BP 20 -#define H_VD 1024 -#define H_FP 280 - -#define V_PW 2 -#define V_BP 2 -#define V_VD 600 -#define V_FP 34 - -#define LCD_WIDTH 154//1024 -#define LCD_HEIGHT 91//600 -/* Other */ -#ifdef CONFIG_RK610_LVDS -#define DCLK_POL 1 -#else -#define DCLK_POL 0 -#endif - -#define DEN_POL 0 -#define VSYNC_POL 0 -#define HSYNC_POL 0 - -#define SWAP_RB 0 -#define SWAP_RG 0 -#define SWAP_GB 0 - -int dsp_lut[256] ={ - 0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707, - 0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f, - 0x00101010, 0x00111111, 0x00121212, 0x00131313, 0x00141414, 0x00151515, 0x00161616, 0x00171717, - 0x00181818, 0x00191919, 0x001a1a1a, 0x001b1b1b, 0x001c1c1c, 0x001d1d1d, 0x001e1e1e, 0x001f1f1f, - 0x00202020, 0x00212121, 0x00222222, 0x00232323, 0x00242424, 0x00252525, 0x00262626, 0x00272727, - 0x00282828, 0x00292929, 0x002a2a2a, 0x002b2b2b, 0x002c2c2c, 0x002d2d2d, 0x002e2e2e, 0x002f2f2f, - 0x00303030, 0x00313131, 0x00323232, 0x00333333, 0x00343434, 0x00353535, 0x00363636, 0x00373737, - 0x00383838, 0x00393939, 0x003a3a3a, 0x003b3b3b, 0x003c3c3c, 0x003d3d3d, 0x003e3e3e, 0x003f3f3f, - 0x00404040, 0x00414141, 0x00424242, 0x00434343, 0x00444444, 0x00454545, 0x00464646, 0x00474747, - 0x00484848, 0x00494949, 0x004a4a4a, 0x004b4b4b, 0x004c4c4c, 0x004d4d4d, 0x004e4e4e, 0x004f4f4f, - 0x00505050, 0x00515151, 0x00525252, 0x00535353, 0x00545454, 0x00555555, 0x00565656, 0x00575757, - 0x00585858, 0x00595959, 0x005a5a5a, 0x005b5b5b, 0x005c5c5c, 0x005d5d5d, 0x005e5e5e, 0x005f5f5f, - 0x00606060, 0x00616161, 0x00626262, 0x00636363, 0x00646464, 0x00656565, 0x00666666, 0x00676767, - 0x00686868, 0x00696969, 0x006a6a6a, 0x006b6b6b, 0x006c6c6c, 0x006d6d6d, 0x006e6e6e, 0x006f6f6f, - 0x00707070, 0x00717171, 0x00727272, 0x00737373, 0x00747474, 0x00757575, 0x00767676, 0x00777777, - 0x00787878, 0x00797979, 0x007a7a7a, 0x007b7b7b, 0x007c7c7c, 0x007d7d7d, 0x007e7e7e, 0x007f7f7f, - 0x00808080, 0x00818181, 0x00828282, 0x00838383, 0x00848484, 0x00858585, 0x00868686, 0x00878787, - 0x00888888, 0x00898989, 0x008a8a8a, 0x008b8b8b, 0x008c8c8c, 0x008d8d8d, 0x008e8e8e, 0x008f8f8f, - 0x00909090, 0x00919191, 0x00929292, 0x00939393, 0x00949494, 0x00959595, 0x00969696, 0x00979797, - 0x00989898, 0x00999999, 0x009a9a9a, 0x009b9b9b, 0x009c9c9c, 0x009d9d9d, 0x009e9e9e, 0x009f9f9f, - 0x00a0a0a0, 0x00a1a1a1, 0x00a2a2a2, 0x00a3a3a3, 0x00a4a4a4, 0x00a5a5a5, 0x00a6a6a6, 0x00a7a7a7, - 0x00a8a8a8, 0x00a9a9a9, 0x00aaaaaa, 0x00ababab, 0x00acacac, 0x00adadad, 0x00aeaeae, 0x00afafaf, - 0x00b0b0b0, 0x00b1b1b1, 0x00b2b2b2, 0x00b3b3b3, 0x00b4b4b4, 0x00b5b5b5, 0x00b6b6b6, 0x00b7b7b7, - 0x00b8b8b8, 0x00b9b9b9, 0x00bababa, 0x00bbbbbb, 0x00bcbcbc, 0x00bdbdbd, 0x00bebebe, 0x00bfbfbf, - 0x00c0c0c0, 0x00c1c1c1, 0x00c2c2c2, 0x00c3c3c3, 0x00c4c4c4, 0x00c5c5c5, 0x00c6c6c6, 0x00c7c7c7, - 0x00c8c8c8, 0x00c9c9c9, 0x00cacaca, 0x00cbcbcb, 0x00cccccc, 0x00cdcdcd, 0x00cecece, 0x00cfcfcf, - 0x00d0d0d0, 0x00d1d1d1, 0x00d2d2d2, 0x00d3d3d3, 0x00d4d4d4, 0x00d5d5d5, 0x00d6d6d6, 0x00d7d7d7, - 0x00d8d8d8, 0x00d9d9d9, 0x00dadada, 0x00dbdbdb, 0x00dcdcdc, 0x00dddddd, 0x00dedede, 0x00dfdfdf, - 0x00e0e0e0, 0x00e1e1e1, 0x00e2e2e2, 0x00e3e3e3, 0x00e4e4e4, 0x00e5e5e5, 0x00e6e6e6, 0x00e7e7e7, - 0x00e8e8e8, 0x00e9e9e9, 0x00eaeaea, 0x00ebebeb, 0x00ececec, 0x00ededed, 0x00eeeeee, 0x00efefef, - 0x00f0f0f0, 0x00f1f1f1, 0x00f2f2f2, 0x00f3f3f3, 0x00f4f4f4, 0x00f5f5f5, 0x00f6f6f6, 0x00f7f7f7, - 0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff, -}; - -#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS) - -/* scaler Timing */ -//1920*1080*60 - -#define S_OUT_CLK SCALE_RATE(148500000,50625000) -#define S_H_PW 10 -#define S_H_BP 10 -#define S_H_VD 1024 -#define S_H_FP 306 - -#define S_V_PW 10 -#define S_V_BP 10 -#define S_V_VD 600 -#define S_V_FP 5 - -#define S_H_ST 0 -#define S_V_ST 5 - -//1920*1080*50 -#define S1_OUT_CLK SCALE_RATE(148500000,45375000) -#define S1_H_PW 10 -#define S1_H_BP 10 -#define S1_H_VD 1024 -#define S1_H_FP 408 - -#define S1_V_PW 10 -#define S1_V_BP 10 -#define S1_V_VD 600 -#define S1_V_FP 5 - -#define S1_H_ST 0 -#define S1_V_ST 5 - -//1280*720*60 -#define S2_OUT_CLK SCALE_RATE(74250000,50625000) -#define S2_H_PW 10 -#define S2_H_BP 10 -#define S2_H_VD 1024 -#define S2_H_FP 306 - -#define S2_V_PW 10 -#define S2_V_BP 10 -#define S2_V_VD 600 -#define S2_V_FP 5 - -#define S2_H_ST 0 -#define S2_V_ST 3 - -//1280*720*50 - -#define S3_OUT_CLK SCALE_RATE(74250000,44343750) -#define S3_H_PW 10 -#define S3_H_BP 10 -#define S3_H_VD 1024 -#define S3_H_FP 375 - -#define S3_V_PW 10 -#define S3_V_BP 10 -#define S3_V_VD 600 -#define S3_V_FP 3 - -#define S3_H_ST 0 -#define S3_V_ST 3 - -//720*576*50 -#define S4_OUT_CLK SCALE_RATE(27000000,46875000) -#define S4_H_PW 10 -#define S4_H_BP 10 -#define S4_H_VD 1024 -#define S4_H_FP 396 - -#define S4_V_PW 10 -#define S4_V_BP 10 -#define S4_V_VD 600 -#define S4_V_FP 31 - -#define S4_H_ST 0 -#define S4_V_ST 28 - -//720*480*60 -#define S5_OUT_CLK SCALE_RATE(27000000,56250000) //m=100 n=9 no=4 -#define S5_H_PW 10 -#define S5_H_BP 10 -#define S5_H_VD 1024 -#define S5_H_FP 386 - -#define S5_V_PW 10 -#define S5_V_BP 10 -#define S5_V_VD 600 -#define S5_V_FP 35 - -#define S5_H_ST 0 -#define S5_V_ST 22 - -#define S_DCLK_POL 1 - -static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution) -{ - screen->s_clk_inv = S_DCLK_POL; - screen->s_den_inv = 0; - screen->s_hv_sync_inv = 0; - switch(hdmi_resolution){ - case HDMI_1920x1080p_60Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S_OUT_CLK; - screen->s_hsync_len = S_H_PW; - screen->s_left_margin = S_H_BP; - screen->s_right_margin = S_H_FP; - screen->s_hsync_len = S_H_PW; - screen->s_upper_margin = S_V_BP; - screen->s_lower_margin = S_V_FP; - screen->s_vsync_len = S_V_PW; - screen->s_hsync_st = S_H_ST; - screen->s_vsync_st = S_V_ST; - break; - case HDMI_1920x1080p_50Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S1_OUT_CLK; - screen->s_hsync_len = S1_H_PW; - screen->s_left_margin = S1_H_BP; - screen->s_right_margin = S1_H_FP; - screen->s_hsync_len = S1_H_PW; - screen->s_upper_margin = S1_V_BP; - screen->s_lower_margin = S1_V_FP; - screen->s_vsync_len = S1_V_PW; - screen->s_hsync_st = S1_H_ST; - screen->s_vsync_st = S1_V_ST; - break; - case HDMI_1280x720p_60Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S2_OUT_CLK; - screen->s_hsync_len = S2_H_PW; - screen->s_left_margin = S2_H_BP; - screen->s_right_margin = S2_H_FP; - screen->s_hsync_len = S2_H_PW; - screen->s_upper_margin = S2_V_BP; - screen->s_lower_margin = S2_V_FP; - screen->s_vsync_len = S2_V_PW; - screen->s_hsync_st = S2_H_ST; - screen->s_vsync_st = S2_V_ST; - break; - case HDMI_1280x720p_50Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S3_OUT_CLK; - screen->s_hsync_len = S3_H_PW; - screen->s_left_margin = S3_H_BP; - screen->s_right_margin = S3_H_FP; - screen->s_hsync_len = S3_H_PW; - screen->s_upper_margin = S3_V_BP; - screen->s_lower_margin = S3_V_FP; - screen->s_vsync_len = S3_V_PW; - screen->s_hsync_st = S3_H_ST; - screen->s_vsync_st = S3_V_ST; - break; - case HDMI_720x576p_50Hz_4_3: - case HDMI_720x576p_50Hz_16_9: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S4_OUT_CLK; - screen->s_hsync_len = S4_H_PW; - screen->s_left_margin = S4_H_BP; - screen->s_right_margin = S4_H_FP; - screen->s_hsync_len = S4_H_PW; - screen->s_upper_margin = S4_V_BP; - screen->s_lower_margin = S4_V_FP; - screen->s_vsync_len = S4_V_PW; - screen->s_hsync_st = S4_H_ST; - screen->s_vsync_st = S4_V_ST; - break; - case HDMI_720x480p_60Hz_16_9: - case HDMI_720x480p_60Hz_4_3: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S5_OUT_CLK; - screen->s_hsync_len = S5_H_PW; - screen->s_left_margin = S5_H_BP; - screen->s_right_margin = S5_H_FP; - screen->s_hsync_len = S5_H_PW; - screen->s_upper_margin = S5_V_BP; - screen->s_lower_margin = S5_V_FP; - screen->s_vsync_len = S5_V_PW; - screen->s_hsync_st = S5_H_ST; - screen->s_vsync_st = S5_V_ST; - break; - default : - printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution); - return -1; - break; - } - - return 0; -} -#else -#define set_scaler_info NULL -#endif - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; -#ifdef CONFIG_RK610_LVDS - screen->hw_format = LVDS_FORMAT; -#endif - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = HSYNC_POL; - screen->pin_vsync = VSYNC_POL; - screen->pin_den = DEN_POL; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = SWAP_RG; - screen->swap_gb = SWAP_GB; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; - screen->dsp_lut = dsp_lut; - screen->sscreen_get = set_scaler_info; -#ifdef CONFIG_RK610_LVDS - screen->sscreen_set = rk610_lcd_scaler_set_param; -#endif -} - -size_t get_fb_size(void) -{ - size_t size = 0; - #if defined(CONFIG_THREE_FB_BUFFER) - size = ((H_VD)*(V_VD)<<2)* 3; //three buffer - #else - size = ((H_VD)*(V_VD)<<2)<<1; //two buffer - #endif - return ALIGN(size,SZ_1M); -} - - diff --git a/drivers/video/display/screen/lcd_hdmi_1024x768.c b/drivers/video/display/screen/lcd_hdmi_1024x768.c deleted file mode 100644 index fef8148a5451..000000000000 --- a/drivers/video/display/screen/lcd_hdmi_1024x768.c +++ /dev/null @@ -1,302 +0,0 @@ -#include -#include -#include -#include -#include -#if defined(CONFIG_RK_HDMI) -#include "../../rockchip/hdmi/rk_hdmi.h" -#endif -#ifdef CONFIG_RK610_LVDS -#include "../transmitter/rk610_lcd.h" -#endif - - -/* Base */ -#define OUT_TYPE SCREEN_LVDS - -#define LVDS_FORMAT LVDS_8BIT_2 -#define OUT_FACE OUT_D888_P666 -#define OUT_CLK 65000000 -#define LCDC_ACLK 500000000//312000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 10 -#define H_BP 100 -#define H_VD 1024 -#define H_FP 210 - -#define V_PW 10 -#define V_BP 10 -#define V_VD 768 -#define V_FP 18 - -#define LCD_WIDTH 202 -#define LCD_HEIGHT 152 - -/* scaler Timing */ -//1920*1080*60 -#define S_OUT_CLK SCALE_RATE(148500000,66000000) //m=16 n=9 no=4 -#define S_H_PW 100 -#define S_H_BP 100 -#define S_H_VD 1024 -#define S_H_FP 151 - -#define S_V_PW 5 -#define S_V_BP 15 -#define S_V_VD 768 -#define S_V_FP 12 - -#define S_H_ST 1757 -#define S_V_ST 14 - -//1920*1080*50 -#define S1_OUT_CLK SCALE_RATE(148500000,54000000) //m=16 n=11 no=4 -#define S1_H_PW 100 -#define S1_H_BP 100 -#define S1_H_VD 1024 -#define S1_H_FP 126 - -#define S1_V_PW 5 -#define S1_V_BP 15 -#define S1_V_VD 768 -#define S1_V_FP 12 - -#define S1_H_ST 1757 -#define S1_V_ST 14 - -//1280*720*60 -#define S2_OUT_CLK SCALE_RATE(74250000,66000000) //m=32 n=9 no=4 -#define S2_H_PW 100 -#define S2_H_BP 100 -#define S2_H_VD 1024 -#define S2_H_FP 151 - -#define S2_V_PW 5 -#define S2_V_BP 15 -#define S2_V_VD 768 -#define S2_V_FP 12 - -#define S2_H_ST 0 -#define S2_V_ST 12 -//1280*720*50 - -#define S3_OUT_CLK SCALE_RATE(74250000,54000000) // m=32 n=11 no=4 -#define S3_H_PW 100 -#define S3_H_BP 100 -#define S3_H_VD 1024 -#define S3_H_FP 151 - -#define S3_V_PW 5 -#define S3_V_BP 15 -#define S3_V_VD 768 -#define S3_V_FP 12 - -#define S3_H_ST 0 -#define S3_V_ST 12 - -//720*576*50 -#define S4_OUT_CLK SCALE_RATE(27000000,54375000) //m=145 n=9 no=8 -#define S4_H_PW 100 -#define S4_H_BP 100 -#define S4_H_VD 1024 -#define S4_H_FP 81 - -#define S4_V_PW 5 -#define S4_V_BP 15 -#define S4_V_VD 768 -#define S4_V_FP 45 - - -#define S4_H_ST 435 -#define S4_V_ST 45 -//720*480*60 -#define S5_OUT_CLK SCALE_RATE(27000000,72000000) //m=32 n=3 no=4 -#define S5_H_PW 100 -#define S5_H_BP 100 -#define S5_H_VD 1024 -#define S5_H_FP 81 - -#define S5_V_PW 5 -#define S5_V_BP 15 -#define S5_V_VD 768 -#define S5_V_FP 51 - -#define S5_H_ST 858 -#define S5_V_ST 45 - -#define S_DCLK_POL 0 - -/* Other */ -#define DCLK_POL 0 - -#define DEN_POL 0 -#define VSYNC_POL 0 -#define HSYNC_POL 0 - -#define SWAP_RB 0 -#define SWAP_RG 0 -#define SWAP_GB 0 - - -#if ( defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS) ) || defined(CONFIG_HDMI_DUAL_DISP) -static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution) -{ - screen->s_clk_inv = S_DCLK_POL; - screen->s_den_inv = 0; - screen->s_hv_sync_inv = 0; - switch(hdmi_resolution){ - case HDMI_1920x1080p_60Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S_OUT_CLK; - screen->s_hsync_len = S_H_PW; - screen->s_left_margin = S_H_BP; - screen->s_right_margin = S_H_FP; - screen->s_hsync_len = S_H_PW; - screen->s_upper_margin = S_V_BP; - screen->s_lower_margin = S_V_FP; - screen->s_vsync_len = S_V_PW; - screen->s_hsync_st = S_H_ST; - screen->s_vsync_st = S_V_ST; - break; - case HDMI_1920x1080p_50Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S1_OUT_CLK; - screen->s_hsync_len = S1_H_PW; - screen->s_left_margin = S1_H_BP; - screen->s_right_margin = S1_H_FP; - screen->s_hsync_len = S1_H_PW; - screen->s_upper_margin = S1_V_BP; - screen->s_lower_margin = S1_V_FP; - screen->s_vsync_len = S1_V_PW; - screen->s_hsync_st = S1_H_ST; - screen->s_vsync_st = S1_V_ST; - break; - case HDMI_1280x720p_60Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S2_OUT_CLK; - screen->s_hsync_len = S2_H_PW; - screen->s_left_margin = S2_H_BP; - screen->s_right_margin = S2_H_FP; - screen->s_hsync_len = S2_H_PW; - screen->s_upper_margin = S2_V_BP; - screen->s_lower_margin = S2_V_FP; - screen->s_vsync_len = S2_V_PW; - screen->s_hsync_st = S2_H_ST; - screen->s_vsync_st = S2_V_ST; - break; - case HDMI_1280x720p_50Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S3_OUT_CLK; - screen->s_hsync_len = S3_H_PW; - screen->s_left_margin = S3_H_BP; - screen->s_right_margin = S3_H_FP; - screen->s_hsync_len = S3_H_PW; - screen->s_upper_margin = S3_V_BP; - screen->s_lower_margin = S3_V_FP; - screen->s_vsync_len = S3_V_PW; - screen->s_hsync_st = S3_H_ST; - screen->s_vsync_st = S3_V_ST; - break; - case HDMI_720x576p_50Hz_4_3: - case HDMI_720x576p_50Hz_16_9: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S4_OUT_CLK; - screen->s_hsync_len = S4_H_PW; - screen->s_left_margin = S4_H_BP; - screen->s_right_margin = S4_H_FP; - screen->s_hsync_len = S4_H_PW; - screen->s_upper_margin = S4_V_BP; - screen->s_lower_margin = S4_V_FP; - screen->s_vsync_len = S4_V_PW; - screen->s_hsync_st = S4_H_ST; - screen->s_vsync_st = S4_V_ST; - break; - case HDMI_720x480p_60Hz_16_9: - case HDMI_720x480p_60Hz_4_3: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S5_OUT_CLK; - screen->s_hsync_len = S5_H_PW; - screen->s_left_margin = S5_H_BP; - screen->s_right_margin = S5_H_FP; - screen->s_hsync_len = S5_H_PW; - screen->s_upper_margin = S5_V_BP; - screen->s_lower_margin = S5_V_FP; - screen->s_vsync_len = S5_V_PW; - screen->s_hsync_st = S5_H_ST; - screen->s_vsync_st = S5_V_ST; - break; - default : - printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution); - return -1; - break; - } - - return 0; -} -#else -static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution){return 0;} -#endif - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - screen->hw_format = LVDS_FORMAT; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = HSYNC_POL; - screen->pin_vsync = VSYNC_POL; - screen->pin_den = DEN_POL; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = SWAP_RG; - screen->swap_gb = SWAP_GB; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; - screen->sscreen_get = set_scaler_info; -#ifdef CONFIG_RK610_LVDS - screen->sscreen_set = rk610_lcd_scaler_set_param; -#endif -} - -size_t get_fb_size(void) -{ - size_t size = 0; - #if defined(CONFIG_THREE_FB_BUFFER) - size = ((H_VD)*(V_VD)<<2)* 3; //three buffer - #else - size = ((H_VD)*(V_VD)<<2)<<1; //two buffer - #endif - return ALIGN(size,SZ_1M); -} - diff --git a/drivers/video/display/screen/lcd_hdmi_1280x800.c b/drivers/video/display/screen/lcd_hdmi_1280x800.c deleted file mode 100644 index e6af99f8ce59..000000000000 --- a/drivers/video/display/screen/lcd_hdmi_1280x800.c +++ /dev/null @@ -1,306 +0,0 @@ -#include -#include -#include -#include -#include -#if defined(CONFIG_RK_HDMI) -#include "../../rockchip/hdmi/rk_hdmi.h" -#endif -#ifdef CONFIG_RK610_LVDS -#include "../transmitter/rk610_lcd.h" -#endif - - - -/* Base */ -#define OUT_TYPE SCREEN_LVDS - -#define LVDS_FORMAT LVDS_8BIT_2 - -#define OUT_FACE OUT_D888_P666 -#define OUT_CLK 65000000 -#define LCDC_ACLK 500000000//312000000 //29 lcdc axi DMA ƵÂÊ - - -/* Timing */ -#define H_PW 10 -#define H_BP 10 -#define H_VD 1280 -#define H_FP 20 - -#define V_PW 10 -#define V_BP 10 -#define V_VD 800 -#define V_FP 13 - -#define LCD_WIDTH 202 -#define LCD_HEIGHT 152 - -/* scaler Timing */ -//1920*1080*60 - -#define S_OUT_CLK SCALE_RATE(148500000,66000000) //m=16 n=9 no=4 -#define S_H_PW 10 -#define S_H_BP 10 -#define S_H_VD 1280 -#define S_H_FP 20 - -#define S_V_PW 10 -#define S_V_BP 10 -#define S_V_VD 800 -#define S_V_FP 13 - -#define S_H_ST 440 -#define S_V_ST 13 - -//1920*1080*50 -#define S1_OUT_CLK SCALE_RATE(148500000,57375000) //m=17 n=11 no=4 -#define S1_H_PW 10 -#define S1_H_BP 10 -#define S1_H_VD 1280 -#define S1_H_FP 77 - -#define S1_V_PW 10 -#define S1_V_BP 10 -#define S1_V_VD 800 -#define S1_V_FP 13 - -#define S1_H_ST 459 -#define S1_V_ST 13 - -//1280*720*60 -#define S2_OUT_CLK SCALE_RATE(74250000,66000000) //m=32 n=9 no=4 -#define S2_H_PW 10 -#define S2_H_BP 10 -#define S2_H_VD 1280 -#define S2_H_FP 20 - -#define S2_V_PW 10 -#define S2_V_BP 10 -#define S2_V_VD 800 -#define S2_V_FP 13 - -#define S2_H_ST 440 -#define S2_V_ST 13 - -//1280*720*50 - -#define S3_OUT_CLK SCALE_RATE(74250000,57375000) // m=34 n=11 no=4 -#define S3_H_PW 10 -#define S3_H_BP 10 -#define S3_H_VD 1280 -#define S3_H_FP 77 - -#define S3_V_PW 10 -#define S3_V_BP 10 -#define S3_V_VD 800 -#define S3_V_FP 13 - -#define S3_H_ST 459 -#define S3_V_ST 13 - -//720*576*50 -#define S4_OUT_CLK SCALE_RATE(27000000,63281250) //m=75 n=4 no=8 -#define S4_H_PW 10 -#define S4_H_BP 10 -#define S4_H_VD 1280 -#define S4_H_FP 185 - -#define S4_V_PW 10 -#define S4_V_BP 10 -#define S4_V_VD 800 -#define S4_V_FP 48 - -#define S4_H_ST 81 -#define S4_V_ST 48 - -//720*480*60 -#define S5_OUT_CLK SCALE_RATE(27000000,75000000) //m=100 n=9 no=4 -#define S5_H_PW 10 -#define S5_H_BP 10 -#define S5_H_VD 1280 -#define S5_H_FP 130 - -#define S5_V_PW 10 -#define S5_V_BP 10 -#define S5_V_VD 800 -#define S5_V_FP 54 - -#define S5_H_ST 476 -#define S5_V_ST 48 - -#define S_DCLK_POL 0 - -/* Other */ -#define DCLK_POL 0 -#define DEN_POL 0 -#define VSYNC_POL 0 -#define HSYNC_POL 0 - -#define SWAP_RB 0 -#define SWAP_RG 0 -#define SWAP_GB 0 - - -#if ( defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS) ) || defined(CONFIG_HDMI_DUAL_DISP) -static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution) -{ - screen->s_clk_inv = S_DCLK_POL; - screen->s_den_inv = 0; - screen->s_hv_sync_inv = 0; - switch(hdmi_resolution){ - case HDMI_1920x1080p_60Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S_OUT_CLK; - screen->s_hsync_len = S_H_PW; - screen->s_left_margin = S_H_BP; - screen->s_right_margin = S_H_FP; - screen->s_hsync_len = S_H_PW; - screen->s_upper_margin = S_V_BP; - screen->s_lower_margin = S_V_FP; - screen->s_vsync_len = S_V_PW; - screen->s_hsync_st = S_H_ST; - screen->s_vsync_st = S_V_ST; - break; - case HDMI_1920x1080p_50Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S1_OUT_CLK; - screen->s_hsync_len = S1_H_PW; - screen->s_left_margin = S1_H_BP; - screen->s_right_margin = S1_H_FP; - screen->s_hsync_len = S1_H_PW; - screen->s_upper_margin = S1_V_BP; - screen->s_lower_margin = S1_V_FP; - screen->s_vsync_len = S1_V_PW; - screen->s_hsync_st = S1_H_ST; - screen->s_vsync_st = S1_V_ST; - break; - case HDMI_1280x720p_60Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S2_OUT_CLK; - screen->s_hsync_len = S2_H_PW; - screen->s_left_margin = S2_H_BP; - screen->s_right_margin = S2_H_FP; - screen->s_hsync_len = S2_H_PW; - screen->s_upper_margin = S2_V_BP; - screen->s_lower_margin = S2_V_FP; - screen->s_vsync_len = S2_V_PW; - screen->s_hsync_st = S2_H_ST; - screen->s_vsync_st = S2_V_ST; - break; - case HDMI_1280x720p_50Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S3_OUT_CLK; - screen->s_hsync_len = S3_H_PW; - screen->s_left_margin = S3_H_BP; - screen->s_right_margin = S3_H_FP; - screen->s_hsync_len = S3_H_PW; - screen->s_upper_margin = S3_V_BP; - screen->s_lower_margin = S3_V_FP; - screen->s_vsync_len = S3_V_PW; - screen->s_hsync_st = S3_H_ST; - screen->s_vsync_st = S3_V_ST; - break; - case HDMI_720x576p_50Hz_4_3: - case HDMI_720x576p_50Hz_16_9: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S4_OUT_CLK; - screen->s_hsync_len = S4_H_PW; - screen->s_left_margin = S4_H_BP; - screen->s_right_margin = S4_H_FP; - screen->s_hsync_len = S4_H_PW; - screen->s_upper_margin = S4_V_BP; - screen->s_lower_margin = S4_V_FP; - screen->s_vsync_len = S4_V_PW; - screen->s_hsync_st = S4_H_ST; - screen->s_vsync_st = S4_V_ST; - break; - case HDMI_720x480p_60Hz_16_9: - case HDMI_720x480p_60Hz_4_3: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S5_OUT_CLK; - screen->s_hsync_len = S5_H_PW; - screen->s_left_margin = S5_H_BP; - screen->s_right_margin = S5_H_FP; - screen->s_hsync_len = S5_H_PW; - screen->s_upper_margin = S5_V_BP; - screen->s_lower_margin = S5_V_FP; - screen->s_vsync_len = S5_V_PW; - screen->s_hsync_st = S5_H_ST; - screen->s_vsync_st = S5_V_ST; - break; - default : - printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution); - return -1; - break; - } - - return 0; -} -#else -static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution){return 0;} -#endif -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - screen->hw_format = LVDS_FORMAT; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = HSYNC_POL; - screen->pin_vsync = VSYNC_POL; - screen->pin_den = DEN_POL; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = SWAP_RG; - screen->swap_gb = SWAP_GB; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; - screen->sscreen_get = set_scaler_info; -#ifdef CONFIG_RK610_LVDS - screen->sscreen_set = rk610_lcd_scaler_set_param; -#endif -} - - -size_t get_fb_size(void) -{ - size_t size = 0; - #if defined(CONFIG_THREE_FB_BUFFER) - size = ((H_VD)*(V_VD)<<2)* 3; //three buffer - #else - size = ((H_VD)*(V_VD)<<2)<<1; //two buffer - #endif - return ALIGN(size,SZ_1M); -} - diff --git a/drivers/video/display/screen/lcd_hdmi_1366x768.c b/drivers/video/display/screen/lcd_hdmi_1366x768.c deleted file mode 100644 index 6d14591a4148..000000000000 --- a/drivers/video/display/screen/lcd_hdmi_1366x768.c +++ /dev/null @@ -1,345 +0,0 @@ -#include -#include -#include -#include -#include -#if defined(CONFIG_RK_HDMI) -#include "../../rockchip/hdmi/rk_hdmi.h" -#endif -#ifdef CONFIG_RK610_LVDS -#include "../transmitter/rk610_lcd.h" -#endif - - - -/* Base */ -#define OUT_TYPE SCREEN_LVDS -#define OUT_FORMAT LVDS_8BIT_1 - - -#define OUT_FACE OUT_D888_P666 -//#define OUT_FACE OUT_P888 - - -#define OUT_CLK 95000000 // 1280x800x1.13x60(hz) -#define LCDC_ACLK 500000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 34 -#define H_BP 120 -#define H_VD 1366 -#define H_FP 80 - -#define V_PW 8 -#define V_BP 50 -#define V_VD 768 -#define V_FP 12 - -#define LCD_WIDTH 1366 -#define LCD_HEIGHT 768 - -int dsp_lut[256] ={ - 0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707, - 0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f, - 0x00101010, 0x00111111, 0x00121212, 0x00131313, 0x00141414, 0x00151515, 0x00161616, 0x00171717, - 0x00181818, 0x00191919, 0x001a1a1a, 0x001b1b1b, 0x001c1c1c, 0x001d1d1d, 0x001e1e1e, 0x001f1f1f, - 0x00202020, 0x00212121, 0x00222222, 0x00232323, 0x00242424, 0x00252525, 0x00262626, 0x00272727, - 0x00282828, 0x00292929, 0x002a2a2a, 0x002b2b2b, 0x002c2c2c, 0x002d2d2d, 0x002e2e2e, 0x002f2f2f, - 0x00303030, 0x00313131, 0x00323232, 0x00333333, 0x00343434, 0x00353535, 0x00363636, 0x00373737, - 0x00383838, 0x00393939, 0x003a3a3a, 0x003b3b3b, 0x003c3c3c, 0x003d3d3d, 0x003e3e3e, 0x003f3f3f, - 0x00404040, 0x00414141, 0x00424242, 0x00434343, 0x00444444, 0x00454545, 0x00464646, 0x00474747, - 0x00484848, 0x00494949, 0x004a4a4a, 0x004b4b4b, 0x004c4c4c, 0x004d4d4d, 0x004e4e4e, 0x004f4f4f, - 0x00505050, 0x00515151, 0x00525252, 0x00535353, 0x00545454, 0x00555555, 0x00565656, 0x00575757, - 0x00585858, 0x00595959, 0x005a5a5a, 0x005b5b5b, 0x005c5c5c, 0x005d5d5d, 0x005e5e5e, 0x005f5f5f, - 0x00606060, 0x00616161, 0x00626262, 0x00636363, 0x00646464, 0x00656565, 0x00666666, 0x00676767, - 0x00686868, 0x00696969, 0x006a6a6a, 0x006b6b6b, 0x006c6c6c, 0x006d6d6d, 0x006e6e6e, 0x006f6f6f, - 0x00707070, 0x00717171, 0x00727272, 0x00737373, 0x00747474, 0x00757575, 0x00767676, 0x00777777, - 0x00787878, 0x00797979, 0x007a7a7a, 0x007b7b7b, 0x007c7c7c, 0x007d7d7d, 0x007e7e7e, 0x007f7f7f, - 0x00808080, 0x00818181, 0x00828282, 0x00838383, 0x00848484, 0x00858585, 0x00868686, 0x00878787, - 0x00888888, 0x00898989, 0x008a8a8a, 0x008b8b8b, 0x008c8c8c, 0x008d8d8d, 0x008e8e8e, 0x008f8f8f, - 0x00909090, 0x00919191, 0x00929292, 0x00939393, 0x00949494, 0x00959595, 0x00969696, 0x00979797, - 0x00989898, 0x00999999, 0x009a9a9a, 0x009b9b9b, 0x009c9c9c, 0x009d9d9d, 0x009e9e9e, 0x009f9f9f, - 0x00a0a0a0, 0x00a1a1a1, 0x00a2a2a2, 0x00a3a3a3, 0x00a4a4a4, 0x00a5a5a5, 0x00a6a6a6, 0x00a7a7a7, - 0x00a8a8a8, 0x00a9a9a9, 0x00aaaaaa, 0x00ababab, 0x00acacac, 0x00adadad, 0x00aeaeae, 0x00afafaf, - 0x00b0b0b0, 0x00b1b1b1, 0x00b2b2b2, 0x00b3b3b3, 0x00b4b4b4, 0x00b5b5b5, 0x00b6b6b6, 0x00b7b7b7, - 0x00b8b8b8, 0x00b9b9b9, 0x00bababa, 0x00bbbbbb, 0x00bcbcbc, 0x00bdbdbd, 0x00bebebe, 0x00bfbfbf, - 0x00c0c0c0, 0x00c1c1c1, 0x00c2c2c2, 0x00c3c3c3, 0x00c4c4c4, 0x00c5c5c5, 0x00c6c6c6, 0x00c7c7c7, - 0x00c8c8c8, 0x00c9c9c9, 0x00cacaca, 0x00cbcbcb, 0x00cccccc, 0x00cdcdcd, 0x00cecece, 0x00cfcfcf, - 0x00d0d0d0, 0x00d1d1d1, 0x00d2d2d2, 0x00d3d3d3, 0x00d4d4d4, 0x00d5d5d5, 0x00d6d6d6, 0x00d7d7d7, - 0x00d8d8d8, 0x00d9d9d9, 0x00dadada, 0x00dbdbdb, 0x00dcdcdc, 0x00dddddd, 0x00dedede, 0x00dfdfdf, - 0x00e0e0e0, 0x00e1e1e1, 0x00e2e2e2, 0x00e3e3e3, 0x00e4e4e4, 0x00e5e5e5, 0x00e6e6e6, 0x00e7e7e7, - 0x00e8e8e8, 0x00e9e9e9, 0x00eaeaea, 0x00ebebeb, 0x00ececec, 0x00ededed, 0x00eeeeee, 0x00efefef, - 0x00f0f0f0, 0x00f1f1f1, 0x00f2f2f2, 0x00f3f3f3, 0x00f4f4f4, 0x00f5f5f5, 0x00f6f6f6, 0x00f7f7f7, - 0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff, -}; -/* scaler Timing */ -//1920*1080*60 - -#define S_OUT_CLK SCALE_RATE(148500000,79199997) //m=32 n=15 no=4 -#define S_H_PW 34 -#define S_H_BP 120 -#define S_H_VD 1366 -#define S_H_FP 130 - -#define S_V_PW 8 -#define S_V_BP 10 -#define S_V_VD 768 -#define S_V_FP 13 - -#define S_H_ST 0 -#define S_V_ST 15 - -//1920*1080*50 -#define S1_OUT_CLK SCALE_RATE(148500000,66000000) //m=16 n=9 no=4 -#define S1_H_PW 34 -#define S1_H_BP 120 -#define S1_H_VD 1366 -#define S1_H_FP 130 - -#define S1_V_PW 8 -#define S1_V_BP 10 -#define S1_V_VD 768 -#define S1_V_FP 14 - -#define S1_H_ST 0 -#define S1_V_ST 15 - - -//1280*720p 60HZ -#define S2_OUT_CLK SCALE_RATE(74250000,79199997) //m=64 n=15 no=4 -#define S2_H_PW 34 -#define S2_H_BP 120 -#define S2_H_VD 1366 -#define S2_H_FP 130 - -#define S2_V_PW 8 -#define S2_V_BP 10 -#define S2_V_VD 768 -#define S2_V_FP 13 - -#define S2_H_ST 0 -#define S2_V_ST 8 - -//1280*720*50 - -#define S3_OUT_CLK SCALE_RATE(74250000,66000000) // m=16 n=5 no=4 -#define S3_H_PW 34 -#define S3_H_BP 120 -#define S3_H_VD 1366 -#define S3_H_FP 130 - -#define S3_V_PW 8 -#define S3_V_BP 10 -#define S3_V_VD 768 -#define S3_V_FP 14 - -#define S3_H_ST 0 -#define S3_V_ST 8 - - -//720*576*50 //run -#define S4_OUT_CLK SCALE_RATE(27000000,60000000) //m=91 n=9 no=4 -#define S4_H_PW 34 -#define S4_H_BP 20 -#define S4_H_VD 1366 -#define S4_H_FP 20 - -#define S4_V_PW 8 -#define S4_V_BP 10 -#define S4_V_VD 768 -#define S4_V_FP 47 - -#define S4_H_ST 0 -#define S4_V_ST 33 - -//720*480*60 -#define S5_OUT_CLK SCALE_RATE(27000000,72000000) //m=79 n=7 no=4 -#define S5_H_PW 34 -#define S5_H_BP 20 -#define S5_H_VD 1366 -#define S5_H_FP 10 - -#define S5_V_PW 8 -#define S5_V_BP 10 -#define S5_V_VD 768 -#define S5_V_FP 53 - -#define S5_H_ST 0 -#define S5_V_ST 29 - -#define S_DCLK_POL 1 - -/* Other */ -#define DCLK_POL 1 -#define DEN_POL 0 -#define VSYNC_POL 0 -#define HSYNC_POL 0 - -#define SWAP_RB 0 -#define SWAP_RG 0 -#define SWAP_GB 0 - - -#if ( defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS) ) || defined(CONFIG_HDMI_DUAL_DISP) -static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution) -{ - screen->s_clk_inv = S_DCLK_POL; - screen->s_den_inv = 0; - screen->s_hv_sync_inv = 0; - switch(hdmi_resolution){ - case HDMI_1920x1080p_60Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S_OUT_CLK; - screen->s_hsync_len = S_H_PW; - screen->s_left_margin = S_H_BP; - screen->s_right_margin = S_H_FP; - screen->s_hsync_len = S_H_PW; - screen->s_upper_margin = S_V_BP; - screen->s_lower_margin = S_V_FP; - screen->s_vsync_len = S_V_PW; - screen->s_hsync_st = S_H_ST; - screen->s_vsync_st = S_V_ST; - break; - case HDMI_1920x1080p_50Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S1_OUT_CLK; - screen->s_hsync_len = S1_H_PW; - screen->s_left_margin = S1_H_BP; - screen->s_right_margin = S1_H_FP; - screen->s_hsync_len = S1_H_PW; - screen->s_upper_margin = S1_V_BP; - screen->s_lower_margin = S1_V_FP; - screen->s_vsync_len = S1_V_PW; - screen->s_hsync_st = S1_H_ST; - screen->s_vsync_st = S1_V_ST; - break; - case HDMI_1280x720p_60Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S2_OUT_CLK; - screen->s_hsync_len = S2_H_PW; - screen->s_left_margin = S2_H_BP; - screen->s_right_margin = S2_H_FP; - screen->s_hsync_len = S2_H_PW; - screen->s_upper_margin = S2_V_BP; - screen->s_lower_margin = S2_V_FP; - screen->s_vsync_len = S2_V_PW; - screen->s_hsync_st = S2_H_ST; - screen->s_vsync_st = S2_V_ST; - break; - case HDMI_1280x720p_50Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S3_OUT_CLK; - screen->s_hsync_len = S3_H_PW; - screen->s_left_margin = S3_H_BP; - screen->s_right_margin = S3_H_FP; - screen->s_hsync_len = S3_H_PW; - screen->s_upper_margin = S3_V_BP; - screen->s_lower_margin = S3_V_FP; - screen->s_vsync_len = S3_V_PW; - screen->s_hsync_st = S3_H_ST; - screen->s_vsync_st = S3_V_ST; - break; - case HDMI_720x576p_50Hz_4_3: - case HDMI_720x576p_50Hz_16_9: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S4_OUT_CLK; - screen->s_hsync_len = S4_H_PW; - screen->s_left_margin = S4_H_BP; - screen->s_right_margin = S4_H_FP; - screen->s_hsync_len = S4_H_PW; - screen->s_upper_margin = S4_V_BP; - screen->s_lower_margin = S4_V_FP; - screen->s_vsync_len = S4_V_PW; - screen->s_hsync_st = S4_H_ST; - screen->s_vsync_st = S4_V_ST; - break; - case HDMI_720x480p_60Hz_16_9: - case HDMI_720x480p_60Hz_4_3: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S5_OUT_CLK; - screen->s_hsync_len = S5_H_PW; - screen->s_left_margin = S5_H_BP; - screen->s_right_margin = S5_H_FP; - screen->s_hsync_len = S5_H_PW; - screen->s_upper_margin = S5_V_BP; - screen->s_lower_margin = S5_V_FP; - screen->s_vsync_len = S5_V_PW; - screen->s_hsync_st = S5_H_ST; - screen->s_vsync_st = S5_V_ST; - break; - default : - printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution); - return -1; - break; - } - - return 0; -} -#else -static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution){return 0;} -#endif -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->face = OUT_FACE; - screen->type = OUT_TYPE; - screen->hw_format = OUT_FORMAT; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = HSYNC_POL; - screen->pin_vsync = VSYNC_POL; - screen->pin_den = DEN_POL; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = SWAP_RG; - screen->swap_gb = SWAP_GB; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; - //screen->dsp_lut = dsp_lut; - screen->sscreen_get = set_scaler_info; -#ifdef CONFIG_RK610_LVDS - screen->sscreen_set = rk610_lcd_scaler_set_param; -#endif -} - - -size_t get_fb_size(void) -{ - size_t size = 0; - #if defined(CONFIG_THREE_FB_BUFFER) - size = ((H_VD)*(V_VD)<<2)* 3; //three buffer - #else - size = ((H_VD)*(V_VD)<<2)<<1; //two buffer - #endif - return ALIGN(size,SZ_1M); -} - diff --git a/drivers/video/display/screen/lcd_hdmi_800x480.c b/drivers/video/display/screen/lcd_hdmi_800x480.c deleted file mode 100644 index 9d1e6574d091..000000000000 --- a/drivers/video/display/screen/lcd_hdmi_800x480.c +++ /dev/null @@ -1,298 +0,0 @@ -#include -#include -#include -#include -#if defined(CONFIG_RK_HDMI) -#include "../../rockchip/hdmi/rk_hdmi.h" -#endif -#ifdef CONFIG_RK610_LVDS -#include "../transmitter/rk610_lcd.h" -#endif - - -/* Base */ -#define OUT_TYPE SCREEN_RGB - -#define OUT_FACE OUT_P888 -#define OUT_CLK 33000000 -#define LCDC_ACLK 150000000//312000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 1 -#define H_BP 88 -#define H_VD 800 -#define H_FP 40 - -#define V_PW 3 -#define V_BP 29 -#define V_VD 480 -#define V_FP 13 - -#define LCD_WIDTH 154 -#define LCD_HEIGHT 85 - -/* scaler Timing */ -//1920*1080*60 - -#define S_OUT_CLK SCALE_RATE(148500000,33000000) -#define S_H_PW 1 -#define S_H_BP 88 -#define S_H_VD 800 -#define S_H_FP 211 - -#define S_V_PW 3 -#define S_V_BP 10 -#define S_V_VD 480 -#define S_V_FP 7 - -#define S_H_ST 244 -#define S_V_ST 11 - -//1920*1080*50 -#define S1_OUT_CLK SCALE_RATE(148500000,30375000) -#define S1_H_PW 1 -#define S1_H_BP 88 -#define S1_H_VD 800 -#define S1_H_FP 326 - -#define S1_V_PW 3 -#define S1_V_BP 9 -#define S1_V_VD 480 -#define S1_V_FP 8 - -#define S1_H_ST 270 -#define S1_V_ST 13 -//1280*720*60 -#define S2_OUT_CLK SCALE_RATE(74250000,33000000) -#define S2_H_PW 1 -#define S2_H_BP 88 -#define S2_H_VD 800 -#define S2_H_FP 211 - -#define S2_V_PW 3 -#define S2_V_BP 9 -#define S2_V_VD 480 -#define S2_V_FP 8 - -#define S2_H_ST 0 -#define S2_V_ST 8 -//1280*720*50 - -#define S3_OUT_CLK SCALE_RATE(74250000,30375000) -#define S3_H_PW 1 -#define S3_H_BP 88 -#define S3_H_VD 800 -#define S3_H_FP 326 - -#define S3_V_PW 3 -#define S3_V_BP 9 -#define S3_V_VD 480 -#define S3_V_FP 8 - -#define S3_H_ST 0 -#define S3_V_ST 8 - -//720*576*50 -#define S4_OUT_CLK SCALE_RATE(27000000,30000000) -#define S4_H_PW 1 -#define S4_H_BP 88 -#define S4_H_VD 800 -#define S4_H_FP 263 - -#define S4_V_PW 3 -#define S4_V_BP 9 -#define S4_V_VD 480 -#define S4_V_FP 28 - -#define S4_H_ST 0 -#define S4_V_ST 33 -//720*480*60 -#define S5_OUT_CLK SCALE_RATE(27000000,31500000) -#define S5_H_PW 1 -#define S5_H_BP 88 -#define S5_H_VD 800 -#define S5_H_FP 112 - -#define S5_V_PW 3 -#define S5_V_BP 9 -#define S5_V_VD 480 -#define S5_V_FP 28 - -#define S5_H_ST 0 -#define S5_V_ST 29 - -#define S_DCLK_POL 0 - -/* Other */ -#define DCLK_POL 0 -#define DEN_POL 0 -#define VSYNC_POL 0 -#define HSYNC_POL 0 - -#define SWAP_RB 0 -#define SWAP_RG 0 -#define SWAP_GB 0 - - -#if ( defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS) ) || defined(CONFIG_HDMI_DUAL_DISP) - -static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution) -{ - screen->s_clk_inv = S_DCLK_POL; - screen->s_den_inv = 0; - screen->s_hv_sync_inv = 0; - switch(hdmi_resolution){ - case HDMI_1920x1080p_60Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S_OUT_CLK; - screen->s_hsync_len = S_H_PW; - screen->s_left_margin = S_H_BP; - screen->s_right_margin = S_H_FP; - screen->s_hsync_len = S_H_PW; - screen->s_upper_margin = S_V_BP; - screen->s_lower_margin = S_V_FP; - screen->s_vsync_len = S_V_PW; - screen->s_hsync_st = S_H_ST; - screen->s_vsync_st = S_V_ST; - break; - case HDMI_1920x1080p_50Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S1_OUT_CLK; - screen->s_hsync_len = S1_H_PW; - screen->s_left_margin = S1_H_BP; - screen->s_right_margin = S1_H_FP; - screen->s_hsync_len = S1_H_PW; - screen->s_upper_margin = S1_V_BP; - screen->s_lower_margin = S1_V_FP; - screen->s_vsync_len = S1_V_PW; - screen->s_hsync_st = S1_H_ST; - screen->s_vsync_st = S1_V_ST; - break; - case HDMI_1280x720p_60Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S2_OUT_CLK; - screen->s_hsync_len = S2_H_PW; - screen->s_left_margin = S2_H_BP; - screen->s_right_margin = S2_H_FP; - screen->s_hsync_len = S2_H_PW; - screen->s_upper_margin = S2_V_BP; - screen->s_lower_margin = S2_V_FP; - screen->s_vsync_len = S2_V_PW; - screen->s_hsync_st = S2_H_ST; - screen->s_vsync_st = S2_V_ST; - break; - case HDMI_1280x720p_50Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S3_OUT_CLK; - screen->s_hsync_len = S3_H_PW; - screen->s_left_margin = S3_H_BP; - screen->s_right_margin = S3_H_FP; - screen->s_hsync_len = S3_H_PW; - screen->s_upper_margin = S3_V_BP; - screen->s_lower_margin = S3_V_FP; - screen->s_vsync_len = S3_V_PW; - screen->s_hsync_st = S3_H_ST; - screen->s_vsync_st = S3_V_ST; - break; - case HDMI_720x576p_50Hz_4_3: - case HDMI_720x576p_50Hz_16_9: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S4_OUT_CLK; - screen->s_hsync_len = S4_H_PW; - screen->s_left_margin = S4_H_BP; - screen->s_right_margin = S4_H_FP; - screen->s_hsync_len = S4_H_PW; - screen->s_upper_margin = S4_V_BP; - screen->s_lower_margin = S4_V_FP; - screen->s_vsync_len = S4_V_PW; - screen->s_hsync_st = S4_H_ST; - screen->s_vsync_st = S4_V_ST; - break; - case HDMI_720x480p_60Hz_16_9: - case HDMI_720x480p_60Hz_4_3: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S5_OUT_CLK; - screen->s_hsync_len = S5_H_PW; - screen->s_left_margin = S5_H_BP; - screen->s_right_margin = S5_H_FP; - screen->s_hsync_len = S5_H_PW; - screen->s_upper_margin = S5_V_BP; - screen->s_lower_margin = S5_V_FP; - screen->s_vsync_len = S5_V_PW; - screen->s_hsync_st = S5_H_ST; - screen->s_vsync_st = S5_V_ST; - break; - default : - printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution); - return -1; - break; - } - - return 0; -} -#else -static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution){return 0;} -#endif - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = HSYNC_POL; - screen->pin_vsync = VSYNC_POL; - screen->pin_den = DEN_POL; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = SWAP_RG; - screen->swap_gb = SWAP_GB; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; - screen->sscreen_get = set_scaler_info; -#ifdef CONFIG_RK610_LVDS - screen->sscreen_set = rk610_lcd_scaler_set_param; -#endif -} - -size_t get_fb_size(void) -{ - size_t size = 0; - #if defined(CONFIG_THREE_FB_BUFFER) - size = ((H_VD)*(V_VD)<<2)* 3; //three buffer - #else - size = ((H_VD)*(V_VD)<<2)<<1; //two buffer - #endif - return ALIGN(size,SZ_1M); -} - diff --git a/drivers/video/display/screen/lcd_hdmi_rk3168m_b101ew05.c b/drivers/video/display/screen/lcd_hdmi_rk3168m_b101ew05.c deleted file mode 100755 index 98eaf911daa3..000000000000 --- a/drivers/video/display/screen/lcd_hdmi_rk3168m_b101ew05.c +++ /dev/null @@ -1,353 +0,0 @@ - -#include -#include -#include -#include -#include -#if defined(CONFIG_RK_HDMI) -#include "../../rockchip/hdmi/rk_hdmi.h" -#endif - - -#ifdef CONFIG_RK610_LVDS -#include "../transmitter/rk610_lcd.h" -#endif - - -/* Base */ -#ifdef CONFIG_RK610_LVDS -#define OUT_TYPE SCREEN_LVDS -#define OUT_FORMAT LVDS_8BIT_2 -#else -#define OUT_TYPE SCREEN_RGB -#endif - -#define OUT_FACE OUT_D888_P666 - - -#define OUT_CLK 71000000 -#define LCDC_ACLK 300000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 10 -#define H_BP 100 -#define H_VD 1280 -#define H_FP 18 - -#define V_PW 2 -#define V_BP 8 -#define V_VD 800 -#define V_FP 6 - -#define LCD_WIDTH 216 -#define LCD_HEIGHT 135 -/* Other */ -#ifdef CONFIG_RK610_LVDS -#define DCLK_POL 1 -#else -#define DCLK_POL 0 -#endif -#define DEN_POL 0 -#define VSYNC_POL 0 -#define HSYNC_POL 0 - -#define SWAP_RB 0 -#define SWAP_RG 0 -#define SWAP_GB 0 - -int dsp_lut[256] ={ - 0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707, - 0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f, - 0x00101010, 0x00111111, 0x00121212, 0x00131313, 0x00141414, 0x00151515, 0x00161616, 0x00171717, - 0x00181818, 0x00191919, 0x001a1a1a, 0x001b1b1b, 0x001c1c1c, 0x001d1d1d, 0x001e1e1e, 0x001f1f1f, - 0x00202020, 0x00212121, 0x00222222, 0x00232323, 0x00242424, 0x00252525, 0x00262626, 0x00272727, - 0x00282828, 0x00292929, 0x002a2a2a, 0x002b2b2b, 0x002c2c2c, 0x002d2d2d, 0x002e2e2e, 0x002f2f2f, - 0x00303030, 0x00313131, 0x00323232, 0x00333333, 0x00343434, 0x00353535, 0x00363636, 0x00373737, - 0x00383838, 0x00393939, 0x003a3a3a, 0x003b3b3b, 0x003c3c3c, 0x003d3d3d, 0x003e3e3e, 0x003f3f3f, - 0x00404040, 0x00414141, 0x00424242, 0x00434343, 0x00444444, 0x00454545, 0x00464646, 0x00474747, - 0x00484848, 0x00494949, 0x004a4a4a, 0x004b4b4b, 0x004c4c4c, 0x004d4d4d, 0x004e4e4e, 0x004f4f4f, - 0x00505050, 0x00515151, 0x00525252, 0x00535353, 0x00545454, 0x00555555, 0x00565656, 0x00575757, - 0x00585858, 0x00595959, 0x005a5a5a, 0x005b5b5b, 0x005c5c5c, 0x005d5d5d, 0x005e5e5e, 0x005f5f5f, - 0x00606060, 0x00616161, 0x00626262, 0x00636363, 0x00646464, 0x00656565, 0x00666666, 0x00676767, - 0x00686868, 0x00696969, 0x006a6a6a, 0x006b6b6b, 0x006c6c6c, 0x006d6d6d, 0x006e6e6e, 0x006f6f6f, - 0x00707070, 0x00717171, 0x00727272, 0x00737373, 0x00747474, 0x00757575, 0x00767676, 0x00777777, - 0x00787878, 0x00797979, 0x007a7a7a, 0x007b7b7b, 0x007c7c7c, 0x007d7d7d, 0x007e7e7e, 0x007f7f7f, - 0x00808080, 0x00818181, 0x00828282, 0x00838383, 0x00848484, 0x00858585, 0x00868686, 0x00878787, - 0x00888888, 0x00898989, 0x008a8a8a, 0x008b8b8b, 0x008c8c8c, 0x008d8d8d, 0x008e8e8e, 0x008f8f8f, - 0x00909090, 0x00919191, 0x00929292, 0x00939393, 0x00949494, 0x00959595, 0x00969696, 0x00979797, - 0x00989898, 0x00999999, 0x009a9a9a, 0x009b9b9b, 0x009c9c9c, 0x009d9d9d, 0x009e9e9e, 0x009f9f9f, - 0x00a0a0a0, 0x00a1a1a1, 0x00a2a2a2, 0x00a3a3a3, 0x00a4a4a4, 0x00a5a5a5, 0x00a6a6a6, 0x00a7a7a7, - 0x00a8a8a8, 0x00a9a9a9, 0x00aaaaaa, 0x00ababab, 0x00acacac, 0x00adadad, 0x00aeaeae, 0x00afafaf, - 0x00b0b0b0, 0x00b1b1b1, 0x00b2b2b2, 0x00b3b3b3, 0x00b4b4b4, 0x00b5b5b5, 0x00b6b6b6, 0x00b7b7b7, - 0x00b8b8b8, 0x00b9b9b9, 0x00bababa, 0x00bbbbbb, 0x00bcbcbc, 0x00bdbdbd, 0x00bebebe, 0x00bfbfbf, - 0x00c0c0c0, 0x00c1c1c1, 0x00c2c2c2, 0x00c3c3c3, 0x00c4c4c4, 0x00c5c5c5, 0x00c6c6c6, 0x00c7c7c7, - 0x00c8c8c8, 0x00c9c9c9, 0x00cacaca, 0x00cbcbcb, 0x00cccccc, 0x00cdcdcd, 0x00cecece, 0x00cfcfcf, - 0x00d0d0d0, 0x00d1d1d1, 0x00d2d2d2, 0x00d3d3d3, 0x00d4d4d4, 0x00d5d5d5, 0x00d6d6d6, 0x00d7d7d7, - 0x00d8d8d8, 0x00d9d9d9, 0x00dadada, 0x00dbdbdb, 0x00dcdcdc, 0x00dddddd, 0x00dedede, 0x00dfdfdf, - 0x00e0e0e0, 0x00e1e1e1, 0x00e2e2e2, 0x00e3e3e3, 0x00e4e4e4, 0x00e5e5e5, 0x00e6e6e6, 0x00e7e7e7, - 0x00e8e8e8, 0x00e9e9e9, 0x00eaeaea, 0x00ebebeb, 0x00ececec, 0x00ededed, 0x00eeeeee, 0x00efefef, - 0x00f0f0f0, 0x00f1f1f1, 0x00f2f2f2, 0x00f3f3f3, 0x00f4f4f4, 0x00f5f5f5, 0x00f6f6f6, 0x00f7f7f7, - 0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff, -}; - -#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS) - -/* scaler Timing */ -//1920*1080*60 - -#define S_OUT_CLK SCALE_RATE(148500000,74250000) //m=16 n=9 no=4 -#define S_H_PW 48 -#define S_H_BP 98 -#define S_H_VD 1280 -#define S_H_FP 59 - -#define S_V_PW 6 -#define S_V_BP 25 -#define S_V_VD 800 -#define S_V_FP 2 - -#define S_H_ST 0 -#define S_V_ST 13 - -//1920*1080*50 -#define S1_OUT_CLK SCALE_RATE(148500000,57375000) //m=17 n=11 no=4 -#define S1_H_PW 10 -#define S1_H_BP 10 -#define S1_H_VD 1280 -#define S1_H_FP 77 - -#define S1_V_PW 10 -#define S1_V_BP 10 -#define S1_V_VD 800 -#define S1_V_FP 13 - -#define S1_H_ST 0 -#define S1_V_ST 13 - -//1280*720*60 -#define S2_OUT_CLK SCALE_RATE(74250000,74250000) //m=32 n=9 no=4 -#define S2_H_PW 48 -#define S2_H_BP 98 -#define S2_H_VD 1280 -#define S2_H_FP 59 - -#define S2_V_PW 6 -#define S2_V_BP 5 -#define S2_V_VD 800 -#define S2_V_FP 2 - -#define S2_H_ST 0 -#define S2_V_ST 15 - -//1280*720*50 - -#define S3_OUT_CLK SCALE_RATE(74250000,67500000) // m=34 n=11 no=4 -#define S3_H_PW 48 -#define S3_H_BP 233 -#define S3_H_VD 1280 -#define S3_H_FP 59 - -#define S3_V_PW 6 -#define S3_V_BP 5 -#define S3_V_VD 800 -#define S3_V_FP 2 - -#define S3_H_ST 0 -#define S3_V_ST 15 - -//720*576*50 -#define S4_OUT_CLK SCALE_RATE(27000000,70312500) //m=75 n=4 no=8 -#define S4_H_PW 48 -#define S4_H_BP 233 -#define S4_H_VD 1280 -#define S4_H_FP 59 - -#define S4_V_PW 9 -#define S4_V_BP 57 -#define S4_V_VD 800 -#define S4_V_FP 2 - -#define S4_H_ST 90 -#define S4_V_ST 2 - -//720*480*60 -#define S5_OUT_CLK SCALE_RATE(27000000,75000000) //m=100 n=9 no=4 -#define S5_H_PW 48 -#define S5_H_BP 86 -#define S5_H_VD 1280 -#define S5_H_FP 16 - -#define S5_V_PW 9 -#define S5_V_BP 35 -#define S5_V_VD 800 -#define S5_V_FP 30 - -#define S5_H_ST 476 -#define S5_V_ST 12 - -#define S_DCLK_POL 1 - - -static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution) -{ - screen->s_clk_inv = S_DCLK_POL; - screen->s_den_inv = 0; - screen->s_hv_sync_inv = 0; - switch(hdmi_resolution){ - case HDMI_1920x1080p_60Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S_OUT_CLK; - screen->s_hsync_len = S_H_PW; - screen->s_left_margin = S_H_BP; - screen->s_right_margin = S_H_FP; - screen->s_hsync_len = S_H_PW; - screen->s_upper_margin = S_V_BP; - screen->s_lower_margin = S_V_FP; - screen->s_vsync_len = S_V_PW; - screen->s_hsync_st = S_H_ST; - screen->s_vsync_st = S_V_ST; - break; - case HDMI_1920x1080p_50Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S1_OUT_CLK; - screen->s_hsync_len = S1_H_PW; - screen->s_left_margin = S1_H_BP; - screen->s_right_margin = S1_H_FP; - screen->s_hsync_len = S1_H_PW; - screen->s_upper_margin = S1_V_BP; - screen->s_lower_margin = S1_V_FP; - screen->s_vsync_len = S1_V_PW; - screen->s_hsync_st = S1_H_ST; - screen->s_vsync_st = S1_V_ST; - break; - case HDMI_1280x720p_60Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S2_OUT_CLK; - screen->s_hsync_len = S2_H_PW; - screen->s_left_margin = S2_H_BP; - screen->s_right_margin = S2_H_FP; - screen->s_hsync_len = S2_H_PW; - screen->s_upper_margin = S2_V_BP; - screen->s_lower_margin = S2_V_FP; - screen->s_vsync_len = S2_V_PW; - screen->s_hsync_st = S2_H_ST; - screen->s_vsync_st = S2_V_ST; - break; - case HDMI_1280x720p_50Hz: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S3_OUT_CLK; - screen->s_hsync_len = S3_H_PW; - screen->s_left_margin = S3_H_BP; - screen->s_right_margin = S3_H_FP; - screen->s_hsync_len = S3_H_PW; - screen->s_upper_margin = S3_V_BP; - screen->s_lower_margin = S3_V_FP; - screen->s_vsync_len = S3_V_PW; - screen->s_hsync_st = S3_H_ST; - screen->s_vsync_st = S3_V_ST; - break; - case HDMI_720x576p_50Hz_4_3: - case HDMI_720x576p_50Hz_16_9: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S4_OUT_CLK; - screen->s_hsync_len = S4_H_PW; - screen->s_left_margin = S4_H_BP; - screen->s_right_margin = S4_H_FP; - screen->s_hsync_len = S4_H_PW; - screen->s_upper_margin = S4_V_BP; - screen->s_lower_margin = S4_V_FP; - screen->s_vsync_len = S4_V_PW; - screen->s_hsync_st = S4_H_ST; - screen->s_vsync_st = S4_V_ST; - break; - case HDMI_720x480p_60Hz_16_9: - case HDMI_720x480p_60Hz_4_3: - /* Scaler Timing */ - screen->hdmi_resolution = hdmi_resolution; - screen->s_pixclock = S5_OUT_CLK; - screen->s_hsync_len = S5_H_PW; - screen->s_left_margin = S5_H_BP; - screen->s_right_margin = S5_H_FP; - screen->s_hsync_len = S5_H_PW; - screen->s_upper_margin = S5_V_BP; - screen->s_lower_margin = S5_V_FP; - screen->s_vsync_len = S5_V_PW; - screen->s_hsync_st = S5_H_ST; - screen->s_vsync_st = S5_V_ST; - break; - default : - printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution); - return -1; - break; - } - - return 0; -} -#else -#define set_scaler_info NULL -#endif - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->face = OUT_FACE; - screen->type = OUT_TYPE; -#ifdef CONFIG_RK610_LVDS - screen->hw_format = OUT_FORMAT; -#endif - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = HSYNC_POL; - screen->pin_vsync = VSYNC_POL; - screen->pin_den = DEN_POL; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = SWAP_RG; - screen->swap_gb = SWAP_GB; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; - screen->dsp_lut = dsp_lut; - screen->sscreen_get = set_scaler_info; -#ifdef CONFIG_RK610_LVDS - screen->sscreen_set = rk610_lcd_scaler_set_param; -#endif -} - -size_t get_fb_size(void) -{ - size_t size = 0; - #if defined(CONFIG_THREE_FB_BUFFER) - size = ((H_VD)*(V_VD)<<2)* 3; //three buffer - #else - size = ((H_VD)*(V_VD)<<2)<<1; //two buffer - #endif - return ALIGN(size,SZ_1M); -} diff --git a/drivers/video/display/screen/lcd_hh070d_lvds.c b/drivers/video/display/screen/lcd_hh070d_lvds.c deleted file mode 100755 index 9e8683593751..000000000000 --- a/drivers/video/display/screen/lcd_hh070d_lvds.c +++ /dev/null @@ -1,77 +0,0 @@ -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include "screen.h" - -/* Base */ -#define OUT_TYPE SCREEN_LVDS -#define OUT_FORMAT 1//LVDS_8BIT_2 - -#define OUT_FACE OUT_D888_P666 -#define OUT_CLK 60000000 -#define LCDC_ACLK 300000000//500000000//312000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 100 -#define H_BP 100 -#define H_VD 1024 -#define H_FP 120 - -#define V_PW 10 -#define V_BP 10 -#define V_VD 600 -#define V_FP 150 - -#define LCD_WIDTH 202 -#define LCD_HEIGHT 152 -/* Other */ -#define DCLK_POL 1 -#define SWAP_RB 0 - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - screen->hw_format = OUT_FORMAT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; -} - - - diff --git a/drivers/video/display/screen/lcd_hj050na_06a.c b/drivers/video/display/screen/lcd_hj050na_06a.c deleted file mode 100644 index c651649db90b..000000000000 --- a/drivers/video/display/screen/lcd_hj050na_06a.c +++ /dev/null @@ -1,420 +0,0 @@ -/* - * Copyright (C) 2012 ROCKCHIP, Inc. - * - * author: hhb@rock-chips.com - * creat date: 2012-04-19 - * route:drivers/video/display/screen/lcd_hj050na_06a.c - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include -#include -#include -#include -#include -#include -#include - - -/* Base */ -#define OUT_TYPE SCREEN_RGB - -#define OUT_FACE OUT_D888_P666// OUT_D888_P666 //OUT_P888 - - -#define OUT_CLK 50000000 //50MHz -#define LCDC_ACLK 300000000 //29 lcdc axi DMA - -/* Timing */ -#define H_PW 5 -#define H_BP 50 -#define H_VD 640 -#define H_FP 130 - -#define V_PW 3 -#define V_BP 20//23 -#define V_VD 960 -#define V_FP 12 - -#define LCD_WIDTH 71 //uint mm the lenth of lcd active area -#define LCD_HEIGHT 106 -/* Other */ -#define DCLK_POL 0 -#define SWAP_RB 0 - - -#define CONFIG_DEEP_STANDBY_MODE 0 - - -/* define spi write command and data interface function */ - -#define SIMULATION_SPI 1 -#ifdef SIMULATION_SPI - - #define TXD_PORT gLcd_info->txd_pin - #define CLK_PORT gLcd_info->clk_pin - #define CS_PORT gLcd_info->cs_pin - #define LCD_RST_PORT gLcd_info->reset_pin - - #define CS_OUT() gpio_direction_output(CS_PORT, 0) - #define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) - #define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) - #define CLK_OUT() gpio_direction_output(CLK_PORT, 0) - #define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) - #define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) - #define TXD_OUT() gpio_direction_output(TXD_PORT, 0) - #define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) - #define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) - #define LCD_RST_OUT() gpio_direction_output(LCD_RST_PORT, 0) - #define LCD_RST(i) gpio_set_value(LCD_RST_PORT, i) - - #define bits_9 - #ifdef bits_9 //9bits - #define Write_ADDR(cmd) spi_write_9bit(0, cmd) - #define Write_DATA(dat) spi_write_9bit(0x100, dat) - #else //16bits - #define Write_ADDR(cmd) spi_write_16bit(0, cmd) - #define Write_DATA(dat) spi_write_16bit(1, dat) - #endif - #define Lcd_EnvidOnOff(i) - -#else - - #define bits_9 1 - #ifdef bits_9 //9bits - #define LCDSPI_InitCMD(cmd) - #define LCDSPI_InitDAT(dat) - #else //16bits - #define LCDSPI_InitCMD(cmd) - #define LCDSPI_InitDAT(dat) - #endif - -#endif - - -static struct rk29lcd_info *gLcd_info = NULL; -int lcd_init(void); -int lcd_standby(u8 enable); - - -/* spi write a data frame,type mean command or data */ -int spi_write_9bit(u32 type, u32 value) -{ -// if(type != 0 && type != 1) -// return -1; - /*make a data frame of 9 bits,the 8th bit 0:mean command,1:mean data*/ - value &= 0xff; - value |= type; - type = 9; - CS_CLR(); - //udelay(2); - while(type--) { - CLK_CLR(); - if(value & 0x100) - TXD_SET(); - else - TXD_CLR(); - value <<= 1; - //udelay(2); - CLK_SET(); - //udelay(2); - } - CS_SET(); - TXD_SET(); - - return 0; -} - - -int lcd_init(void) -{ - if(gLcd_info) - gLcd_info->io_init(); - - printk("lcd hj050a_06a...\n"); -#if 1 - gpio_direction_output(LCD_RST_PORT, 0); - usleep_range(2*1000, 3*1000); - gpio_set_value(LCD_RST_PORT, 1); - usleep_range(7*1000, 7*1000); -#endif - - Write_ADDR(0x0001); // Software Reset - msleep(10); - - Write_ADDR(0x0011); // Sleep Out - msleep(60); - -//<<<<<<<<<<<<<<>>>>>>>>>>>>>> - Write_ADDR(0x00B0); //Manufacture Command Access Protect - Write_DATA(0x0004); - -//<<<<<<<<<<<>>>>>>>>>>>> - Write_ADDR(0x00B3); //Number of Source outputs & Pixel Format setting - Write_DATA(0x0000); //PSEL[2:0] = 640 RGB - -//<<<<<<<<<<<>>>>>>>>>>>>>>>> - Write_ADDR(0x00B6); - Write_DATA(0x0052); - Write_DATA(0x0083); - Write_DATA(0x0045); - Write_DATA(0x0000); - -//<<<<<<<<<<<>>>>>>>>>>> - Write_ADDR(0x00B8); //Back Light Control(1) - Write_DATA(0x0000); //P1: CABCON = 0; - Write_DATA(0x001A); //P2: SSD_THRE = 1A; - Write_DATA(0x0018); //P3: SD_THRE = 18; - Write_DATA(0x0002); //P4: IPK_INTPO = 02; - Write_DATA(0x0040); //P5: IPK_TRANS = 40; - - Write_ADDR(0x00BB); //Back Light Control(1) - Write_DATA(0x0000); //LEDPWME[3] = 1,PWMWM[1] = 0,PWMON[0] = 0; - Write_DATA(0x00FF); //BDCV = FF; - Write_DATA(0x0001); //PWMDIC=1 - -//<<<<<<<<<<<>>>>>>>>>>> - Write_ADDR(0x00C0); //PANEL DRIVING SETTING 1 (36h=00) - Write_DATA(0x000B); //BLREV[5:4];REV[3];UD[2]=0:forward;BGR[1]=1:RGB->BGR;SS=1:S1920->S1 - Write_DATA(0x00BF); //NL[7:0] NL = 3BF : 960 Line - Write_DATA(0x0003); //NL[10:8] - Write_DATA(0x0011); //VBP[5:0] Vertical back porch - Write_DATA(0x0002); //DIV[3:0] - Write_DATA(0x0009); //PCDIVL[4:0] PCLKD Low Period - Write_DATA(0x0009); //PCDIVH[4:0] PCLKD High Period - - Write_ADDR(0x00C1); //PANEL DRIVING SETTING 2 - Write_DATA(0x0000); //GDS_MODE = 0 : GIP Ctrl(single scan) - Write_DATA(0x0010); //LINEINV[6:4]:2 Line inversion; MFPOL[1]:No Phase inversion; PNSER[0]:Spatial mode1 - Write_DATA(0x0004); //SEQMODE[7]:Source Pre-charge Mode; SEQGND[3:0]: GND Pre-charge 3clk - Write_DATA(0x0088); //SEQVN[7:4]:VCL pre-charge 2clk ;SEQVP[3:0]:VCL pre-charge 2clk - Write_DATA(0x001B); //DPM[7:6]: ;GEQ2W[5:3]/GEQ1W[2:0]:Gate pre-charge - Write_DATA(0x0001); //SDT[5:0] = 8 : Source output delay - Write_DATA(0x0060); //PSEUDO_EN = 0; - Write_DATA(0x0001); //GEM - - Write_ADDR(0x00C3); //PANEL DRIVING SETTING 4 - Write_DATA(0x0000); //GIPPAT[6:4]:Pattern-1 ; GIPMOD[2:0]: GIP mode 1 - Write_DATA(0x0000); //STPEOFF:normal ; FWBWOFF:normal ; T_GALH:normal - Write_DATA(0x0021); //GSPF[5:0]: 33clk - Write_DATA(0x0021); //GSPS[5:0]: 33clk - Write_DATA(0x0000); //VFSTEN[7]: NO END Pulse ; VFST[4:0]: 0 line - Write_DATA(0x0060); //FL1[6]: ; GLOL[5:4]: ; VGSET[3]: ; GIPSIDE=0:Single drive mode ; GOVERSEL=0:Overlap ; GIPSEL=0:8-phase clk - Write_DATA(0x0003); //VBPEX[6]: ; STVG[5:3]: ; STVGA[2:0]: - Write_DATA(0x0000); //ACBF[7:6]: ; ACF[5:4]: ; ACBR[3:2]: ; ACR[1:0]: - Write_DATA(0x0000); //ACBF2[7:6]: ; ACF2[5:4]: ; ACBR2[3:2]: ; ACR2[1:0]: - Write_DATA(0x0090); //9xH ACCYC[3:2]: ; ACFIX[1;0]: - Write_DATA(0x001D); //GOFF_L[7:0] - Write_DATA(0x00FE); //GOFF_L[15:8] - Write_DATA(0x0003); //GOFF_L[17:16] - Write_DATA(0x001D); //GOFF_R[7:0] - Write_DATA(0x00FE); //GOFF_R[15:8] - Write_DATA(0x0003); //GOFF_R[17:16] - -//<<<<<<<<<>>>>>>>>> - Write_ADDR(0x00C7); //TCON Unusual Operation Setting - Write_DATA(0x0000); //P1: - Write_DATA(0x0000); //P2: - Write_DATA(0x0000); //P3: - Write_DATA(0x0000); //P4: - Write_DATA(0x0000); //P5: - Write_DATA(0x0000); //P6: - Write_DATA(0x0000); //P7: - Write_DATA(0x0000); //P8: - Write_DATA(0x0000); //P9: - Write_DATA(0x0000); //P10: - Write_DATA(0x0000); //P11: - Write_DATA(0x0000); //P12: - Write_DATA(0x0000); //P13: - Write_DATA(0x0000); //P14: - -//<<<<<<<<<>>>>>>>>> - Write_ADDR(0x00C8); //Gamma Setting - Write_DATA(0x0003); - Write_DATA(0x000F); - Write_DATA(0x0015); - Write_DATA(0x0018); - Write_DATA(0x001A); - Write_DATA(0x0023); - Write_DATA(0x0025); - Write_DATA(0x0024); - Write_DATA(0x0021); - Write_DATA(0x001E); - Write_DATA(0x0015); - Write_DATA(0x000A); - - Write_DATA(0x0003); - Write_DATA(0x000F); - Write_DATA(0x0015); - Write_DATA(0x0018); - Write_DATA(0x001A); - Write_DATA(0x0023); - Write_DATA(0x0025); - Write_DATA(0x0024); - Write_DATA(0x0021); - Write_DATA(0x001E); - Write_DATA(0x0015); - Write_DATA(0x000A); - -//<<<<<<<<<>>>>>>>>> - Write_ADDR(0x00C9); //COLOR ENHANCEMENT SETTING - Write_DATA(0x0000); //CE_ON = 0; - Write_DATA(0x0080); - Write_DATA(0x0080); - Write_DATA(0x0080); - Write_DATA(0x0080); - Write_DATA(0x0080); - Write_DATA(0x0080); - Write_DATA(0x0080); - Write_DATA(0x0080); - Write_DATA(0x0000); - Write_DATA(0x0000); - Write_DATA(0x0002); - Write_DATA(0x0080); - -//<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>> - Write_ADDR(0x00D0); //POWER SETTING(CHARGE PUMP) - Write_DATA(0x0054); //P1:VC1 = 7; DC23 = 4 - Write_DATA(0x0019); //P2:BT3 = 2; BT2 = 1 09 - Write_DATA(0x00DD); //P3:VLMT1M = D; VLMT1 = D - Write_DATA(0x0016); //P4:VC3 = B; VC2 =B 3B - Write_DATA(0x0092); //P5:VLMT2B = 0; VLMT2 = 0A - Write_DATA(0x00A1); //P6:VLMT3B = 0; VLMT3 = 0F A1 - Write_DATA(0x0000); //P7:VBSON = 0; VBS = 00 - Write_DATA(0x00C0); //P8:VGGON = 0; LVGLON = 0; VC6 = 0 - Write_DATA(0x00CC); //P9:DC56 = ? - - Write_ADDR(0x00D1); //POWER SETTING(SWITCHING REGULATOR) - Write_DATA(0x004D); //P1:VDF1 = 4; VDF0 = D - Write_DATA(0x0024); //P2:DC1CLKEN = 0; DC1MCLKEN = 0; VDF2 =4 - Write_DATA(0x0034); //P3:VDWS2 = 3; VDWS1 = 4 - Write_DATA(0x0055); //P4:VDW12 = 5; VDW11 = 5 - Write_DATA(0x0055); //P5:VDW14 = 5; VDW13 = 5 - Write_DATA(0x0077); //P6:VDW22 = 7; VDW21 = 7 - Write_DATA(0x0077); //P7:VDW24 = 7; VDW23 = 7 - Write_DATA(0x0006); //P8:LSWPH = 6 - -//<<<<<<<<<<<<<<>>>>>>>>>>>>>> - Write_ADDR(0x00D5); //VPLVL/VNLVL SETTING - Write_DATA(0x0020); //P1:PVH = 24 - Write_DATA(0x0020); //P2:NVH = 24 - -//<<<<<<<<<<<<<<>>>>>>>>>>>>>>> - Write_ADDR(0x00D6); - Write_DATA(0x00A8); - -//<<<<<<<<<<<<<<>>>>>>>>>>>>>> - Write_ADDR(0x00DE); //VCOMDC SETTING - Write_DATA(0x0003); //P1:WCVDCB.[1] = 1; WCVDCF.[0] = 1 - Write_DATA(0x005A); //P2:VDCF.[7:0] = ? //57 - Write_DATA(0x005A); //P3:VDCB.[7:0] = ? //57 - - -//<<<<<<<<<<<<<<>>>>>>>>>>>>>> - Write_ADDR(0x00B0); //MANUFACTURE COMMAND ACCESS PROTECT - Write_DATA(0x0003); // - msleep(17); - - Write_ADDR(0x0036); // - Write_DATA(0x0000); // - msleep(17); - Write_ADDR(0x003A); // - Write_DATA(0x0060); // - msleep(17); - Write_ADDR(0x0029); // - - if(gLcd_info) - gLcd_info->io_deinit(); - - return 0; - -} - - - -int lcd_standby(u8 enable) -{ - if(enable) { - if(gLcd_info) - gLcd_info->io_init(); - printk("lcd_standby...\n"); - Write_ADDR(0x0028); //set Display Off - Write_ADDR(0x0010); //enter sleep mode - msleep(50); //wait at least 3 frames time -#if 1 - Write_ADDR(0x00b0); - Write_DATA(0x0004); - Write_ADDR(0x00b1); - Write_DATA(0x0001); - msleep(1); //wait at least 1ms - gpio_direction_output(LCD_RST_PORT, 0); -#endif - - if(gLcd_info) - gLcd_info->io_deinit(); - - } else { - lcd_init(); - } - - return 0; -} - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = lcd_init; - screen->standby = lcd_standby; - - if(lcd_info) - gLcd_info = lcd_info; - - if(LCD_RST_PORT){ - if (gpio_request(LCD_RST_PORT, NULL) != 0) { - gpio_free(LCD_RST_PORT); - printk("%s: request LCD_RST_PORT error\n", __func__); - } - } -} diff --git a/drivers/video/display/screen/lcd_hj080na.c b/drivers/video/display/screen/lcd_hj080na.c deleted file mode 100755 index 103f5ffcf2bd..000000000000 --- a/drivers/video/display/screen/lcd_hj080na.c +++ /dev/null @@ -1,76 +0,0 @@ -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include "screen.h" - - -/* Base */ -#define OUT_TYPE SCREEN_RGB - -#define OUT_FACE OUT_P888 -#define OUT_CLK 65000000 -#define LCDC_ACLK 500000000//312000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 100 -#define H_BP 100 -#define H_VD 1024 -#define H_FP 120 - -#define V_PW 10 -#define V_BP 10 -#define V_VD 768 -#define V_FP 15 - -#define LCD_WIDTH 216 -#define LCD_HEIGHT 162 -/* Other */ -#define DCLK_POL 0 -#define SWAP_RB 0 - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; -} - - - diff --git a/drivers/video/display/screen/lcd_hj101na.c b/drivers/video/display/screen/lcd_hj101na.c deleted file mode 100644 index 7c96027a89b7..000000000000 --- a/drivers/video/display/screen/lcd_hj101na.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * This Lcd Driver is for BYD 5' LCD BM800480-8545FTGE. - * written by Michael Lin, 2010-06-18 - */ - -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include "screen.h" - - -/* Base */ -#define OUT_TYPE SCREEN_RGB -#define OUT_FACE OUT_P888 -#define OUT_CLK 71000000 -#define LCDC_ACLK 300000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 10 -#define H_BP 160 -#define H_VD 1280 -#define H_FP 16 - -#define V_PW 3 -#define V_BP 23 -#define V_VD 800 -#define V_FP 12 - - -/* Other */ -#define DCLK_POL 0 -#define SWAP_RB 0 - -#define LCD_WIDTH 216 //need modify -#define LCD_HEIGHT 135 - -static struct rk29lcd_info *gLcd_info = NULL; - -#define DRVDelayUs(i) udelay(i*2) - -static int init(void); -static int standby(u8 enable); - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - /*screen->init = init;*/ - screen->init = NULL; - screen->standby = standby; -} - -size_t get_fb_size(void) -{ - size_t size = 0; - #if defined(CONFIG_THREE_FB_BUFFER) - size = ((H_VD)*(V_VD)<<2)* 3; //three buffer - #else - size = ((H_VD)*(V_VD)<<2)<<1; //two buffer - #endif - return ALIGN(size,SZ_1M); -} -static int standby(u8 enable) -{ - printk(KERN_INFO "byd1024x600 lcd standby, enable=%d\n", enable); - if (enable) - { - //rockchip_mux_api_set(LED_CON_IOMUX_PINNAME, LED_CON_IOMUX_PINDIR); - //GPIOSetPinDirection(LED_CON_IOPIN,GPIO_OUT); - //GPIOSetPinLevel(LED_CON_IOPIN,GPIO_HIGH); -// gpio_set_value(LCD_DISP_ON_IOPIN, GPIO_LOW); - } - else - { - //rockchip_mux_api_set(LED_CON_IOMUX_PINNAME, 1); -// gpio_set_value(LCD_DISP_ON_IOPIN, GPIO_HIGH); - } - return 0; -} - diff --git a/drivers/video/display/screen/lcd_hl070vm4.c b/drivers/video/display/screen/lcd_hl070vm4.c deleted file mode 100644 index 6c2953395517..000000000000 --- a/drivers/video/display/screen/lcd_hl070vm4.c +++ /dev/null @@ -1,206 +0,0 @@ - -#include -#include -#include -#include -#include - - -/* Base */ -#define OUT_TYPE SCREEN_RGB -#define OUT_FACE OUT_P888 -#define OUT_CLK 27000000 -#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 10 -#define H_BP 206 -#define H_VD 800 -#define H_FP 40 - -#define V_PW 10 -#define V_BP 25 -#define V_VD 480 -#define V_FP 10 - - -#define LCD_WIDTH 800 //need modify -#define LCD_HEIGHT 480 - -/* Other */ -#define DCLK_POL 1 ///0 -#define SWAP_RB 0 - -#define TXD_PORT gLcd_info->txd_pin -#define CLK_PORT gLcd_info->clk_pin -#define CS_PORT gLcd_info->cs_pin - -#define CS_OUT() gpio_direction_output(CS_PORT, 0) -#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) -#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) -#define CLK_OUT() gpio_direction_output(CLK_PORT, 0) -#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) -#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) -#define TXD_OUT() gpio_direction_output(TXD_PORT, 0) -#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) -#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) - -static struct rk29lcd_info *gLcd_info = NULL; - -#define DRVDelayUs(i) udelay(i*2) - -int init(void); -int standby(u8 enable); - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = init; - screen->standby = standby; - if(lcd_info) - gLcd_info = lcd_info; -} - - -//void spi_screenreg_set(uint32 Addr, uint32 Data) -void spi_screenreg_set(u32 Data) -{ - u32 i; - TXD_OUT(); - CLK_OUT(); - CS_OUT(); - DRVDelayUs(2); - DRVDelayUs(2); - - CS_SET(); - TXD_SET(); - CLK_SET(); - DRVDelayUs(2); - - CS_CLR(); - for(i = 0; i < 16; i++) //reg - { - if(Data &(1<<(15-i))) - TXD_SET(); - else - TXD_CLR(); - - // \u6a21\u62dfCLK - CLK_CLR(); - DRVDelayUs(2); - CLK_SET(); - DRVDelayUs(2); - } - -/* - TXD_CLR(); //write - - // \u6a21\u62dfCLK - CLK_CLR(); - DRVDelayUs(2); - CLK_SET(); - DRVDelayUs(2); - - TXD_SET(); //highz - - // \u6a21\u62dfCLK - CLK_CLR(); - DRVDelayUs(2); - CLK_SET(); - DRVDelayUs(2); - - - //for(i = 0; i < 8; i++) //data - for(i = 0; i < 16; i++) - { - if(Data &(1<<(15-i))) - TXD_SET(); - else - TXD_CLR(); - - // \u6a21\u62dfCLK - CLK_CLR(); - DRVDelayUs(2); - CLK_SET(); - DRVDelayUs(2); - } -*/ - CS_SET(); - CLK_CLR(); - TXD_CLR(); - DRVDelayUs(2); - -} - - -int init(void) -{ - if(gLcd_info) - gLcd_info->io_init(); -/* -r0 00000010 11011011 -r1 00010001 01101111 -r2 00100000 10000000 -r3 00110000 00001000 -r4 01000001 10010000-->>01000001 10011111 -r5 01100001 11001110 -*/ - spi_screenreg_set(0x02db); - spi_screenreg_set(0x116f); - spi_screenreg_set(0x2080); - spi_screenreg_set(0x3008); - spi_screenreg_set(0x419f); - spi_screenreg_set(0x61ce); - if(gLcd_info) - gLcd_info->io_deinit(); - return 0; -} - -int standby(u8 enable) -{ - if(gLcd_info) - gLcd_info->io_init(); - if(!enable) { - init(); - } //else { -// spi_screenreg_set(0x03, 0x5f); -// } - if(gLcd_info) - gLcd_info->io_deinit(); - return 0; -} - diff --git a/drivers/video/display/screen/lcd_hsd100pxn.c b/drivers/video/display/screen/lcd_hsd100pxn.c old mode 100755 new mode 100644 diff --git a/drivers/video/display/screen/lcd_hsd100pxn_for_tdw851.c b/drivers/video/display/screen/lcd_hsd100pxn_for_tdw851.c deleted file mode 100644 index c69d1b3d3e6b..000000000000 --- a/drivers/video/display/screen/lcd_hsd100pxn_for_tdw851.c +++ /dev/null @@ -1,323 +0,0 @@ -/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */ -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include "screen.h" - -/* Base */ -#define OUT_TYPE SCREEN_RGB -#define OUT_FACE OUT_P888//OUT_D888_P666 //OUT_D888_P565 -#define OUT_CLK 24000000 -#define LCDC_ACLK 456000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 10 -#define H_BP 10 -#define H_VD 480 -#define H_FP 12 - -#define V_PW 4 -#define V_BP 4 -#define V_VD 800 -#define V_FP 8 - -/* Other */ -#define DCLK_POL 1 -#define SWAP_RB 0 - -#define LCD_WIDTH 68//800 //need modify -#define LCD_HEIGHT 112//480 - -static struct rk29lcd_info *gLcd_info = NULL; - -#define TXD_PORT gLcd_info->txd_pin -#define CLK_PORT gLcd_info->clk_pin -#define CS_PORT gLcd_info->cs_pin -#define RST_PORT gLcd_info->reset_pin - - -#define CS_OUT() gpio_direction_output(CS_PORT, 1) -#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) -#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) - -#define CLK_OUT() gpio_direction_output(CLK_PORT, 0) -#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) -#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) - -#define TXD_OUT() gpio_direction_output(TXD_PORT, 1) -#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) -#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) - -#define RST_OUT() gpio_direction_output(RST_PORT, 1) -#define RST_SET() gpio_set_value(RST_PORT, GPIO_HIGH) -#define RST_CLR() gpio_set_value(RST_PORT, GPIO_LOW) - -#define UDELAY_TIME 1 -#define MDELAY_TIME 120 -void Spi_Write_index(unsigned char index) -{ - int j; - CS_CLR(); - TXD_CLR(); //0 - udelay(UDELAY_TIME); - - CLK_CLR(); - udelay(3);// - - CLK_SET(); - udelay(UDELAY_TIME); - - TXD_CLR(); - CLK_CLR(); - - for(j=0;j<8;j++) - { - if(index&0x80) - { - TXD_SET(); - } - else - { - TXD_CLR(); - } - index<<=1; - - CLK_CLR(); - udelay(UDELAY_TIME); - CLK_SET(); - udelay(UDELAY_TIME); - } - CS_SET(); -} - -void Spi_Write_data(unsigned char data) -{ - int j; - CS_CLR(); - TXD_SET(); - udelay(UDELAY_TIME); - - CLK_CLR(); - udelay(3); - - CLK_SET(); - udelay(UDELAY_TIME); - - TXD_CLR(); - CLK_CLR(); - - for(j=0;j<8;j++) - { - if(data&0x80) - { - TXD_SET(); - } - else - { - TXD_CLR(); - } - data<<=1; - - CLK_CLR(); - udelay(UDELAY_TIME); - CLK_SET(); - udelay(UDELAY_TIME); - } - CS_SET(); -} - -void Lcd_WriteSpi_initial3(void) //HX8363A+IVO 20111128 canshu -{ - //FOR IVO5.2 + HX8363-A - //Set_EXTC - printk("Lcd_WriteSpi_initial3-------------\n"); - Spi_Write_index(0xB9); - Spi_Write_data(0xFF); - Spi_Write_data(0x83); - Spi_Write_data(0x63); - - //Set_VCOM - Spi_Write_index(0xB6); - Spi_Write_data(0x27);//09 - - - //Set_POWER - Spi_Write_index(0xB1); - Spi_Write_data(0x81); - Spi_Write_data(0x30); - Spi_Write_data(0x07);//04 - Spi_Write_data(0x33); - Spi_Write_data(0x02); - Spi_Write_data(0x13); - Spi_Write_data(0x11); - Spi_Write_data(0x00); - Spi_Write_data(0x24); - Spi_Write_data(0x2B); - Spi_Write_data(0x3F); - Spi_Write_data(0x3F); - - Spi_Write_index(0xBf); // - Spi_Write_data(0x00); - Spi_Write_data(0x10); - - //Sleep Out - Spi_Write_index(0x11); - mdelay(MDELAY_TIME); - - - //Set COLMOD - Spi_Write_index(0x3A); - Spi_Write_data(0x70); - - - //Set_RGBIF - Spi_Write_index(0xB3); - Spi_Write_data(0x01); - - - //Set_CYC - Spi_Write_index(0xB4); - Spi_Write_data(0x08); - Spi_Write_data(0x16); - Spi_Write_data(0x5C); - Spi_Write_data(0x0B); - Spi_Write_data(0x01); - Spi_Write_data(0x1E); - Spi_Write_data(0x7B); - Spi_Write_data(0x01); - Spi_Write_data(0x4D); - - //Set_PANEL - Spi_Write_index(0xCC); - //Spi_Write_data(0x01); - Spi_Write_data(0x09); - mdelay(5); - - - //Set Gamma 2.2 - Spi_Write_index(0xE0); - Spi_Write_data(0x00); - Spi_Write_data(0x1E); - Spi_Write_data(0x63); - Spi_Write_data(0x15); - Spi_Write_data(0x11); - Spi_Write_data(0x30); - Spi_Write_data(0x0C); - Spi_Write_data(0x8F); - Spi_Write_data(0x8F); - Spi_Write_data(0x15); - Spi_Write_data(0x17); - Spi_Write_data(0xD5); - Spi_Write_data(0x56); - Spi_Write_data(0x0e); - Spi_Write_data(0x15); - Spi_Write_data(0x00); - Spi_Write_data(0x1E); - Spi_Write_data(0x63); - Spi_Write_data(0x15); - Spi_Write_data(0x11); - Spi_Write_data(0x30); - Spi_Write_data(0x0C); - Spi_Write_data(0x8F); - Spi_Write_data(0x8F); - Spi_Write_data(0x15); - Spi_Write_data(0x17); - Spi_Write_data(0xD5); - Spi_Write_data(0x56); - Spi_Write_data(0x0e); - Spi_Write_data(0x15); - mdelay(5); - - //Display On - Spi_Write_index(0x29); - Spi_Write_index(0x2c); -} - - -static int init(void) -{ - if(gLcd_info) - gLcd_info->io_init(); - - TXD_OUT(); - CLK_OUT(); - CS_OUT(); - - RST_CLR(); - CS_SET(); - CLK_SET(); - - mdelay(5); - RST_SET(); - mdelay(2); - - Lcd_WriteSpi_initial3(); - - return 0; -} -static int deinit(void) -{ - Spi_Write_index(0x10); - if(gLcd_info) - gLcd_info->io_deinit(); - return 0; - -} -static int standby(u8 enable) -{ - if(!enable) - init(); - else - deinit(); - return 0; -} - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - printk("%s\n",__func__); - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin= H_FP; - screen->hsync_len = H_PW; - screen->upper_margin= V_BP; - screen->lower_margin= V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - /*screen->init = init;*/ - screen->init = init; - screen->standby = standby; - if(lcd_info) - gLcd_info = lcd_info; -} - - diff --git a/drivers/video/display/screen/lcd_hsd800x480.c b/drivers/video/display/screen/lcd_hsd800x480.c deleted file mode 100644 index b55cd3fb707e..000000000000 --- a/drivers/video/display/screen/lcd_hsd800x480.c +++ /dev/null @@ -1,246 +0,0 @@ -/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */ -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include "screen.h" - - -/* Base */ -#define OUT_TYPE SCREEN_RGB -#define OUT_FACE OUT_P888 -#define OUT_CLK 33000000 -#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 8 //10 -#define H_BP 88 //100 -#define H_VD 800 //1024 -#define H_FP 40 //210 - -#define V_PW 3 //10 -#define V_BP 10 //10 -#define V_VD 480 //768 -#define V_FP 32 //18 - -/* Other */ -#define DCLK_POL 0 -#define SWAP_RB 0 - -#define LCD_WIDTH 154 //need modify -#define LCD_HEIGHT 85 - -#define TXD_PORT gLcd_info->txd_pin -#define CLK_PORT gLcd_info->clk_pin -#define CS_PORT gLcd_info->cs_pin - -#define CS_OUT() gpio_direction_output(CS_PORT, 0) -#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) -#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) -#define CLK_OUT() gpio_direction_output(CLK_PORT, 0) -#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) -#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) -#define TXD_OUT() gpio_direction_output(TXD_PORT, 0) -#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) -#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) - -static struct rk29lcd_info *gLcd_info = NULL; - -#define DRVDelayUs(i) udelay(i*2) - -int init(void); -int standby(u8 enable); - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - /*screen->init = init;*/ - screen->init = NULL; - screen->standby = standby; - if(lcd_info) - gLcd_info = lcd_info; -} -//cannot need init,so set screen->init = null at rk29_fb.c file - -void spi_screenreg_set(u32 Addr, u32 Data) -{ - u32 i; - - TXD_OUT(); - CLK_OUT(); - CS_OUT(); - DRVDelayUs(2); - DRVDelayUs(2); - - CS_SET(); - TXD_SET(); - CLK_SET(); - DRVDelayUs(2); - - CS_CLR(); - for(i = 0; i < 6; i++) //reg - { - if(Addr &(1<<(5-i))) - TXD_SET(); - else - TXD_CLR(); - - // \u6a21\u62dfCLK - CLK_CLR(); - DRVDelayUs(2); - CLK_SET(); - DRVDelayUs(2); - } - - TXD_CLR(); //write - - // \u6a21\u62dfCLK - CLK_CLR(); - DRVDelayUs(2); - CLK_SET(); - DRVDelayUs(2); - - TXD_SET(); //highz - - // \u6a21\u62dfCLK - CLK_CLR(); - DRVDelayUs(2); - CLK_SET(); - DRVDelayUs(2); - - - for(i = 0; i < 8; i++) //data - { - if(Data &(1<<(7-i))) - TXD_SET(); - else - TXD_CLR(); - - // \u6a21\u62dfCLK - CLK_CLR(); - DRVDelayUs(2); - CLK_SET(); - DRVDelayUs(2); - } - - CS_SET(); - CLK_CLR(); - TXD_CLR(); - DRVDelayUs(2); - -} - - -int init(void) -{ - if(gLcd_info) - gLcd_info->io_init(); - - spi_screenreg_set(0x02, 0x07); - spi_screenreg_set(0x03, 0x5f); - spi_screenreg_set(0x04, 0x17); - spi_screenreg_set(0x05, 0x20); - spi_screenreg_set(0x06, 0x08); - spi_screenreg_set(0x07, 0x20); - spi_screenreg_set(0x08, 0x20); - spi_screenreg_set(0x09, 0x20); - spi_screenreg_set(0x0a, 0x20); - spi_screenreg_set(0x0b, 0x22); - spi_screenreg_set(0x0c, 0x22); - spi_screenreg_set(0x0d, 0x22); - spi_screenreg_set(0x0e, 0x10); - spi_screenreg_set(0x0f, 0x10); - spi_screenreg_set(0x10, 0x10); - - spi_screenreg_set(0x11, 0x15); - spi_screenreg_set(0x12, 0xAA); - spi_screenreg_set(0x13, 0xFF); - spi_screenreg_set(0x14, 0xb0); - spi_screenreg_set(0x15, 0x8e); - spi_screenreg_set(0x16, 0xd6); - spi_screenreg_set(0x17, 0xfe); - spi_screenreg_set(0x18, 0x28); - spi_screenreg_set(0x19, 0x52); - spi_screenreg_set(0x1A, 0x7c); - - spi_screenreg_set(0x1B, 0xe9); - spi_screenreg_set(0x1C, 0x42); - spi_screenreg_set(0x1D, 0x88); - spi_screenreg_set(0x1E, 0xb8); - spi_screenreg_set(0x1F, 0xFF); - spi_screenreg_set(0x20, 0xF0); - spi_screenreg_set(0x21, 0xF0); - spi_screenreg_set(0x22, 0x09); - - if(gLcd_info) - gLcd_info->io_deinit(); - return 0; -} - -int standby(u8 enable) -{ -#if 1 - if(gLcd_info) - gLcd_info->io_init(); - if(enable) { - spi_screenreg_set(0x03, 0xde); - } else { - spi_screenreg_set(0x03, 0x5f); - } - if(gLcd_info) - gLcd_info->io_deinit(); -#else - - GPIOSetPinDirection(GPIOPortB_Pin3, GPIO_OUT); - GPIOSetPinDirection(GPIOPortB_Pin2, GPIO_OUT); - - if(enable) - { - GPIOSetPinLevel(GPIOPortB_Pin3, GPIO_LOW); - GPIOSetPinLevel(GPIOPortB_Pin2, GPIO_HIGH); - } - else - { - GPIOSetPinLevel(GPIOPortB_Pin3, GPIO_HIGH); - GPIOSetPinLevel(GPIOPortB_Pin2, GPIO_LOW); - } -#endif - return 0; -} - diff --git a/drivers/video/display/screen/lcd_hv070wsa.c b/drivers/video/display/screen/lcd_hv070wsa.c deleted file mode 100755 index b13c20ffcfc3..000000000000 --- a/drivers/video/display/screen/lcd_hv070wsa.c +++ /dev/null @@ -1,76 +0,0 @@ -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include "screen.h" - - -/* Base */ -#define OUT_TYPE SCREEN_RGB - -#define OUT_FACE OUT_P888 -#define OUT_CLK 50000000 -#define LCDC_ACLK 500000000//312000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 100 -#define H_BP 100 -#define H_VD 1024 -#define H_FP 120 - -#define V_PW 10 -#define V_BP 10 -#define V_VD 600 -#define V_FP 15 - -#define LCD_WIDTH 202 -#define LCD_HEIGHT 152 -/* Other */ -#define DCLK_POL 0 -#define SWAP_RB 0 - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; -} - - - diff --git a/drivers/video/display/screen/lcd_hx8357.c b/drivers/video/display/screen/lcd_hx8357.c deleted file mode 100644 index 463ae0b5552a..000000000000 --- a/drivers/video/display/screen/lcd_hx8357.c +++ /dev/null @@ -1,401 +0,0 @@ -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include "screen.h" - - -/* Base */ -#define OUT_TYPE SCREEN_RGB -#define OUT_FACE OUT_P666 /*OUT_P888*/ -#define OUT_CLK 10000000 //***27 -#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 8 -#define H_BP 6 -#define H_VD 320 //***800 -#define H_FP 60 - -#define V_PW 12 -#define V_BP 4 -#define V_VD 480 //***480 -#define V_FP 40 - -#define LCD_WIDTH 320 //need modify -#define LCD_HEIGHT 480 - -/* Other */ -#define DCLK_POL 0 -#define SWAP_RB 0 - -static struct rk29lcd_info *gLcd_info = NULL; -int init(void); -int standby(u8 enable); - - -#define TXD_PORT gLcd_info->txd_pin -#define CLK_PORT gLcd_info->clk_pin -#define CS_PORT gLcd_info->cs_pin - -#define CS_OUT() gpio_direction_output(CS_PORT, 0) -#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) -#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) -#define CLK_OUT() gpio_direction_output(CLK_PORT, 0) -#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) -#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) -#define TXD_OUT() gpio_direction_output(TXD_PORT, 0) -#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) -#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) - -#if 0 -static void screen_set_iomux(u8 enable) -{ - int ret=-1; - if(enable) - { - rk29_mux_api_set(GPIOH6_IQ_SEL_NAME, 0); - ret = gpio_request(RK29_PIN_PH6, NULL); - if(0)//(ret != 0) - { - gpio_free(RK29_PIN_PH6); - printk(">>>>>> lcd cs gpio_request err \n "); - goto pin_err; - } - - rk29_mux_api_set(GPIOE_I2C0_SEL_NAME, 1); - - ret = gpio_request(RK29_PIN_PE5, NULL); - if(0)//(ret != 0) - { - gpio_free(RK29_PIN_PE5); - printk(">>>>>> lcd clk gpio_request err \n "); - goto pin_err; - } - - ret = gpio_request(RK29_PIN_PE4, NULL); - if(0)//(ret != 0) - { - gpio_free(RK29_PIN_PE4); - printk(">>>>>> lcd txd gpio_request err \n "); - goto pin_err; - } - } - else - { - gpio_free(RK29_PIN_PH6); - // rk29_mux_api_set(CXGPIO_HSADC_SEL_NAME, 1); - - gpio_free(RK29_PIN_PE5); - gpio_free(RK29_PIN_PE4); - rk29_mux_api_set(GPIOE_I2C0_SEL_NAME, 0); - } - return ; -pin_err: - return ; - -} -#endif - -void spi_screenreg_set(u32 Addr, u32 Data) -{ -#define DRVDelayUs(i) udelay(i*2) - - u32 i; - u32 control_bit; - - - TXD_OUT(); - CLK_OUT(); - CS_OUT(); - DRVDelayUs(2); - DRVDelayUs(2); - - CS_SET(); - TXD_SET(); - CLK_SET(); - DRVDelayUs(2); - - CS_CLR(); - control_bit = 0x70<<8; - Addr = (control_bit | Addr); - //printk("addr is 0x%x \n", Addr); - for(i = 0; i < 16; i++) //reg - { - if(Addr &(1<<(15-i))) - TXD_SET(); - else - TXD_CLR(); - - // \u6a21\u62dfCLK - CLK_CLR(); - DRVDelayUs(2); - CLK_SET(); - DRVDelayUs(2); - } - - CS_SET(); - TXD_SET(); - CLK_SET(); - DRVDelayUs(2); - CS_CLR(); - - control_bit = 0x72<<8; - Data = (control_bit | Data); - //printk("data is 0x%x \n", Data); - for(i = 0; i < 16; i++) //data - { - if(Data &(1<<(15-i))) - TXD_SET(); - else - TXD_CLR(); - - // \u6a21\u62dfCLK - CLK_CLR(); - DRVDelayUs(2); - CLK_SET(); - DRVDelayUs(2); - } - - CS_SET(); - CLK_CLR(); - TXD_CLR(); - DRVDelayUs(2); -} - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - //printk("lcd_hx8357 set_lcd_info \n"); - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; /*>2*/ - screen->right_margin = H_FP; /*>2*/ - screen->hsync_len = H_PW; /*>2*/ //***all > 326, 4upper_margin = V_BP; /*>2*/ - screen->lower_margin = V_FP; /*>2*/ - screen->vsync_len = V_PW; /*>6*/ - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = init; - screen->standby = standby; - if(lcd_info) - gLcd_info = lcd_info; -} - -int init(void) -{ - - if(gLcd_info) - gLcd_info->io_init(); - -#if 0 //***Õâ¾ä´úÂëÊDz»ÊÇд´íÁË - spi_screenreg_set(0x02, 0x07); - spi_screenreg_set(0x03, 0x5f); - spi_screenreg_set(0x04, 0x17); - spi_screenreg_set(0x05, 0x20); - spi_screenreg_set(0x06, 0x08); - spi_screenreg_set(0x07, 0x20); - spi_screenreg_set(0x08, 0x20); - spi_screenreg_set(0x09, 0x20); - spi_screenreg_set(0x0a, 0x20); - spi_screenreg_set(0x0b, 0x22); - spi_screenreg_set(0x0c, 0x22); - spi_screenreg_set(0x0d, 0x22); - spi_screenreg_set(0x0e, 0x10); - spi_screenreg_set(0x0f, 0x10); - spi_screenreg_set(0x10, 0x10); - - spi_screenreg_set(0x11, 0x15); - spi_screenreg_set(0x12, 0xAA); - spi_screenreg_set(0x13, 0xFF); - spi_screenreg_set(0x14, 0xb0); - spi_screenreg_set(0x15, 0x8e); - spi_screenreg_set(0x16, 0xd6); - spi_screenreg_set(0x17, 0xfe); - spi_screenreg_set(0x18, 0x28); - spi_screenreg_set(0x19, 0x52); - spi_screenreg_set(0x1A, 0x7c); - - spi_screenreg_set(0x1B, 0xe9); - spi_screenreg_set(0x1C, 0x42); - spi_screenreg_set(0x1D, 0x88); - spi_screenreg_set(0x1E, 0xb8); - spi_screenreg_set(0x1F, 0xFF); - spi_screenreg_set(0x20, 0xF0); - spi_screenreg_set(0x21, 0xF0); - spi_screenreg_set(0x22, 0x09); -#else - spi_screenreg_set(0xff, 0x00); - spi_screenreg_set(0x16, 0x08); - spi_screenreg_set(0x01, 0x02); - spi_screenreg_set(0xe2, 0x00); - spi_screenreg_set(0xe3, 0x00); - spi_screenreg_set(0xf2, 0x00); - spi_screenreg_set(0xe4, 0x1c); - spi_screenreg_set(0xe5, 0x1c); - spi_screenreg_set(0xe6, 0x00); - spi_screenreg_set(0xe7, 0x1c); - - spi_screenreg_set(0x19, 0x01); - mdelay(10); - spi_screenreg_set(0x2a, 0x00); - spi_screenreg_set(0x2b, 0x13); - spi_screenreg_set(0x2f, 0x01); - spi_screenreg_set(0x02, 0x00); - spi_screenreg_set(0x03, 0x00); - spi_screenreg_set(0x04, 0x01); - spi_screenreg_set(0x05, 0x3f); - spi_screenreg_set(0x06, 0x00); - spi_screenreg_set(0x07, 0x00); - - spi_screenreg_set(0x08, 0x01); - spi_screenreg_set(0x09, 0xdf); - spi_screenreg_set(0x24, 0x91); - spi_screenreg_set(0x25, 0x8a); - spi_screenreg_set(0x29, 0x01); - spi_screenreg_set(0x18, 0x22); - spi_screenreg_set(0x1b, 0x30); - mdelay(10); - spi_screenreg_set(0x1d, 0x22); - mdelay(10); - spi_screenreg_set(0x40, 0x00); - spi_screenreg_set(0x41, 0x3c); - spi_screenreg_set(0x42, 0x38); - spi_screenreg_set(0x43, 0x34); - spi_screenreg_set(0x44, 0x2e); - spi_screenreg_set(0x45, 0x2f); - spi_screenreg_set(0x46, 0x41); - spi_screenreg_set(0x47, 0x7d); - spi_screenreg_set(0x48, 0x0b); - spi_screenreg_set(0x49, 0x05); - spi_screenreg_set(0x4a, 0x06); - spi_screenreg_set(0x4b, 0x12); - spi_screenreg_set(0x4c, 0x16); - spi_screenreg_set(0x50, 0x10); - spi_screenreg_set(0x51, 0x11); - spi_screenreg_set(0x52, 0x0b); - spi_screenreg_set(0x53, 0x07); - spi_screenreg_set(0x54, 0x03); - spi_screenreg_set(0x55, 0x3f); - spi_screenreg_set(0x56, 0x02); - spi_screenreg_set(0x57, 0x3e); - spi_screenreg_set(0x58, 0x09); - spi_screenreg_set(0x59, 0x0d); - spi_screenreg_set(0x5a, 0x19); - spi_screenreg_set(0x5b, 0x1a); - spi_screenreg_set(0x5c, 0x14); - spi_screenreg_set(0x5d, 0xc0); - spi_screenreg_set(0x1a, 0x05); - mdelay(10); - - spi_screenreg_set(0x1c, 0x03); - mdelay(10); - spi_screenreg_set(0x1f, 0x90); - mdelay(10); - spi_screenreg_set(0x1f, 0xd2); - mdelay(10); - spi_screenreg_set(0x28, 0x04); - mdelay(40); - spi_screenreg_set(0x28, 0x38); - mdelay(40); - spi_screenreg_set(0x28, 0x3c); - mdelay(40); - spi_screenreg_set(0x80, 0x00); - spi_screenreg_set(0x81, 0x00); - spi_screenreg_set(0x82, 0x00); - spi_screenreg_set(0x83, 0x00); - - spi_screenreg_set(0x60, 0x08); - spi_screenreg_set(0x31, 0x02); - spi_screenreg_set(0x32, 0x08 /*0x00*/); - spi_screenreg_set(0x17, 0x60); //***RGB666 - spi_screenreg_set(0x2d, 0x1f); - spi_screenreg_set(0xe8, 0x90); -#endif - if(gLcd_info) - gLcd_info->io_deinit(); - - return 0; -} - -int standby(u8 enable) //***enable =1 means suspend, 0 means resume -{ - - if(gLcd_info) - gLcd_info->io_init(); - if(enable) { - //printk("---------hx8357 screen suspend--------------\n"); - #if 0 - spi_screenreg_set(0x03, 0xde); - #else - //modify by robert - #if 0 - spi_screenreg_set(0x1f, 0x91); - spi_screenreg_set(0x19, 0x00); - #else - spi_screenreg_set(0x28, 0x38); - msleep(10); - spi_screenreg_set(0x28, 0x24); - msleep(10); - spi_screenreg_set(0x28, 0x04); - #endif - //modify end - #endif - } else { - //printk("--------- hx8357 screen resume--------------\n "); - #if 0 - spi_screenreg_set(0x03, 0x5f); - #else - //modify by robert - #if 0 - spi_screenreg_set(0x19, 0x01); - spi_screenreg_set(0x1f, 0x90); - mdelay(10); - spi_screenreg_set(0x1f, 0xd2); - #else - spi_screenreg_set(0x28, 0x38); - msleep(10); - spi_screenreg_set(0x28, 0x3c); - msleep(10); - spi_screenreg_set(0x80, 0x00); - spi_screenreg_set(0x81, 0x00); - spi_screenreg_set(0x82, 0x00); - spi_screenreg_set(0x83, 0x00); - - #endif - //modify end - #endif - } - - if(gLcd_info) - gLcd_info->io_deinit(); - return 0; -} - diff --git a/drivers/video/display/screen/lcd_ili9803_cpt4_3.c b/drivers/video/display/screen/lcd_ili9803_cpt4_3.c deleted file mode 100755 index aba60562dbc3..000000000000 --- a/drivers/video/display/screen/lcd_ili9803_cpt4_3.c +++ /dev/null @@ -1,380 +0,0 @@ -/* - * Copyright (C) 2011 ROCKCHIP, Inc. - * - * author: hhb@rock-chips.com - * creat date: 2011-05-14 - * route:drivers/video/display/screen/lcd_ili9803_cpt4_3.c - driver for rk29 phone sdk or rk29 a22 - * station:haven been tested in a22 hardware platform - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - - - -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include "screen.h" - - -/* Base */ -#define OUT_TYPE SCREEN_RGB -#define OUT_FACE OUT_P666 -#define OUT_CLK 26000000 -#define LCDC_ACLK 150000000 //29 lcdc axi DMA - -/* Timing */ -#define H_PW 8 -#define H_BP 6 -#define H_VD 480 -#define H_FP 60 - -#define V_PW 2 -#define V_BP 12 -#define V_VD 800 -#define V_FP 4 - - -#define LCD_WIDTH 480 //need modify -#define LCD_HEIGHT 800 - -/* Other */ -#define DCLK_POL 1 -#define SWAP_RB 0 - - -/* define spi write command and data interface function */ - -#define SIMULATION_SPI 1 -#ifdef SIMULATION_SPI - - #define TXD_PORT gLcd_info->txd_pin - #define CLK_PORT gLcd_info->clk_pin - #define CS_PORT gLcd_info->cs_pin - #define LCD_RST_PORT RK29_PIN6_PC6 - - #define CS_OUT() gpio_direction_output(CS_PORT, 0) - #define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) - #define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) - #define CLK_OUT() gpio_direction_output(CLK_PORT, 0) - #define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) - #define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) - #define TXD_OUT() gpio_direction_output(TXD_PORT, 0) - #define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) - #define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) - #define LCD_RST_OUT() gpio_direction_output(LCD_RST_PORT, 0) - #define LCD_RST(i) gpio_set_value(LCD_RST_PORT, i) - - #define bits_9 - #ifdef bits_9 //9bits - - #define LCD_ILI9803_CMD(cmd) spi_write_9bit(0, cmd) - #define LCD_ILI9803_Parameter(dat) spi_write_9bit(1, dat) - #else //16bits - #define LCD_ILI9803_CMD(cmd) spi_write_16bit(0, cmd) - #define LCD_ILI9803_Parameter(dat) spi_write_16bit(1, dat) - #endif - #define Lcd_EnvidOnOff(i) - -#else - - #define bits_9 1 - #ifdef bits_9 //9bits - #define LCD_ILI9803_CMD(cmd) - #define LCD_ILI9803_Parameter(dat) - #else //16bits - #define LCD_ILI9803_CMD(cmd) - #define LCD_ILI9803_Parameter(dat) - #endif - -#endif - - -/* define lcd command */ -#define ENTER_SLEEP_MODE 0x10 -#define EXIT_SLEEP_MODE 0x11 -#define SET_COLUMN_ADDRESS 0x2a -#define SET_PAGE_ADDRESS 0x2b -#define WRITE_MEMORY_START 0x2c -#define SET_DISPLAY_ON 0x29 -#define SET_DISPLAY_OFF 0x28 -#define SET_ADDRESS_MODE 0x36 -#define SET_PIXEL_FORMAT 0x3a - - -#define DRVDelayUs(i) udelay(i*2) - -static struct rk29lcd_info *gLcd_info = NULL; -int lcd_init(void); -int lcd_standby(u8 enable); - - -/* spi write a data frame,type mean command or data */ -int spi_write_9bit(u32 type, u32 value) -{ - u32 i = 0; - - if(type != 0 && type != 1) - { - return -1; - } - /*make a data frame of 9 bits,the 8th bit 0:mean command,1:mean data*/ - value &= 0xff; - value |= (type << 8); -// if(0 == type){ - TXD_OUT(); - CLK_OUT(); - CS_OUT(); - DRVDelayUs(2); - DRVDelayUs(2); - CS_SET(); - TXD_SET(); - CLK_SET(); - DRVDelayUs(2); - CS_CLR(); -// } - - for(i = 0; i < 9; i++) //reg - { - - CLK_CLR(); - DRVDelayUs(2); - if(value & (1 << (8-i))) - { - TXD_SET(); - } - else - { - TXD_CLR(); - } - CLK_SET(); - DRVDelayUs(2); - } - -// if(0 == type){ - CS_SET(); - CLK_CLR(); - TXD_CLR(); -// } - - DRVDelayUs(2); - return 0; -} - - -int lcd_init(void) -{ - if(gLcd_info) - gLcd_info->io_init(); - printk("*****lcd_init...*****\n"); -/* reset lcd to start init lcd by software if there is no hardware reset circuit for the lcd */ -#ifdef LCD_RST_PORT - gpio_request(LCD_RST_PORT, NULL); - LCD_RST_OUT(); - LCD_RST(1); - msleep(1); - LCD_RST(0); - msleep(10); - LCD_RST(1); - msleep(120); - -#endif - - TXD_OUT(); - CLK_OUT(); - CS_OUT(); - CS_SET(); - TXD_SET(); - CLK_SET(); - - LCD_ILI9803_CMD(0xB1); - LCD_ILI9803_Parameter(0x00); - LCD_ILI9803_CMD(0xB2); - LCD_ILI9803_Parameter(0x10); - LCD_ILI9803_Parameter(0xC7); - LCD_ILI9803_CMD(0xB3); - LCD_ILI9803_Parameter(0x00); - LCD_ILI9803_CMD(0xB4); - LCD_ILI9803_Parameter(0x00); - LCD_ILI9803_CMD(0xB9); - LCD_ILI9803_Parameter(0x00); - LCD_ILI9803_CMD(0xC3); - LCD_ILI9803_Parameter(0x07); - LCD_ILI9803_CMD(0xB2); - LCD_ILI9803_Parameter(0x04); - LCD_ILI9803_Parameter(0x0B); - LCD_ILI9803_Parameter(0x0B); - LCD_ILI9803_Parameter(0x00); - LCD_ILI9803_Parameter(0x07); - LCD_ILI9803_Parameter(0x04); - LCD_ILI9803_CMD(0xC5); - LCD_ILI9803_Parameter(0x6E); - LCD_ILI9803_CMD(0xC2); - LCD_ILI9803_Parameter(0x20); - LCD_ILI9803_Parameter(0x00); - LCD_ILI9803_Parameter(0x10); - msleep(20); - LCD_ILI9803_CMD(0xC8); - LCD_ILI9803_Parameter(0xA3); - LCD_ILI9803_CMD(0xC9); - LCD_ILI9803_Parameter(0x32); - LCD_ILI9803_Parameter(0x06); - LCD_ILI9803_CMD(0xD7); - LCD_ILI9803_Parameter(0x03); - LCD_ILI9803_Parameter(0x00); - LCD_ILI9803_Parameter(0x0F); - LCD_ILI9803_Parameter(0x0F); - LCD_ILI9803_CMD(0xCF); - LCD_ILI9803_Parameter(0x00); - LCD_ILI9803_Parameter(0x08); - LCD_ILI9803_CMD(0xB6); - LCD_ILI9803_Parameter(0x20); - LCD_ILI9803_Parameter(0xC2); - LCD_ILI9803_Parameter(0xFF); - LCD_ILI9803_Parameter(0x04); - LCD_ILI9803_CMD(0xEA); - LCD_ILI9803_Parameter(0x00); - LCD_ILI9803_CMD(0x2A); - LCD_ILI9803_Parameter(0x00); - LCD_ILI9803_Parameter(0x00); - LCD_ILI9803_Parameter(0x01); - LCD_ILI9803_Parameter(0xDF); - LCD_ILI9803_CMD(0x2B); - LCD_ILI9803_Parameter(0x00); - LCD_ILI9803_Parameter(0x00); - LCD_ILI9803_Parameter(0x03); - LCD_ILI9803_Parameter(0xEF); - LCD_ILI9803_CMD(0xB0); - LCD_ILI9803_Parameter(0x01); - LCD_ILI9803_CMD(0x0C); - LCD_ILI9803_Parameter(0x50); - LCD_ILI9803_CMD(0x36); - LCD_ILI9803_Parameter(0x48); - LCD_ILI9803_CMD(0x3A); - LCD_ILI9803_Parameter(0x66); - LCD_ILI9803_CMD(0xE0); - LCD_ILI9803_Parameter(0x05); - LCD_ILI9803_Parameter(0x07); - LCD_ILI9803_Parameter(0x0B); - LCD_ILI9803_Parameter(0x14); - LCD_ILI9803_Parameter(0x11); - LCD_ILI9803_Parameter(0x14); - LCD_ILI9803_Parameter(0x0A); - LCD_ILI9803_Parameter(0x07); - LCD_ILI9803_Parameter(0x04); - LCD_ILI9803_Parameter(0x0B); - LCD_ILI9803_Parameter(0x02); - LCD_ILI9803_Parameter(0x00); - LCD_ILI9803_Parameter(0x04); - LCD_ILI9803_Parameter(0x33); - LCD_ILI9803_Parameter(0x36); - LCD_ILI9803_Parameter(0x1F); - LCD_ILI9803_CMD(0xE1); - LCD_ILI9803_Parameter(0x1F); - LCD_ILI9803_Parameter(0x36); - LCD_ILI9803_Parameter(0x33); - LCD_ILI9803_Parameter(0x04); - LCD_ILI9803_Parameter(0x00); - LCD_ILI9803_Parameter(0x02); - LCD_ILI9803_Parameter(0x0B); - LCD_ILI9803_Parameter(0x04); - LCD_ILI9803_Parameter(0x07); - LCD_ILI9803_Parameter(0x0A); - LCD_ILI9803_Parameter(0x14); - LCD_ILI9803_Parameter(0x11); - LCD_ILI9803_Parameter(0x14); - LCD_ILI9803_Parameter(0x0B); - LCD_ILI9803_Parameter(0x07); - LCD_ILI9803_Parameter(0x05); - LCD_ILI9803_CMD(EXIT_SLEEP_MODE); - msleep(70); - LCD_ILI9803_CMD(SET_DISPLAY_ON); - msleep(10); - LCD_ILI9803_CMD(WRITE_MEMORY_START); - - if(gLcd_info) - gLcd_info->io_deinit(); - - return 0; -} - -extern void rk29_lcd_spim_spin_lock(void); -extern void rk29_lcd_spim_spin_unlock(void); -int lcd_standby(u8 enable) -{ - rk29_lcd_spim_spin_lock(); - if(gLcd_info) - gLcd_info->io_init(); - - if(enable) { - LCD_ILI9803_CMD(ENTER_SLEEP_MODE); - msleep(150); - printk("lcd enter sleep mode\n"); - } else { - LCD_ILI9803_CMD(EXIT_SLEEP_MODE); - msleep(150); - printk("lcd exit sleep mode\n"); - } - - if(gLcd_info) - gLcd_info->io_deinit(); - rk29_lcd_spim_spin_unlock(); - - return 0; -} - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = lcd_init; - screen->standby = lcd_standby; - if(lcd_info) - gLcd_info = lcd_info; -} - - - diff --git a/drivers/video/display/screen/lcd_ips1p5680_v1_e.c b/drivers/video/display/screen/lcd_ips1p5680_v1_e.c deleted file mode 100644 index 4dafd4d5db69..000000000000 --- a/drivers/video/display/screen/lcd_ips1p5680_v1_e.c +++ /dev/null @@ -1,239 +0,0 @@ -/* - * Copyright (C) 2011 ROCKCHIP, Inc. - * - * author: hhb@rock-chips.com - * creat date: 2011-03-07 - * route:drivers/video/display/screen/lcd_ips1p5680_v1_e.c - driver for rk29 phone sdk - * station:haven't been tested in any hardware platform - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include "screen.h" - -/* Base */ -#define OUT_TYPE SCREEN_MCU -#define OUT_FACE OUT_P565 - -/* Timing */ -#define H_PW 1 -#define H_BP 1 -#define H_VD 320 -#define H_FP 5 - -#define V_PW 1 -#define V_BP 1 -#define V_VD 480 -#define V_FP 1 - -#define LCD_WIDTH 320 //need modify -#define LCD_HEIGHT 480 - -#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ - -#define P_WR 27 -#define USE_FMARK 0 //2 ÊÇ·ñʹÓÃFMK (0:²»Ö§³Ö 1:ºáÆÁÖ§³Ö 2:ºáÊúÆÁ¶ŒÖ§³Ö) -#define FRMRATE 60 //MCUÆÁµÄË¢ÐÂÂÊ (FMKÓÐЧʱÓÃ) - - -/* Other */ -#define DCLK_POL 0 -#define SWAP_RB 0 - - -/* define lcd command */ -#define ENTER_SLEEP_MODE 0x10 -#define EXIT_SLEEP_MODE 0x11 -#define SET_COLUMN_ADDRESS 0x2a -#define SET_PAGE_ADDRESS 0x2b -#define WRITE_MEMORY_START 0x2c -#define SET_DISPLAY_ON 0x29 -#define SET_DISPLAY_OFF 0x28 -#define SET_ADDRESS_MODE 0x36 -#define SET_PIXEL_FORMAT 0x3a - - -/* initialize the lcd registers to make it function noamally*/ - -int lcd_init(void) -{ - int i =0; - mcu_ioctl(MCU_SETBYPASS, 1); - msleep(5); - mcu_ioctl(MCU_WRCMD, SET_ADDRESS_MODE); //set address normal mode - mcu_ioctl(MCU_WRDATA, 0); - mcu_ioctl(MCU_WRCMD, SET_PIXEL_FORMAT); //set 16 bits per pixel - mcu_ioctl(MCU_WRDATA, 0x55); - mcu_ioctl(MCU_WRCMD, EXIT_SLEEP_MODE); //set lcd exit sleep mode,because the lcd is in sleep mode when power on - msleep(1000*6 / FRMRATE + 10); //wait for about 6 frames' time - mcu_ioctl(MCU_WRCMD, SET_DISPLAY_ON); //set display on - msleep(1000/FRMRATE); - - /*init lcd internal ram,so lcd won't display randomly*/ - mcu_ioctl(MCU_WRCMD, SET_COLUMN_ADDRESS); - mcu_ioctl(MCU_WRDATA, 0); - mcu_ioctl(MCU_WRDATA, 0); - mcu_ioctl(MCU_WRDATA, (LCD_WIDTH >> 8) & 0x0003); - mcu_ioctl(MCU_WRDATA, LCD_WIDTH & 0x00ff); - msleep(10); - mcu_ioctl(MCU_WRCMD, SET_PAGE_ADDRESS); - mcu_ioctl(MCU_WRDATA, 0); - mcu_ioctl(MCU_WRDATA, 0); - mcu_ioctl(MCU_WRDATA, (LCD_HEIGHT >> 8) & 0x0003); - mcu_ioctl(MCU_WRDATA, LCD_HEIGHT & 0x00ff); - msleep(10); - mcu_ioctl(MCU_WRCMD, WRITE_MEMORY_START); - - for(i = 0; i < LCD_WIDTH*LCD_HEIGHT; i++) - { - mcu_ioctl(MCU_WRDATA, 0x00000000); - } - - mcu_ioctl(MCU_SETBYPASS, 0); - return 0; -} - -/* set lcd to sleep mode or not */ - -int lcd_standby(u8 enable) -{ - mcu_ioctl(MCU_SETBYPASS, 1); - - if(enable) { - mcu_ioctl(MCU_WRCMD, ENTER_SLEEP_MODE); - } else { - mcu_ioctl(MCU_WRCMD, EXIT_SLEEP_MODE); - } - - mcu_ioctl(MCU_SETBYPASS, 0); - - return 0; -} - -/* set lcd to write memory mode, so the lcdc of RK29xx can send the fb content to the lcd internal ram in hold mode*/ - -int lcd_refresh(u8 arg) -{ - mcu_ioctl(MCU_SETBYPASS, 1); - - switch(arg) - { - case REFRESH_PRE: //start to write the image data to lcd ram - mcu_ioctl(MCU_WRCMD, SET_COLUMN_ADDRESS); //set - mcu_ioctl(MCU_WRDATA, 0); - mcu_ioctl(MCU_WRDATA, 0); - mcu_ioctl(MCU_WRDATA, (LCD_WIDTH >> 8) & 0x0003); - mcu_ioctl(MCU_WRDATA, LCD_WIDTH & 0x00ff); - msleep(10); - mcu_ioctl(MCU_WRCMD, SET_PAGE_ADDRESS); - mcu_ioctl(MCU_WRDATA, 0); - mcu_ioctl(MCU_WRDATA, 0); - mcu_ioctl(MCU_WRDATA, (LCD_HEIGHT >> 8) & 0x0003); - mcu_ioctl(MCU_WRDATA, LCD_HEIGHT & 0x00ff); - msleep(10); - mcu_ioctl(MCU_WRCMD, WRITE_MEMORY_START); - break; - - case REFRESH_END: //set display on - mcu_ioctl(MCU_WRCMD, SET_DISPLAY_ON); - break; - - default: - break; - } - - mcu_ioctl(MCU_SETBYPASS, 0); - - return 0; -} - - -/* not used */ - -int lcd_scandir(u16 dir) -{ - mcu_ioctl(MCU_SETBYPASS, 1); - -// mcu_ioctl(MCU_WRCMD, SET_DISPLAY_OFF); - - mcu_ioctl(MCU_SETBYPASS, 0); - return 0; -} - - -/* not used */ - -int lcd_disparea(u8 area) -{ - mcu_ioctl(MCU_SETBYPASS, 1); - mcu_ioctl(MCU_SETBYPASS, 0); - return (0); -} - - -/* set real information about lcd which we use in this harware platform */ - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - screen->mcu_wrperiod = P_WR; - screen->mcu_usefmk = USE_FMARK; - screen->mcu_frmrate = FRMRATE; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = lcd_init; - screen->standby = lcd_standby; - screen->scandir = lcd_scandir; - screen->refresh = lcd_refresh; - screen->disparea = lcd_disparea; -} - - - - - - diff --git a/drivers/video/display/screen/lcd_mcu_tft480800_25_e.c b/drivers/video/display/screen/lcd_mcu_tft480800_25_e.c deleted file mode 100644 index f88c493a184f..000000000000 --- a/drivers/video/display/screen/lcd_mcu_tft480800_25_e.c +++ /dev/null @@ -1,556 +0,0 @@ -/* - * Copyright (C) 2011 ROCKCHIP, Inc. - * - * author: hhb@rock-chips.com - * creat date: 2011-03-11 - * route:drivers/video/display/screen/lcd_mcu_tft480800_25_e.c - driver for rk29 phone sdk - * station:haven't been tested in any hardware platform - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include "screen.h" - -/* Base */ -#define OUT_TYPE SCREEN_MCU -#define OUT_FACE OUT_P888 - -/* Timing */ -#define H_PW 1 -#define H_BP 1 -#define H_VD 480 -#define H_FP 5 - -#define V_PW 1 -#define V_BP 1 -#define V_VD 800 -#define V_FP 1 - -#define LCD_WIDTH 480 //need modify -#define LCD_HEIGHT 800 - -#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ - -#define P_WR 27 -#define USE_FMARK 0 //2 ÊÇ·ñʹÓÃFMK (0:²»Ö§³Ö 1:ºáÆÁÖ§³Ö 2:ºáÊúÆÁ¶ŒÖ§³Ö) -#define FRMRATE 60 //MCUÆÁµÄË¢ÐÂÂÊ (FMKÓÐЧʱÓÃ) - - -/* Other */ -#define DCLK_POL 0 -#define SWAP_RB 0 - - -/* define lcd command */ -#define ENTER_SLEEP_MODE 0x10 -#define EXIT_SLEEP_MODE 0x11 -#define SET_COLUMN_ADDRESS 0x2a -#define SET_PAGE_ADDRESS 0x2b -#define WRITE_MEMORY_START 0x2c -#define SET_DISPLAY_ON 0x29 -#define SET_DISPLAY_OFF 0x28 -#define SET_ADDRESS_MODE 0x36 -#define SET_PIXEL_FORMAT 0x3a - - -#define WMLCDCOM(command) mcu_ioctl(MCU_WRCMD,command) -#define WMLCDDATA(data) mcu_ioctl(MCU_WRDATA,data) - - - - -/* initialize the lcd registers to make it function noamally*/ - -int lcd_init(void) -{ - int k = 0; - mcu_ioctl(MCU_SETBYPASS, 1); - -#if 1 //HX8369-A - - WMLCDCOM(0xB9); // SET password - WMLCDDATA(0xFF); - WMLCDDATA(0x83); - WMLCDDATA(0x69); - - WMLCDCOM(0xB0); //Enable internal oscillator - WMLCDDATA(0x01); - WMLCDDATA(0x0B); - - - WMLCDCOM(0xB1); //Set Power - WMLCDDATA(0x85); - WMLCDDATA(0x00); - WMLCDDATA(0x34); - WMLCDDATA(0x0A); - WMLCDDATA(0x00); - WMLCDDATA(0x0F); - WMLCDDATA(0x0F); - WMLCDDATA(0x2A); - WMLCDDATA(0x32); - WMLCDDATA(0x3F); - WMLCDDATA(0x3F); - WMLCDDATA(0x01); //update VBIAS - WMLCDDATA(0x23); - WMLCDDATA(0x01); - WMLCDDATA(0xE6); - WMLCDDATA(0xE6); - WMLCDDATA(0xE6); - WMLCDDATA(0xE6); - WMLCDDATA(0xE6); - - - WMLCDCOM(0xB2); // SET Display 480x800 - WMLCDDATA(0x00); - WMLCDDATA(0x20); - WMLCDDATA(0x05); - WMLCDDATA(0x05); - WMLCDDATA(0x70); //70 - WMLCDDATA(0x00); //00 - WMLCDDATA(0xFF); //FF - WMLCDDATA(0x00); - WMLCDDATA(0x00); - WMLCDDATA(0x00); - WMLCDDATA(0x00); //1 - WMLCDDATA(0x03); - WMLCDDATA(0x03); - WMLCDDATA(0x00); - WMLCDDATA(0x01); - - - - WMLCDCOM(0xB4); // SET Display 480x800 - WMLCDDATA(0x00); //00 - WMLCDDATA(0x18); //18 - WMLCDDATA(0x80); //80 - WMLCDDATA(0x06); - WMLCDDATA(0x02); - - WMLCDCOM(0xB6); // SET VCOM - WMLCDDATA(0x3A); // Update VCOM - WMLCDDATA(0x3A); - - - /************CABC test ***************/ - - WMLCDCOM(0X51);//Write Display Brightness - WMLCDDATA(0Xff);//DBV[7:0]=0XE4 - msleep(20); - - /* - WMLCDCOM(0XC9);//SETCABC - WMLCDDATA(0X5F);//PWM_DIV="110" PWM_CLK 64·ÖƵ INVPULS="1" - WMLCDDATA(0X7F);//WMLCDDATA(0X7F); - WMLCDDATA(0X20);//PWM_EPERIOD - WMLCDDATA(0X00);//SAVEPOWER[6:0] - WMLCDDATA(0X20);//DIM_FRAM[6:0] - WMLCDDATA(0X00);// - WMLCDDATA(0X03);//CABC_FLM - WMLCDDATA(0X20);// - msleep(20); - */ - - WMLCDCOM(0X53);//WRITE CTRL DISPLAY - WMLCDDATA(0X24);//WMLCDDATA(0X26) BCTRL="1" BL="1" DD="1"/"0" - msleep(20); - - WMLCDCOM(0X55); - WMLCDDATA(0X02);//STILL PICTURE - msleep(20); - - //WMLCDCOM(0X5E);//Write CABC minimum brightness (5Eh) - //WMLCDDATA(0X00);//CMB[7:0=0X00 - //msleep(20); - - - /***************************************/ - - WMLCDCOM(0x2A); //set window - WMLCDDATA(0x00); - WMLCDDATA(0x00); - WMLCDDATA(0x0); - WMLCDDATA(0xF0); - - WMLCDCOM(0x2B); - WMLCDDATA(0x00); - WMLCDDATA(0x00); - WMLCDDATA(0x01); - WMLCDDATA(0x40); - - WMLCDCOM(0xD5); //Set GIP - WMLCDDATA(0x00); - WMLCDDATA(0x04); - WMLCDDATA(0x03); - WMLCDDATA(0x00); - WMLCDDATA(0x01); - WMLCDDATA(0x05); - WMLCDDATA(0x28); - WMLCDDATA(0x70); - WMLCDDATA(0x01); - WMLCDDATA(0x03); - WMLCDDATA(0x00); - WMLCDDATA(0x00); - WMLCDDATA(0x40); - WMLCDDATA(0x06); - WMLCDDATA(0x51); - WMLCDDATA(0x07); - WMLCDDATA(0x00); - WMLCDDATA(0x00); - WMLCDDATA(0x41); - WMLCDDATA(0x06); - WMLCDDATA(0x50); - WMLCDDATA(0x07); - WMLCDDATA(0x07); - WMLCDDATA(0x0F); - WMLCDDATA(0x04); - WMLCDDATA(0x00); - - - //Gamma2.2 - WMLCDCOM(0xE0); - WMLCDDATA(0x00); - WMLCDDATA(0x13); - WMLCDDATA(0x19); - WMLCDDATA(0x38); - WMLCDDATA(0x3D); - WMLCDDATA(0x3F); - WMLCDDATA(0x28); - WMLCDDATA(0x46); - WMLCDDATA(0x07); - WMLCDDATA(0x0D); - WMLCDDATA(0x0E); - WMLCDDATA(0x12); - WMLCDDATA(0x15); - WMLCDDATA(0x12); - WMLCDDATA(0x14); - WMLCDDATA(0x0F); - WMLCDDATA(0x17); - WMLCDDATA(0x00); - WMLCDDATA(0x13); - WMLCDDATA(0x19); - WMLCDDATA(0x38); - WMLCDDATA(0x3D); - WMLCDDATA(0x3F); - WMLCDDATA(0x28); - WMLCDDATA(0x46); - WMLCDDATA(0x07); - WMLCDDATA(0x0D); - WMLCDDATA(0x0E); - WMLCDDATA(0x12); - WMLCDDATA(0x15); - WMLCDDATA(0x12); - WMLCDDATA(0x14); - WMLCDDATA(0x0F); - WMLCDDATA(0x17); - msleep(10); - - //DGC Setting - WMLCDCOM(0xC1); - WMLCDDATA(0x01); - - //R - WMLCDDATA(0x00); - WMLCDDATA(0x04); - WMLCDDATA(0x11); - WMLCDDATA(0x19); - WMLCDDATA(0x20); - WMLCDDATA(0x29); - WMLCDDATA(0x30); - WMLCDDATA(0x37); - WMLCDDATA(0x40); - WMLCDDATA(0x4A); - WMLCDDATA(0x52); - WMLCDDATA(0x59); - WMLCDDATA(0x60); - WMLCDDATA(0x68); - WMLCDDATA(0x70); - WMLCDDATA(0x79); - WMLCDDATA(0x81); - WMLCDDATA(0x89); - WMLCDDATA(0x91); - WMLCDDATA(0x99); - WMLCDDATA(0xA1); - WMLCDDATA(0xA8); - WMLCDDATA(0xB0); - WMLCDDATA(0xB8); - WMLCDDATA(0xC1); - WMLCDDATA(0xC9); - WMLCDDATA(0xD0); - WMLCDDATA(0xD8); - WMLCDDATA(0xE1); - WMLCDDATA(0xE8); - WMLCDDATA(0xF1); - WMLCDDATA(0xF8); - WMLCDDATA(0xFF); - WMLCDDATA(0x31); - WMLCDDATA(0x9C); - WMLCDDATA(0x57); - WMLCDDATA(0xED); - WMLCDDATA(0x57); - WMLCDDATA(0x7F); - WMLCDDATA(0x61); - WMLCDDATA(0xAD); - WMLCDDATA(0xC0); -//G - WMLCDDATA(0x00); - WMLCDDATA(0x04); - WMLCDDATA(0x11); - WMLCDDATA(0x19); - WMLCDDATA(0x20); - WMLCDDATA(0x29); - WMLCDDATA(0x30); - WMLCDDATA(0x37); - WMLCDDATA(0x40); - WMLCDDATA(0x4A); - WMLCDDATA(0x52); - WMLCDDATA(0x59); - WMLCDDATA(0x60); - WMLCDDATA(0x68); - WMLCDDATA(0x70); - WMLCDDATA(0x79); - WMLCDDATA(0x81); - WMLCDDATA(0x89); - WMLCDDATA(0x91); - WMLCDDATA(0x99); - WMLCDDATA(0xA1); - WMLCDDATA(0xA8); - WMLCDDATA(0xB0); - WMLCDDATA(0xB8); - WMLCDDATA(0xC1); - WMLCDDATA(0xC9); - WMLCDDATA(0xD0); - WMLCDDATA(0xD8); - WMLCDDATA(0xE1); - WMLCDDATA(0xE8); - WMLCDDATA(0xF1); - WMLCDDATA(0xF8); - WMLCDDATA(0xFF); - WMLCDDATA(0x31); - WMLCDDATA(0x9C); - WMLCDDATA(0x57); - WMLCDDATA(0xED); - WMLCDDATA(0x57); - WMLCDDATA(0x7F); - WMLCDDATA(0x61); - WMLCDDATA(0xAD); - WMLCDDATA(0xC0); - //B - WMLCDDATA(0x00); - WMLCDDATA(0x04); - WMLCDDATA(0x11); - WMLCDDATA(0x19); - WMLCDDATA(0x20); - WMLCDDATA(0x29); - WMLCDDATA(0x30); - WMLCDDATA(0x37); - WMLCDDATA(0x40); - WMLCDDATA(0x4A); - WMLCDDATA(0x52); - WMLCDDATA(0x59); - WMLCDDATA(0x60); - WMLCDDATA(0x68); - WMLCDDATA(0x70); - WMLCDDATA(0x79); - WMLCDDATA(0x81); - WMLCDDATA(0x89); - WMLCDDATA(0x91); - WMLCDDATA(0x99); - WMLCDDATA(0xA1); - WMLCDDATA(0xA8); - WMLCDDATA(0xB0); - WMLCDDATA(0xB8); - WMLCDDATA(0xC1); - WMLCDDATA(0xC9); - WMLCDDATA(0xD0); - WMLCDDATA(0xD8); - WMLCDDATA(0xE1); - WMLCDDATA(0xE8); - WMLCDDATA(0xF1); - WMLCDDATA(0xF8); - WMLCDDATA(0xFF); - WMLCDDATA(0x31); - WMLCDDATA(0x9C); - WMLCDDATA(0x57); - WMLCDDATA(0xED); - WMLCDDATA(0x57); - WMLCDDATA(0x7F); - WMLCDDATA(0x61); - WMLCDDATA(0xAD); - WMLCDDATA(0xC0); - WMLCDCOM(0x2D);//Look up table - - for(k = 0; k < 64; k++) //RED - { - WMLCDDATA(8*k); - } - for(k = 0; k < 64; k++) //GREEN - { - WMLCDDATA(4*k); - } - for(k = 0; k < 64; k++) //BLUE - { - WMLCDDATA(8*k); - } - - msleep(10); - WMLCDCOM(SET_PIXEL_FORMAT); //pixel format setting - WMLCDDATA(0x77); - - WMLCDCOM(EXIT_SLEEP_MODE); - msleep(120); - - WMLCDCOM(SET_DISPLAY_ON); //Display on - WMLCDCOM(WRITE_MEMORY_START); - -#endif - - mcu_ioctl(MCU_SETBYPASS, 0); - return 0; -} - -/* set lcd to sleep mode or not */ - -int lcd_standby(u8 enable) -{ - mcu_ioctl(MCU_SETBYPASS, 1); - - if(enable) { - mcu_ioctl(MCU_WRCMD, ENTER_SLEEP_MODE); - msleep(10); - } else { - mcu_ioctl(MCU_WRCMD, EXIT_SLEEP_MODE); - msleep(20); - } - - mcu_ioctl(MCU_SETBYPASS, 0); - - return 0; -} - -/* set lcd to write memory mode, so the lcdc of RK29xx can send the fb content to the lcd internal ram in hold mode*/ - -int lcd_refresh(u8 arg) -{ - mcu_ioctl(MCU_SETBYPASS, 1); - - switch(arg) - { - case REFRESH_PRE: //start to write the image data to lcd ram - mcu_ioctl(MCU_WRCMD, SET_COLUMN_ADDRESS); //set - mcu_ioctl(MCU_WRDATA, 0); - mcu_ioctl(MCU_WRDATA, 0); - mcu_ioctl(MCU_WRDATA, (LCD_WIDTH >> 8) & 0x00ff); - mcu_ioctl(MCU_WRDATA, LCD_WIDTH & 0x00ff); - msleep(1); - mcu_ioctl(MCU_WRCMD, SET_PAGE_ADDRESS); - mcu_ioctl(MCU_WRDATA, 0); - mcu_ioctl(MCU_WRDATA, 0); - mcu_ioctl(MCU_WRDATA, (LCD_HEIGHT >> 8) & 0x00ff); - mcu_ioctl(MCU_WRDATA, LCD_HEIGHT & 0x00ff); - msleep(1); - mcu_ioctl(MCU_WRCMD, WRITE_MEMORY_START); - break; - - case REFRESH_END: //set display on - mcu_ioctl(MCU_WRCMD, SET_DISPLAY_ON); - break; - - default: - break; - } - - mcu_ioctl(MCU_SETBYPASS, 0); - - return 0; -} - - -/* not used */ - -int lcd_scandir(u16 dir) -{ - mcu_ioctl(MCU_SETBYPASS, 1); - -// mcu_ioctl(MCU_WRCMD, SET_DISPLAY_OFF); - - mcu_ioctl(MCU_SETBYPASS, 0); - return 0; -} - - -/* not used */ - -int lcd_disparea(u8 area) -{ - mcu_ioctl(MCU_SETBYPASS, 1); - mcu_ioctl(MCU_SETBYPASS, 0); - return (0); -} - - -/* set real information about lcd which we use in this harware platform */ - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - screen->mcu_wrperiod = P_WR; - screen->mcu_usefmk = USE_FMARK; - screen->mcu_frmrate = FRMRATE; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = lcd_init; - screen->standby = lcd_standby; - screen->scandir = lcd_scandir; - screen->refresh = lcd_refresh; - screen->disparea = lcd_disparea; -} - - - - - - diff --git a/drivers/video/display/screen/lcd_nt35510.c b/drivers/video/display/screen/lcd_nt35510.c old mode 100755 new mode 100644 diff --git a/drivers/video/display/screen/lcd_nt35580.c b/drivers/video/display/screen/lcd_nt35580.c deleted file mode 100644 index 8fb8b8350f36..000000000000 --- a/drivers/video/display/screen/lcd_nt35580.c +++ /dev/null @@ -1,472 +0,0 @@ -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include "screen.h" - - -/* Base */ -#define OUT_TYPE SCREEN_RGB -#define OUT_FACE OUT_P888 -#define OUT_CLK 24000000 -#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 1 -#define H_BP 1 -#define H_VD 480 -#define H_FP 2 - -#define V_PW 1 -#define V_BP 4 -#define V_VD 800 -#define V_FP 2 - -#define LCD_WIDTH 480 //need modify -#define LCD_HEIGHT 800 - -/* Other */ -#define DCLK_POL 0 -#define SWAP_RB 0 - -#define TXD_PORT gLcd_info->txd_pin -#define CLK_PORT gLcd_info->clk_pin -#define CS_PORT gLcd_info->cs_pin - -#define CS_OUT() gpio_direction_output(CS_PORT, 0) -#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) -#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) -#define CLK_OUT() gpio_direction_output(CLK_PORT, 0) -#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) -#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) -#define TXD_OUT() gpio_direction_output(TXD_PORT, 0) -#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) -#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) -#define TXD_IN() gpio_direction_input(TXD_PORT) -#define TXD_GET() gpio_get_value(TXD_PORT) - - -#define delay_us(i) udelay(i) -static struct rk29lcd_info *gLcd_info = NULL; - -u32 spi_screenreg_get(u32 Addr) -{ - u32 i; - u8 addr_h = (Addr>>8) & 0x000000ff; - u8 addr_l = Addr & 0x000000ff; - u8 cmd1 = 0x20; //0010 0000 - u8 cmd2 = 0x00; //0000 0000 - u8 cmd3 = 0x00; //0000 0000 - - u8 data_l = 0; - u8 tmp; - - TXD_OUT(); - CLK_OUT(); - CS_OUT(); - delay_us(8); - - CS_SET(); - CLK_CLR(); - TXD_CLR(); - delay_us(4); - - // first transmit - CS_CLR(); - delay_us(4); - for(i = 0; i < 8; i++) - { - if(cmd1 &(1<<(7-i))) - TXD_SET(); - else - TXD_CLR(); - - CLK_CLR(); - delay_us(4); - CLK_SET(); - delay_us(4); - } - for(i = 0; i < 8; i++) - { - if(addr_h &(1<<(7-i))) - TXD_SET(); - else - TXD_CLR(); - - CLK_CLR(); - delay_us(4); - CLK_SET(); - delay_us(4); - } - CLK_CLR(); - TXD_CLR(); - delay_us(4); - CS_SET(); - delay_us(8); - - // second transmit - CS_CLR(); - delay_us(4); - for(i = 0; i < 8; i++) - { - if(cmd2 &(1<<(7-i))) - TXD_SET(); - else - TXD_CLR(); - - CLK_CLR(); - delay_us(4); - CLK_SET(); - delay_us(4); - } - for(i = 0; i < 8; i++) - { - if(addr_l &(1<<(7-i))) - TXD_SET(); - else - TXD_CLR(); - - CLK_CLR(); - delay_us(4); - CLK_SET(); - delay_us(4); - } - CLK_CLR(); - TXD_CLR(); - delay_us(4); - CS_SET(); - delay_us(8); - - // third transmit - CS_CLR(); - delay_us(4); - for(i = 0; i < 8; i++) - { - if(cmd3 &(1<<(7-i))) - TXD_SET(); - else - TXD_CLR(); - - CLK_CLR(); - delay_us(4); - CLK_SET(); - delay_us(4); - } - TXD_CLR(); - TXD_IN(); - for(i = 0; i < 8; i++) - { - CLK_CLR(); - delay_us(4); - CLK_SET(); - - tmp = TXD_GET(); - data_l += (tmp<<(7-i)); - - delay_us(4); - } - CLK_CLR(); - TXD_CLR(); - delay_us(4); - CS_SET(); - delay_us(8); - - return data_l; -} - - -void spi_screenreg_set(u32 Addr, u32 Data) -{ - u32 i; - u8 addr_h = (Addr>>8) & 0x000000ff; - u8 addr_l = Addr & 0x000000ff; - u8 data_l = Data & 0x000000ff; - u8 cmd1 = 0x20; //0010 0000 - u8 cmd2 = 0x00; //0000 0000 - u8 cmd3 = 0x40; //0100 0000 - - TXD_OUT(); - CLK_OUT(); - CS_OUT(); - delay_us(8); - - CS_SET(); - CLK_CLR(); - TXD_CLR(); - delay_us(4); - - // first transmit - CS_CLR(); - delay_us(4); - for(i = 0; i < 8; i++) - { - if(cmd1 &(1<<(7-i))) - TXD_SET(); - else - TXD_CLR(); - - CLK_CLR(); - delay_us(4); - CLK_SET(); - delay_us(4); - } - for(i = 0; i < 8; i++) - { - if(addr_h &(1<<(7-i))) - TXD_SET(); - else - TXD_CLR(); - - CLK_CLR(); - delay_us(4); - CLK_SET(); - delay_us(4); - } - CLK_CLR(); - TXD_CLR(); - delay_us(4); - CS_SET(); - delay_us(8); - - // second transmit - CS_CLR(); - delay_us(4); - for(i = 0; i < 8; i++) - { - if(cmd2 &(1<<(7-i))) - TXD_SET(); - else - TXD_CLR(); - - CLK_CLR(); - delay_us(4); - CLK_SET(); - delay_us(4); - } - for(i = 0; i < 8; i++) - { - if(addr_l &(1<<(7-i))) - TXD_SET(); - else - TXD_CLR(); - - CLK_CLR(); - delay_us(4); - CLK_SET(); - delay_us(4); - } - CLK_CLR(); - TXD_CLR(); - delay_us(4); - CS_SET(); - delay_us(8); - - // third transmit - CS_CLR(); - delay_us(4); - for(i = 0; i < 8; i++) - { - if(cmd3 &(1<<(7-i))) - TXD_SET(); - else - TXD_CLR(); - - CLK_CLR(); - delay_us(4); - CLK_SET(); - delay_us(4); - } - for(i = 0; i < 8; i++) - { - if(data_l &(1<<(7-i))) - TXD_SET(); - else - TXD_CLR(); - - CLK_CLR(); - delay_us(4); - CLK_SET(); - delay_us(4); - } - CLK_CLR(); - TXD_CLR(); - delay_us(4); - CS_SET(); - delay_us(8); - - //printk("Addr=0x%04x, WData=0x%02x, RData=0x%02x \n", Addr, Data, spi_screenreg_get(Addr)); - -} - - - - - -int lcd_init(void) -{ - -#if 0 - GPIO_SetPinDirection(reset_pin, GPIO_OUT); - GPIO_SetPinLevel(reset_pin,GPIO_HIGH); - DelayMs_nops(100); - GPIO_SetPinLevel(reset_pin,GPIO_LOW); - DelayMs_nops(100); - GPIO_SetPinLevel(reset_pin,GPIO_HIGH); -#endif - - if(gLcd_info) - gLcd_info->io_init(); - - spi_screenreg_set(0x2E80, 0x0001); - spi_screenreg_set(0x0680, 0x002D); - spi_screenreg_set(0xD380, 0x0004); - spi_screenreg_set(0xD480, 0x0060); - spi_screenreg_set(0xD580, 0x0007); - spi_screenreg_set(0xD680, 0x005A); - spi_screenreg_set(0xD080, 0x000F); - spi_screenreg_set(0xD180, 0x0016); - spi_screenreg_set(0xD280, 0x0004); - spi_screenreg_set(0xDC80, 0x0004); - spi_screenreg_set(0xD780, 0x0001); - - spi_screenreg_set(0x2280, 0x000F); - spi_screenreg_set(0x2480, 0x0068); - spi_screenreg_set(0x2580, 0x0000); - spi_screenreg_set(0x2780, 0x00AF); - - spi_screenreg_set(0x3A00, 0x0060); - spi_screenreg_set(0x3B00, 0x0003); - spi_screenreg_set(0x3B02, 0x0005); - spi_screenreg_set(0x3B03, 0x0002); - spi_screenreg_set(0x3B04, 0x0002); - spi_screenreg_set(0x3B05, 0x0002); - - spi_screenreg_set(0x0180, 0x0000); - spi_screenreg_set(0x4080, 0x0051); - spi_screenreg_set(0x4180, 0x0055); - spi_screenreg_set(0x4280, 0x0058); - spi_screenreg_set(0x4380, 0x0064); - spi_screenreg_set(0x4480, 0x001A); - spi_screenreg_set(0x4580, 0x002E); - spi_screenreg_set(0x4680, 0x005F); - spi_screenreg_set(0x4780, 0x0021); - spi_screenreg_set(0x4880, 0x001C); - spi_screenreg_set(0x4980, 0x0022); - spi_screenreg_set(0x4A80, 0x005D); - spi_screenreg_set(0x4B80, 0x0019); - spi_screenreg_set(0x4C80, 0x0046); - spi_screenreg_set(0x4D80, 0x0062); - spi_screenreg_set(0x4E80, 0x0048); - spi_screenreg_set(0x4F80, 0x005B); - - spi_screenreg_set(0x5080, 0x002F); - spi_screenreg_set(0x5180, 0x005E); - spi_screenreg_set(0x5880, 0x002E); - spi_screenreg_set(0x5980, 0x003B); - spi_screenreg_set(0x5A80, 0x008D); - spi_screenreg_set(0x5B80, 0x00A7); - spi_screenreg_set(0x5C80, 0x0027); - spi_screenreg_set(0x5D80, 0x0039); - spi_screenreg_set(0x5E80, 0x0065); - spi_screenreg_set(0x5F80, 0x0055); - - spi_screenreg_set(0x6080, 0x001A); - spi_screenreg_set(0x6180, 0x0021); - spi_screenreg_set(0x6280, 0x008F); - spi_screenreg_set(0x6380, 0x0022); - spi_screenreg_set(0x6480, 0x0053); - spi_screenreg_set(0x6580, 0x0066); - spi_screenreg_set(0x6680, 0x008A); - spi_screenreg_set(0x6780, 0x0097); - spi_screenreg_set(0x6880, 0x001F); - spi_screenreg_set(0x6980, 0x0026); - - spi_screenreg_set(0x1100, 0x0000); - msleep(150); - spi_screenreg_set(0x2900, 0x0000); - -#if 0 - printk("spi_screenreg_set(0x5555, 0x0055)... \n"); - while(1) { - spi_screenreg_set(0x5555, 0x0055); - msleep(1); - } -#endif - -#if 0 - while(1) { - int i = 0; - for(i=0; i<400*480; i++) - mcu_ioctl(MCU_WRDATA, 0xffffffff); - for(i=0; i<400*480; i++) - mcu_ioctl(MCU_WRDATA, 0x00000000); - msleep(1000); - printk(">>>>> MCU_WRDATA ...\n"); - - for(i=0; i<400*480; i++) - mcu_ioctl(MCU_WRDATA, 0x00000000); - for(i=0; i<400*480; i++) - mcu_ioctl(MCU_WRDATA, 0xffffffff); - msleep(1000); - printk(">>>>> MCU_WRDATA ...\n"); - } -#endif - - if(gLcd_info) - gLcd_info->io_deinit(); - return 0; -} - - -int lcd_standby(u8 enable) -{ - return 0; -} - - -void set_lcd_info(struct rk29fb_screen *screen, struct rk2918lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = lcd_init; - screen->standby = lcd_standby; - if(lcd_info) - gLcd_info = lcd_info; -} - - diff --git a/drivers/video/display/screen/lcd_nt35582.c b/drivers/video/display/screen/lcd_nt35582.c deleted file mode 100644 index 8835a2187a65..000000000000 --- a/drivers/video/display/screen/lcd_nt35582.c +++ /dev/null @@ -1,436 +0,0 @@ -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include "screen.h" - -/* Base */ -#define OUT_TYPE SCREEN_MCU -#define OUT_FACE OUT_P888 - -/* Timing */ -#define H_PW 1 -#define H_BP 1 -#define H_VD 480 -#define H_FP 5 - -#define V_PW 1 -#define V_BP 1 -#define V_VD 800 -#define V_FP 1 - -#define LCD_WIDTH 480 //need modify -#define LCD_HEIGHT 800 - -#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ - -#define P_WR 27 -#define USE_FMARK 0 //2 //ÊÇ·ñʹÓÃFMK (0:²»Ö§³Ö 1:ºáÆÁÖ§³Ö 2:ºáÊúÆÁ¶¼Ö§³Ö) -#define FRMRATE 60 //MCUÆÁµÄË¢ÐÂÂÊ (FMKÓÐЧʱÓÃ) - - -/* Other */ -#define DCLK_POL 0 -#define SWAP_RB 0 - -void Set_LCD_8B_REG(unsigned char regh,unsigned char regl, u32 data) -{ - u32 cmd; - cmd = (regh<<8) + regl; - if(-1==data) { - mcu_ioctl(MCU_WRCMD,cmd); - } else { - mcu_ioctl(MCU_WRCMD,cmd); - mcu_ioctl(MCU_WRDATA,data); - } -} - -int lcd_init(void) -{ - int i = 0; - -#if 0 - GPIO_SetPinDirection(reset_pin, GPIO_OUT); - GPIO_SetPinLevel(reset_pin,GPIO_HIGH); - DelayMs_nops(100); - GPIO_SetPinLevel(reset_pin,GPIO_LOW); - DelayMs_nops(100); - GPIO_SetPinLevel(reset_pin,GPIO_HIGH); -#endif - - mcu_ioctl(MCU_SETBYPASS, 1); - - - - Set_LCD_8B_REG(0xC0,0X00,0x86); - - Set_LCD_8B_REG(0xC0,0X01,0x00); - Set_LCD_8B_REG(0xC0,0X02,0x86); - Set_LCD_8B_REG(0xC0,0X03,0x00); - - Set_LCD_8B_REG(0xC1,0X00,0x60); //0x004f - Set_LCD_8B_REG(0xC2,0X00,0x21); - Set_LCD_8B_REG(0xC2,0X02,0x70); //0x0202 - - Set_LCD_8B_REG(0xB6,0x00,0x10); //0x0030 - Set_LCD_8B_REG(0xB6,0x02,0x30); - - Set_LCD_8B_REG(0xC7,0X00,0x6F); - - Set_LCD_8B_REG(0xE0,0X00,0X0E); - Set_LCD_8B_REG(0xE0,0X01,0X14); - Set_LCD_8B_REG(0xE0,0X02,0X29); - Set_LCD_8B_REG(0xE0,0X03,0X3A); - Set_LCD_8B_REG(0xE0,0X04,0X1D); - Set_LCD_8B_REG(0xE0,0X05,0X30); - Set_LCD_8B_REG(0xE0,0X06,0X61); - Set_LCD_8B_REG(0xE0,0X07,0X3D); - Set_LCD_8B_REG(0xE0,0X08,0X22); - Set_LCD_8B_REG(0xE0,0X09,0X2A); - Set_LCD_8B_REG(0xE0,0X0A,0X87); - Set_LCD_8B_REG(0xE0,0X0B,0X16); - Set_LCD_8B_REG(0xE0,0X0C,0X3B); - Set_LCD_8B_REG(0xE0,0X0D,0X4C); - Set_LCD_8B_REG(0xE0,0X0E,0X78); - Set_LCD_8B_REG(0xE0,0X0F,0X96); - Set_LCD_8B_REG(0xE0,0X10,0X4A); - Set_LCD_8B_REG(0xE0,0X11,0X4D); - - Set_LCD_8B_REG(0xE1,0X00,0X0E); - Set_LCD_8B_REG(0xE1,0X01,0X14); - Set_LCD_8B_REG(0xE1,0X02,0X29); - Set_LCD_8B_REG(0xE1,0X03,0X3A); - Set_LCD_8B_REG(0xE1,0X04,0X1D); - Set_LCD_8B_REG(0xE1,0X05,0X30); - Set_LCD_8B_REG(0xE1,0X06,0X61); - Set_LCD_8B_REG(0xE1,0X07,0X3F); - Set_LCD_8B_REG(0xE1,0X08,0X20); - Set_LCD_8B_REG(0xE1,0X09,0X26); - Set_LCD_8B_REG(0xE1,0X0A,0X83); - Set_LCD_8B_REG(0xE1,0X0B,0X16); - Set_LCD_8B_REG(0xE1,0X0C,0X3B); - Set_LCD_8B_REG(0xE1,0X0D,0X4C); - Set_LCD_8B_REG(0xE1,0X0E,0X78); - Set_LCD_8B_REG(0xE1,0X0F,0X96); - Set_LCD_8B_REG(0xE1,0X10,0X4A); - Set_LCD_8B_REG(0xE1,0X11,0X4D); - - Set_LCD_8B_REG(0xE2,0X00,0X0E); - Set_LCD_8B_REG(0xE2,0X01,0X14); - Set_LCD_8B_REG(0xE2,0X02,0X29); - Set_LCD_8B_REG(0xE2,0X03,0X3A); - Set_LCD_8B_REG(0xE2,0X04,0X1D); - Set_LCD_8B_REG(0xE2,0X05,0X30); - Set_LCD_8B_REG(0xE2,0X06,0X61); - Set_LCD_8B_REG(0xE2,0X07,0X3D); - Set_LCD_8B_REG(0xE2,0X08,0X22); - Set_LCD_8B_REG(0xE2,0X09,0X2A); - Set_LCD_8B_REG(0xE2,0X0A,0X87); - Set_LCD_8B_REG(0xE2,0X0B,0X16); - Set_LCD_8B_REG(0xE2,0X0C,0X3B); - Set_LCD_8B_REG(0xE2,0X0D,0X4C); - Set_LCD_8B_REG(0xE2,0X0E,0X78); - Set_LCD_8B_REG(0xE2,0X0F,0X96); - Set_LCD_8B_REG(0xE2,0X10,0X4A); - Set_LCD_8B_REG(0xE2,0X11,0X4D); - - Set_LCD_8B_REG(0xE3,0X00,0X0E); - Set_LCD_8B_REG(0xE3,0X01,0X14); - Set_LCD_8B_REG(0xE3,0X02,0X29); - Set_LCD_8B_REG(0xE3,0X03,0X3A); - Set_LCD_8B_REG(0xE3,0X04,0X1D); - Set_LCD_8B_REG(0xE3,0X05,0X30); - Set_LCD_8B_REG(0xE3,0X06,0X61); - Set_LCD_8B_REG(0xE3,0X07,0X3F); - Set_LCD_8B_REG(0xE3,0X08,0X20); - Set_LCD_8B_REG(0xE3,0X09,0X26); - Set_LCD_8B_REG(0xE3,0X0A,0X83); - Set_LCD_8B_REG(0xE3,0X0B,0X16); - Set_LCD_8B_REG(0xE3,0X0C,0X3B); - Set_LCD_8B_REG(0xE3,0X0D,0X4C); - Set_LCD_8B_REG(0xE3,0X0E,0X78); - Set_LCD_8B_REG(0xE3,0X0F,0X96); - Set_LCD_8B_REG(0xE3,0X10,0X4A); - Set_LCD_8B_REG(0xE3,0X11,0X4D); - - Set_LCD_8B_REG(0xE4,0X00,0X0E); - Set_LCD_8B_REG(0xE4,0X01,0X14); - Set_LCD_8B_REG(0xE4,0X02,0X29); - Set_LCD_8B_REG(0xE4,0X03,0X3A); - Set_LCD_8B_REG(0xE4,0X04,0X1D); - Set_LCD_8B_REG(0xE4,0X05,0X30); - Set_LCD_8B_REG(0xE4,0X06,0X61); - Set_LCD_8B_REG(0xE4,0X07,0X3D); - Set_LCD_8B_REG(0xE4,0X08,0X22); - Set_LCD_8B_REG(0xE4,0X09,0X2A); - Set_LCD_8B_REG(0xE4,0X0A,0X87); - Set_LCD_8B_REG(0xE4,0X0B,0X16); - Set_LCD_8B_REG(0xE4,0X0C,0X3B); - Set_LCD_8B_REG(0xE4,0X0D,0X4C); - Set_LCD_8B_REG(0xE4,0X0E,0X78); - Set_LCD_8B_REG(0xE4,0X0F,0X96); - Set_LCD_8B_REG(0xE4,0X10,0X4A); - Set_LCD_8B_REG(0xE4,0X11,0X4D); - - Set_LCD_8B_REG(0xE5,0X00,0X0E); - Set_LCD_8B_REG(0xE5,0X01,0X14); - Set_LCD_8B_REG(0xE5,0X02,0X29); - Set_LCD_8B_REG(0xE5,0X03,0X3A); - Set_LCD_8B_REG(0xE5,0X04,0X1D); - Set_LCD_8B_REG(0xE5,0X05,0X30); - Set_LCD_8B_REG(0xE5,0X06,0X61); - Set_LCD_8B_REG(0xE5,0X07,0X3F); - Set_LCD_8B_REG(0xE5,0X08,0X20); - Set_LCD_8B_REG(0xE5,0X09,0X26); - Set_LCD_8B_REG(0xE5,0X0A,0X83); - Set_LCD_8B_REG(0xE5,0X0B,0X16); - Set_LCD_8B_REG(0xE5,0X0C,0X3B); - Set_LCD_8B_REG(0xE5,0X0D,0X4C); - Set_LCD_8B_REG(0xE5,0X0E,0X78); - Set_LCD_8B_REG(0xE5,0X0F,0X96); - Set_LCD_8B_REG(0xE5,0X10,0X4A); - Set_LCD_8B_REG(0xE5,0X11,0X4D); - - Set_LCD_8B_REG(0x36,0X01,0X01); - - Set_LCD_8B_REG(0x11,0X00,0X00); - msleep(100); - Set_LCD_8B_REG(0x29,0X00,0X00); - msleep(100); - - - Set_LCD_8B_REG(0x2a,0X00,0X00); - Set_LCD_8B_REG(0x2a,0X01,0X00); - Set_LCD_8B_REG(0x2a,0X02,0X01); - Set_LCD_8B_REG(0x2a,0X03,0Xdf); - msleep(100); - Set_LCD_8B_REG(0x2b,0X00,0X00); - Set_LCD_8B_REG(0x2b,0X01,0X00); - Set_LCD_8B_REG(0x2b,0X02,0X03); - Set_LCD_8B_REG(0x2b,0X03,0X1f); - msleep(100); - { - u32 fte = 0; - Set_LCD_8B_REG(0x44,0x00,(fte>>8)&0xff); - Set_LCD_8B_REG(0x44,0x01,(fte)&0xff); - } - Set_LCD_8B_REG(0x0E,0X00,0X80); - Set_LCD_8B_REG(0x35,0X00,0X80); - -#if (480==H_VD) - Set_LCD_8B_REG(0x36,0X00,0x00); -#else - Set_LCD_8B_REG(0x36,0X00,0x22); -#endif - Set_LCD_8B_REG(0x2c,0X00,-1); - - for(i=0; i<480*800; i++) { - mcu_ioctl(MCU_WRDATA, 0x00000000); - } - -#if 0 - // for test - while(1) { - int i = 0; - for(i=0; i<400*480; i++) - mcu_ioctl(MCU_WRDATA, 0xffffffff); - for(i=0; i<400*480; i++) - mcu_ioctl(MCU_WRDATA, 0x00000000); - msleep(1000); - printk(">>>>> MCU_WRDATA ...\n"); - - for(i=0; i<400*480; i++) - mcu_ioctl(MCU_WRDATA, 0x00000000); - for(i=0; i<400*480; i++) - mcu_ioctl(MCU_WRDATA, 0xffffffff); - msleep(1000); - printk(">>>>> MCU_WRDATA ...\n"); - } -#endif - - mcu_ioctl(MCU_SETBYPASS, 0); - return 0; -} - - -int lcd_standby(u8 enable) -{ - mcu_ioctl(MCU_SETBYPASS, 1); - if(enable) { - Set_LCD_8B_REG(0x10,0X00,-1); - } else { - Set_LCD_8B_REG(0x11,0X00,-1); - } - mcu_ioctl(MCU_SETBYPASS, 0); - return 0; -} - - -int lcd_refresh(u8 arg) -{ - switch(arg) - { - case REFRESH_PRE: //DMA´«ËÍÇ°×¼±¸ - mcu_ioctl(MCU_SETBYPASS, 1); - Set_LCD_8B_REG(0x2c,0X00,-1); - mcu_ioctl(MCU_SETBYPASS, 0); - break; - - case REFRESH_END: //DMA´«ËͽáÊøºó - mcu_ioctl(MCU_SETBYPASS, 1); - Set_LCD_8B_REG(0x29,0X00,-1); - mcu_ioctl(MCU_SETBYPASS, 0); - break; - - default: - break; - } - - return 0; -} - - -int lcd_scandir(u16 dir) -{ - mcu_ioctl(MCU_SETBYPASS, 1); - - // ÔÝʱ¹Ø±ÕMCUÏÔʾ,ÔÚlcd_refreshµÄcase REFRESH_ENDÔÙ´ò¿ª - // ·ñÔò»­Ãæ»áÒì³£ - Set_LCD_8B_REG(0x28,0X00,-1); - - Set_LCD_8B_REG(0x2a,0X00,0X00); - Set_LCD_8B_REG(0x2a,0X01,0X00); - Set_LCD_8B_REG(0x2a,0X02,0X01); - Set_LCD_8B_REG(0x2a,0X03,0Xdf); - Set_LCD_8B_REG(0x2b,0X00,0X00); - Set_LCD_8B_REG(0x2b,0X01,0X00); - Set_LCD_8B_REG(0x2b,0X02,0X03); - Set_LCD_8B_REG(0x2b,0X03,0X1f); - - switch(dir) - { - case 0: - Set_LCD_8B_REG(0x36,0X00,0x00); - break; - case 90: - Set_LCD_8B_REG(0x36,0X00,0x22); - break; - case 180: - Set_LCD_8B_REG(0x36,0X00,0x03); - break; - case 270: - Set_LCD_8B_REG(0x36,0X00,0x21); - break; - default: - break; - } - - mcu_ioctl(MCU_SETBYPASS, 0); - return 0; -} - - -int lcd_disparea(u8 area) -{ - u32 x0, y0, x1, y1, fte; - - mcu_ioctl(MCU_SETBYPASS, 1); - - switch(area) - { - case 0: - fte = 0; - x0 = 0; - y0 = 0; - x1 = 399; - y1 = 479; - break; - - case 2: - x0 = 0; - y0 = 0; - x1 = 799; - y1 = 479; - break; - - case 1: - default: - fte = 400; - x0 = 400; - y0 = 0; - x1 = 799; - y1 = 479; - break; - } - - //Set_LCD_8B_REG(0x44,0x00,(fte>>8)&0xff); - //Set_LCD_8B_REG(0x44,0x01,(fte)&0xff); - Set_LCD_8B_REG(0x2a,0X00,(y0>>8)&0xff); - Set_LCD_8B_REG(0x2a,0X01,y0&0xff); - Set_LCD_8B_REG(0x2a,0X02,(y1>>8)&0xff); - Set_LCD_8B_REG(0x2a,0X03,y1&0xff); - - Set_LCD_8B_REG(0x2b,0X00,(x0>>8)&0xff); - Set_LCD_8B_REG(0x2b,0X01,x0&0xff); - Set_LCD_8B_REG(0x2b,0X02,(x1>>8)&0xff); - Set_LCD_8B_REG(0x2b,0X03,x1&0xff); - Set_LCD_8B_REG(0x2c,0X00,-1); - - mcu_ioctl(MCU_SETBYPASS, 0); - - return (0); - -} - -void set_lcd_info(struct rk29fb_screen *screen) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - screen->mcu_wrperiod = P_WR; - screen->mcu_usefmk = USE_FMARK; - screen->mcu_frmrate = FRMRATE; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = lcd_init; - screen->standby = lcd_standby; - screen->scandir = lcd_scandir; - screen->refresh = lcd_refresh; - screen->disparea = lcd_disparea; -} - - - - - diff --git a/drivers/video/display/screen/lcd_null.c b/drivers/video/display/screen/lcd_null.c old mode 100755 new mode 100644 diff --git a/drivers/video/display/screen/lcd_rgb_tft480800_25_e.c b/drivers/video/display/screen/lcd_rgb_tft480800_25_e.c deleted file mode 100644 index 1591300955c0..000000000000 --- a/drivers/video/display/screen/lcd_rgb_tft480800_25_e.c +++ /dev/null @@ -1,603 +0,0 @@ -/* - * Copyright (C) 2011 ROCKCHIP, Inc. - * - * author: hhb@rock-chips.com - * creat date: 2011-03-11 - * route:drivers/video/display/screen/lcd_rgb_tft480800_25_e.c - driver for rk29 phone sdk - * station:haven't been tested in any hardware platform - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - - - -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include "screen.h" - - -/* Base */ -#define OUT_TYPE SCREEN_RGB -#define OUT_FACE OUT_P888 -#define OUT_CLK 26000000 -#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ�� - -/* Timing */ -#define H_PW 8 -#define H_BP 6 -#define H_VD 480 -#define H_FP 60 - -#define V_PW 2 -#define V_BP 12 -#define V_VD 800 -#define V_FP 4 - - -#define LCD_WIDTH 800 //need modify -#define LCD_HEIGHT 480 - -/* Other */ -#define DCLK_POL 1 -#define SWAP_RB 0 - - -/* define spi write command and data interface function */ - -#define SIMULATION_SPI 1 -#ifdef SIMULATION_SPI - - #define TXD_PORT gLcd_info->txd_pin - #define CLK_PORT gLcd_info->clk_pin - #define CS_PORT gLcd_info->cs_pin - #define LCD_RST_PORT RK29_PIN6_PC6 - - #define CS_OUT() gpio_direction_output(CS_PORT, 0) - #define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) - #define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) - #define CLK_OUT() gpio_direction_output(CLK_PORT, 0) - #define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) - #define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) - #define TXD_OUT() gpio_direction_output(TXD_PORT, 0) - #define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) - #define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) - #define LCD_RST_OUT() gpio_direction_output(LCD_RST_PORT, 0) - #define LCD_RST(i) gpio_set_value(LCD_RST_PORT, i) - -// #define bits_9 - #ifdef bits_9 //9bits - #define LCDSPI_InitCMD(cmd) spi_write_9bit(0, cmd) - #define LCDSPI_InitDAT(dat) spi_write_9bit(1, dat) - #else //16bits - #define LCDSPI_InitCMD(cmd) spi_write_16bit(0, cmd) - #define LCDSPI_InitDAT(dat) spi_write_16bit(1, dat) - #endif - #define Lcd_EnvidOnOff(i) - -#else - - #define bits_9 1 - #ifdef bits_9 //9bits - #define LCDSPI_InitCMD(cmd) - #define LCDSPI_InitDAT(dat) - #else //16bits - #define LCDSPI_InitCMD(cmd) - #define LCDSPI_InitDAT(dat) - #endif - -#endif - - -/* define lcd command */ -#define ENTER_SLEEP_MODE 0x10 -#define EXIT_SLEEP_MODE 0x11 -#define SET_COLUMN_ADDRESS 0x2a -#define SET_PAGE_ADDRESS 0x2b -#define WRITE_MEMORY_START 0x2c -#define SET_DISPLAY_ON 0x29 -#define SET_DISPLAY_OFF 0x28 -#define SET_ADDRESS_MODE 0x36 -#define SET_PIXEL_FORMAT 0x3a - - -#define DRVDelayUs(i) udelay(i*2) - -static struct rk29lcd_info *gLcd_info = NULL; -int lcd_init(void); -int lcd_standby(u8 enable); - - -/* spi write a data frame,type mean command or data */ -int spi_write_9bit(u32 type, u32 value) -{ - u32 i = 0; - - if(type != 0 && type != 1) - { - return -1; - } - /*make a data frame of 9 bits,the 8th bit 0:mean command,1:mean data*/ - value &= 0xff; - value &= (type << 8); - - TXD_OUT(); - CLK_OUT(); - CS_OUT(); - DRVDelayUs(2); - DRVDelayUs(2); - - CS_SET(); - TXD_SET(); - CLK_SET(); - DRVDelayUs(2); - - CS_CLR(); - for(i = 0; i < 9; i++) //reg - { - if(value & (1 << (8-i))) - { - TXD_SET(); - } - else - { - TXD_CLR(); - } - - CLK_CLR(); - DRVDelayUs(2); - CLK_SET(); - DRVDelayUs(2); - } - - CS_SET(); - CLK_CLR(); - TXD_CLR(); - DRVDelayUs(2); - return 0; -} - - -/* spi write a data frame,type mean command or data */ -int spi_write_16bit(u32 type, u32 value) -{ - u32 i = 0; - u32 data = 0; - - if(type != 0 && type != 1) - { - return -1; - } - /*make a data frame of 16 bits,the 8th bit 0:mean command,1:mean data*/ - data = (type << 8)|value; - - TXD_OUT(); - CLK_OUT(); - CS_OUT(); - DRVDelayUs(2); - DRVDelayUs(2); - - CS_SET(); - TXD_SET(); - CLK_SET(); - DRVDelayUs(2); - - CS_CLR(); - for(i = 0; i < 16; i++) //reg - { - if(data & (1 << (15-i))) - { - TXD_SET(); - } - else - { - TXD_CLR(); - } - - CLK_CLR(); - DRVDelayUs(2); - CLK_SET(); - DRVDelayUs(2); - } - - CS_SET(); - CLK_CLR(); - TXD_CLR(); - DRVDelayUs(2); - return 0; -} -int lcd_init(void) -{ - if(gLcd_info) - gLcd_info->io_init(); - printk("lcd_init...\n"); -/* reset lcd to start init lcd by software if there is no hardware reset circuit for the lcd */ -#ifdef LCD_RST_PORT - gpio_request(LCD_RST_PORT, NULL); -#endif - -#if 1 - TXD_OUT(); - CLK_OUT(); - CS_OUT(); - CS_SET(); - TXD_SET(); - CLK_SET(); - LCD_RST_OUT(); - LCD_RST(1); - msleep(10); - LCD_RST(0); - msleep(100); - LCD_RST(1); - msleep(100); -#endif - -#if 1 - - LCDSPI_InitCMD(0xB9); // SET password - LCDSPI_InitDAT(0xFF); - LCDSPI_InitDAT(0x83); - LCDSPI_InitDAT(0x69); - - LCDSPI_InitCMD(0xB1); //Set Power - LCDSPI_InitDAT(0x85); - LCDSPI_InitDAT(0x00); - LCDSPI_InitDAT(0x34); - LCDSPI_InitDAT(0x07); - LCDSPI_InitDAT(0x00); - LCDSPI_InitDAT(0x0F); - LCDSPI_InitDAT(0x0F); - LCDSPI_InitDAT(0x2A); - LCDSPI_InitDAT(0x32); - LCDSPI_InitDAT(0x3F); - LCDSPI_InitDAT(0x3F); - LCDSPI_InitDAT(0x01); //update VBIAS - LCDSPI_InitDAT(0x3A); - LCDSPI_InitDAT(0x01); - LCDSPI_InitDAT(0xE6); - LCDSPI_InitDAT(0xE6); - LCDSPI_InitDAT(0xE6); - LCDSPI_InitDAT(0xE6); - LCDSPI_InitDAT(0xE6); - - - - LCDSPI_InitCMD(0xB2); // SET Display 480x800 - LCDSPI_InitDAT(0x00); - LCDSPI_InitDAT(0x28); //23 - LCDSPI_InitDAT(0x05); //03 - LCDSPI_InitDAT(0x05); //03 - LCDSPI_InitDAT(0x70); - LCDSPI_InitDAT(0x00); - LCDSPI_InitDAT(0xFF); - LCDSPI_InitDAT(0x00); - LCDSPI_InitDAT(0x00); - LCDSPI_InitDAT(0x00); - LCDSPI_InitDAT(0x00); - LCDSPI_InitDAT(0x03); - LCDSPI_InitDAT(0x03); - LCDSPI_InitDAT(0x00); - LCDSPI_InitDAT(0x01); - - - LCDSPI_InitCMD(0xB4); // SET Display 480x800 - LCDSPI_InitDAT(0x00); - LCDSPI_InitDAT(0x18); - LCDSPI_InitDAT(0x80); - LCDSPI_InitDAT(0x06); - LCDSPI_InitDAT(0x02); - - - - LCDSPI_InitCMD(0xB6); // SET VCOM - LCDSPI_InitDAT(0x42); // Update VCOM - LCDSPI_InitDAT(0x42); - - - - LCDSPI_InitCMD(0xD5); - LCDSPI_InitDAT(0x00); - LCDSPI_InitDAT(0x04); - LCDSPI_InitDAT(0x03); - LCDSPI_InitDAT(0x00); - LCDSPI_InitDAT(0x01); - LCDSPI_InitDAT(0x05); - LCDSPI_InitDAT(0x28); - LCDSPI_InitDAT(0x70); - LCDSPI_InitDAT(0x01); - LCDSPI_InitDAT(0x03); - LCDSPI_InitDAT(0x00); - LCDSPI_InitDAT(0x00); - LCDSPI_InitDAT(0x40); - LCDSPI_InitDAT(0x06); - LCDSPI_InitDAT(0x51); - LCDSPI_InitDAT(0x07); - LCDSPI_InitDAT(0x00); - LCDSPI_InitDAT(0x00); - LCDSPI_InitDAT(0x41); - LCDSPI_InitDAT(0x06); - LCDSPI_InitDAT(0x50); - LCDSPI_InitDAT(0x07); - LCDSPI_InitDAT(0x07); - LCDSPI_InitDAT(0x0F); - LCDSPI_InitDAT(0x04); - LCDSPI_InitDAT(0x00); - - - ///Gamma2.2 - LCDSPI_InitCMD(0xE0); - LCDSPI_InitDAT(0x00); - LCDSPI_InitDAT(0x13); - LCDSPI_InitDAT(0x19); - LCDSPI_InitDAT(0x38); - LCDSPI_InitDAT(0x3D); - LCDSPI_InitDAT(0x3F); - LCDSPI_InitDAT(0x28); - LCDSPI_InitDAT(0x46); - LCDSPI_InitDAT(0x07); - LCDSPI_InitDAT(0x0D); - LCDSPI_InitDAT(0x0E); - LCDSPI_InitDAT(0x12); - LCDSPI_InitDAT(0x15); - LCDSPI_InitDAT(0x12); - LCDSPI_InitDAT(0x14); - LCDSPI_InitDAT(0x0F); - LCDSPI_InitDAT(0x17); - LCDSPI_InitDAT(0x00); - LCDSPI_InitDAT(0x13); - LCDSPI_InitDAT(0x19); - LCDSPI_InitDAT(0x38); - LCDSPI_InitDAT(0x3D); - LCDSPI_InitDAT(0x3F); - LCDSPI_InitDAT(0x28); - LCDSPI_InitDAT(0x46); - LCDSPI_InitDAT(0x07); - LCDSPI_InitDAT(0x0D); - LCDSPI_InitDAT(0x0E); - LCDSPI_InitDAT(0x12); - LCDSPI_InitDAT(0x15); - LCDSPI_InitDAT(0x12); - LCDSPI_InitDAT(0x14); - LCDSPI_InitDAT(0x0F); - LCDSPI_InitDAT(0x17); - - - msleep(10); - -///DGC Setting - LCDSPI_InitCMD(0xC1); - LCDSPI_InitDAT(0x01); -//R - LCDSPI_InitDAT(0x04); - LCDSPI_InitDAT(0x13); - LCDSPI_InitDAT(0x1a); - LCDSPI_InitDAT(0x20); - LCDSPI_InitDAT(0x27); - LCDSPI_InitDAT(0x2c); - LCDSPI_InitDAT(0x32); - LCDSPI_InitDAT(0x36); - LCDSPI_InitDAT(0x3f); - LCDSPI_InitDAT(0x47); - LCDSPI_InitDAT(0x50); - LCDSPI_InitDAT(0x59); - LCDSPI_InitDAT(0x60); - LCDSPI_InitDAT(0x68); - LCDSPI_InitDAT(0x71); - LCDSPI_InitDAT(0x7B); - LCDSPI_InitDAT(0x82); - LCDSPI_InitDAT(0x89); - LCDSPI_InitDAT(0x91); - LCDSPI_InitDAT(0x98); - LCDSPI_InitDAT(0xA0); - LCDSPI_InitDAT(0xA8); - LCDSPI_InitDAT(0xB0); - LCDSPI_InitDAT(0xB8); - LCDSPI_InitDAT(0xC1); - LCDSPI_InitDAT(0xC9); - LCDSPI_InitDAT(0xD0); - LCDSPI_InitDAT(0xD7); - LCDSPI_InitDAT(0xE0); - LCDSPI_InitDAT(0xE7); - LCDSPI_InitDAT(0xEF); - LCDSPI_InitDAT(0xF7); - LCDSPI_InitDAT(0xFE); - LCDSPI_InitDAT(0xCF); - LCDSPI_InitDAT(0x52); - LCDSPI_InitDAT(0x34); - LCDSPI_InitDAT(0xF8); - LCDSPI_InitDAT(0x51); - LCDSPI_InitDAT(0xF5); - LCDSPI_InitDAT(0x9D); - LCDSPI_InitDAT(0x75); - LCDSPI_InitDAT(0x00); -//G - LCDSPI_InitDAT(0x04); - LCDSPI_InitDAT(0x13); - LCDSPI_InitDAT(0x1a); - LCDSPI_InitDAT(0x20); - LCDSPI_InitDAT(0x27); - LCDSPI_InitDAT(0x2c); - LCDSPI_InitDAT(0x32); - LCDSPI_InitDAT(0x36); - LCDSPI_InitDAT(0x3f); - LCDSPI_InitDAT(0x47); - LCDSPI_InitDAT(0x50); - LCDSPI_InitDAT(0x59); - LCDSPI_InitDAT(0x60); - LCDSPI_InitDAT(0x68); - LCDSPI_InitDAT(0x71); - LCDSPI_InitDAT(0x7B); - LCDSPI_InitDAT(0x82); - LCDSPI_InitDAT(0x89); - LCDSPI_InitDAT(0x91); - LCDSPI_InitDAT(0x98); - LCDSPI_InitDAT(0xA0); - LCDSPI_InitDAT(0xA8); - LCDSPI_InitDAT(0xB0); - LCDSPI_InitDAT(0xB8); - LCDSPI_InitDAT(0xC1); - LCDSPI_InitDAT(0xC9); - LCDSPI_InitDAT(0xD0); - LCDSPI_InitDAT(0xD7); - LCDSPI_InitDAT(0xE0); - LCDSPI_InitDAT(0xE7); - LCDSPI_InitDAT(0xEF); - LCDSPI_InitDAT(0xF7); - LCDSPI_InitDAT(0xFE); - LCDSPI_InitDAT(0xCF); - LCDSPI_InitDAT(0x52); - LCDSPI_InitDAT(0x34); - LCDSPI_InitDAT(0xF8); - LCDSPI_InitDAT(0x51); - LCDSPI_InitDAT(0xF5); - LCDSPI_InitDAT(0x9D); - LCDSPI_InitDAT(0x75); - LCDSPI_InitDAT(0x00); -//B - LCDSPI_InitDAT(0x04); - LCDSPI_InitDAT(0x13); - LCDSPI_InitDAT(0x1a); - LCDSPI_InitDAT(0x20); - LCDSPI_InitDAT(0x27); - LCDSPI_InitDAT(0x2c); - LCDSPI_InitDAT(0x32); - LCDSPI_InitDAT(0x36); - LCDSPI_InitDAT(0x3f); - LCDSPI_InitDAT(0x47); - LCDSPI_InitDAT(0x50); - LCDSPI_InitDAT(0x59); - LCDSPI_InitDAT(0x60); - LCDSPI_InitDAT(0x68); - LCDSPI_InitDAT(0x71); - LCDSPI_InitDAT(0x7B); - LCDSPI_InitDAT(0x82); - LCDSPI_InitDAT(0x89); - LCDSPI_InitDAT(0x91); - LCDSPI_InitDAT(0x98); - LCDSPI_InitDAT(0xA0); - LCDSPI_InitDAT(0xA8); - LCDSPI_InitDAT(0xB0); - LCDSPI_InitDAT(0xB8); - LCDSPI_InitDAT(0xC1); - LCDSPI_InitDAT(0xC9); - LCDSPI_InitDAT(0xD0); - LCDSPI_InitDAT(0xD7); - LCDSPI_InitDAT(0xE0); - LCDSPI_InitDAT(0xE7); - LCDSPI_InitDAT(0xEF); - LCDSPI_InitDAT(0xF7); - LCDSPI_InitDAT(0xFE); - LCDSPI_InitDAT(0xCF); - LCDSPI_InitDAT(0x52); - LCDSPI_InitDAT(0x34); - LCDSPI_InitDAT(0xF8); - LCDSPI_InitDAT(0x51); - LCDSPI_InitDAT(0xF5); - LCDSPI_InitDAT(0x9D); - LCDSPI_InitDAT(0x75); - LCDSPI_InitDAT(0x00); - - msleep(10); - - - //LCDSPI_InitCMD(0x36); - //LCDSPI_InitDAT(0x80); //µ÷Õû36HÖеIJÎÊý¿ÉÒÔʵÏÖGATEºÍSOURCEµÄ·­×ª - - LCDSPI_InitCMD(SET_PIXEL_FORMAT); - LCDSPI_InitDAT(0x77); - - LCDSPI_InitCMD(EXIT_SLEEP_MODE); - msleep(120); - - LCDSPI_InitCMD(SET_DISPLAY_ON); - - LCDSPI_InitCMD(WRITE_MEMORY_START); -#endif - - if(gLcd_info) - gLcd_info->io_deinit(); - - return 0; -} - -int lcd_standby(u8 enable) -{ - if(gLcd_info) - gLcd_info->io_init(); - - if(enable) { - Lcd_EnvidOnOff(0); //RGB TIMENG OFF - LCDSPI_InitCMD(ENTER_SLEEP_MODE); - Lcd_EnvidOnOff(1); //RGB TIMENG ON - msleep(200); - Lcd_EnvidOnOff(0); //RGB TIMENG OFF - msleep(100); - } else { - //LCD_RESET(); - LCDSPI_InitCMD(EXIT_SLEEP_MODE); - msleep(200); - Lcd_EnvidOnOff(1); //RGB TIMENG ON - msleep(200); - } - - if(gLcd_info) - gLcd_info->io_deinit(); - - return 0; -} - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = lcd_init; - screen->standby = lcd_standby; - if(lcd_info) - gLcd_info = lcd_info; -} - - - diff --git a/drivers/video/display/screen/lcd_rk2928.c b/drivers/video/display/screen/lcd_rk2928.c deleted file mode 100755 index 92c09b11b707..000000000000 --- a/drivers/video/display/screen/lcd_rk2928.c +++ /dev/null @@ -1,78 +0,0 @@ -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include -#include "../../rockchip/hdmi/rk_hdmi.h" -#include "screen.h" - -enum { - OUT_TYPE_INDEX = 0, - OUT_FACE_INDEX, - OUT_CLK_INDEX, - LCDC_ACLK_INDEX, - H_PW_INDEX, - H_BP_INDEX, - H_VD_INDEX, - H_FP_INDEX, - V_PW_INDEX, - V_BP_INDEX, - V_VD_INDEX, - V_FP_INDEX, - LCD_WIDTH_INDEX, - LCD_HEIGHT_INDEX, - DCLK_POL_INDEX, - SWAP_RB_INDEX, - LCD_PARAM_MAX, -}; -uint lcd_param[LCD_PARAM_MAX] = DEF_LCD_PARAM; -module_param_array(lcd_param, uint, NULL, 0644); - -#define set_scaler_info NULL - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = lcd_param[OUT_TYPE_INDEX]; - screen->face = lcd_param[OUT_FACE_INDEX]; - screen->hw_format = 1; - - /* Screen size */ - screen->x_res = lcd_param[H_VD_INDEX]; - screen->y_res = lcd_param[V_VD_INDEX]; - - screen->width = lcd_param[LCD_WIDTH_INDEX]; - screen->height = lcd_param[LCD_HEIGHT_INDEX]; - - /* Timing */ - screen->lcdc_aclk = lcd_param[LCDC_ACLK_INDEX]; - screen->pixclock = lcd_param[OUT_CLK_INDEX]; - screen->left_margin = lcd_param[H_BP_INDEX]; - screen->right_margin = lcd_param[H_FP_INDEX]; - screen->hsync_len = lcd_param[H_PW_INDEX]; - screen->upper_margin = lcd_param[V_BP_INDEX]; - screen->lower_margin = lcd_param[V_FP_INDEX]; - screen->vsync_len = lcd_param[V_PW_INDEX]; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = lcd_param[DCLK_POL_INDEX]; - - /* Swap rule */ - screen->swap_rb = lcd_param[SWAP_RB_INDEX]; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; -} - - - diff --git a/drivers/video/display/screen/lcd_s1d13521.c b/drivers/video/display/screen/lcd_s1d13521.c deleted file mode 100644 index 06db84f22ae5..000000000000 --- a/drivers/video/display/screen/lcd_s1d13521.c +++ /dev/null @@ -1,355 +0,0 @@ -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include "screen.h" - -#include "s1d13521.h" -#include "s1d13521ioctl.h" - -/* Base */ -#define OUT_TYPE SCREEN_MCU -#define OUT_FACE OUT_P16BPP4 -#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 1 -#define H_BP 1 -#define H_VD 600 -#define H_FP 5 - -#define V_PW 1 -#define V_BP 1 -#define V_VD 800 -#define V_FP 1 - -#define P_WR 200 - -#define LCD_WIDTH 600 //need modify -#define LCD_HEIGHT 800 - -/* Other */ -#define DCLK_POL 0 -#define SWAP_RB 0 - - - -int s1d13521if_refresh(u8 arg); - -#define GPIO_RESET_L RK2818_PIN_PC0//reset pin -#define GPIO_HIRQ RK2818_PIN_PC1 //IRQ -#define GPIO_HDC RK2818_PIN_PC2 //Data(HIHG) or Command(LOW) -#define GPIO_HCS_L RK2818_PIN_PC3 //Chip select -#define GPIO_HRD_L RK2818_PIN_PC4 //Read mode, low active -#define GPIO_HWE_L RK2818_PIN_PC5 //Write mode, low active -#define GPIO_HRDY RK2818_PIN_PC6 //Bus ready -#define GPIO_RMODE RK2818_PIN_PC7 //rmode ->CNF1 - - -//---------------------------------------------------------------------------- -// PRIVATE FUNCTION: -// Set registers to initial values -//---------------------------------------------------------------------------- - -int s1d13521if_wait_for_ready(void) -{ - int cnt = 1000; - int d = 0; - gpio_request(GPIO_HRDY, 0); - d = gpio_get_value(GPIO_HRDY); - - while (d == 0) - { - mdelay(1); - - if (--cnt <= 0) // Avoid endless loop - { - printk(">>>>>> wait_for_ready -- timeout! \n"); - return -1; - } - - d = gpio_get_value(GPIO_HRDY); - } - gpio_free(GPIO_HRDY); - return 0; -} - - -int s1d13521if_cmd(unsigned ioctlcmd,s1d13521_ioctl_cmd_params *params, int numparams) -{ - int i; - s1d13521if_wait_for_ready(); - - mcu_ioctl(MCU_WRCMD, ioctlcmd); - for (i = 0; i < numparams; i++) { - mcu_ioctl(MCU_WRDATA, params->param[i]); - } - - return 0; -} - -void s1d13521if_WriteReg16(u16 Index, u16 Value) -{ - s1d13521if_wait_for_ready(); - mcu_ioctl(MCU_WRCMD, WR_REG); - mcu_ioctl(MCU_WRDATA, Index); - mcu_ioctl(MCU_WRDATA, Value); -} - - -void s1d13521fb_InitRegisters(void) -{ - unsigned i, cmd,j,numparams; - s1d13521_ioctl_cmd_params cmd_params; - S1D_INSTANTIATE_REGISTERS(static,InitCmdArray); - - i = 0; - - while (i < sizeof(InitCmdArray)/sizeof(InitCmdArray[0])) - { - cmd = InitCmdArray[i++]; - numparams = InitCmdArray[i++]; - - for (j = 0; j < numparams; j++) - cmd_params.param[j] = InitCmdArray[i++]; - - s1d13521if_cmd(cmd,&cmd_params,numparams); - } -} - -void s1d13521if_init_gpio(void) -{ - int i; - int ret=0; - - rk29_mux_api_set(GPIOC_LCDC18BIT_SEL_NAME, IOMUXB_GPIO0_C01); - rk29_mux_api_set(GPIOC_LCDC24BIT_SEL_NAME, IOMUXB_GPIO0_C2_7); - - for(i = 0; i < 8; i++) - { - if(i == 1 || i == 6)//HIRQ, HRDY - { - ret = gpio_request(GPIO_RESET_L+i, NULL); - if(ret != 0) - { - gpio_free(GPIO_RESET_L+i); - printk(">>>>>> lcd cs gpio_request err \n "); - } - gpio_direction_input(GPIO_RESET_L+i); - gpio_free(GPIO_RESET_L+i); - } - else //RESET_L, HD/C, HCS_L, HRD_L, HWE_L, RMODE - { - ret = gpio_request(GPIO_RESET_L+i, NULL); - if(ret != 0) - { - gpio_free(GPIO_RESET_L+i); - printk(">>>>>> lcd cs gpio_request err \n "); - } - gpio_direction_output(GPIO_RESET_L+i, 0); - gpio_set_value(GPIO_RESET_L+i, GPIO_HIGH); - gpio_free(GPIO_RESET_L+i); - } - } -} - -void s1d13521if_set_reset(void) -{ - gpio_request(GPIO_RMODE, 0); - gpio_set_value(GPIO_RMODE, GPIO_HIGH); - gpio_request(GPIO_RESET_L, 0); - - // reset pulse - mdelay(10); - gpio_set_value(GPIO_RESET_L, GPIO_LOW); - mdelay(10); - gpio_set_value(GPIO_RESET_L, GPIO_HIGH); - mdelay(10); - gpio_free(GPIO_RMODE); - gpio_free(GPIO_RESET_L); - - //s1d13521if_WaitForHRDY(); -} - - - -int s1d13521if_init(void) -{ - int i=0; - s1d13521_ioctl_cmd_params cmd_params; - - s1d13521if_init_gpio(); - s1d13521if_set_reset(); - - mcu_ioctl(MCU_SETBYPASS, 1); - - s1d13521fb_InitRegisters(); - -#if 1 - s1d13521if_WriteReg16(0x330,0x84); // LUT AutoSelect+P4N - s1d13521if_cmd(WAIT_DSPE_TRG,&cmd_params,0); - cmd_params.param[0] = (0x2 << 4); - s1d13521if_cmd(LD_IMG,&cmd_params,1); - cmd_params.param[0] = 0x154; - s1d13521if_cmd(WR_REG,&cmd_params,1); - - for(i=0; i<600*200; i++) { - mcu_ioctl(MCU_WRDATA, 0xffff); - } - - s1d13521if_cmd(LD_IMG_END,&cmd_params,0); - cmd_params.param[0] = ((WF_MODE_INIT<<8) |0x4000); - s1d13521if_cmd(UPD_FULL,&cmd_params,1); // update all pixels - s1d13521if_cmd(WAIT_DSPE_TRG,&cmd_params,0); - s1d13521if_cmd(WAIT_DSPE_FREND,&cmd_params,0); -#endif - - mcu_ioctl(MCU_SETBYPASS, 0); - - -#if 0 - // ³õʼ»¯Í¼Ïó - mcu_ioctl(MCU_SETBYPASS, 1); - while(1) - { - int i=0, j=0; - // Copy virtual framebuffer to display framebuffer. - - unsigned mode = WF_MODE_GC; - unsigned cmd = UPD_FULL; - -// unsigned reg330 = s1d13521if_ReadReg16(0x330); - s1d13521if_WriteReg16(0x330,0x84); // LUT AutoSelect + P4N - // Copy virtual framebuffer to hardware via indirect interface burst mode write - s1d13521if_cmd(WAIT_DSPE_TRG,&cmd_params,0); - cmd_params.param[0] = (0x2<<4); - s1d13521if_cmd(LD_IMG,&cmd_params,1); - cmd_params.param[0] = 0x154; - s1d13521if_cmd(WR_REG,&cmd_params,1); - - for(i=0; i<600*100; i++) { - mcu_ioctl(MCU_WRDATA, 0xffff); - } - for(i=0; i<600*100; i++) { - mcu_ioctl(MCU_WRDATA, 0x0000); - } - - s1d13521if_cmd(LD_IMG_END,&cmd_params,0); - cmd_params.param[0] = (mode<<8); - s1d13521if_cmd(cmd,&cmd_params,1); // update all pixels - s1d13521if_cmd(WAIT_DSPE_TRG,&cmd_params,0); - s1d13521if_cmd(WAIT_DSPE_FREND,&cmd_params,0); - - msleep(2000); - printk(">>>>>> lcd_init : send test image! \n"); - } - mcu_ioctl(MCU_SETBYPASS, 0); -#endif - - - return 0; -} - -int s1d13521if_standby(u8 enable) -{ - return 0; -} - -int s1d13521if_refresh(u8 arg) -{ - mcu_ioctl(MCU_SETBYPASS, 1); - - switch(arg) - { - case REFRESH_PRE: //DMA´«ËÍÇ°×¼±¸ - { - // Copy virtual framebuffer to display framebuffer. - s1d13521_ioctl_cmd_params cmd_params; - - // unsigned reg330 = s1d13521if_ReadReg16(0x330); - s1d13521if_WriteReg16(0x330,0x84); // LUT AutoSelect + P4N - - // Copy virtual framebuffer to hardware via indirect interface burst mode write - s1d13521if_cmd(WAIT_DSPE_TRG,&cmd_params,0); - cmd_params.param[0] = (0x2<<4); - s1d13521if_cmd(LD_IMG,&cmd_params,1); - cmd_params.param[0] = 0x154; - s1d13521if_cmd(WR_REG,&cmd_params,1); - } - printk(">>>>>> lcd_refresh : REFRESH_PRE! \n"); - break; - - case REFRESH_END: //DMA´«ËͽáÊøºó - { - s1d13521_ioctl_cmd_params cmd_params; - unsigned mode = WF_MODE_GC; - unsigned cmd = UPD_FULL; - - s1d13521if_cmd(LD_IMG_END,&cmd_params,0); - - cmd_params.param[0] = (mode<<8); - s1d13521if_cmd(cmd,&cmd_params,1); // update all pixels - - s1d13521if_cmd(WAIT_DSPE_TRG,&cmd_params,0); - s1d13521if_cmd(WAIT_DSPE_FREND,&cmd_params,0); - } - printk(">>>>>> lcd_refresh : REFRESH_END! \n"); - break; - - default: - break; - } - - mcu_ioctl(MCU_SETBYPASS, 0); - - return 0; -} - - - -void set_lcd_info(struct rk28fb_screen *screen) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - screen->mcu_wrperiod = P_WR; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = s1d13521if_init; - screen->standby = s1d13521if_standby; - screen->refresh = s1d13521if_refresh; -} - - - - diff --git a/drivers/video/display/screen/lcd_td043mgea1.c b/drivers/video/display/screen/lcd_td043mgea1.c deleted file mode 100644 index 6301ac5d089b..000000000000 --- a/drivers/video/display/screen/lcd_td043mgea1.c +++ /dev/null @@ -1,235 +0,0 @@ -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include "screen.h" - - -/* Base */ -#define OUT_TYPE SCREEN_RGB -#define OUT_FACE OUT_P888 -#define OUT_CLK 27000000 -#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 10 -#define H_BP 206 -#define H_VD 800 -#define H_FP 40 - -#define V_PW 10 -#define V_BP 25 -#define V_VD 480 -#define V_FP 10 - -#define LCD_WIDTH 800 //need modify -#define LCD_HEIGHT 480 - -/* Other */ -#define DCLK_POL 0 -#define SWAP_RB 0 - -#define TXD_PORT gLcd_info->txd_pin -#define CLK_PORT gLcd_info->clk_pin -#define CS_PORT gLcd_info->cs_pin - -#if 0 -#define CS_OUT() gpio_direction_output(CS_PORT, 0) -#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) -#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) -#define CLK_OUT() gpio_direction_output(CLK_PORT, 0) -#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) -#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) -#define TXD_OUT() gpio_direction_output(TXD_PORT, 0) -#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) -#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) -#endif - - -static struct rk29lcd_info *gLcd_info = NULL; -int init(void); -int standby(u8 enable); - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = init; - screen->standby = standby; - if(lcd_info) - gLcd_info = lcd_info; -} - -#if 0 -void spi_screenreg_set(u32 Addr, u32 Data) -{ - -#define DRVDelayUs(i) udelay(i*2) - - u32 i; - - TXD_OUT(); - CLK_OUT(); - CS_OUT(); - DRVDelayUs(2); - DRVDelayUs(2); - - CS_SET(); - TXD_SET(); - CLK_SET(); - DRVDelayUs(2); - - CS_CLR(); - for(i = 0; i < 6; i++) //reg - { - if(Addr &(1<<(5-i))) - TXD_SET(); - else - TXD_CLR(); - - // \u6a21\u62dfCLK - CLK_CLR(); - DRVDelayUs(2); - CLK_SET(); - DRVDelayUs(2); - } - - TXD_CLR(); //write - - // \u6a21\u62dfCLK - CLK_CLR(); - DRVDelayUs(2); - CLK_SET(); - DRVDelayUs(2); - - TXD_SET(); //highz - - // \u6a21\u62dfCLK - CLK_CLR(); - DRVDelayUs(2); - CLK_SET(); - DRVDelayUs(2); - - - for(i = 0; i < 8; i++) //data - { - if(Data &(1<<(7-i))) - TXD_SET(); - else - TXD_CLR(); - - // \u6a21\u62dfCLK - CLK_CLR(); - DRVDelayUs(2); - CLK_SET(); - DRVDelayUs(2); - } - - CS_SET(); - CLK_CLR(); - TXD_CLR(); - DRVDelayUs(2); - -} -#endif - - -int init(void) -{ - if(gLcd_info) - gLcd_info->io_init(); - -#if 0 - spi_screenreg_set(0x02, 0x07); - spi_screenreg_set(0x03, 0x5f); - spi_screenreg_set(0x04, 0x17); - spi_screenreg_set(0x05, 0x20); - spi_screenreg_set(0x06, 0x08); - spi_screenreg_set(0x07, 0x20); - spi_screenreg_set(0x08, 0x20); - spi_screenreg_set(0x09, 0x20); - spi_screenreg_set(0x0a, 0x20); - spi_screenreg_set(0x0b, 0x22); - spi_screenreg_set(0x0c, 0x22); - spi_screenreg_set(0x0d, 0x22); - spi_screenreg_set(0x0e, 0x10); - spi_screenreg_set(0x0f, 0x10); - spi_screenreg_set(0x10, 0x10); - - spi_screenreg_set(0x11, 0x15); - spi_screenreg_set(0x12, 0xAA); - spi_screenreg_set(0x13, 0xFF); - spi_screenreg_set(0x14, 0xb0); - spi_screenreg_set(0x15, 0x8e); - spi_screenreg_set(0x16, 0xd6); - spi_screenreg_set(0x17, 0xfe); - spi_screenreg_set(0x18, 0x28); - spi_screenreg_set(0x19, 0x52); - spi_screenreg_set(0x1A, 0x7c); - - spi_screenreg_set(0x1B, 0xe9); - spi_screenreg_set(0x1C, 0x42); - spi_screenreg_set(0x1D, 0x88); - spi_screenreg_set(0x1E, 0xb8); - spi_screenreg_set(0x1F, 0xFF); - spi_screenreg_set(0x20, 0xF0); - spi_screenreg_set(0x21, 0xF0); - spi_screenreg_set(0x22, 0x09); -#endif - - if(gLcd_info) - gLcd_info->io_deinit(); - return 0; -} - -int standby(u8 enable) -{ - if(gLcd_info) - gLcd_info->io_init(); -#if 0 - if(enable) { - spi_screenreg_set(0x03, 0xde); - } else { - spi_screenreg_set(0x03, 0x5f); - } -#endif - if(gLcd_info) - gLcd_info->io_deinit(); - return 0; -} - diff --git a/drivers/video/display/screen/lcd_tj048nc01ca.c b/drivers/video/display/screen/lcd_tj048nc01ca.c deleted file mode 100644 index 1799321e0845..000000000000 --- a/drivers/video/display/screen/lcd_tj048nc01ca.c +++ /dev/null @@ -1,210 +0,0 @@ -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include "screen.h" - - -/* Base */ -#define OUT_TYPE SCREEN_RGB -#define OUT_FACE OUT_P888 -#define OUT_CLK 23000000 -#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 1 -#define H_BP 120 -#define H_VD 800 -#define H_FP 20 - -#define V_PW 1 -#define V_BP 20 -#define V_VD 480 -#define V_FP 4 - -#define LCD_WIDTH 800 //need modify -#define LCD_HEIGHT 480 - -/* Other */ -#define DCLK_POL 1 -#define SWAP_RB 0 - -#define TXD_PORT gLcd_info->txd_pin -#define CLK_PORT gLcd_info->clk_pin -#define CS_PORT gLcd_info->cs_pin - -#define CS_OUT() gpio_direction_output(CS_PORT, 0) -#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) -#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) -#define CLK_OUT() gpio_direction_output(CLK_PORT, 0) -#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) -#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) -#define TXD_OUT() gpio_direction_output(TXD_PORT, 0) -#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) -#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) - -#define DRVDelayUs(i) udelay(i*2) - -static struct rk29lcd_info *gLcd_info = NULL; -int lcd_init(void); -int lcd_standby(u8 enable); - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = lcd_init; - screen->standby = lcd_standby; - if(lcd_info) - gLcd_info = lcd_info; -} - -void spi_screenreg_set(u32 Addr, u32 Data) -{ - u32 i; - - TXD_OUT(); - CLK_OUT(); - CS_OUT(); - DRVDelayUs(2); - DRVDelayUs(2); - - CS_SET(); - TXD_CLR(); - CLK_CLR(); - DRVDelayUs(2); - - CS_CLR(); - for(i = 0; i < 7; i++) //reg - { - if(Addr &(1<<(6-i))) - TXD_SET(); - else - TXD_CLR(); - - // \u6a21\u62dfCLK - CLK_CLR(); - DRVDelayUs(2); - CLK_SET(); - DRVDelayUs(2); - } - - TXD_CLR(); //write - - // \u6a21\u62dfCLK - CLK_CLR(); - DRVDelayUs(2); - CLK_SET(); - DRVDelayUs(2); - - for(i = 0; i < 8; i++) //data - { - if(Data &(1<<(7-i))) - TXD_SET(); - else - TXD_CLR(); - - // \u6a21\u62dfCLK - CLK_CLR(); - DRVDelayUs(2); - CLK_SET(); - DRVDelayUs(2); - } - - CS_SET(); - CLK_CLR(); - TXD_CLR(); - DRVDelayUs(2); - -} - - -int lcd_init(void) -{ - if(gLcd_info) - gLcd_info->io_init(); - //R(0xess (A5~A0) Data(D7~D0) -#if 0 - spi_screenreg_set(0x03, 0x86); - spi_screenreg_set(0x05, 0x33); - spi_screenreg_set(0x09, 0xFF); - spi_screenreg_set(0x3A, 0x95); - spi_screenreg_set(0x3C, 0xE0); - spi_screenreg_set(0x3D, 0xF4); - spi_screenreg_set(0x3E, 0x21); - spi_screenreg_set(0x3F, 0x87); - spi_screenreg_set(0x15, 0x55); - spi_screenreg_set(0x16, 0xAF); - spi_screenreg_set(0x17, 0xFC); - spi_screenreg_set(0x18, 0x00); - spi_screenreg_set(0x19, 0x4B); - spi_screenreg_set(0x1A, 0x80); - spi_screenreg_set(0x1B, 0xFF); - spi_screenreg_set(0x1C, 0x39); - spi_screenreg_set(0x1D, 0x69); - spi_screenreg_set(0x1E, 0x9F); - spi_screenreg_set(0x1F, 0x09); - spi_screenreg_set(0x20, 0x8F); - spi_screenreg_set(0x21, 0xF0); - spi_screenreg_set(0x22, 0x2B); - spi_screenreg_set(0x23, 0x58); - spi_screenreg_set(0x24, 0x7C); - spi_screenreg_set(0x25, 0xA5); - spi_screenreg_set(0x26, 0xFF); -#endif - - if(gLcd_info) - gLcd_info->io_deinit(); - return 0; -} - -int lcd_standby(u8 enable) -{ - if(gLcd_info) - gLcd_info->io_init(); - if(enable) { - spi_screenreg_set(0x43, 0x20); - } else { - spi_screenreg_set(0x43, 0xE0); - } - if(gLcd_info) - gLcd_info->io_deinit(); - return 0; -} - - diff --git a/drivers/video/display/screen/lcd_tl5001_mipi.c b/drivers/video/display/screen/lcd_tl5001_mipi.c deleted file mode 100644 index b9b4135d1a46..000000000000 --- a/drivers/video/display/screen/lcd_tl5001_mipi.c +++ /dev/null @@ -1,406 +0,0 @@ -/* - * Copyright (C) 2012 ROCKCHIP, Inc. - * - * author: hhb@rock-chips.com - * creat date: 2012-04-19 - * route:drivers/video/display/screen/lcd_hj050na_06a.c - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include "../transmitter/tc358768.h" - -/* Base */ -#define OUT_TYPE SCREEN_RGB -#define OUT_FACE OUT_P888 -#define BYTE_PP 3 //bytes per pixel - - -#define OUT_CLK 65000000 // in fact it is 61384615 -#define LCDC_ACLK 300000000 - -/* Timing */ -#define H_PW 10 -#define H_BP 20 -#define H_VD 720 -#define H_FP 82 - -#define V_PW 8 -#define V_BP 6 -#define V_VD 1280 -#define V_FP 4 - - -#define LCD_WIDTH 62 //uint mm the lenth of lcd active area -#define LCD_HEIGHT 111 -/* Other */ -#define VSYNC_POL 0 -#define HSYNC_POL VSYNC_POL -#define DCLK_POL 1 -#define DEN_POL 0 //positive -#define SWAP_RB 0 - - -#define LCD_TEST 0 -#define CONFIG_DEEP_STANDBY_MODE 0 -#define CONFIG_TC358768_INIT_MODE 0 //1:ARRAY 0:FUNCTION - -#define dsi_init(data) mipi_dsi.dsi_init(data, ARRAY_SIZE(data)) -#define dsi_send_dcs_packet(data) mipi_dsi.dsi_send_dcs_packet(data, ARRAY_SIZE(data)) -#define dsi_hs_start(data) mipi_dsi.dsi_hs_start(data, ARRAY_SIZE(data)) - -#define lap_define ktime_t k0,k1; -#define lap_start k0 = ktime_get(); -#define lap_end { k1 = ktime_get(); k1 = ktime_sub(k1, k0); } - -static struct rk29lcd_info *gLcd_info = NULL; -struct mipi_dsi_t mipi_dsi; -struct tc358768_t *lcd_tc358768 = NULL; - -int lcd_init(void); -int lcd_standby(u8 enable); - - -#if CONFIG_TC358768_INIT_MODE -struct spi_cmd_data32 { - unsigned int delay; - unsigned int value; -}; - -struct spi_cmd_data32 TC358768XBG_INIT[] = { - - {0xffffffff, 0xffffffff} -}; - -#else - -//high speed mode -static unsigned int re_initialize[] = { - - -}; - -static unsigned int initialize[] = { -// ************************************************** -// Initizlize -> Display On after power-on -// ************************************************** -// ************************************************** -// Power on TC358768XBG according to recommended power-on sequence -// Relase reset (RESX="H") -// Start input REFCK and PCLK -// ************************************************** -// ************************************************** -// TC358768XBG Software Reset -// ************************************************** - 0x00020001, //SYSctl, S/W Reset - 10, - 0x00020000, //SYSctl, S/W Reset release - -// ************************************************** -// TC358768XBG PLL,Clock Setting -// ************************************************** - 0x00161063, //PLL Control Register 0 (PLL_PRD,PLL_FBD) - 0x00180603, //PLL_FRS,PLL_LBWS, PLL oscillation enable - 1000, - 0x00180613, //PLL_FRS,PLL_LBWS, PLL clock out enable - -// ************************************************** -// TC358768XBG DPI Input Control -// ************************************************** - 0x00060032, //FIFO Control Register - -// ************************************************** -// TC358768XBG D-PHY Setting -// ************************************************** - 0x01400000, //D-PHY Clock lane enable - 0x01420000, // - 0x01440000, //D-PHY Data lane0 enable - 0x01460000, // - 0x01480000, //D-PHY Data lane1 enable - 0x014A0000, // - 0x014C0000, //D-PHY Data lane2 enable - 0x014E0000, // - 0x01500000, //D-PHY Data lane3 enable - 0x01520000, // - -// ************************************************** -// TC358768XBG DSI-TX PPI Control -// ************************************************** - 0x021009C4, //LINEINITCNT - 0x02120000, // - 0x02140002, //LPTXTIMECNT - 0x02160000, // - 0x02200002, //THS_HEADERCNT - 0x02220000, // - 0x02244268, //TWAKEUPCNT - 0x02260000, // - 0x022C0001, //THS_TRAILCNT - 0x022E0000, // - 0x02300005, //HSTXVREGCNT - 0x02320000, // - 0x0234001F, //HSTXVREGEN enable - 0x02360000, // - 0x02380001, //DSI clock Enable/Disable during LP - 0x023A0000, // - 0x023C0001, //BTACNTRL1 - 0x023E0002, // - 0x02040001, //STARTCNTRL - 0x02060000, // - -// ************************************************** -// TC358768XBG DSI-TX Timing Control -// ************************************************** - 0x06200001, //Sync Pulse/Sync Event mode setting - 0x0622000E, //V Control Register1 - 0x06240006, //V Control Register2 - 0x06260500, //V Control Register3 - 0x0628005E, //H Control Register1 - 0x062A003F, //H Control Register2 - 0x062C0870, //H Control Register3 - - 0x05180001, //DSI Start - 0x051A0000, // - -}; - - - -static unsigned int start_dsi_hs_mode[] = { - -// ************************************************** -// Set to HS mode -// ************************************************** - 0x05000087, //DSI lane setting, DSI mode=HS - 0x0502A300, //bit set - 0x05008000, //Switch to DSI mode - 0x0502C300, // - -// ************************************************** -// Host: RGB(DPI) input start -// ************************************************** - - 0x00080037, //DSI-TX Format setting - 0x0050003E, //DSI-TX Pixel stream packet Data Type setting - 0x00040044 //Configuration Control Register - - -}; - -#endif - -static unsigned char boe_set_extension_command[] = {0xB9, 0xFF, 0x83, 0x94}; -static unsigned char boe_set_MIPI_ctrl[] = {0xBA, 0x13}; -static unsigned char boe_set_power[] = {0xB1, 0x7C, 0x00, 0x34, 0x09, 0x01, 0x11, 0x11, 0x36, 0x3E, 0x26, 0x26, 0x57, 0x12, 0x01, 0xE6}; -static unsigned char boe_setcyc[] = {0xB4, 0x00, 0x00, 0x00, 0x05, 0x06, 0x41, 0x42, 0x02, 0x41, 0x42, 0x43, 0x47, 0x19, 0x58, - 0x60, 0x08, 0x85, 0x10}; -static unsigned char boe_config05[] = {0xC7, 0x00, 0x20}; -static unsigned char boe_set_gip[] = {0xD5,0x4C,0x01,0x00,0x01,0xCD,0x23,0xEF,0x45,0x67,0x89,0xAB,0x11,0x00,0xDC,0x10,0xFE,0x32, - 0xBA,0x98,0x76,0x54,0x00,0x11,0x40}; - -//static unsigned char boe_set_panel[] = {0xCC, 0x01}; -//static unsigned char boe_set_vcom[] = {0xB6, 0x2a}; -static unsigned char boe_set_panel[] = {0xCC, 0x05}; -static unsigned char boe_set_vcom[] = {0xB6, 0x31}; - -static unsigned char boe_set_gamma[] = {0xE0,0x24,0x33,0x36,0x3F,0x3f,0x3f,0x3c,0x56,0x05,0x0C,0x0e,0x11,0x13,0x12,0x14,0x12,0x1e, - 0x24,0x33,0x36,0x3F,0x3f,0x3F,0x3c,0x56,0x05,0x0c, 0x0e,0x11,0x13,0x12,0x14,0x12, 0x1e}; // -static unsigned char boe_set_addr_mode[] = {0x36, 0x00}; -static unsigned char boe_set_pixel[] = {0x3a, 0x60}; - -static unsigned char boe_enter_sleep_mode[] = {0x10}; -static unsigned char boe_exit_sleep_mode[] = {0x11}; -static unsigned char boe_set_diaplay_on[] = {0x29}; -static unsigned char boe_set_diaplay_off[] = {0x28}; -static unsigned char boe_enter_invert_mode[] = {0x21}; -static unsigned char boe_all_pixel_on[] = {0x23}; -static unsigned char boe_set_id[] = {0xc3, 0xaa, 0x55, 0xee}; - - -void lcd_power_on(void) { - - -} - -void lcd_power_off(void) { - - -} -#if LCD_TEST -void lcd_test(void) { - u8 buf[8]; - printk("**mipi lcd test\n"); - buf[0] = 0x0c; - mipi_dsi.dsi_read_dcs_packet(buf, 1); - printk("**Get_pixel_format 0x0c:%02x\n", buf[0]); - buf[0] = 0x0a; - mipi_dsi.dsi_read_dcs_packet(buf, 1); - printk("**Get_power_mode 0x0a:%02x\n", buf[0]); - buf[0] = 0x0f; - mipi_dsi.dsi_read_dcs_packet(buf, 1); - printk("**Get_diagnostic_result 0x0f:%02x\n", buf[0]); - buf[0] = 0x09; - mipi_dsi.dsi_read_dcs_packet(buf, 4); - printk("**Read Display Status 0x09:%02x,%02x,%02x,%02x\n", buf[0],buf[1],buf[2],buf[3]); -} -#endif - - - -static unsigned char boe_set_wrdisbv[] = {0x51, 0xff}; -static unsigned char boe_set_wrctrld[] = {0x53, 0x24}; -static unsigned char boe_set_wrcabc[] = {0x55, 0x02}; -static unsigned char boe_set_wrcabcmb[] = {0x5e, 0x0}; -static unsigned char boe_set_cabc[] = {0xc9, 0x0d, 0x01, 0x0, 0x0, 0x0, 0x22, 0x0, 0x0, 0x0}; -static unsigned char boe_set_cabc_gain[] = {0xca, 0x32, 0x2e, 0x2c, 0x2a, 0x28, 0x26, 0x24, 0x22, 0x20}; - - -void lcd_cabc(u8 brightness) { - -} - - - -int lcd_init(void) -{ - - int i = 0; - lap_define - //power on - lcd_tc358768->power_up(NULL); - - if(gLcd_info) - gLcd_info->io_init(); - - i = 0; - lap_start - //Re-Initialize -#if CONFIG_TC358768_INIT_MODE - i = 0; - while (1) { - if(TC358768XBG_INIT[i].delay == 0xffffffff) - break; - tc358768_wr_reg_32bits_delay(TC358768XBG_INIT[i].delay, TC358768XBG_INIT[i].value); - i++; - } -#else - dsi_init(initialize); - - - //lcd init - dsi_send_dcs_packet(boe_exit_sleep_mode); - msleep(150); - dsi_send_dcs_packet(boe_set_extension_command); - msleep(1); - dsi_send_dcs_packet(boe_set_MIPI_ctrl); - msleep(1); - dsi_send_dcs_packet(boe_set_power); - msleep(1); - dsi_send_dcs_packet(boe_setcyc); - msleep(1); - dsi_send_dcs_packet(boe_set_vcom); - msleep(1); - dsi_send_dcs_packet(boe_set_panel); - msleep(1); - dsi_send_dcs_packet(boe_set_gip); - msleep(1); - dsi_send_dcs_packet(boe_set_gamma); - msleep(1); - dsi_send_dcs_packet(boe_set_addr_mode); - msleep(1); - dsi_send_dcs_packet(boe_set_diaplay_on); -#if LCD_TEST - lcd_test(); -#endif - dsi_hs_start(start_dsi_hs_mode); - - msleep(10); -#endif - lap_end - printk(">>time:%lld\n", k1.tv64); - return 0; - -} - -int lcd_standby(u8 enable) -{ - //int ret = 0; - if(enable) { - - printk("suspend lcd\n"); - //power down - if(gLcd_info) - gLcd_info->io_deinit(); - - lcd_tc358768->power_down(NULL); - - } else { - lcd_init(); - } - - return 0; -} - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = HSYNC_POL; - screen->pin_vsync = VSYNC_POL; - screen->pin_den = DEN_POL; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = lcd_init; - screen->standby = lcd_standby; - - if(lcd_info) - gLcd_info = lcd_info; - - if(tc358768_init(&mipi_dsi) == 0) - lcd_tc358768 = (struct tc358768_t *)mipi_dsi.chip; - else - printk("%s: %s:%d",__FILE__, __func__, __LINE__); - -} diff --git a/drivers/video/display/screen/lcd_tx23d88vm.c b/drivers/video/display/screen/lcd_tx23d88vm.c deleted file mode 100644 index d0fce5c9886c..000000000000 --- a/drivers/video/display/screen/lcd_tx23d88vm.c +++ /dev/null @@ -1,78 +0,0 @@ -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include "screen.h" - - -/* Base */ -#define OUT_TYPE SCREEN_RGB - -#define OUT_FACE OUT_D888_P666 -//#define OUT_FACE OUT_P888//modify by xhh - - -#define OUT_CLK 66000000//64000000 -#define LCDC_ACLK 500000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 10 -#define H_BP 20 -#define H_VD 1200 -#define H_FP 70 - -#define V_PW 2 -#define V_BP 4 -#define V_VD 800 -#define V_FP 14 - -#define LCD_WIDTH 188 -#define LCD_HEIGHT 125 -/* Other */ -#define DCLK_POL 0 -//#define DCLK_POL 1//xhh -#define SWAP_RB 0 - - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; -} diff --git a/drivers/video/display/screen/lcd_wy_800x480.c b/drivers/video/display/screen/lcd_wy_800x480.c deleted file mode 100755 index 5be80d6c5d5a..000000000000 --- a/drivers/video/display/screen/lcd_wy_800x480.c +++ /dev/null @@ -1,109 +0,0 @@ -#include -#include -#include "../../rk29_fb.h" -#include -#include -#include -#include "screen.h" - -/* Base */ -#define LCD_WIDTH 154 //need modify -#define LCD_HEIGHT 85 - -#define OUT_TYPE SCREEN_RGB -#define OUT_FACE OUT_P666 -#define OUT_CLK 33000000 -#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ - -/* Timing */ -#define H_PW 30 -#define H_BP 16 -#define H_VD 800 -#define H_FP 210 - -#define V_PW 13 -#define V_BP 10 -#define V_VD 480 -#define V_FP 22 - -/* Other */ -#define DCLK_POL 0 -#define SWAP_RB 0 - -static struct rk29lcd_info *gLcd_info = NULL; - -static int init(void) -{ - int ret = 0; - - if(gLcd_info && gLcd_info->io_init) - gLcd_info->io_init(); - - return 0; -} - -static int standby(u8 enable) -{ - if(!enable) - { - if(gLcd_info && gLcd_info->io_enable) - gLcd_info->io_enable(); - } - else - { - if(gLcd_info && gLcd_info->io_disable) - gLcd_info->io_disable(); - } - return 0; -} - -void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) -{ - /* screen type & face */ - screen->type = OUT_TYPE; - screen->face = OUT_FACE; - - /* Screen size */ - screen->x_res = H_VD; - screen->y_res = V_VD; - - screen->width = LCD_WIDTH; - screen->height = LCD_HEIGHT; - - /* Timing */ - screen->lcdc_aclk = LCDC_ACLK; - screen->pixclock = OUT_CLK; - screen->left_margin = H_BP; - screen->right_margin = H_FP; - screen->hsync_len = H_PW; - screen->upper_margin = V_BP; - screen->lower_margin = V_FP; - screen->vsync_len = V_PW; - - /* Pin polarity */ - screen->pin_hsync = 0; - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = DCLK_POL; - - /* Swap rule */ - screen->swap_rb = SWAP_RB; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = init; - screen->standby = standby; - if(lcd_info) - { - gLcd_info = lcd_info; - } - else - { - printk("%s lcd_info==NULL\n", __func__); - } - -} - diff --git a/drivers/video/display/screen/s1d13521.h b/drivers/video/display/screen/s1d13521.h deleted file mode 100755 index edaf6292aac0..000000000000 --- a/drivers/video/display/screen/s1d13521.h +++ /dev/null @@ -1,95 +0,0 @@ -/*=============================================================================== -** Generic Header information generated by 13521CFG.EXE (Build 4) -** (C)SEIKO EPSON CORPORATION 2002-2007. All rights reserved. -** -** DISPLAYS WxH FREQ SUBTYPE -** ------------- ----------- ------- ------------------------------------------- -** *LCD1=Parallel 800x600 NA EPD Panel -** -** DIMENSIONS WxHxBPP @ STRIDE START SADDR ADDITIONAL -** ----------- ---------------------- ------- --------- ----------------------- -** *Main 800x600x4 @ 800 NA 000EA600h LUTAuto=on -** -** CLOCKS FREQ SOURCE -** ------------- ----------- --------------------------------------------------- -** INCLK 132.000 MHz PLL -** SYSCLK 66.000 MHz PLL/2 -** PCLK 26.400 MHz PLL/5 -** SPICLK 13.200 MHz SYSCLK/5 -** I2CCLK 4.125 MHz PLL/16 -** SDRAMCLK 132.000 MHz PLL -** SDRAMREFCLK 63.954 KHz CLKI/516 -** -** This file defines the configuration environment and registers, -** which can be used by any software, such as display drivers. -** -** Note: If you transfer this file to any non-PC system, use ASCII -** mode (not BINARY) to maintain system-specific line terminators. -**===============================================================================*/ - -#define S1D_13521 - -#define S1D_DISPLAY_WIDTH 600 -#define S1D_DISPLAY_HEIGHT 800 - -#define S1D_DISPLAY_BPP 8 - -//#define S1D_DISPLAY_SCANLINE_BYTES 600 -#define S1D_DISPLAY_FRAME_RATE 0 -#define S1D_DISPLAY_PCLK 26400000L -#define S1D_PHYSICAL_REG_ADDR 0x00000000L -#define S1D_PHYSICAL_REG_SIZE 90L -#define S1D_PHYSICAL_VMEM_REQUIRED 640000L -#define S1D_PALETTE_SIZE 256 -#define S1D_POWER_DELAY_OFF 0 -#define S1D_POWER_DELAY_ON 0 -#define S1D_HWBLT -#define S1D_SWBLT - - -#define BS60_INIT_HSIZE 800 -#define BS60_INIT_VSIZE 600 - -#define BS60_INIT_FSLEN 4 -#define BS60_INIT_FBLEN 4 -#define BS60_INIT_FELEN 10 -#define BS60_INIT_LSLEN 10 -#define BS60_INIT_LBLEN 4 -#define BS60_INIT_LELEN 100 -#define BS60_INIT_PIXCLKDIV 6 -#define BS60_INIT_SDRV_CFG (100 | (1<< 8) | (1<<9)) -#define BS60_INIT_GDRV_CFG 0x2 -#define BS60_INIT_LUTIDXFMT (4 | (1<<7)) -#define BS60_INIT_ROTMODE 3 // rotation mode = 180 degrees - -#define WF_MODE_INIT 0 -#define WF_MODE_MU 1 -#define WF_MODE_GU 2 -#define WF_MODE_GC 3 -#define WF_MODE_PU 4 - -typedef unsigned short S1D_INDEX; -typedef unsigned short S1D_VALUE; - -#define S1D_INSTANTIATE_REGISTERS(scope_prefix,variable_name) \ - scope_prefix S1D_VALUE variable_name[] = \ - { \ - INIT_SYS_RUN, 0, \ - INIT_DSPE_CFG, 5, BS60_INIT_HSIZE, \ - BS60_INIT_VSIZE, \ - BS60_INIT_SDRV_CFG, \ - BS60_INIT_GDRV_CFG, \ - BS60_INIT_LUTIDXFMT, \ - INIT_DSPE_TMG, 5, BS60_INIT_FSLEN, \ - (BS60_INIT_FELEN<<8)|BS60_INIT_FBLEN, \ - BS60_INIT_LSLEN, \ - (BS60_INIT_LELEN<<8)|BS60_INIT_LBLEN, \ - BS60_INIT_PIXCLKDIV, \ - RD_WFM_INFO, 2, 0x0886, 0, \ - UPD_GDRV_CLR, 0, \ - WAIT_DSPE_TRG, 0, \ - INIT_ROTMODE, 1, (BS60_INIT_ROTMODE << 8) \ - } - - - diff --git a/drivers/video/display/screen/s1d13521ioctl.h b/drivers/video/display/screen/s1d13521ioctl.h deleted file mode 100755 index 3170b90d807e..000000000000 --- a/drivers/video/display/screen/s1d13521ioctl.h +++ /dev/null @@ -1,134 +0,0 @@ -//----------------------------------------------------------------------------- -// -// linux/drivers/video/epson/s1d1352ioctl.h -- IOCTL definitions for Epson -// S1D13521 controller frame buffer driver. -// -// Copyright(c) Seiko Epson Corporation 2009. -// All rights reserved. -// -// This file is subject to the terms and conditions of the GNU General Public -// License. See the file COPYING in the main directory of this archive for -// more details. -// -//---------------------------------------------------------------------------- - -/* ioctls - 0x45 is 'E' */ - -struct s1d13521_ioctl_hwc -{ - unsigned addr; - unsigned value; - void* buffer; -}; - -#define S1D13521_REGREAD 0x4540 -#define S1D13521_REGWRITE 0x4541 -#define S1D13521_MEMBURSTREAD 0x4546 -#define S1D13521_MEMBURSTWRITE 0x4547 -#define S1D13521_VBUF_REFRESH 0x4548 - -// System commands -#define INIT_CMD_SET 0x00 -#define INIT_PLL_STANDBY 0x01 -#define RUN_SYS 0x02 -#define STBY 0x04 -#define SLP 0x05 -#define INIT_SYS_RUN 0x06 -#define INIT_SYS_STBY 0x07 -#define INIT_SDRAM 0x08 -#define INIT_DSPE_CFG 0x09 -#define INIT_DSPE_TMG 0x0A -#define INIT_ROTMODE 0x0B - -// Register and memory access commands -#define RD_REG 0x10 -#define WR_REG 0x11 -#define RD_SFM 0x12 -#define WR_SFM 0x13 -#define END_SFM 0x14 - -// Burst access commands -#define BST_RD_SDR 0x1C -#define BST_WR_SDR 0x1D -#define BST_END_SDR 0x1E - -// Image loading commands -#define LD_IMG 0x20 -#define LD_IMG_AREA 0x22 -#define LD_IMG_END 0x23 -#define LD_IMG_WAIT 0x24 -#define LD_IMG_SETADR 0x25 -#define LD_IMG_DSPEADR 0x26 - -// Polling commands -#define WAIT_DSPE_TRG 0x28 -#define WAIT_DSPE_FREND 0x29 -#define WAIT_DSPE_LUTFREE 0x2A -#define WAIT_DSPE_MLUTFREE 0x2B - -// Waveform update commands -#define RD_WFM_INFO 0x30 -#define UPD_INIT 0x32 -#define UPD_FULL 0x33 -#define UPD_FULL_AREA 0x34 -#define UPD_PART 0x35 -#define UPD_PART_AREA 0x36 -#define UPD_GDRV_CLR 0x37 -#define UPD_SET_IMGADR 0x38 - -#pragma pack(1) - -typedef struct -{ - u16 param[5]; -}s1d13521_ioctl_cmd_params; - -#pragma pack() - -#define S1D13521_INIT_CMD_SET (0x4500 | INIT_CMD_SET) -#define S1D13521_INIT_PLL_STANDBY (0x4500 | INIT_PLL_STANDBY) -#define S1D13521_RUN_SYS (0x4500 | RUN_SYS) -#define S1D13521_STBY (0x4500 | STBY) -#define S1D13521_SLP (0x4500 | SLP) -#define S1D13521_INIT_SYS_RUN (0x4500 | INIT_SYS_RUN) -#define S1D13521_INIT_SYS_STBY (0x4500 | INIT_SYS_STBY) -#define S1D13521_INIT_SDRAM (0x4500 | INIT_SDRAM) -#define S1D13521_INIT_DSPE_CFG (0x4500 | INIT_DSPE_CFG) -#define S1D13521_INIT_DSPE_TMG (0x4500 | INIT_DSPE_TMG) -#define S1D13521_INIT_ROTMODE (0x4500 | INIT_ROTMODE) -#define S1D13521_RD_REG (0x4500 | RD_REG) -#define S1D13521_WR_REG (0x4500 | WR_REG) -#define S1D13521_RD_SFM (0x4500 | RD_SFM) -#define S1D13521_WR_SFM (0x4500 | WR_SFM) -#define S1D13521_END_SFM (0x4500 | END_SFM) - -// Burst access commands -#define S1D13521_BST_RD_SDR (0x4500 | BST_RD_SDR) -#define S1D13521_BST_WR_SDR (0x4500 | BST_WR_SDR) -#define S1D13521_BST_END_SDR (0x4500 | BST_END_SDR) - -// Image loading IOCTL commands -#define S1D13521_LD_IMG (0x4500 | LD_IMG) -#define S1D13521_LD_IMG_AREA (0x4500 | LD_IMG_AREA) -#define S1D13521_LD_IMG_END (0x4500 | LD_IMG_END) -#define S1D13521_LD_IMG_WAIT (0x4500 | LD_IMG_WAIT) -#define S1D13521_LD_IMG_SETADR (0x4500 | LD_IMG_SETADR) -#define S1D13521_LD_IMG_DSPEADR (0x4500 | LD_IMG_DSPEADR) - -// Polling commands -#define S1D13521_WAIT_DSPE_TRG (0x4500 | WAIT_DSPE_TRG) -#define S1D13521_WAIT_DSPE_FREND (0x4500 | WAIT_DSPE_FREND) -#define S1D13521_WAIT_DSPE_LUTFREE (0x4500 | WAIT_DSPE_LUTFREE) -#define S1D13521_WAIT_DSPE_MLUTFREE (0x4500 | WAIT_DSPE_MLUTFREE) - -// Waveform update IOCTL commands -#define S1D13521_RD_WFM_INFO (0x4500 | RD_WFM_INFO) -#define S1D13521_UPD_INIT (0x4500 | UPD_INIT) -#define S1D13521_UPD_FULL (0x4500 | UPD_FULL) -#define S1D13521_UPD_FULL_AREA (0x4500 | UPD_FULL_AREA) -#define S1D13521_UPD_PART (0x4500 | UPD_PART) -#define S1D13521_UPD_PART_AREA (0x4500 | UPD_PART_AREA) -#define S1D13521_UPD_GDRV_CLR (0x4500 | UPD_GDRV_CLR) -#define S1D13521_UPD_SET_IMGADR (0x4500 | UPD_SET_IMGADR) - diff --git a/drivers/video/display/screen/screen.h b/drivers/video/display/screen/screen.h old mode 100755 new mode 100644 diff --git a/drivers/video/display/transmitter/Kconfig b/drivers/video/display/transmitter/Kconfig deleted file mode 100644 index 9f8bba9b36d8..000000000000 --- a/drivers/video/display/transmitter/Kconfig +++ /dev/null @@ -1,39 +0,0 @@ -choice - depends on DISPLAY_SUPPORT - prompt "Display interface transmitter Select" - -config NO_TRSM - bool "no transmitter needed" - -config RK610_LVDS - bool "RK610(Jetta) lvds transmitter support" - depends on MFD_RK610 - help - Support Jetta(RK610) to output LCD1 and LVDS. - -config RK616_LVDS - bool "RK616(JettaB) lvds,lcd,scaler vido interface support" - depends on MFD_RK616 - help - RK616(Jetta B) LVDS,LCD,scaler transmitter support. - - -config DP_ANX6345 - bool "RGB to Display Port transmitter anx6345,anx9804,anx9805 support" - -config DP501 - bool"RGB to Display Port transmitter dp501 support" - -config TC358768_RGB2MIPI - bool "toshiba TC358768 RGB to MIPI DSI" - help - "a chip that change RGB interface parallel signal into DSI serial signal" - -config SSD2828_RGB2MIPI - bool "solomon SSD2828 RGB to MIPI DSI" - help - "a chip that change RGB interface parallel signal into DSI serial signal" - -endchoice - - diff --git a/drivers/video/display/transmitter/Makefile b/drivers/video/display/transmitter/Makefile deleted file mode 100644 index 7c9ccf2a360c..000000000000 --- a/drivers/video/display/transmitter/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Makefile for display transmitter like lvds edp mipi -# -obj-$(CONFIG_RK610_LVDS) += rk610_lcd.o -obj-$(CONFIG_RK616_LVDS) += rk616_lvds.o -obj-$(CONFIG_TC358768_RGB2MIPI) += mipi_dsi.o tc358768.o -obj-$(CONFIG_SSD2828_RGB2MIPI) += mipi_dsi.o ssd2828.o -obj-$(CONFIG_DP_ANX6345) += dp_anx6345.o -obj-$(CONFIG_DP501) += dp501.o diff --git a/drivers/video/display/transmitter/dp501.c b/drivers/video/display/transmitter/dp501.c deleted file mode 100644 index 0414ae84e9df..000000000000 --- a/drivers/video/display/transmitter/dp501.c +++ /dev/null @@ -1,294 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - - -static int dp501_write_reg(struct i2c_client *client,char index,char reg,char val) -{ - int ret; - if(index == 0) //page 0 - { - client->addr = (DP501_P0_ADDR >> 1); - } - else if(index == 1) //page1 - { - client->addr = (DP501_P1_ADDR >> 1); - } - else if(index == 2) //page 2 - { - client->addr = (DP501_P2_ADDR >> 1); - } - else if(index == 3) - { - client->addr = (DP501_P3_ADDR >> 1); - } - else - { - dev_err(&client->dev,"invalid page number\n"); - return -EINVAL; - } - ret = i2c_master_reg8_send(client, reg, &val, 1,DP501_SCL_RATE); - if(ret < 0) - { - - dev_err(&client->dev,"%s page%d:0x%x err\n",__func__,index,reg); - ret = -EINVAL; - } - - return ret; - -} - -static char dp501_read_reg(struct i2c_client *client,char index,char reg) -{ - int ret; - char val; - if(index == 0) //page 0 - { - client->addr = (DP501_P0_ADDR >> 1); - } - else if(index == 1) //page1 - { - client->addr = (DP501_P1_ADDR>>1); - } - else if(index == 2) //page 2 - { - client->addr = (DP501_P2_ADDR>>1); - } - else if(index == 3) - { - client->addr = (DP501_P3_ADDR>>1); - } - else - { - dev_err(&client->dev,"invalid page number\n"); - return -EINVAL; - } - - - ret = i2c_master_reg8_recv(client, reg, &val, 1, DP501_SCL_RATE); - if(ret < 0) - { - dev_err(&client->dev,"%s page%d:0x%x err\n",__func__,index,reg); - return -EINVAL; - } - - return val; - -} -static int get_dp_chip_id(struct i2c_client *client) -{ - char c1,c2; - int id; - c1 = dp501_read_reg(client,2,CHIP_ID_L); - c2 = dp501_read_reg(client,2,CHIP_ID_H); - id = c2; - return (id<<8)|c1; - return 0; -} - -static int dp501_init(struct i2c_client *client) -{ - char val,val1; - - dp501_write_reg(client,2,0x00,0x6C); - dp501_write_reg(client,2,0x01,0x68); - dp501_write_reg(client,2,0x02,0x28); - dp501_write_reg(client,2,0x03,0x2A); - dp501_write_reg(client,2,0x16,0x50); - dp501_write_reg(client,2,0x24,0x22); - dp501_write_reg(client,2,0x25,0x04); - dp501_write_reg(client,2,0x26,0x10); //PIO setting - - dp501_write_reg(client,0,0x0a,0x0c); //block 74 & 76 - dp501_write_reg(client,0,0x20,0x00); - dp501_write_reg(client,0,0x27,0x30); //auto detect CRTC - dp501_write_reg(client,0,0x2f,0x82); //reset tpfifo at v blank - dp501_write_reg(client,0,0x24,0xc0); //DVO mapping ; crtc follow mode - dp501_write_reg(client,0,0x28,0x07); //crtc follow mode - dp501_write_reg(client,0,0x87,0x7f); //aux retry - dp501_write_reg(client,0,0x88,0x1e); //aux retry - dp501_write_reg(client,0,0xbb,0x06); //aux retry - dp501_write_reg(client,0,0x72,0xa9); //DPCD readable - dp501_write_reg(client,0,0x60,0x00); //Scramble on - dp501_write_reg(client,0,0x8f,0x02); //debug select, read P0.0x8d[2] can check HPD - - - //second, set up training - dp501_write_reg(client,0,0x5d,0x06); //training link rate(2.7Gbps) - dp501_write_reg(client,0,0x5e,0x84); //training lane count(4Lanes), - dp501_write_reg(client,0,0x74,0x00); //idle pattern - dp501_write_reg(client,0,0x5f,0x0d); //trigger training - mdelay(100); //delay 100ms - - //then, check training result - val = dp501_read_reg(client,0,0x63); - val1 = dp501_read_reg(client,0,0x64); //Each 4bits stand for one lane, 0x77/0x77 means training succeed with 4Lanes. - dev_info(&client->dev,"training result:>>val:0x%x>>val1:0x%x\n",val,val1); - - return 0; -} - - - -static int edp_reg_show(struct seq_file *s, void *v) -{ - int i = 0; - char val; - struct dp501 *dp501= s->private; - - seq_printf(s,"page 0:\n"); - for(i=0;i< MAX_REG;i++) - { - val = dp501_read_reg(dp501->client,0,i); - seq_printf(s,"0x%02x>>0x%02x\n",i,val); - } - - seq_printf(s,"page 1:\n"); - for(i=0;i< MAX_REG;i++) - { - val = dp501_read_reg(dp501->client,1,i); - seq_printf(s,"0x%02x>>0x%02x\n",i,val); - } - - seq_printf(s,"page 2:\n"); - for(i=0;i< MAX_REG;i++) - { - val = dp501_read_reg(dp501->client,0,i); - seq_printf(s,"0x%02x>>0x%02x\n",2,val); - } - - seq_printf(s,"page 3:\n"); - for(i=0;i< MAX_REG;i++) - { - val = dp501_read_reg(dp501->client,3,i); - seq_printf(s,"0x%02x>>0x%02x\n",i,val); - } - - return 0; -} - -static int edp_reg_open(struct inode *inode, struct file *file) -{ - struct dp501 *dp501 = inode->i_private; - return single_open(file,edp_reg_show,dp501); -} - -static const struct file_operations edp_reg_fops = { - .owner = THIS_MODULE, - .open = edp_reg_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -#ifdef CONFIG_HAS_EARLYSUSPEND -static void dp501_early_suspend(struct early_suspend *h) -{ - struct dp501 *dp501 = container_of(h, struct dp501, early_suspend); - gpio_set_value(dp501->pdata->dvdd33_en_pin,!dp501->pdata->dvdd33_en_val); - gpio_set_value(dp501->pdata->dvdd18_en_pin,!dp501->pdata->dvdd18_en_val); - -} - -static void dp501_late_resume(struct early_suspend *h) -{ - struct dp501 *dp501 = container_of(h, struct dp501, early_suspend); - gpio_set_value(dp501->pdata->dvdd33_en_pin,dp501->pdata->dvdd33_en_val); - gpio_set_value(dp501->pdata->dvdd18_en_pin,dp501->pdata->dvdd18_en_val); - gpio_set_value(dp501->pdata->edp_rst_pin,0); - msleep(10); - gpio_set_value(dp501->pdata->edp_rst_pin,1); - dp501->edp_init(dp501->client); -} -#endif -static int dp501_i2c_probe(struct i2c_client *client,const struct i2c_device_id *id) -{ - int ret; - - struct dp501 *dp501 = NULL; - int chip_id; - - - if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) - { - dev_err(&client->dev, "Must have I2C_FUNC_I2C.\n"); - ret = -ENODEV; - } - dp501 = kzalloc(sizeof(struct dp501), GFP_KERNEL); - if (dp501 == NULL) - { - dev_err(&client->dev,"alloc for struct dp501 fail\n"); - ret = -ENOMEM; - } - - dp501->client = client; - dp501->pdata = client->dev.platform_data; - i2c_set_clientdata(client,dp501); - if(dp501->pdata->power_ctl) - dp501->pdata->power_ctl(); - - debugfs_create_file("edp-reg", S_IRUSR,NULL,dp501,&edp_reg_fops); - -#ifdef CONFIG_HAS_EARLYSUSPEND - dp501->early_suspend.suspend = dp501_early_suspend; - dp501->early_suspend.resume = dp501_late_resume; - dp501->early_suspend.level = EARLY_SUSPEND_LEVEL_STOP_DRAWING; - register_early_suspend(&dp501->early_suspend); -#endif - - chip_id = get_dp_chip_id(client); - dp501->edp_init = dp501_init; - dp501->edp_init(client); - - - printk("edp dp%x probe ok\n",chip_id); - - return ret; -} - -static int __devexit dp501_i2c_remove(struct i2c_client *client) -{ - return 0; -} - - -static const struct i2c_device_id id_table[] = { - {"dp501", 0 }, - { } -}; - -static struct i2c_driver dp501_i2c_driver = { - .driver = { - .name = "dp501", - .owner = THIS_MODULE, - }, - .probe = &dp501_i2c_probe, - .remove = &dp501_i2c_remove, - .id_table = id_table, -}; - - -static int __init dp501_module_init(void) -{ - return i2c_add_driver(&dp501_i2c_driver); -} - -static void __exit dp501_module_exit(void) -{ - i2c_del_driver(&dp501_i2c_driver); -} - -fs_initcall_sync(dp501_module_init); -module_exit(dp501_module_exit); - diff --git a/drivers/video/display/transmitter/dp_anx6345.c b/drivers/video/display/transmitter/dp_anx6345.c deleted file mode 100755 index 13ae7d9adeed..000000000000 --- a/drivers/video/display/transmitter/dp_anx6345.c +++ /dev/null @@ -1,849 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_DEBUG_FS) -#include -#include -#include -#endif - - -//#define BIST_MODE 0 - -static int anx6345_i2c_read_p0_reg(struct i2c_client *client, char reg, char *val) -{ - int ret; - client->addr = DP_TX_PORT0_ADDR >> 1; - ret = i2c_master_reg8_recv(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL; - if(ret < 0) - { - printk(KERN_ERR "%s>>err\n",__func__); - } - - return ret; -} -static int anx6345_i2c_write_p0_reg(struct i2c_client *client, char reg, char *val) -{ - int ret; - client->addr = DP_TX_PORT0_ADDR >> 1; - ret = i2c_master_reg8_send(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL; - if(ret < 0) - { - printk(KERN_ERR "%s>>err\n",__func__); - } - - return ret; -} -static int anx6345_i2c_read_p1_reg(struct i2c_client *client, char reg, char *val) -{ - int ret; - client->addr = HDMI_TX_PORT0_ADDR >> 1; - ret = i2c_master_reg8_recv(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL; - if(ret < 0) - { - printk(KERN_ERR "%s>>err\n",__func__); - } - - return ret; -} - -static int anx6345_i2c_write_p1_reg(struct i2c_client *client, char reg, char *val) -{ - int ret; - client->addr = HDMI_TX_PORT0_ADDR >> 1; - ret = i2c_master_reg8_send(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL; - if(ret < 0) - { - printk(KERN_ERR "%s>>err\n",__func__); - } - - return ret; -} - -#if defined(CONFIG_DEBUG_FS) -static int edp_reg_show(struct seq_file *s, void *v) -{ - int i = 0; - char val; - struct edp_anx6345 *anx6345 = s->private; - if(!anx6345) - { - printk(KERN_ERR "no edp device!\n"); - return 0; - } - - seq_printf(s,"0x70:\n"); - for(i=0;i< MAX_REG;i++) - { - anx6345_i2c_read_p0_reg(anx6345->client, i , &val); - seq_printf(s,"0x%02x>>0x%02x\n",i,val); - } - - - seq_printf(s,"\n0x72:\n"); - for(i=0;i< MAX_REG;i++) - { - anx6345_i2c_read_p1_reg(anx6345->client, i , &val); - seq_printf(s,"0x%02x>>0x%02x\n",i,val); - } - return 0; -} - -static int edp_reg_open(struct inode *inode, struct file *file) -{ - struct edp_anx6345 *anx6345 = inode->i_private; - return single_open(file, edp_reg_show, anx6345); -} - -static const struct file_operations edp_reg_fops = { - .owner = THIS_MODULE, - .open = edp_reg_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; -#endif - -//get chip ID. Make sure I2C is OK -static int get_dp_chip_id(struct i2c_client *client) -{ - char c1,c2; - int id; - anx6345_i2c_read_p1_reg(client,SP_TX_DEV_IDL_REG,&c1); - anx6345_i2c_read_p1_reg(client,SP_TX_DEV_IDH_REG,&c2); - id = c2; - return (id<<8)|c1; -} - - -static int anx980x_bist_mode(struct i2c_client *client) -{ - char val,i; - u8 cnt=0; - - //Power on total and select DP mode - val = 00; - anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val); - - //HW reset - val = DP_TX_RST_HW_RST; - anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val); - msleep(10); - val = 0x00; - anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val); - - - anx6345_i2c_read_p1_reg(client, DP_POWERD_CTRL_REG, &val); - val = 0x00; - anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val); - - - //get chip ID. Make sure I2C is OK - anx6345_i2c_read_p1_reg(client, DP_TX_DEV_IDH_REG , &val); - if (val==0x98) - printk("Chip found\n"); - - //for clocl detect - for(i=0;i<100;i++) - { - anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val); - anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val); - anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val); - if((val&DP_TX_SYS_CTRL1_DET_STA)!=0) - { - printk("clock is detected.\n"); - break; - } - - msleep(10); - } - //check whther clock is stable - for(i=0;i<50;i++) - { - anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val); - anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val); - anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val); - if((val&DP_TX_SYS_CTRL2_CHA_STA)==0) - { - printk("clock is stable.\n"); - break; - } - msleep(10); - } - - //VESA range, 8bits BPC, RGB - val = 0x10; - anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL2_REG, &val); - //RK_EDP chip analog setting - val = 0x07; - anx6345_i2c_write_p0_reg(client, DP_TX_PLL_CTRL_REG, &val); - val = 0x19; - anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL3, &val); - val = 0xd9; - anx6345_i2c_write_p1_reg(client, DP_TX_PLL_CTRL3, &val); - - //Select AC mode - val = 0x40; - anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val); - - //RK_EDP chip analog setting - val = 0xf0; - anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val); - val = 0x99; - anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG3, &val); - val = 0x7b; - anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val); - val = 0x30; - anx6345_i2c_write_p0_reg(client, DP_TX_LINK_DEBUG_REG,&val); - val = 0x06; - anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL, &val); - - //force HPD - val = 0x30; - anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL3_REG, &val); - //power on 4 lanes - val = 0x00; - anx6345_i2c_write_p0_reg(client, 0xc8, &val); - //lanes setting - anx6345_i2c_write_p0_reg(client, 0xa3, &val); - anx6345_i2c_write_p0_reg(client, 0xa4, &val); - anx6345_i2c_write_p0_reg(client, 0xa5,&val); - anx6345_i2c_write_p0_reg(client, 0xa6, &val); - - //reset AUX CH - val = 0x44; - anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val); - val = 0x40; - anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val); - - //Select 1.62G - val = 0x06; - anx6345_i2c_write_p0_reg(client, DP_TX_LINK_BW_SET_REG, &val); - //Select 4 lanes - val = 0x04; - anx6345_i2c_write_p0_reg(client, DP_TX_LANE_COUNT_SET_REG, &val); - - //strart link traing - //DP_TX_LINK_TRAINING_CTRL_EN is self clear. If link training is OK, it will self cleared. - #if 1 - val = DP_TX_LINK_TRAINING_CTRL_EN; - anx6345_i2c_write_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val); - msleep(5); - anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val); - while((val&0x01)&&(cnt++ < 10)) - { - printk("Waiting...\n"); - msleep(5); - anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val); - } - - if(cnt >= 10) - { - printk(KERN_INFO "HW LT fail\n"); - } - else - { - printk(KERN_INFO "HW LT success ...cnt:%d\n",cnt); - } - #else - DP_TX_HW_LT(client,0x0a,0x04); //2.7Gpbs 4lane - #endif - //DP_TX_Write_Reg(0x7a, 0x7c, 0x02); - - //Set bist format 2048x1536 - val = 0x2c; - anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_LINEL_REG, &val); - val = 0x06; - anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_LINEH_REG, &val); - - val = 0x00; - anx6345_i2c_write_p1_reg(client, DP_TX_ACT_LINEL_REG, &val); - val = 0x06; - anx6345_i2c_write_p1_reg(client, DP_TX_ACT_LINEH_REG,&val); - val = 0x02; - anx6345_i2c_write_p1_reg(client, DP_TX_VF_PORCH_REG, &val); - val = 0x04; - anx6345_i2c_write_p1_reg(client, DP_TX_VSYNC_CFG_REG,&val); - val = 0x26; - anx6345_i2c_write_p1_reg(client, DP_TX_VB_PORCH_REG, &val); - val = 0x50; - anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_PIXELL_REG, &val); - val = 0x04; - anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_PIXELH_REG, &val); - val = 0x00; - anx6345_i2c_write_p1_reg(client, DP_TX_ACT_PIXELL_REG, &val); - val = 0x04; - anx6345_i2c_write_p1_reg(client, DP_TX_ACT_PIXELH_REG, &val); - - val = 0x18; - anx6345_i2c_write_p1_reg(client, DP_TX_HF_PORCHL_REG, &val); - val = 0x00; - anx6345_i2c_write_p1_reg(client, DP_TX_HF_PORCHH_REG, &val); - - val = 0x10; - anx6345_i2c_write_p1_reg(client, DP_TX_HSYNC_CFGL_REG,&val); - val = 0x00; - anx6345_i2c_write_p1_reg(client, DP_TX_HSYNC_CFGH_REG,&val); - val = 0x28; - anx6345_i2c_write_p1_reg(client, DP_TX_HB_PORCHL_REG, &val); - val = 0x00; - anx6345_i2c_write_p1_reg(client, DP_TX_HB_PORCHH_REG, &val); - val = 0x03; - anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL10_REG, &val); - - //enable BIST - val = DP_TX_VID_CTRL4_BIST; - anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL4_REG, &val); - //enable video input - val = 0x8d; - anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val); - //force HPD and stream valid - val = 0x33; - anx6345_i2c_write_p0_reg(client, 0x82, &val); - - return 0; -} - -static int anx980x_aux_rst(struct i2c_client *client) -{ - char val; - anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL2_REG, &val); - val |= DP_TX_AUX_RST; - anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val); - val &= ~DP_TX_AUX_RST; - anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val); - return 0; -} - - -static int anx980x_wait_aux_finished(struct i2c_client *client) -{ - char val,cnt; - cnt = 0; - - anx6345_i2c_read_p0_reg(client,DP_TX_AUX_CTRL_REG2, &val); - while(val&0x01) - { - //delay_ms(20); - cnt ++; - if(cnt == 10) - { - printk("aux break"); - anx980x_aux_rst(client); - //cnt = 0; - break; - } - anx6345_i2c_read_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val); - } - - return 0; -} - -static int anx980x_aux_dpcdread_bytes(struct i2c_client *client,unsigned long addr, char cCount,char* pBuf) -{ - char val,i; - - val = 0x80; - anx6345_i2c_write_p0_reg(client, DP_TX_BUF_DATA_COUNT_REG, &val); - - //set read cmd and count - val = (((char)(cCount-1) <<4)&(0xf0))|0x09; - anx6345_i2c_write_p0_reg(client, DP_TX_AUX_CTRL_REG, &val); - - //set aux address15:0 - val = (char)addr&0xff; - anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_7_0_REG, &val); - val = (char)((addr>>8)&0xff); - anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_15_8_REG, &val); - - //set address19:16 and enable aux - anx6345_i2c_read_p0_reg(client, DP_TX_AUX_ADDR_19_16_REG, &val); - val &=(0xf0)|(char)((addr>>16)&0xff); - anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_19_16_REG, &val); - - //Enable Aux - anx6345_i2c_read_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val); - val |= 0x01; - anx6345_i2c_write_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val); - - //delay_ms(2); - anx980x_wait_aux_finished(client); - - for(i =0;i= MAX_BUF_CNT) - return 1; - //break; - } - - return 0; - - -} - -static int anx_video_map_config(struct i2c_client *client) -{ - char val = 0; - char i = 0; - anx6345_i2c_write_p1_reg(client, 0x40, &val); - anx6345_i2c_write_p1_reg(client, 0x41, &val); - anx6345_i2c_write_p1_reg(client, 0x48, &val); - anx6345_i2c_write_p1_reg(client, 0x49, &val); - anx6345_i2c_write_p1_reg(client, 0x50, &val); - anx6345_i2c_write_p1_reg(client, 0x51, &val); - for(i=0; i<6; i++) - { - val = i; - anx6345_i2c_write_p1_reg(client, 0x42+i, &val); - } - - for(i=0; i<6; i++) - { - val = 6+i; - anx6345_i2c_write_p1_reg(client, 0x4a+i, &val); - } - - for(i=0; i<6; i++) - { - val = 0x0c+i; - anx6345_i2c_write_p1_reg(client, 0x52+i, &val); - } - - return 0; - -} -static int anx980x_eanble_video_input(struct i2c_client *client) -{ - char val; - - anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val); - val |= DP_TX_VID_CTRL1_VID_EN; - anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val); - - anx_video_map_config(client); - - return 0; -} - -static int anx980x_init(struct i2c_client *client) -{ - char val = 0x00; - char safe_mode = 0; - char ByteBuf[2]; - char dp_tx_bw,dp_tx_lane_count; - char cnt = 10; - -#if defined(BIST_MODE) - return anx980x_bist_mode(client); -#endif - //power on all block and select DisplayPort mode - val |= DP_POWERD_AUDIO_REG; - anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val ); - - anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val); - val &= ~DP_TX_VID_CTRL1_VID_EN; - anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val); - - //software reset - anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL_REG, &val); - val |= DP_TX_RST_SW_RST; - anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG,&val); - val &= ~DP_TX_RST_SW_RST; - anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val); - - - val = 0x07; - anx6345_i2c_write_p0_reg(client, DP_TX_PLL_CTRL_REG, &val); - val = 0x50; - anx6345_i2c_write_p0_reg(client, DP_TX_EXTRA_ADDR_REG, &val); - - //24bit SDR,negedge latch, and wait video stable - val = 0x01; - anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);//72:08 for 9804 SDR, neg edge 05/04/09 extra pxl - val = 0x19; - anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL3, &val); - val = 0xd9; - anx6345_i2c_write_p1_reg(client, DP_TX_PLL_CTRL3, &val); - - //serdes ac mode. - anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL2_REG, &val); - val |= DP_TX_AC_MODE; - anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val); - - //set termination - val = 0xf0; - anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val); - //set duty cycle - val = 0x99; - anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG3, &val); - - anx6345_i2c_read_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val); - val |= 0x2a; - anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val); - - //anx6345_i2c_write_p0_reg(client, DP_TX_HDCP_CTRL, 0x01); - val = 0x30; - anx6345_i2c_write_p0_reg(client, DP_TX_LINK_DEBUG_REG,&val); - - //for DP link CTS - anx6345_i2c_read_p0_reg(client, DP_TX_GNS_CTRL_REG, &val); - val |= 0x40; - anx6345_i2c_write_p0_reg(client, DP_TX_GNS_CTRL_REG, &val); - - //power down PLL filter - val = 0x06; - anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL,&val); - - anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE0_SET_REG, &val); - anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE1_SET_REG, &val); - anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE2_SET_REG, &val); - anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE3_SET_REG, &val); - - val = 0x06; - anx6345_i2c_write_p0_reg(client, DP_TX_LINK_BW_SET_REG, &val); - val = 0x04; - anx6345_i2c_write_p0_reg(client, DP_TX_LANE_COUNT_SET_REG, &val); - - val = DP_TX_LINK_TRAINING_CTRL_EN; - anx6345_i2c_write_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG,&val); - msleep(2); - anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val); - while((val & DP_TX_LINK_TRAINING_CTRL_EN)&&(cnt--)) - { - anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val); - cnt--; - } - if(cnt < 0) - { - printk(KERN_INFO "HW LT fail\n"); - } - else - printk(KERN_INFO "HW LT Success!>>:times:%d\n",(11-cnt)); - //DP_TX_Config_Video(client); - anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val); - anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val); - if(!(val & DP_TX_SYS_CTRL1_DET_STA)) - { - printk("No pclk\n"); - //return; //mask by yxj - } - - anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val); - anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val); - anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val); - if(val & DP_TX_SYS_CTRL2_CHA_STA) - { - printk("pclk not stable!\n"); - //return; mask by yxj - } - - anx980x_aux_dpcdread_bytes(client,(unsigned long)0x00001,2,ByteBuf); - dp_tx_bw = ByteBuf[0]; - dp_tx_lane_count = ByteBuf[1] & 0x0f; - printk("%s..lc:%d--bw:%d\n",__func__,dp_tx_lane_count,dp_tx_bw); - - if(!safe_mode) - { - //set Input BPC mode & color space - anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL2_REG, &val); - val &= 0x8c; - val = val |((char)(0) << 4); //8bits ,rgb - anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL2_REG, &val); - } - - - - //enable video input - anx980x_eanble_video_input(client); - - return 0; -} - -static int anx6345_bist_mode(struct i2c_client *client) -{ - char val = 0x00; - //these register are for bist mode - val = 0x2c; - anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEL_REG,&val); - val = 0x06; - anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEH_REG,&val); - val = 0x00; - anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEL_REG,&val); - val = 0x06; - anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEH_REG,&val); - val = 0x02; - anx6345_i2c_write_p1_reg(client,SP_TX_VF_PORCH_REG,&val); - val = 0x04; - anx6345_i2c_write_p1_reg(client,SP_TX_VSYNC_CFG_REG,&val); - val = 0x26; - anx6345_i2c_write_p1_reg(client,SP_TX_VB_PORCH_REG,&val); - val = 0x50; - anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELL_REG,&val); - val = 0x04; - anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELH_REG,&val); - val = 0x00; - anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELL_REG,&val); - val = 0x04; - anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELH_REG,&val); - val = 0x18; - anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHL_REG,&val); - val = 0x00; - anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHH_REG,&val); - val = 0x10; - anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGL_REG,&val); - val = 0x00; - anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGH_REG,&val); - val = 0x28; - anx6345_i2c_write_p1_reg(client,SP_TX_HB_PORCHL_REG,&val); - val = 0x13; - anx6345_i2c_write_p1_reg(client,SP_TX_VID_CTRL10_REG,&val); - - - //enable BIST. In normal mode, don't need to config this reg - val = 0x08; - anx6345_i2c_write_p1_reg(client, 0x0b, &val); - printk("anx6345 enter bist mode\n"); - - return 0; -} -static int anx6345_init(struct i2c_client *client) -{ - char val = 0x00; - char i = 0; - char lc,bw; - char cnt = 50; - - val = 0x30; - anx6345_i2c_write_p1_reg(client,SP_POWERD_CTRL_REG,&val); - - //clock detect - for(i=0;i<50;i++) - { - - anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val); - anx6345_i2c_write_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val); - anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val); - if((val&SP_TX_SYS_CTRL1_DET_STA)!=0) - { - break; - } - - mdelay(10); - } - if(i>49) - printk("no clock detected by anx6345\n"); - - //check whether clock is stable - for(i=0;i<50;i++) - { - anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL2_REG, &val); - anx6345_i2c_write_p0_reg(client,SP_TX_SYS_CTRL2_REG, &val); - anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL2_REG, &val); - if((val&SP_TX_SYS_CTRL2_CHA_STA)==0) - { - break; - } - mdelay(10); - } - if(i>49) - printk("clk is not stable\n"); - - //VESA range, 6bits BPC, RGB - val = 0x00; - anx6345_i2c_write_p1_reg(client, SP_TX_VID_CTRL2_REG, &val); - - //ANX6345 chip pll setting - val = 0x00; - anx6345_i2c_write_p0_reg(client, SP_TX_PLL_CTRL_REG, &val); //UPDATE: FROM 0X07 TO 0X00 - - - //ANX chip analog setting - val = 0x70; - anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val); //UPDATE: FROM 0XF0 TO 0X70 - val = 0x30; - anx6345_i2c_write_p0_reg(client, SP_TX_LINK_DEBUG_REG, &val); - - //force HPD - //anx6345_i2c_write_p0_reg(client, SP_TX_SYS_CTRL3_REG, &val); - - - //reset AUX - anx6345_i2c_read_p1_reg(client, SP_TX_RST_CTRL2_REG, &val); - val |= SP_TX_AUX_RST; - anx6345_i2c_write_p1_reg(client, SP_TX_RST_CTRL2_REG, &val); - val &= ~SP_TX_AUX_RST; - anx6345_i2c_write_p1_reg(client, SP_TX_RST_CTRL2_REG, &val); - - //Select 2.7G - val = 0x0a; - anx6345_i2c_write_p0_reg(client, SP_TX_LINK_BW_SET_REG, &val); - //Select 2 lanes - val = 0x02; - anx6345_i2c_write_p0_reg(client,SP_TX_LANE_COUNT_SET_REG,&val); - - val = SP_TX_LINK_TRAINING_CTRL_EN; - anx6345_i2c_write_p0_reg(client, SP_TX_LINK_TRAINING_CTRL_REG, &val); - mdelay(5); - anx6345_i2c_read_p0_reg(client, SP_TX_LINK_TRAINING_CTRL_REG, &val); - while((val&0x80)&&(cnt)) //UPDATE: FROM 0X01 TO 0X80 - { - printk("Waiting...\n"); - mdelay(5); - anx6345_i2c_read_p0_reg(client,SP_TX_LINK_TRAINING_CTRL_REG,&val); - cnt--; - } - if(cnt <= 0) - { - printk(KERN_INFO "HW LT fail\n"); - } - else - printk("HW LT Success>>:times:%d\n",(51-cnt)); - - - - //enable video input, set DDR mode, the input DCLK should be 102.5MHz; - //In normal mode, set this reg to 0x81, SDR mode, the input DCLK should be 205MHz - -#if defined(BIST_MODE) - anx6345_bist_mode(client); - val = 0x8f; -#else - val = 0x81; -#endif - anx6345_i2c_write_p1_reg(client,SP_TX_VID_CTRL1_REG,&val); - - anx_video_map_config(client); - //force HPD and stream valid - val = 0x33; - anx6345_i2c_write_p0_reg(client,SP_TX_SYS_CTRL3_REG,&val); - - anx6345_i2c_read_p0_reg(client,SP_TX_LANE_COUNT_SET_REG, &lc); - anx6345_i2c_read_p0_reg(client,SP_TX_LINK_BW_SET_REG, &bw); - printk("%s..lc:%d--bw:%d\n",__func__,lc,bw); - - return 0; -} - - -#ifdef CONFIG_HAS_EARLYSUSPEND -static void anx6345_early_suspend(struct early_suspend *h) -{ - struct edp_anx6345 *anx6345 = container_of(h, struct edp_anx6345, early_suspend); - gpio_set_value(anx6345->pdata->dvdd33_en_pin,!anx6345->pdata->dvdd33_en_val); - gpio_set_value(anx6345->pdata->dvdd18_en_pin,!anx6345->pdata->dvdd18_en_val); -} - -static void anx6345_late_resume(struct early_suspend *h) -{ - struct edp_anx6345 *anx6345 = container_of(h, struct edp_anx6345, early_suspend); - gpio_set_value(anx6345->pdata->dvdd33_en_pin,anx6345->pdata->dvdd33_en_val); - msleep(5); - gpio_set_value(anx6345->pdata->dvdd18_en_pin,anx6345->pdata->dvdd18_en_val); - gpio_set_value(anx6345->pdata->edp_rst_pin,0); - msleep(50); - gpio_set_value(anx6345->pdata->edp_rst_pin,1); - anx6345->edp_anx_init(anx6345->client); -} -#endif - -static int anx6345_i2c_probe(struct i2c_client *client,const struct i2c_device_id *id) -{ - int ret; - - struct edp_anx6345 *anx6345 = NULL; - int chip_id; - - - if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) - { - dev_err(&client->dev, "Must have I2C_FUNC_I2C.\n"); - ret = -ENODEV; - } - anx6345 = kzalloc(sizeof(struct edp_anx6345), GFP_KERNEL); - if (anx6345 == NULL) - { - printk(KERN_ALERT "alloc for struct anx6345 fail\n"); - ret = -ENOMEM; - } - - anx6345->client = client; - anx6345->pdata = client->dev.platform_data; - i2c_set_clientdata(client,anx6345); - if(anx6345->pdata->power_ctl) - anx6345->pdata->power_ctl(); - -#if defined(CONFIG_DEBUG_FS) - anx6345->debugfs_dir = debugfs_create_dir("edp", NULL); - if (IS_ERR(anx6345->debugfs_dir)) - { - printk(KERN_ERR "failed to create debugfs dir for edp!\n"); - } - else - debugfs_create_file("edp-reg", S_IRUSR,anx6345->debugfs_dir,anx6345,&edp_reg_fops); -#endif - -#ifdef CONFIG_HAS_EARLYSUSPEND - anx6345->early_suspend.suspend = anx6345_early_suspend; - anx6345->early_suspend.resume = anx6345_late_resume; - anx6345->early_suspend.level = EARLY_SUSPEND_LEVEL_STOP_DRAWING; - register_early_suspend(&anx6345->early_suspend); -#endif - chip_id = get_dp_chip_id(client); - if(chip_id == 0x9805) - anx6345->edp_anx_init = anx980x_init; - else - anx6345->edp_anx_init = anx6345_init; - - anx6345->edp_anx_init(client); - - printk("edp anx%x probe ok\n",get_dp_chip_id(client)); - - return ret; -} - -static int __devexit anx6345_i2c_remove(struct i2c_client *client) -{ - return 0; -} - -static const struct i2c_device_id id_table[] = { - {"anx6345", 0 }, - { } -}; - -static struct i2c_driver anx6345_i2c_driver = { - .driver = { - .name = "anx6345", - .owner = THIS_MODULE, - }, - .probe = &anx6345_i2c_probe, - .remove = &anx6345_i2c_remove, - .id_table = id_table, -}; - - -static int __init anx6345_module_init(void) -{ - return i2c_add_driver(&anx6345_i2c_driver); -} - -static void __exit anx6345_module_exit(void) -{ - i2c_del_driver(&anx6345_i2c_driver); -} - -fs_initcall_sync(anx6345_module_init); -module_exit(anx6345_module_exit); - diff --git a/drivers/video/display/transmitter/mipi_dsi.c b/drivers/video/display/transmitter/mipi_dsi.c deleted file mode 100644 index e14fd2a1800a..000000000000 --- a/drivers/video/display/transmitter/mipi_dsi.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Copyright (C) 2012 ROCKCHIP, Inc. - * drivers/video/display/transmitter/mipi_dsi.c - * author: hhb@rock-chips.com - * create date: 2013-01-17 - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include "mipi_dsi.h" -#include -#include -#include - -#define MAX_DSI_CHIPS 5 - -static struct mipi_dsi_ops *dsi_ops[MAX_DSI_CHIPS] = {NULL}; -static struct mipi_dsi_ops *cur_dsi_ops; - -int register_dsi_ops(struct mipi_dsi_ops *ops) { - - int i = 0; - for(i = 0; i < MAX_DSI_CHIPS; i++) { - if(!dsi_ops[i]) { - dsi_ops[i] = ops; - break; - } - } - if(i == MAX_DSI_CHIPS) { - printk("dsi ops support 5 chips at most\n"); - return -1; - } - return 0; -} -EXPORT_SYMBOL(register_dsi_ops); - - -int del_dsi_ops(struct mipi_dsi_ops *ops) { - - int i = 0; - for(i = 0; i < MAX_DSI_CHIPS; i++) { - if(dsi_ops[i] == ops) { - dsi_ops[i] = NULL; - break; - } - } - if(cur_dsi_ops == ops) - cur_dsi_ops = NULL; - if(i == MAX_DSI_CHIPS) { - printk("dsi ops not found\n"); - return -1; - } - return 0; -} -EXPORT_SYMBOL(del_dsi_ops); - -int dsi_probe_current_chip(void) { - - u32 i = 0, id; - struct mipi_dsi_ops *ops = NULL; - if(cur_dsi_ops) - return 0; - for(i = 0; i < MAX_DSI_CHIPS; i++) { - if(dsi_ops[i]) { - ops = dsi_ops[i]; - id = ops->get_id(); - if(id == ops->id) { - cur_dsi_ops = ops; - printk("load mipi dsi chip:%s id:%08x\n", ops->name, ops->id); - break; - } else { - printk("mipi dsi chip is not found, read id:%08x, but %08x is correct\n", id, ops->id); - dsi_ops[i] = NULL; - cur_dsi_ops = NULL; - } - } - } - if(i == MAX_DSI_CHIPS) - printk("no mipi dsi chip\n"); - - return 0; -} -EXPORT_SYMBOL(dsi_probe_current_chip); - -int dsi_power_up(void) { - - if(!cur_dsi_ops) - return -1; - if(cur_dsi_ops->power_up) - cur_dsi_ops->power_up(); - return 0; -} -EXPORT_SYMBOL(dsi_power_up); - - -int dsi_power_off(void) { - - if(!cur_dsi_ops) - return -1; - if(cur_dsi_ops->power_down) - cur_dsi_ops->power_down(); - return 0; -} -EXPORT_SYMBOL(dsi_power_off); - -int dsi_set_regs(void *array, int n) { - - if(!cur_dsi_ops) - return -1; - if(cur_dsi_ops->dsi_set_regs) - cur_dsi_ops->dsi_set_regs(array, n); - return 0; -} -EXPORT_SYMBOL(dsi_set_regs); - -int dsi_init(void *array, int n) { - - if(!cur_dsi_ops) - return -1; - if(cur_dsi_ops->dsi_init) - cur_dsi_ops->dsi_init(array, n); - return 0; -} -EXPORT_SYMBOL(dsi_init); - - -int dsi_send_dcs_packet(unsigned char *packet, int n) { - - if(!cur_dsi_ops) - return -1; - if(cur_dsi_ops->dsi_send_dcs_packet) - cur_dsi_ops->dsi_send_dcs_packet(packet, n); - return 0; -} -EXPORT_SYMBOL(dsi_send_dcs_packet); - - -int dsi_read_dcs_packet(unsigned char *packet, int n) { - - if(!cur_dsi_ops) - return -1; - if(cur_dsi_ops->dsi_read_dcs_packet) - cur_dsi_ops->dsi_read_dcs_packet(packet, n); - return 0; -} -EXPORT_SYMBOL(dsi_read_dcs_packet); - - -int dsi_send_packet(void *packet, int n) { - - if(!cur_dsi_ops) - return -1; - if(cur_dsi_ops->dsi_send_packet) - cur_dsi_ops->dsi_send_packet(packet, n); - - return 0; -} -EXPORT_SYMBOL(dsi_send_packet); diff --git a/drivers/video/display/transmitter/mipi_dsi.h b/drivers/video/display/transmitter/mipi_dsi.h deleted file mode 100644 index b0d54f803539..000000000000 --- a/drivers/video/display/transmitter/mipi_dsi.h +++ /dev/null @@ -1,136 +0,0 @@ - -//drivers/video/display/transmitter/mipi_dsi.h - -#ifndef MIPI_DSI_H_ -#define MIPI_DSI_H_ - -#include -#include -#include -#include -#include - - -//DSI DATA TYPE -#define DTYPE_DCS_SWRITE_0P 0X05 -#define DTYPE_DCS_SWRITE_1P 0X15 -#define DTYPE_DCS_LWRITE 0X39 -#define DTYPE_GEN_LWRITE 0X29 -#define DTYPE_GEN_SWRITE_2P 0X23 -#define DTYPE_GEN_SWRITE_1P 0X13 -#define DTYPE_GEN_SWRITE_0P 0X03 - -//Video Mode -#define VM_NBMWSP 0X00 //Non burst mode with sync pulses -#define VM_NBMWSE 0X01 //Non burst mode with sync events -#define VM_BM 0X02 //Burst mode - -//Video Pixel Format -#define VPF_16BPP 0X00 -#define VPF_18BPP 0X01 //packed -#define VPF_18BPPL 0X02 //loosely packed -#define VPF_24BPP 0X03 - -//iomux -#define OLD_RK_IOMUX 0 - -struct spi_t { - int cs; -#if OLD_RK_IOMUX - char* cs_mux_name; -#endif - int sck; -#if OLD_RK_IOMUX - char* sck_mux_name; -#endif - int miso; -#if OLD_RK_IOMUX - char* miso_mux_name; -#endif - int mosi; -#if OLD_RK_IOMUX - char* mosi_mux_name; -#endif -}; - -struct power_t { - int enable_pin; //gpio that control power -#if OLD_RK_IOMUX - char* mux_name; - u32 mux_mode; -#endif - u32 effect_value; - - char *name; - u32 voltage; - int (*enable)(void *); - int (*disable)(void *); -}; - -struct reset_t { - int reset_pin; //gpio that control reset -#if OLD_RK_IOMUX - char* mux_name; - u32 mux_mode; -#endif - u32 effect_value; - - u32 time_before_reset; //ms - u32 time_after_reset; - - int (*do_reset)(void *); -}; - -struct tc358768_t { - u32 id; - struct reset_t reset; - struct power_t vddc; - struct power_t vddio; - struct power_t vdd_mipi; - struct i2c_client *client; - int (*gpio_init)(void *); - int (*gpio_deinit)(void *); - int (*power_up)(void); - int (*power_down)(void); -}; - - -struct ssd2828_t { - u32 id; - struct reset_t reset; - struct power_t shut; - struct power_t vddio; - struct power_t vdd_mipi; - - struct spi_t spi; - int (*gpio_init)(void *); - int (*gpio_deinit)(void *); - int (*power_up)(void); - int (*power_down)(void); -}; - -struct mipi_dsi_ops { - u32 id; - char *name; - int (*get_id)(void); - int (*dsi_init)(void *, int n); - int (*dsi_set_regs)(void *, int n); - int (*dsi_send_dcs_packet)(unsigned char *, int n); - int (*dsi_read_dcs_packet)(unsigned char *, int n); - int (*dsi_send_packet)(void *, int n); - int (*power_up)(void); - int (*power_down)(void); -}; - - -int register_dsi_ops(struct mipi_dsi_ops *ops); -int del_dsi_ops(struct mipi_dsi_ops *ops); -int dsi_power_up(void); -int dsi_power_off(void); -int dsi_probe_current_chip(void); -int dsi_init(void *array, int n); -int dsi_set_regs(void *array, int n); -int dsi_send_dcs_packet(unsigned char *packet, int n); -int dsi_read_dcs_packet(unsigned char *packet, int n); -int dsi_send_packet(void *packet, int n); -#endif /* end of MIPI_DSI_H_ */ diff --git a/drivers/video/display/transmitter/rk610_lcd.c b/drivers/video/display/transmitter/rk610_lcd.c deleted file mode 100644 index ef51241959c2..000000000000 --- a/drivers/video/display/transmitter/rk610_lcd.c +++ /dev/null @@ -1,414 +0,0 @@ -#include -#include -#include -#include -#include -#include "rk610_lcd.h" -#include -#include -#include "../../rockchip/hdmi/rk_hdmi.h" - -static struct rk610_lcd_info *g_lcd_inf = NULL; -//static int rk610_scaler_read_p0_reg(struct i2c_client *client, char reg, char *val) -//{ - //return i2c_master_reg8_recv(client, reg, val, 1, 100*1000) > 0? 0: -EINVAL; -//} - -static int rk610_scaler_write_p0_reg(struct i2c_client *client, char reg, char *val) -{ - return i2c_master_reg8_send(client, reg, val, 1, 100*1000) > 0? 0: -EINVAL; -} -static void rk610_scaler_pll_enable(struct i2c_client *client) -{ - char c; - RK610_DBG(&client->dev,"%s \n",__FUNCTION__); - - g_lcd_inf->scl_inf.pll_pwr = ENABLE; - - c = S_PLL_PWR(0)|S_PLL_RESET(0)|S_PLL_BYPASS(0); - rk610_scaler_write_p0_reg(client, S_PLL_CON2, &c); -} -static void rk610_scaler_pll_disable(struct i2c_client *client) -{ - char c; - RK610_DBG(&client->dev,"%s \n",__FUNCTION__); - - g_lcd_inf->scl_inf.pll_pwr = DISABLE; - - c = S_PLL_PWR(1) |S_PLL_RESET(0) |S_PLL_BYPASS(1); - rk610_scaler_write_p0_reg(client, S_PLL_CON2, &c); -} -static void rk610_scaler_enable(struct i2c_client *client) -{ - char c; - bool den_inv = 0,hv_sync_inv = 0,clk_inv = 0; - RK610_DBG(&client->dev,"%s \n",__FUNCTION__); - g_lcd_inf->scl_inf.scl_pwr = ENABLE; - #if defined(CONFIG_HDMI_DUAL_DISP) || defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF) - if(g_lcd_inf->screen !=NULL){ - den_inv = g_lcd_inf->screen->s_den_inv; - hv_sync_inv = g_lcd_inf->screen->s_hv_sync_inv; - clk_inv = g_lcd_inf->screen->s_clk_inv; - } - #endif - c= SCL_BYPASS(0) |SCL_DEN_INV(den_inv) |SCL_H_V_SYNC_INV(hv_sync_inv) |SCL_OUT_CLK_INV(clk_inv) |SCL_ENABLE(ENABLE); - rk610_scaler_write_p0_reg(client, SCL_CON0, &c); -} -static void rk610_scaler_disable(struct i2c_client *client) -{ - char c; - bool den_inv = 0,hv_sync_inv = 0,clk_inv = 0; - RK610_DBG(&client->dev,"%s \n",__FUNCTION__); - - g_lcd_inf->scl_inf.scl_pwr = DISABLE; - #if defined(CONFIG_HDMI_DUAL_DISP) || defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF) - if(g_lcd_inf->screen !=NULL){ - den_inv = g_lcd_inf->screen->s_den_inv; - hv_sync_inv = g_lcd_inf->screen->s_hv_sync_inv; - clk_inv = g_lcd_inf->screen->s_clk_inv; - } - #endif - c= SCL_BYPASS(1) |SCL_DEN_INV(den_inv) |SCL_H_V_SYNC_INV(hv_sync_inv) |SCL_OUT_CLK_INV(clk_inv) |SCL_ENABLE(DISABLE); - rk610_scaler_write_p0_reg(client, SCL_CON0, &c); -} - -static int rk610_output_config(struct i2c_client *client,struct rk29fb_screen *screen,int mode) -{ - char c=0; - RK610_DBG(&client->dev,"%s \n",__FUNCTION__); - if(SCREEN_LVDS == screen->type){ - if(mode == LCD_OUT_SCL || mode == LCD_OUT_BYPASS){ - c = LVDS_OUT_CLK_PIN(0) |LVDS_OUT_CLK_PWR_PIN(1) |LVDS_PLL_PWR_PIN(0) \ - |LVDS_LANE_IN_FORMAT(DATA_D0_MSB) |LVDS_INPUT_SOURCE(FROM_LCD0_OR_SCL) \ - |LVDS_OUTPUT_FORMAT(screen->hw_format) | LVDS_BIASE_PWR(1); - rk610_scaler_write_p0_reg(client, LVDS_CON0, &c); - c = LVDS_OUT_ENABLE(0x0) |LVDS_TX_PWR_ENABLE(0x0); - rk610_scaler_write_p0_reg(client, LVDS_CON1, &c); - } - else{ - c = LVDS_OUT_CLK_PIN(0) |LVDS_OUT_CLK_PWR_PIN(0) |LVDS_PLL_PWR_PIN(1) \ - |LVDS_LANE_IN_FORMAT(DATA_D0_MSB) |LVDS_INPUT_SOURCE(FROM_LCD0_OR_SCL) \ - |LVDS_OUTPUT_FORMAT(screen->hw_format) | LVDS_BIASE_PWR(0); - rk610_scaler_write_p0_reg(client, LVDS_CON0, &c); - c = LVDS_OUT_ENABLE(0xf) |LVDS_TX_PWR_ENABLE(0xf); - rk610_scaler_write_p0_reg(client, LVDS_CON1, &c); - - } - }else if(SCREEN_RGB == screen->type){ - if(mode == LCD_OUT_SCL || mode == LCD_OUT_BYPASS){ - c = LCD1_OUT_ENABLE(LCD1_AS_OUT) | LCD1_OUT_SRC((mode == LCD_OUT_SCL)?LCD1_FROM_SCL : LCD1_FROM_LCD0); - rk610_scaler_write_p0_reg(client, LCD1_CON, &c); - } - else { - c = LCD1_OUT_ENABLE(LCD1_AS_IN); - rk610_scaler_write_p0_reg(client, LCD1_CON, &c); - } - } - return 0; -} -#if defined(CONFIG_HDMI_DUAL_DISP) || defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF) -static int rk610_scaler_pll_set(struct i2c_client *client,struct rk29fb_screen *screen,u32 clkin ) -{ - char c=0; - char M=0,N=0,OD=0; - RK610_DBG(&client->dev,"%s \n",__FUNCTION__); - /***************SET SCALER PLL FROM CLKIN ,DIV 0*/ - if(screen->s_pixclock != 0){ - OD = (screen->s_pixclock)&0x3; - N = (screen->s_pixclock >>4)&0xf; - M = (screen->s_pixclock >>8)&0xff; - }else { - RK610_ERR(&client->dev,"RK610 Scaler pll not support rate \n"); - } - c = S_PLL_FROM_DIV<<3 | S_PLL_DIV(0); - rk610_scaler_write_p0_reg(client, CLOCK_CON0, &c); - - c = S_DIV_N(N)| S_DIV_OD(OD); - rk610_scaler_write_p0_reg(client, S_PLL_CON0, &c); - c = S_DIV_M(M); - rk610_scaler_write_p0_reg(client, S_PLL_CON1, &c); - rk610_scaler_pll_enable(client); - return 0; -} - - -static int scale_hv_factor(struct i2c_client *client ,u32 Hin_act, u32 Hout_act, u32 Vin_act, u32 Vout_act) - { - char c; - u32 hfactor_f,vfactor_f,scl_factor_f; - int hfactor; - int vfactor; - struct scl_hv_info HV2; - hfactor_f = ((Hin_act-1)*4096)/(Hout_act-1); - if(hfactor_f==4096) - {hfactor = 0x1000;} - else if(hfactor_f>(int)hfactor_f) - {hfactor = (int)hfactor_f+1;} - else - {hfactor = (int)hfactor_f;} - - scl_factor_f = Vin_act/Vout_act; - if(scl_factor_f<2) - {vfactor_f = ((Vin_act-1)*4096)/(Vout_act-1);} - else - {vfactor_f = ((Vin_act-2)*4096)/(Vout_act-1);} - if(vfactor_f==4096) - {vfactor = 0x1000;} - else if(vfactor_f>(int)vfactor_f) - {vfactor = (int)vfactor_f+1;} - else - {vfactor = (int)vfactor_f;} - - HV2.scl_h= hfactor; - HV2.scl_v= vfactor; - /* SCL FACTOR */ - c = SCL_H_FACTOR_LSB(HV2.scl_h); - rk610_scaler_write_p0_reg(client, SCL_CON1, &c); - c = SCL_H_FACTOR_MSB(HV2.scl_h); - rk610_scaler_write_p0_reg(client, SCL_CON2, &c); - - c = SCL_V_FACTOR_LSB(HV2.scl_v); - rk610_scaler_write_p0_reg(client, SCL_CON3, &c); - c = SCL_V_FACTOR_MSB(HV2.scl_v); - rk610_scaler_write_p0_reg(client, SCL_CON4, &c); - return 0; - } - -static int rk610_scaler_fator_config(struct i2c_client *client ,struct rk29fb_screen *screen) -{ - switch(screen->hdmi_resolution){ - case HDMI_1920x1080p_60Hz: - case HDMI_1920x1080p_50Hz: - rk610_scaler_pll_set(client,screen,148500000); - /***************set scaler factor********************/ - scale_hv_factor(client,1920,screen->x_res,1080,screen->y_res); - break; - case HDMI_1280x720p_60Hz: - case HDMI_1280x720p_50Hz: - rk610_scaler_pll_set(client,screen,74250000); - /***************set scaler factor********************/ - scale_hv_factor(client,1280,screen->x_res,720,screen->y_res); - break; - case HDMI_720x576p_50Hz_16_9: - case HDMI_720x576p_50Hz_4_3: - rk610_scaler_pll_set(client,screen,27000000); - /***************set scaler factor********************/ - scale_hv_factor(client,720,screen->x_res,576,screen->y_res); - break; - case HDMI_720x480p_60Hz_16_9: - case HDMI_720x480p_60Hz_4_3: - rk610_scaler_pll_set(client,screen,27000000); - /***************set scaler factor********************/ - scale_hv_factor(client,720,screen->x_res,480,screen->y_res); - break; - default : - RK610_ERR(&client->dev,"RK610 not support dual display at hdmi resolution=%d \n",screen->hdmi_resolution); - return -1; - break; - } - return 0; -} -static int rk610_scaler_output_timing_config(struct i2c_client *client,struct rk29fb_screen *screen) -{ - char c; - int h_st = screen->s_hsync_st; - int hs_end = screen->s_hsync_len; - int h_act_st = hs_end + screen->s_left_margin; - int xres = screen->x_res; - int h_act_end = h_act_st + xres; - int h_total = h_act_end + screen->s_right_margin; - int v_st = screen->s_vsync_st; - int vs_end = screen->s_vsync_len; - int v_act_st = vs_end + screen->s_upper_margin; - int yres = screen->y_res; - int v_act_end = v_act_st + yres; - int v_total = v_act_end + screen->s_lower_margin; - - /* SCL display Frame start point */ - c = SCL_DSP_HST_LSB(h_st); - rk610_scaler_write_p0_reg(client, SCL_CON5, &c); - c = SCL_DSP_HST_MSB(h_st); - rk610_scaler_write_p0_reg(client, SCL_CON6, &c); - - c = SCL_DSP_VST_LSB(v_st); - rk610_scaler_write_p0_reg(client, SCL_CON7, &c); - c = SCL_DSP_VST_MSB(v_st); - rk610_scaler_write_p0_reg(client, SCL_CON8, &c); - /* SCL output timing */ - - c = SCL_DSP_HTOTAL_LSB(h_total); - rk610_scaler_write_p0_reg(client, SCL_CON9, &c); - c = SCL_DSP_HTOTAL_MSB(h_total); - rk610_scaler_write_p0_reg(client, SCL_CON10, &c); - - c = SCL_DSP_HS_END(hs_end); - rk610_scaler_write_p0_reg(client, SCL_CON11, &c); - - c = SCL_DSP_HACT_ST_LSB(h_act_st); - rk610_scaler_write_p0_reg(client, SCL_CON12, &c); - c = SCL_DSP_HACT_ST_MSB(h_act_st); - rk610_scaler_write_p0_reg(client, SCL_CON13, &c); - - c = SCL_DSP_HACT_END_LSB(h_act_end); - rk610_scaler_write_p0_reg(client, SCL_CON14, &c); - c = SCL_DSP_HACT_END_MSB(h_act_end); - rk610_scaler_write_p0_reg(client, SCL_CON15, &c); - - c = SCL_DSP_VTOTAL_LSB(v_total); - rk610_scaler_write_p0_reg(client, SCL_CON16, &c); - c = SCL_DSP_VTOTAL_MSB(v_total); - rk610_scaler_write_p0_reg(client, SCL_CON17, &c); - - c = SCL_DSP_VS_END(vs_end); - rk610_scaler_write_p0_reg(client, SCL_CON18, &c); - - c = SCL_DSP_VACT_ST(v_act_st); - rk610_scaler_write_p0_reg(client, SCL_CON19, &c); - - c = SCL_DSP_VACT_END_LSB(v_act_end); - rk610_scaler_write_p0_reg(client, SCL_CON20, &c); - c = SCL_DSP_VACT_END_MSB(v_act_end); - rk610_scaler_write_p0_reg(client, SCL_CON21, &c); - - c = SCL_H_BORD_ST_LSB(h_act_st); - rk610_scaler_write_p0_reg(client, SCL_CON22, &c); - c = SCL_H_BORD_ST_MSB(h_act_st); - rk610_scaler_write_p0_reg(client, SCL_CON23, &c); - - c = SCL_H_BORD_END_LSB(h_act_end); - rk610_scaler_write_p0_reg(client, SCL_CON24, &c); - c = SCL_H_BORD_END_MSB(h_act_end); - rk610_scaler_write_p0_reg(client, SCL_CON25, &c); - - c = SCL_V_BORD_ST(v_act_st); - rk610_scaler_write_p0_reg(client, SCL_CON26, &c); - - c = SCL_V_BORD_END_LSB(v_act_end); - rk610_scaler_write_p0_reg(client, SCL_CON27, &c); - c = SCL_V_BORD_END_MSB(v_act_end); - rk610_scaler_write_p0_reg(client, SCL_CON28, &c); - - return 0; -} -static int rk610_scaler_chg(struct i2c_client *client ,struct rk29fb_screen *screen) -{ - - RK610_DBG(&client->dev,"%s screen->hdmi_resolution=%d\n",__FUNCTION__,screen->hdmi_resolution); - rk610_scaler_fator_config(client,screen); - rk610_scaler_enable(client); - rk610_scaler_output_timing_config(client,screen); - - return 0; - -} -#endif -static int rk610_lcd_scaler_bypass(struct i2c_client *client,bool enable)//enable:0 bypass 1: scale -{ - RK610_DBG(&client->dev,"%s \n",__FUNCTION__); - - rk610_scaler_disable(client); - rk610_scaler_pll_disable(client); - - return 0; -} - -#ifdef CONFIG_HAS_EARLYSUSPEND -static void rk610_lcd_early_suspend(struct early_suspend *h) -{ - struct i2c_client *client = g_lcd_inf->client; - char c; - RK610_DBG(&client->dev,"%s \n",__FUNCTION__); - if(g_lcd_inf->screen != NULL){ - rk610_output_config(client,g_lcd_inf->screen,LCD_OUT_DISABLE); - } - - if(ENABLE == g_lcd_inf->scl_inf.scl_pwr){ - c= SCL_BYPASS(1) |SCL_DEN_INV(0) |SCL_H_V_SYNC_INV(0) |SCL_OUT_CLK_INV(0) |SCL_ENABLE(DISABLE); - rk610_scaler_write_p0_reg(client, SCL_CON0, &c); - } - if(ENABLE == g_lcd_inf->scl_inf.pll_pwr ){ - c = S_PLL_PWR(1) |S_PLL_RESET(0) |S_PLL_BYPASS(1); - rk610_scaler_write_p0_reg(client, S_PLL_CON2, &c); - } -} - -static void rk610_lcd_early_resume(struct early_suspend *h) -{ - struct i2c_client *client = g_lcd_inf->client; - char c; - RK610_DBG(&client->dev,"%s \n",__FUNCTION__); - - if(g_lcd_inf->screen != NULL){ - rk610_output_config(client,g_lcd_inf->screen,g_lcd_inf->disp_mode); - } - if(ENABLE == g_lcd_inf->scl_inf.scl_pwr){ - c= SCL_BYPASS(0) |SCL_DEN_INV(0) |SCL_H_V_SYNC_INV(0) |SCL_OUT_CLK_INV(0) |SCL_ENABLE(ENABLE); - rk610_scaler_write_p0_reg(client, SCL_CON0, &c); - } - if(ENABLE == g_lcd_inf->scl_inf.pll_pwr ){ - c = S_PLL_PWR(1) |S_PLL_RESET(0) |S_PLL_BYPASS(1); - rk610_scaler_write_p0_reg(client, S_PLL_CON2, &c); - } -} -#endif -int rk610_lcd_scaler_set_param(struct rk29fb_screen *screen,bool enable )//enable:0 bypass 1: scale -{ - int ret=0; - struct i2c_client *client = g_lcd_inf->client; - if(client == NULL){ - printk("%s client == NULL FAIL\n",__FUNCTION__); - return -1; - } - if(screen == NULL){ - printk("%s screen == NULL FAIL\n",__FUNCTION__); - return -1; - } - RK610_DBG(&client->dev,"%s \n",__FUNCTION__); - - g_lcd_inf->screen = screen; - -#if defined(CONFIG_HDMI_DUAL_DISP) || defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF) - if(enable == 1){ - g_lcd_inf->disp_mode = LCD_OUT_SCL; - rk610_output_config(client,screen,LCD_OUT_SCL); - ret = rk610_scaler_chg(client,screen); - } - else -#endif - { - g_lcd_inf->disp_mode = LCD_OUT_BYPASS; - rk610_output_config(client,screen,LCD_OUT_BYPASS); - ret = rk610_lcd_scaler_bypass(client,enable); - } - return ret; -} -int rk610_lcd_init(struct rk610_core_info *rk610_core_info) -{ - if(rk610_core_info->client == NULL){ - printk("%s client == NULL FAIL\n",__FUNCTION__); - return -1; - } - RK610_DBG(&rk610_core_info->client->dev,"%s \n",__FUNCTION__); - - g_lcd_inf = kmalloc(sizeof(struct rk610_lcd_info), GFP_KERNEL); - if(!g_lcd_inf) - { - dev_err(&rk610_core_info->client->dev, ">> rk610 inf kmalloc fail!"); - return -ENOMEM; - } - memset(g_lcd_inf, 0, sizeof(struct rk610_lcd_info)); - - g_lcd_inf->client= rk610_core_info->client; - - rk610_core_info->lcd_pdata = (void *)g_lcd_inf; -#ifdef CONFIG_HAS_EARLYSUSPEND - g_lcd_inf->early_suspend.suspend = rk610_lcd_early_suspend; - g_lcd_inf->early_suspend.resume = rk610_lcd_early_resume; - g_lcd_inf->early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB- 1; - register_early_suspend(&g_lcd_inf->early_suspend); -#endif - g_lcd_inf->scl_inf.pll_pwr = DISABLE; - g_lcd_inf->scl_inf.scl_pwr = DISABLE; - g_lcd_inf->disp_mode = LCD_OUT_BYPASS; - return 0; -} diff --git a/drivers/video/display/transmitter/rk610_lcd.h b/drivers/video/display/transmitter/rk610_lcd.h deleted file mode 100644 index 7b3376c69955..000000000000 --- a/drivers/video/display/transmitter/rk610_lcd.h +++ /dev/null @@ -1,230 +0,0 @@ -#ifndef _RK610_LCD_H -#define _RK610_LCD_H -#include -#include -#define ENABLE 1 -#define DISABLE 0 - -//LVDS lane input format -#define DATA_D0_MSB 0 -#define DATA_D7_MSB 1 -//LVDS input source -#define FROM_LCD1 0 -#define FROM_LCD0_OR_SCL 1 - -/* LCD1 config */ -#define LCD1_AS_IN 0 -#define LCD1_AS_OUT 1 - -//LCD1 output source -#define LCD1_FROM_LCD0 0 -#define LCD1_FROM_SCL 1 - -//SCALER config -#define NOBYPASS 0 -#define BYPASS 1 - -//SCALER PLL config -#define S_PLL_PWR_ON 0 -#define S_PLL_PWR_DOWN 1 - -/* clock config */ -#define S_PLL_FROM_DIV 0 -#define S_PLL_FROM_CLKIN 1 -#define S_PLL_DIV(x) ((x)&0x7) -/*********S_PLL_CON************/ -//S_PLL_CON0 -#define S_DIV_N(x) (((x)&0xf)<<4) -#define S_DIV_OD(x) (((x)&3)<<0) -//S_PLL_CON1 -#define S_DIV_M(x) ((x)&0xff) -//S_PLL_CON2 -#define S_PLL_UNLOCK (0<<7) //0:unlock 1:pll_lock -#define S_PLL_LOCK (1<<7) //0:unlock 1:pll_lock -#define S_PLL_PWR(x) (((x)&1)<<2) //0:POWER UP 1:POWER DOWN -#define S_PLL_RESET(x) (((x)&1)<<1) //0:normal 1:reset M/N dividers -#define S_PLL_BYPASS(x) (((x)&1)<<0) //0:normal 1:bypass -//LVDS_CON0 -#define LVDS_OUT_CLK_PIN(x) (((x)&1)<<7) //clk enable pin, 0: enable -#define LVDS_OUT_CLK_PWR_PIN(x) (((x)&1)<<6) //clk pwr enable pin, 1: enable -#define LVDS_PLL_PWR_PIN(x) (((x)&1)<<5) //pll pwr enable pin, 0:enable -#define LVDS_BIASE_PWR(x) (((x)&1)<<4) //0: power down 1: normal work -#define LVDS_LANE_IN_FORMAT(x) (((x)&1)<<3) //0: msb on D0 1:msb on D7 -#define LVDS_INPUT_SOURCE(x) (((x)&1)<<2) //0: from lcd1 1:from lcd0 or scaler -#define LVDS_OUTPUT_FORMAT(x) (((x)&3)<<0) //00:8bit format-1 01:8bit format-2 10:8bit format-3 11:6bit format -//LVDS_CON1 -#define LVDS_OUT_ENABLE(x) (((x)&0xf)<<4) //0:output enable 1:output disable -#define LVDS_TX_PWR_ENABLE(x) (((x)&0xf)<<0) //0:working mode 1:power down -//LCD1_CON -#define LCD1_OUT_ENABLE(x) (((x)&1)<<1) //0:lcd1 as input 1:lcd1 as output -#define LCD1_OUT_SRC(x) (((x)&1)<<0) //0:from lcd0 1:from scaler -//SCL_CON0 -#define SCL_BYPASS(x) (((x)&1)<<4) //0:not bypass 1:bypass -#define SCL_DEN_INV(x) (((x)&1)<<3) //scl_den_inv -#define SCL_H_V_SYNC_INV(x) (((x)&1)<<2) //scl_sync_inv -#define SCL_OUT_CLK_INV(x) (((x)&1)<<1) //scl_dclk_inv -#define SCL_ENABLE(x) (((x)&1)<<0) //scaler enable -//SCL_CON1 -#define SCL_H_FACTOR_LSB(x) ((x)&0xff) //scl_h_factor[7:0] -//SCL_CON2 -#define SCL_H_FACTOR_MSB(x) (((x)>>8)&0x3f) //scl_h_factor[13:8] -//SCL_CON3 -#define SCL_V_FACTOR_LSB(x) ((x)&0xff) //scl_v_factor[7:0] -//SCL_CON4 -#define SCL_V_FACTOR_MSB(x) (((x)>>8)&0x3f) //scl_v_factor[13:8] -//SCL_CON5 -#define SCL_DSP_HST_LSB(x) ((x)&0xff) //dsp_frame_hst[7:0] -//SCL_CON6 -#define SCL_DSP_HST_MSB(x) (((x)>>8)&0xf) //dsp_frame_hst[11:8] -//SCL_CON7 -#define SCL_DSP_VST_LSB(x) ((x)&0xff) //dsp_frame_vst[7:0] -//SCL_CON8 -#define SCL_DSP_VST_MSB(x) (((x)>>8)&0xf) //dsp_frame_vst[11:8] -//SCL_CON9 -#define SCL_DSP_HTOTAL_LSB(x) ((x)&0xff) //dsp_frame_htotal[7:0] -//SCL_CON10 -#define SCL_DSP_HTOTAL_MSB(x) (((x)>>8)&0xf) //dsp_frame_htotal[11:8] -//SCL_CON11 -#define SCL_DSP_HS_END(x) ((x)&0xff) //dsp_hs_end -//SCL_CON12 -#define SCL_DSP_HACT_ST_LSB(x) ((x)&0xff) //dsp_hact_st[7:0] -//SCL_CON13 -#define SCL_DSP_HACT_ST_MSB(x) (((x)>>8)&0x3) //dsp_hact_st[9:8] -//SCL_CON14 -#define SCL_DSP_HACT_END_LSB(x) ((x)&0xff) //dsp_hact_end[7:0] -//SCL_CON15 -#define SCL_DSP_HACT_END_MSB(x) (((x)>>8)&0xf) //dsp_frame_htotal[11:8] -//SCL_CON16 -#define SCL_DSP_VTOTAL_LSB(x) ((x)&0xff) //dsp_frame_vtotal[7:0] -//SCL_CON17 -#define SCL_DSP_VTOTAL_MSB(x) (((x)>>8)&0xf) //dsp_frame_vtotal[11:8] -//SCL_CON18 -#define SCL_DSP_VS_END(x) ((x)&0xff) //dsp_vs_end -//SCL_CON19 -#define SCL_DSP_VACT_ST(x) ((x)&0xff) //dsp_vact_st[7:0] -//SCL_CON20 -#define SCL_DSP_VACT_END_LSB(x) ((x)&0xff) //dsp_vact_end[7:0] -//SCL_CON21 -#define SCL_DSP_VACT_END_MSB(x) (((x)>>8)&0xf) //dsp_frame_vtotal[11:8] -//SCL_CON22 -#define SCL_H_BORD_ST_LSB(x) ((x)&0xff) //dsp_hbord_st[7:0] -//SCL_CON23 -#define SCL_H_BORD_ST_MSB(x) (((x)>>8)&0x3) //dsp_hbord_st[9:8] -//SCL_CON24 -#define SCL_H_BORD_END_LSB(x) ((x)&0xff) //dsp_hbord_end[7:0] -//SCL_CON25 -#define SCL_H_BORD_END_MSB(x) (((x)>>8)&0xf) //dsp_hbord_end[11:8] -//SCL_CON26 -#define SCL_V_BORD_ST(x) ((x)&0xff) //dsp_vbord_st[7:0] -//SCL_CON27 -#define SCL_V_BORD_END_LSB(x) ((x)&0xff) //dsp_vbord_end[7:0] -//SCL_CON25 -#define SCL_V_BORD_END_MSB(x) (((x)>>8)&0xf) //dsp_vbord_end[11:8] - -/* Scaler PLL CONFIG */ -#define S_PLL_NO_1 0 -#define S_PLL_NO_2 1 -#define S_PLL_NO_4 2 -#define S_PLL_NO_8 3 -#define S_PLL_M(x) (((x)&0xff)<<8) -#define S_PLL_N(x) (((x)&0xf)<<4) -#define S_PLL_NO(x) ((S_PLL_NO_##x)&0x3) - -enum{ - HDMI_RATE_148500000, - HDMI_RATE_74250000, - HDMI_RATE_27000000, -}; -/* Scaler clk setting */ -#define SCALE_PLL(_parent_rate,_rate,_m,_n,_no) \ - HDMI_RATE_ ## _parent_rate ##_S_RATE_ ## _rate \ - = S_PLL_M(_m) | S_PLL_N(_n) | S_PLL_NO(_no) -#define SCALE_RATE(_parent_rate , _rate) \ - (HDMI_RATE_ ## _parent_rate ## _S_RATE_ ## _rate) - -enum{ - SCALE_PLL(148500000, 66000000, 16, 9, 4), - SCALE_PLL(148500000, 57375000, 17, 11, 4), - SCALE_PLL(148500000, 54000000, 16, 11, 4), - SCALE_PLL(148500000, 33000000, 16, 9, 8), - SCALE_PLL(148500000, 30375000, 18, 11, 8), - SCALE_PLL(148500000, 29700000, 16, 10, 8), - SCALE_PLL(148500000, 25312500, 15, 11, 8), - SCALE_PLL(148500000, 74250000, 12, 6, 4), - SCALE_PLL(148500000, 50625000, 15, 11, 4), - SCALE_PLL(148500000, 79199997, 32, 15, 4), - SCALE_PLL(148500000, 45375000, 22, 9, 8), - - SCALE_PLL(74250000, 66000000, 32, 9, 4), - SCALE_PLL(74250000, 57375000, 34, 11, 4), - SCALE_PLL(74250000, 54000000, 32, 11, 4), - SCALE_PLL(74250000, 33000000, 32, 9, 8), - SCALE_PLL(74250000, 30375000, 36, 11, 8), - SCALE_PLL(74250000, 25312500, 30, 11, 8), - SCALE_PLL(74250000, 74250000, 12, 3, 4), - SCALE_PLL(74250000, 67500000, 40, 11, 4), - SCALE_PLL(74250000, 50625000, 30, 11, 4), - SCALE_PLL(74250000, 79199997, 64,15,4), - SCALE_PLL(74250000, 44343750, 43, 9, 8), - - SCALE_PLL(27000000, 75000000, 100, 9, 4), - SCALE_PLL(27000000, 72000000, 32, 3, 4), - SCALE_PLL(27000000, 63281250, 75, 4, 8), - SCALE_PLL(27000000, 60000000, 80, 9, 4), - SCALE_PLL(27000000, 54375000, 145, 9, 8), - SCALE_PLL(27000000, 31500000, 28, 3, 8), - SCALE_PLL(27000000, 30000000, 80, 9, 8), - SCALE_PLL(27000000, 70312500, 125, 6, 8), - SCALE_PLL(27000000, 46875000, 125, 9, 8), - SCALE_PLL(27000000, 56250000, 25, 3, 4) -}; - -enum { - LCD_OUT_SCL, - LCD_OUT_BYPASS, - LCD_OUT_DISABLE, -}; -struct rk610_pll_info{ - u32 parent_rate; - u32 rate; - int m; - int n; - int od; -}; -struct lcd_mode_inf{ - int h_pw; - int h_bp; - int h_vd; - int h_fp; - int v_pw; - int v_bp; - int v_vd; - int v_fp; - int f_hst; - int f_vst; - struct rk610_pll_info pllclk; -}; -struct scl_hv_info{ - int scl_h ; - int scl_v; - }; - -struct scl_info{ - bool pll_pwr; - bool scl_pwr; - struct scl_hv_info scl_hv; -}; -struct rk610_lcd_info{ - int disp_mode; - - struct rk29fb_screen *screen; - struct scl_info scl_inf; - struct i2c_client *client; - -#ifdef CONFIG_HAS_EARLYSUSPEND - struct early_suspend early_suspend; -#endif -}; -extern int rk610_lcd_init(struct rk610_core_info *rk610_core_info); -extern int rk610_lcd_scaler_set_param(struct rk29fb_screen *screen,bool enable ); -#endif diff --git a/drivers/video/display/transmitter/rk616_lvds.c b/drivers/video/display/transmitter/rk616_lvds.c deleted file mode 100644 index fd1339481755..000000000000 --- a/drivers/video/display/transmitter/rk616_lvds.c +++ /dev/null @@ -1,223 +0,0 @@ -#include -#include -#include -#include -#include "rk616_lvds.h" - -struct rk616_lvds *g_lvds; - - -static int rk616_lvds_cfg(struct mfd_rk616 *rk616,rk_screen *screen) -{ - struct rk616_route *route = &rk616->route; - u32 val = 0; - int ret; - int odd = (screen->left_margin&0x01)?0:1; - - if(!route->lvds_en) //lvds port is not used ,power down lvds - { - val &= ~(LVDS_CH1TTL_EN | LVDS_CH0TTL_EN | LVDS_CH1_PWR_EN | - LVDS_CH0_PWR_EN | LVDS_CBG_PWR_EN); - val |= LVDS_PLL_PWR_DN | (LVDS_CH1TTL_EN << 16) | (LVDS_CH0TTL_EN << 16) | - (LVDS_CH1_PWR_EN << 16) | (LVDS_CH0_PWR_EN << 16) | - (LVDS_CBG_PWR_EN << 16) | (LVDS_PLL_PWR_DN << 16); - ret = rk616->write_dev(rk616,CRU_LVDS_CON0,&val); - - if(!route->lcd1_input) //set lcd1 port for output as RGB interface - { - val = (LCD1_INPUT_EN << 16); - ret = rk616->write_dev(rk616,CRU_IO_CON0,&val); - } - } - else - { - if(route->lvds_mode) //lvds mode - { - - if(route->lvds_ch_nr == 2) //dual lvds channel - { - val = 0; - val &= ~(LVDS_CH0TTL_EN | LVDS_CH1TTL_EN | LVDS_PLL_PWR_DN); - val = (LVDS_DCLK_INV)|(LVDS_CH1_PWR_EN) |(LVDS_CH0_PWR_EN) | LVDS_HBP_ODD(odd) | - (LVDS_CBG_PWR_EN) | (LVDS_CH_SEL) | (LVDS_OUT_FORMAT(screen->hw_format)) | - (LVDS_CH0TTL_EN << 16) | (LVDS_CH1TTL_EN << 16) |(LVDS_CH1_PWR_EN << 16) | - (LVDS_CH0_PWR_EN << 16) | (LVDS_CBG_PWR_EN << 16) | (LVDS_CH_SEL << 16) | - (LVDS_OUT_FORMAT_MASK) | (LVDS_DCLK_INV << 16) | (LVDS_PLL_PWR_DN << 16) | - (LVDS_HBP_ODD_MASK); - ret = rk616->write_dev(rk616,CRU_LVDS_CON0,&val); - - dev_info(rk616->dev,"rk616 use dual lvds channel.......\n"); - } - else //single lvds channel - { - val = 0; - val &= ~(LVDS_CH0TTL_EN | LVDS_CH1TTL_EN | LVDS_CH1_PWR_EN | LVDS_PLL_PWR_DN | LVDS_CH_SEL); //use channel 0 - val |= (LVDS_CH0_PWR_EN) |(LVDS_CBG_PWR_EN) | (LVDS_OUT_FORMAT(screen->hw_format)) | - (LVDS_CH0TTL_EN << 16) | (LVDS_CH1TTL_EN << 16) |(LVDS_CH0_PWR_EN << 16) | - (LVDS_DCLK_INV ) | (LVDS_CH0TTL_EN << 16) | (LVDS_CH1TTL_EN << 16) |(LVDS_CH0_PWR_EN << 16) | - (LVDS_CBG_PWR_EN << 16)|(LVDS_CH_SEL << 16) | (LVDS_PLL_PWR_DN << 16)| - (LVDS_OUT_FORMAT_MASK) | (LVDS_DCLK_INV << 16); - ret = rk616->write_dev(rk616,CRU_LVDS_CON0,&val); - - dev_info(rk616->dev,"rk616 use single lvds channel.......\n"); - - } - - } - else //mux lvds port to RGB mode - { - val &= ~(LVDS_CBG_PWR_EN| LVDS_CH1_PWR_EN | LVDS_CH0_PWR_EN); - val |= (LVDS_CH0TTL_EN)|(LVDS_CH1TTL_EN )|(LVDS_PLL_PWR_DN)| - (LVDS_CH0TTL_EN<< 16)|(LVDS_CH1TTL_EN<< 16)|(LVDS_CH1_PWR_EN << 16) | - (LVDS_CH0_PWR_EN << 16)|(LVDS_CBG_PWR_EN << 16)|(LVDS_PLL_PWR_DN << 16); - ret = rk616->write_dev(rk616,CRU_LVDS_CON0,&val); - - val &= ~(LVDS_OUT_EN); - val |= (LVDS_OUT_EN << 16); - ret = rk616->write_dev(rk616,CRU_IO_CON0,&val); - dev_info(rk616->dev,"rk616 use RGB output.....\n"); - - } - } - - return 0; - -} - - -static int rk616_dither_cfg(struct mfd_rk616 *rk616,rk_screen *screen,bool enable) -{ - u32 val = 0; - int ret = 0; - val = FRC_DCLK_INV | (FRC_DCLK_INV << 16); - if((screen->face != OUT_P888) && enable) //enable frc dither if the screen is not 24bit - val |= FRC_DITHER_EN | (FRC_DITHER_EN << 16); - //val |= (FRC_DITHER_EN << 16); - else - val |= (FRC_DITHER_EN << 16); - ret = rk616->write_dev(rk616,FRC_REG,&val); - - return 0; - -} - - - - -int rk610_lcd_scaler_set_param(rk_screen *screen,bool enable )//enable:0 bypass 1: scale -{ - int ret; - struct mfd_rk616 *rk616 = g_lvds->rk616; - if(!rk616) - { - printk(KERN_ERR "%s:mfd rk616 is null!\n",__func__); - return -1; - } - g_lvds->screen = screen; - ret = rk616_display_router_cfg(rk616,screen,enable); - - ret = rk616_dither_cfg(rk616,screen,enable); - ret = rk616_lvds_cfg(rk616,screen); - return ret; -} - - - -#if defined(CONFIG_HAS_EARLYSUSPEND) -static void rk616_lvds_early_suspend(struct early_suspend *h) -{ - struct rk616_lvds *lvds = container_of(h, struct rk616_lvds,early_suspend); - struct mfd_rk616 *rk616 = lvds->rk616; - u32 val = 0; - int ret = 0; - - val &= ~(LVDS_CH1_PWR_EN | LVDS_CH0_PWR_EN | LVDS_CBG_PWR_EN); - val |= LVDS_PLL_PWR_DN |(LVDS_CH1_PWR_EN << 16) | (LVDS_CH0_PWR_EN << 16) | - (LVDS_CBG_PWR_EN << 16) | (LVDS_PLL_PWR_DN << 16); - ret = rk616->write_dev(rk616,CRU_LVDS_CON0,&val); - - val = LCD1_INPUT_EN | (LCD1_INPUT_EN << 16); - ret = rk616->write_dev(rk616,CRU_IO_CON0,&val); - - -} - -static void rk616_lvds_late_resume(struct early_suspend *h) -{ - struct rk616_lvds *lvds = container_of(h, struct rk616_lvds,early_suspend); - struct mfd_rk616 *rk616 = lvds->rk616; - rk616_lvds_cfg(rk616,lvds->screen); -} - -#endif - -static int rk616_lvds_probe(struct platform_device *pdev) -{ - struct rk616_lvds *lvds = NULL; - struct mfd_rk616 *rk616 = NULL; - - lvds = kzalloc(sizeof(struct rk616_lvds),GFP_KERNEL); - if(!lvds) - { - printk(KERN_ALERT "alloc for struct rk616_lvds fail\n"); - return -ENOMEM; - } - - rk616 = dev_get_drvdata(pdev->dev.parent); - if(!rk616) - { - dev_err(&pdev->dev,"null mfd device rk616!\n"); - return -ENODEV; - } - else - g_lvds = lvds; - lvds->rk616 = rk616; - -#ifdef CONFIG_HAS_EARLYSUSPEND - lvds->early_suspend.suspend = rk616_lvds_early_suspend; - lvds->early_suspend.resume = rk616_lvds_late_resume; - lvds->early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB - 1; - register_early_suspend(&lvds->early_suspend); -#endif - - - dev_info(&pdev->dev,"rk616 lvds probe success!\n"); - - return 0; - -} - -static int rk616_lvds_remove(struct platform_device *pdev) -{ - - return 0; -} - -static void rk616_lvds_shutdown(struct platform_device *pdev) -{ - - return; -} - -static struct platform_driver rk616_lvds_driver = { - .driver = { - .name = "rk616-lvds", - .owner = THIS_MODULE, - }, - .probe = rk616_lvds_probe, - .remove = rk616_lvds_remove, - .shutdown = rk616_lvds_shutdown, -}; - -static int __init rk616_lvds_init(void) -{ - return platform_driver_register(&rk616_lvds_driver); -} -subsys_initcall_sync(rk616_lvds_init); - -static void __exit rk616_lvds_exit(void) -{ - platform_driver_unregister(&rk616_lvds_driver); -} -module_exit(rk616_lvds_exit); - diff --git a/drivers/video/display/transmitter/rk616_lvds.h b/drivers/video/display/transmitter/rk616_lvds.h deleted file mode 100644 index 2b6b27427ad4..000000000000 --- a/drivers/video/display/transmitter/rk616_lvds.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef __RK616_VIF_H__ -#define __RK616_VIF_H__ -#include -#include -#include - - -struct rk616_lvds { - struct mfd_rk616 *rk616; - rk_screen *screen; -#ifdef CONFIG_HAS_EARLYSUSPEND - struct early_suspend early_suspend; -#endif -}; - -#endif diff --git a/drivers/video/display/transmitter/ssd2828.c b/drivers/video/display/transmitter/ssd2828.c deleted file mode 100644 index 74bb6b3876d2..000000000000 --- a/drivers/video/display/transmitter/ssd2828.c +++ /dev/null @@ -1,689 +0,0 @@ -/* - * Copyright (C) 2012 ROCKCHIP, Inc. - * drivers/video/display/transmitter/ssd2828.c - * author: hhb@rock-chips.com - * create date: 2013-01-17 - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include "mipi_dsi.h" -#include -#include -#include - - -/* define spi gpio*/ -#define TXD_PORT ssd2828->spi.mosi -#define CLK_PORT ssd2828->spi.sck -#define CS_PORT ssd2828->spi.cs -#define RXD_PORT ssd2828->spi.miso - -#define CS_OUT() gpio_direction_output(CS_PORT, 0) -#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) -#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) -#define CLK_OUT() gpio_direction_output(CLK_PORT, 0) -#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) -#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) -#define TXD_OUT() gpio_direction_output(TXD_PORT, 0) -#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) -#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) -#define RXD_INPUT() gpio_direction_input(RXD_PORT) -#define RXD_GET() gpio_get_value(RXD_PORT) - - -struct ssd2828_t *ssd2828 = NULL; -void ssd_set_register(unsigned int reg_and_value); - -int ssd2828_gpio_init(void *data) { - int ret = 0; - struct reset_t *reset = &ssd2828->reset; - struct power_t *vdd = &ssd2828->vddio; - struct spi_t *spi = &ssd2828->spi; - - if(reset->reset_pin > INVALID_GPIO) { - ret = gpio_request(reset->reset_pin, "ssd2828_reset"); - if (ret != 0) { - //gpio_free(reset->reset_pin); - printk("%s: request ssd2828_RST_PIN error\n", __func__); - } else { -#if OLD_RK_IOMUX - if(reset->mux_name) - rk30_mux_api_set(reset->mux_name, 0); -#endif - gpio_direction_output(reset->reset_pin, !reset->effect_value); - } - } - - if(vdd->enable_pin > INVALID_GPIO) { - ret = gpio_request(vdd->enable_pin, "ssd2828_vddio"); - if (ret != 0) { - //gpio_free(vdd->enable_pin); - printk("%s: request ssd2828_vddio_PIN error\n", __func__); - } else { -#if OLD_RK_IOMUX - if(vdd->mux_name) - rk30_mux_api_set(vdd->mux_name, 0); -#endif - gpio_direction_output(vdd->enable_pin, !vdd->effect_value); - } - } - - vdd = &ssd2828->vdd_mipi; - if(vdd->enable_pin > INVALID_GPIO) { - ret = gpio_request(vdd->enable_pin, "ssd2828_vdd_mipi"); - if (ret != 0) { - //gpio_free(vdd->enable_pin); - printk("%s: request ssd2828_vdd_mipi_PIN error\n", __func__); - } else { -#if OLD_RK_IOMUX - if(vdd->mux_name) - rk30_mux_api_set(vdd->mux_name, 0); -#endif - gpio_direction_output(vdd->enable_pin, !vdd->effect_value); - } - } - - vdd = &ssd2828->shut; - if(vdd->enable_pin > INVALID_GPIO) { - ret = gpio_request(vdd->enable_pin, "ssd2828_shut"); - if (ret != 0) { - //gpio_free(vdd->enable_pin); - printk("%s: request ssd2828_shut_PIN error\n", __func__); - } else { -#if OLD_RK_IOMUX - if(vdd->mux_name) - rk30_mux_api_set(vdd->mux_name, 0); -#endif - gpio_direction_output(vdd->enable_pin, !vdd->effect_value); - } - } - - if(spi->cs > INVALID_GPIO) { - ret = gpio_request(spi->cs, "ssd2828_spi_cs"); - if (ret != 0) { - //gpio_free(spi->cs); - printk("%s: request ssd2828_spi->cs_PIN error\n", __func__); - } else { -#if OLD_RK_IOMUX - if(spi->cs_mux_name) - rk30_mux_api_set(spi->cs_mux_name, 0); -#endif - gpio_direction_output(spi->cs, GPIO_HIGH); - } - } - if(spi->sck > INVALID_GPIO) { - ret = gpio_request(spi->sck, "ssd2828_spi_sck"); - if (ret != 0) { - //gpio_free(spi->sck); - printk("%s: request ssd2828_spi->sck_PIN error\n", __func__); - } else { -#if OLD_RK_IOMUX - if(spi->sck_mux_name) - rk30_mux_api_set(spi->sck_mux_name, 0); -#endif - gpio_direction_output(spi->sck, GPIO_HIGH); - } - } - if(spi->mosi > INVALID_GPIO) { - ret = gpio_request(spi->mosi, "ssd2828_spi_mosi"); - if (ret != 0) { - //gpio_free(spi->mosi); - printk("%s: request ssd2828_spi->mosi_PIN error\n", __func__); - } else { -#if OLD_RK_IOMUX - if(spi->mosi_mux_name) - rk30_mux_api_set(spi->mosi_mux_name, 0); -#endif - gpio_direction_output(spi->mosi, GPIO_HIGH); - } - } - if(spi->miso > INVALID_GPIO) { - ret = gpio_request(spi->miso, "ssd2828_spi_miso"); - if (ret != 0) { - //gpio_free(spi->miso); - printk("%s: request ssd2828_spi->miso_PIN error\n", __func__); - } else { -#if OLD_RK_IOMUX - if(spi->miso_mux_name) - rk30_mux_api_set(spi->miso_mux_name, 0); -#endif - gpio_direction_input(spi->miso); - } - } - - return 0; - -} - -int ssd2828_gpio_deinit(void *data) { - struct reset_t *reset = &ssd2828->reset; - struct power_t *vdd = &ssd2828->vddio; - struct spi_t *spi = &ssd2828->spi; - - if(reset->reset_pin > INVALID_GPIO) { - gpio_direction_input(reset->reset_pin); - gpio_free(reset->reset_pin); - } - if(vdd->enable_pin > INVALID_GPIO) { - gpio_direction_input(vdd->enable_pin); - gpio_free(vdd->enable_pin); - } - vdd = &ssd2828->vdd_mipi; - if(vdd->enable_pin > INVALID_GPIO) { - gpio_direction_input(vdd->enable_pin); - gpio_free(vdd->enable_pin); - } - vdd = &ssd2828->shut; - if(vdd->enable_pin > INVALID_GPIO) { - gpio_direction_input(vdd->enable_pin); - gpio_free(vdd->enable_pin); - } - if(spi->cs > INVALID_GPIO) { - gpio_direction_input(spi->cs); - gpio_free(spi->cs); - } - if(spi->sck > INVALID_GPIO) { - gpio_direction_input(spi->sck); - gpio_free(spi->sck); - } - if(spi->mosi > INVALID_GPIO) { - gpio_direction_input(spi->mosi); - gpio_free(spi->mosi); - } - if(spi->miso > INVALID_GPIO) { - gpio_free(spi->miso); - } - return 0; -} - -int ssd2828_reset(void *data) { - int ret = 0; - struct reset_t *reset = &ssd2828->reset; - if(reset->reset_pin <= INVALID_GPIO) - return -1; - gpio_set_value(reset->reset_pin, reset->effect_value); - if(reset->time_before_reset <= 0) - msleep(10); - else - msleep(reset->time_before_reset); - - gpio_set_value(reset->reset_pin, !reset->effect_value); - if(reset->time_after_reset <= 0) - msleep(5); - else - msleep(reset->time_after_reset); - return ret; -} - -int ssd2828_vdd_enable(void *data) { - int ret = 0; - struct power_t *vdd = (struct power_t *)data; - if(vdd->enable_pin > INVALID_GPIO) { - gpio_set_value(vdd->enable_pin, vdd->effect_value); - } else if(vdd->name) { - struct regulator *ldo = regulator_get(NULL, vdd->name); - if (ldo == NULL || IS_ERR(ldo) ){ - printk("%s: get %s ldo failed!\n", __func__, vdd->name); - ret = -1; - return ret; - } - regulator_set_voltage(ldo, vdd->voltage, vdd->voltage); - regulator_enable(ldo); - printk(" %s set %s=%dmV end\n", __func__, vdd->name, regulator_get_voltage(ldo)); - regulator_put(ldo); - } - return ret; -} - -int ssd2828_vdd_disable(void *data) { - int ret = 0; - struct power_t *vdd = (struct power_t *)data; - - if(vdd->enable_pin > INVALID_GPIO) { - gpio_set_value(vdd->enable_pin, !vdd->effect_value); - } else if(vdd->name) { - struct regulator *ldo = regulator_get(NULL, vdd->name); - if (ldo == NULL || IS_ERR(ldo) ){ - printk("%s: get %s ldo failed!\n", __func__, vdd->name); - ret = -1; - return ret; - } - while(regulator_is_enabled(ldo) > 0){ - regulator_disable(ldo); - } - regulator_put(ldo); - } - return ret; -} - - -int ssd2828_power_up(void) { - - int ret = 0; - struct ssd2828_t *ssd = (struct ssd2828_t *)ssd2828; - struct spi_t *spi = &ssd2828->spi; - ssd->vdd_mipi.enable(&ssd->vdd_mipi); - ssd->vddio.enable(&ssd->vddio); - ssd->reset.do_reset(&ssd->reset); - ssd->shut.enable(&ssd->shut); - - gpio_direction_output(spi->cs, GPIO_HIGH); - gpio_direction_output(spi->sck, GPIO_LOW); - gpio_direction_input(spi->miso); - gpio_direction_output(spi->mosi, GPIO_LOW); - - return ret; -} - -int ssd2828_power_down(void) { - - int ret = 0; - struct ssd2828_t *ssd = (struct ssd2828_t *)ssd2828; - struct spi_t *spi = &ssd2828->spi; - - ssd->shut.disable(&ssd->shut); - msleep(10); - - ssd_set_register(0x00b70300); - msleep(1); - ssd_set_register(0x00b70304); - msleep(1); - ssd_set_register(0x00b90000); - msleep(10); - - //set all gpio to low to avoid current leakage - gpio_direction_output(spi->cs, GPIO_LOW); - gpio_direction_output(spi->sck, GPIO_LOW); - gpio_direction_output(spi->miso, GPIO_LOW); - gpio_direction_output(spi->mosi, GPIO_LOW); - gpio_direction_output(ssd->reset.reset_pin, GPIO_LOW); - - ssd->vddio.disable(&ssd->vddio); - ssd->vdd_mipi.disable(&ssd->vdd_mipi); - ssd->shut.enable(&ssd->shut); - - return ret; -} - - - -/* spi write a data frame,type mean command or data - 3 wire 24 bit SPI interface -*/ - -static void spi_send_data(unsigned int data) -{ - unsigned int i; - - CS_SET(); - udelay(1); - CLK_SET(); - TXD_SET(); - - CS_CLR(); - udelay(1); - - for (i = 0; i < 24; i++) - { - //udelay(1); - CLK_CLR(); - udelay(1); - if (data & 0x00800000) { - TXD_SET(); - } else { - TXD_CLR(); - } - udelay(1); - CLK_SET(); - udelay(1); - data <<= 1; - } - - TXD_SET(); - CS_SET(); -} - -static void spi_recv_data(unsigned int* data) -{ - unsigned int i = 0, temp = 0x73; //read data - - CS_SET(); - udelay(1); - CLK_SET(); - TXD_SET(); - - CS_CLR(); - udelay(1); - - for(i = 0; i < 8; i++) // 8 bits Data - { - udelay(1); - CLK_CLR(); - if (temp & 0x80) - TXD_SET(); - else - TXD_CLR(); - temp <<= 1; - udelay(1); - CLK_SET(); - udelay(1); - } - udelay(1); - temp = 0; - for(i = 0; i < 16; i++) // 16 bits Data - { - udelay(1); - CLK_CLR(); - udelay(1); - CLK_SET(); - udelay(1); - temp <<= 1; - if(RXD_GET() == GPIO_HIGH) - temp |= 0x01; - - } - - TXD_SET(); - CS_SET(); - *data = temp; -} - -#define DEVIE_ID (0x70 << 16) -void send_ctrl_cmd(unsigned int cmd) -{ - unsigned int out = (DEVIE_ID | cmd ); - spi_send_data(out); -} - -static void send_data_cmd(unsigned int data) -{ - unsigned int out = (DEVIE_ID | (0x2 << 16) | data ); - spi_send_data(out); -} - -unsigned int ssd_read_register(unsigned int reg) { - unsigned int data = 0; - send_ctrl_cmd(reg); - spi_recv_data(&data); - return data; -} - -void ssd_set_register(unsigned int reg_and_value) -{ - send_ctrl_cmd(reg_and_value >> 16); - send_data_cmd(reg_and_value & 0x0000ffff); -} - -int ssd_set_registers(unsigned int reg_array[], int n) { - - int i = 0; - for(i = 0; i < n; i++) { - if(reg_array[i] < 0x00b00000) { //the lowest address is 0xb0 of ssd2828 - if(reg_array[i] < 20000) - udelay(reg_array[i]); - else { - mdelay(reg_array[i]/1000); - } - } else { - ssd_set_register(reg_array[i]); - } - } - return 0; -} - -int ssd_mipi_dsi_send_dcs_packet(unsigned char regs[], int n) { - //unsigned int data = 0, i = 0; - ssd_set_register(0x00B70343); // - ssd_set_register(0x00B80000); - ssd_set_register(0x00Bc0001); - - ssd_set_register(0x00Bf0000 | regs[0]); - msleep(1); - ssd_set_register(0x00B7034b); - return 0; -} - - -int _ssd2828_send_packet(unsigned char type, unsigned char regs[], int n) { - - - return 0; -} - -int ssd2828_send_packet(unsigned char type, unsigned char regs[], int n) { - return _ssd2828_send_packet(type, regs, n); -} - -int ssd_mipi_dsi_read_dcs_packet(unsigned char *data, int n) { - //DCS READ - unsigned int i = 0; - - i = ssd_read_register(0xc6); - printk("read mipi slave error:%04x\n", i); - ssd_set_register(0x00B70382); - ssd_set_register(0x00BB0008); - ssd_set_register(0x00C1000A); - ssd_set_register(0x00C00001); - ssd_set_register(0x00Bc0001); - ssd_set_register(0x00Bf0000 | *data); - msleep(10); - i = ssd_read_register(0xc6); - printk("read mipi slave error:%04x\n", i); - - if(i & 1) { - i = ssd_read_register(0xff); - printk("read %02x:%04x\n", *data, i); - i = ssd_read_register(0xff); - printk("read %02x:%04x\n", *data, i); - i = ssd_read_register(0xff); - printk("read %02x:%04x\n", *data, i); - - } - - return 0; -} - - -int ssd2828_get_id(void) { - - int id = -1; - ssd2828_power_up(); - id = ssd_read_register(0xb0); - - return id; -} - -static struct mipi_dsi_ops ssd2828_ops = { - .id = 0x2828, - .name = "ssd2828", - .get_id = ssd2828_get_id, - .dsi_set_regs = ssd_set_registers, - .dsi_send_dcs_packet = ssd_mipi_dsi_send_dcs_packet, - .dsi_read_dcs_packet = ssd_mipi_dsi_read_dcs_packet, - .power_up = ssd2828_power_up, - .power_down = ssd2828_power_down, - -}; - -static struct proc_dir_entry *reg_proc_entry; - -int reg_proc_write(struct file *file, const char __user *buff, size_t count, loff_t *offp) -{ - int ret = -1; - char *buf = kmalloc(count, GFP_KERNEL); - char *data = buf; - unsigned int regs_val = 0, read_val = 0; - ret = copy_from_user((void*)buf, buff, count); - - while(1) { - data = strstr(data, "0x"); - if(data == NULL) - goto reg_proc_write_exit; - sscanf(data, "0x%x", ®s_val); - ssd_set_register(regs_val); - read_val = ssd_read_register(regs_val >> 16); - regs_val &= 0xffff; - if(read_val != regs_val) - printk("%s fail:0x%04x\n", __func__, read_val); - data += 3; - } - -reg_proc_write_exit: - kfree(buf); - msleep(10); - return count; -} - -int reg_proc_read(struct file *file, char __user *buff, size_t count, loff_t *offp) -{ -#if 0 - int ret = -1; - const char buf[32] = {0}; - unsigned int regs_val = 0; - ret = copy_from_user((void*)buf, buff, count); - sscanf(buf, "0x%x", ®s_val); - regs_val = ssd_read_register(regs_val); - sprintf(buf, "0x%04x\n", regs_val); - copy_to_user(buff, buf, 4); - - printk("%s:%04x\n", __func__, regs_val); - msleep(10); -#endif - return count; -} - -int reg_proc_open(struct inode *inode, struct file *file) -{ - //printk("%s\n", __func__); - //msleep(10); - return 0; -} - -int reg_proc_close(struct inode *inode, struct file *file) -{ - //printk("%s\n", __func__); - //msleep(10); - return 0; -} - -struct file_operations reg_proc_fops = { - .owner = THIS_MODULE, - .open = reg_proc_open, - .release = reg_proc_close, - .write = reg_proc_write, - .read = reg_proc_read, -}; - -static int reg_proc_init(char *name) -{ - int ret = 0; - reg_proc_entry = create_proc_entry(name, 0666, NULL); - if(reg_proc_entry == NULL) { - printk("Couldn't create proc entry : %s!\n", name); - ret = -ENOMEM; - return ret ; - } - else { - printk("Create proc entry:%s success!\n", name); - reg_proc_entry->proc_fops = ®_proc_fops; - } - - return 0; -} - - -static int ssd2828_probe(struct platform_device *pdev) { - - if(pdev->dev.platform_data) - ssd2828 = pdev->dev.platform_data; - - if(!ssd2828->gpio_init) - ssd2828->gpio_init = ssd2828_gpio_init; - - if(!ssd2828->gpio_deinit) - ssd2828->gpio_deinit = ssd2828_gpio_deinit; - - if(!ssd2828->power_up) - ssd2828->power_up = ssd2828_power_up; - if(!ssd2828->power_down) - ssd2828->power_down = ssd2828_power_down; - - if(!ssd2828->reset.do_reset) - ssd2828->reset.do_reset = ssd2828_reset; - - if(!ssd2828->vddio.enable) - ssd2828->vddio.enable = ssd2828_vdd_enable; - if(!ssd2828->vddio.disable) - ssd2828->vddio.disable = ssd2828_vdd_disable; - - if(!ssd2828->vdd_mipi.enable) - ssd2828->vdd_mipi.enable = ssd2828_vdd_enable; - if(!ssd2828->vdd_mipi.disable) - ssd2828->vdd_mipi.disable = ssd2828_vdd_disable; - - if(!ssd2828->shut.enable) - ssd2828->shut.enable = ssd2828_vdd_enable; - if(!ssd2828->shut.disable) - ssd2828->shut.disable = ssd2828_vdd_disable; - - - ssd2828_gpio_init(NULL); - reg_proc_init(ssd2828_ops.name); - return 0; -} - - -static int ssd2828_remove(struct platform_device *pdev) { - - if(ssd2828) { - ssd2828_gpio_deinit(NULL); - ssd2828 = NULL; - } - return 0; -} - - -static struct platform_driver ssd2828_driver = { - .probe = ssd2828_probe, - .remove = ssd2828_remove, - //.suspend = mipi_dsi_suspend, - //.resume = mipi_dsi_resume, - .driver = { - .name = "ssd2828", - .owner = THIS_MODULE, - } -}; - -static int __init ssd2828_init(void) -{ - platform_driver_register(&ssd2828_driver); - if(!ssd2828) - return -1; - register_dsi_ops(&ssd2828_ops); - if(ssd2828->id > 0) - ssd2828_ops.id = ssd2828->id; - return 0; -} - -static void __exit ssd2828_exit(void) -{ - platform_driver_unregister(&ssd2828_driver); - del_dsi_ops(&ssd2828_ops); -} - -subsys_initcall_sync(ssd2828_init); -module_exit(ssd2828_exit); diff --git a/drivers/video/display/transmitter/tc358768.c b/drivers/video/display/transmitter/tc358768.c deleted file mode 100644 index 5f573b3dce8e..000000000000 --- a/drivers/video/display/transmitter/tc358768.c +++ /dev/null @@ -1,743 +0,0 @@ -/* - * Copyright (C) 2012 ROCKCHIP, Inc. - * drivers/video/display/transmitter/tc358768.c - * author: hhb@rock-chips.com - * create date: 2012-10-26 - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include "mipi_dsi.h" - -#define CONFIG_TC358768_I2C 1 -#define CONFIG_TC358768_I2C_CLK 400*1000 - - -#if 0 -#define dsi_debug printk -#else -#define dsi_debug(fmt...) do { } while (0) -#endif - -#ifdef CONFIG_TC358768_I2C -static struct tc358768_t *tc358768 = NULL; -static struct i2c_client *tc358768_client = NULL; -static struct mipi_dsi_ops tc358768_ops; - - -u32 i2c_write_32bits(u32 value) -{ - struct i2c_msg msgs; - int ret = -1; - char buf[4]; - buf[0] = value>>24; - buf[1] = value>>16; - buf[2] = value>>8; - buf[3] = value; - - msgs.addr = tc358768_client->addr; - msgs.flags = tc358768_client->flags; - msgs.len = 4; - msgs.buf = buf; - msgs.scl_rate = CONFIG_TC358768_I2C_CLK; - msgs.udelay = tc358768_client->udelay; - - ret = i2c_transfer(tc358768_client->adapter, &msgs, 1); - if(ret < 0) - printk("%s:i2c_transfer fail =%d\n",__func__, ret); - return ret; -} - -u32 i2c_read_32bits(u32 value) -{ - struct i2c_msg msgs[2]; - int ret = -1; - char buf[4]; - buf[0] = value>>8; - buf[1] = value; - - msgs[0].addr = tc358768_client->addr; - msgs[0].flags = tc358768_client->flags; - msgs[0].len = 2; - msgs[0].buf = buf; - msgs[0].scl_rate = CONFIG_TC358768_I2C_CLK; - msgs[0].udelay = tc358768_client->udelay; - - msgs[1].addr = tc358768_client->addr; - msgs[1].flags = tc358768_client->flags | I2C_M_RD; - msgs[1].len = 2; - msgs[1].buf = buf; - msgs[1].scl_rate = CONFIG_TC358768_I2C_CLK; - msgs[1].udelay = tc358768_client->udelay; - - ret = i2c_transfer(tc358768_client->adapter, msgs, 2); - if(ret < 0) - printk("%s:i2c_transfer fail =%d\n",__func__, ret); - else - ret = (buf[0]<<8) | buf[1]; - - return ret; -} - - -int tc358768_gpio_init(void *data) { - int ret = 0; - struct reset_t *reset = &tc358768->reset; - struct power_t *vdd = &tc358768->vddc; - if(reset->reset_pin > INVALID_GPIO) { - ret = gpio_request(reset->reset_pin, "tc358768_reset"); - if (ret != 0) { - //gpio_free(reset->reset_pin); - printk("%s: request TC358768_RST_PIN error\n", __func__); - } else { -#if OLD_RK_IOMUX - if(reset->mux_name) - rk30_mux_api_set(reset->mux_name, reset->mux_mode); -#endif - gpio_direction_output(reset->reset_pin, !reset->effect_value); - } - } - - if(vdd->enable_pin > INVALID_GPIO) { - ret = gpio_request(vdd->enable_pin, "tc358768_vddc"); - if (ret != 0) { - //gpio_free(vdd->enable_pin); - printk("%s: request TC358768_vddc_PIN error\n", __func__); - } else { -#if OLD_RK_IOMUX - if(vdd->mux_name) - rk30_mux_api_set(vdd->mux_name, vdd->mux_mode); -#endif - gpio_direction_output(vdd->enable_pin, !vdd->effect_value); - } - } - - vdd = &tc358768->vddio; - if(vdd->enable_pin > INVALID_GPIO) { - ret = gpio_request(vdd->enable_pin, "tc358768_vddio"); - if (ret != 0) { - //gpio_free(vdd->enable_pin); - printk("%s: request TC358768_vddio_PIN error\n", __func__); - } else { -#if OLD_RK_IOMUX - if(vdd->mux_name) - rk30_mux_api_set(vdd->mux_name, vdd->mux_mode); -#endif - gpio_direction_output(vdd->enable_pin, !vdd->effect_value); - } - } - - vdd = &tc358768->vdd_mipi; - if(vdd->enable_pin > INVALID_GPIO) { - ret = gpio_request(vdd->enable_pin, "tc358768_vdd_mipi"); - if (ret != 0) { - //gpio_free(vdd->enable_pin); - printk("%s: request TC358768_vdd_mipi_PIN error\n", __func__); - } else { -#if OLD_RK_IOMUX - if(vdd->mux_name) - rk30_mux_api_set(vdd->mux_name, vdd->mux_mode); -#endif - gpio_direction_output(vdd->enable_pin, !vdd->effect_value); - } - } - return 0; - -} - -int tc358768_gpio_deinit(void *data) { - struct reset_t *reset = &tc358768->reset; - struct power_t *vdd = &tc358768->vddc; - gpio_direction_input(reset->reset_pin); - gpio_free(reset->reset_pin); - - gpio_direction_input(vdd->enable_pin); - gpio_free(vdd->enable_pin); - - vdd = &tc358768->vddio; - gpio_direction_input(vdd->enable_pin); - gpio_free(vdd->enable_pin); - - vdd = &tc358768->vdd_mipi; - gpio_direction_input(vdd->enable_pin); - gpio_free(vdd->enable_pin); - return 0; -} - -int tc358768_reset(void *data) { - int ret = 0; - struct reset_t *reset = &tc358768->reset; - if(reset->reset_pin <= INVALID_GPIO) - return -1; - gpio_set_value(reset->reset_pin, reset->effect_value); - if(reset->time_before_reset <= 0) - msleep(1); - else - msleep(reset->time_before_reset); - - gpio_set_value(reset->reset_pin, !reset->effect_value); - if(reset->time_after_reset <= 0) - msleep(5); - else - msleep(reset->time_after_reset); - return ret; -} - -int tc358768_vdd_enable(void *data) { - int ret = 0; - struct power_t *vdd = (struct power_t *)data; - if(vdd->enable_pin > INVALID_GPIO) { - gpio_set_value(vdd->enable_pin, vdd->effect_value); - } else { - //for other control - } - return ret; -} - -int tc358768_vdd_disable(void *data) { - int ret = 0; - struct power_t *vdd = (struct power_t *)data; - - if(vdd->enable_pin > INVALID_GPIO) { - gpio_set_value(vdd->enable_pin, !vdd->effect_value); - } else { - //for other control - } - return ret; -} - - -int tc358768_power_up(void) { - - int ret = 0; - struct tc358768_t *tc = (struct tc358768_t *)tc358768; - - tc->vddc.enable(&tc->vddc); - tc->vdd_mipi.enable(&tc->vdd_mipi); - tc->vddio.enable(&tc->vddio); - tc->reset.do_reset(&tc->reset); - - return ret; -} - -int tc358768_power_down(void) { - - int ret = 0; - struct tc358768_t *tc = (struct tc358768_t *)tc358768; - - tc->vddio.disable(&tc->vddio); - tc->vdd_mipi.disable(&tc->vdd_mipi); - tc->vddc.disable(&tc->vddc); - - return ret; -} - -static int tc358768_probe(struct i2c_client *client, - const struct i2c_device_id *did) -{ - struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); - int ret = 0; - - if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) { - dev_warn(&adapter->dev, - "I2C-Adapter doesn't support I2C_FUNC_I2C\n"); - return -EIO; - } - - tc358768 = (struct tc358768_t *)client->dev.platform_data; - if(!tc358768) { - ret = -1; - printk("%s:%d tc358768 is null\n", __func__, __LINE__); - return ret; - } - - tc358768_client = client; - if(!tc358768_client) { - ret = -1; - printk("%s:%d tc358768_client is null\n", __func__, __LINE__); - return ret; - } - - if(!tc358768->gpio_init) - tc358768->gpio_init = tc358768_gpio_init; - - if(!tc358768->gpio_deinit) - tc358768->gpio_deinit = tc358768_gpio_deinit; - - if(!tc358768->power_up) - tc358768->power_up = tc358768_power_up; - if(!tc358768->power_down) - tc358768->power_down = tc358768_power_down; - - if(!tc358768->reset.do_reset) - tc358768->reset.do_reset = tc358768_reset; - - if(!tc358768->vddc.enable) - tc358768->vddc.enable = tc358768_vdd_enable; - if(!tc358768->vddc.disable) - tc358768->vddc.disable = tc358768_vdd_disable; - - if(!tc358768->vddio.enable) - tc358768->vddio.enable = tc358768_vdd_enable; - if(!tc358768->vddio.disable) - tc358768->vddio.disable = tc358768_vdd_disable; - - if(!tc358768->vdd_mipi.enable) - tc358768->vdd_mipi.enable = tc358768_vdd_enable; - if(!tc358768->vdd_mipi.disable) - tc358768->vdd_mipi.disable = tc358768_vdd_disable; - - tc358768_gpio_init(NULL); - - return ret; -} -static int tc358768_remove(struct i2c_client *client) -{ - tc358768_gpio_deinit(NULL); - tc358768_client = NULL; - tc358768 = NULL; - return 0; -} - -static const struct i2c_device_id tc358768_id[] = { - {"tc358768", 0 }, - { } -}; -MODULE_DEVICE_TABLE(i2c, tc358768_id); - -static struct i2c_driver tc358768_driver = { - .probe = tc358768_probe, - .remove = tc358768_remove, - .id_table = tc358768_id, - .driver = { - .name = "tc358768", - }, -}; -#else - -u32 spi_read_32bits(u32 addr) -{ - unsigned int i = 32; - //a frame starts - CS_CLR(); - CLK_SET(); - - addr <<= 16; - addr &= 0xfffe0000; - addr |= 0x00010000; - - udelay(2); - while(i--) { - CLK_CLR(); - if(addr & 0x80000000) - TXD_SET(); - else - TXD_CLR(); - addr <<= 1; - udelay(2); - CLK_SET(); - udelay(2); - } - //a frame ends - CS_SET(); - - - udelay(2); - CS_CLR(); - addr = 0xfffe0000; - i = 16; - while(i--) { - CLK_CLR(); - if(addr & 0x80000000) - TXD_SET(); - else - TXD_CLR(); - addr <<= 1; - udelay(2); - CLK_SET(); - udelay(2); - } - - TXD_SET(); - - addr = 0; - i = 16; - while(i--) { - CLK_CLR(); - udelay(1); - CLK_SET(); - udelay(1); - if (gpio_get_value(gLcd_info->rxd_pin) == 1) - addr |= 1 << i; - udelay(1); - } - CS_SET(); - - return addr; -} - - -//32 bits per frame -u32 spi_write_32bits(u32 value) -{ - int i = 32; - - //a frame starts - CS_CLR(); - CLK_SET(); - - while(i--) { - CLK_CLR(); - if(value & 0x80000000) - TXD_SET(); - else - TXD_CLR(); - value <<= 1; - CLK_SET(); - } - //a frame ends - CS_SET(); - - return 0; -} - -#endif - -u32 tc358768_wr_reg_32bits(u32 data) { -#ifdef CONFIG_TC358768_I2C - i2c_write_32bits(data); -#else - spi_write_32bits(data); -#endif - return 0; -} - - -u32 tc358768_wr_reg_32bits_delay(u32 delay, u32 data) { - //wait a minute according to the source format - if(delay < 20000) - udelay(delay); - else { - mdelay(delay/1000); - } - -#ifdef CONFIG_TC358768_I2C - i2c_write_32bits(data); -#else - spi_write_32bits(data); -#endif - return 0; -} - - - -u32 tc358768_rd_reg_32bits(u32 addr) { -#ifdef CONFIG_TC358768_I2C - return i2c_read_32bits(addr); -#else - return spi_read_32bits(addr); -#endif -} - - - -void tc_print(u32 addr) { - dsi_debug("+++++++++++addr->%04x: %04x\n", addr, tc358768_rd_reg_32bits(addr)); -} - -#define tc358768_wr_regs_32bits(reg_array) _tc358768_wr_regs_32bits(reg_array, ARRAY_SIZE(reg_array)) -int _tc358768_wr_regs_32bits(unsigned int reg_array[], int n) { - - int i = 0; - dsi_debug("%s:%d\n", __func__, n); - for(i = 0; i < n; i++) { - if(reg_array[i] < 0x00020000) { - if(reg_array[i] < 20000) - udelay(reg_array[i]); - else { - mdelay(reg_array[i]/1000); - } - } else { - tc358768_wr_reg_32bits(reg_array[i]); - } - } - return 0; -} - -int tc358768_command_tx_less8bytes(unsigned char type, unsigned char *regs, int n) { - int i = 0; - unsigned int command[] = { - 0x06020000, - 0x06040000, - 0x06100000, - 0x06120000, - 0x06140000, - 0x06160000, - }; - - if(n <= 2) - command[0] |= 0x1000; //short packet - else { - command[0] |= 0x4000; //long packet - command[1] |= n; //word count byte - } - command[0] |= type; //data type - - //dsi_debug("*cmd:\n"); - //dsi_debug("0x%08x\n", command[0]); - //dsi_debug("0x%08x\n", command[1]); - - for(i = 0; i < (n + 1)/2; i++) { - command[i+2] |= regs[i*2]; - if((i*2 + 1) < n) - command[i+2] |= regs[i*2 + 1] << 8; - dsi_debug("0x%08x\n", command[i+2]); - } - - _tc358768_wr_regs_32bits(command, (n + 1)/2 + 2); - tc358768_wr_reg_32bits(0x06000001); //Packet Transfer - //wait until packet is out - i = 100; - while(tc358768_rd_reg_32bits(0x0600) & 0x01) { - if(i-- == 0) - break; - tc_print(0x0600); - } - //udelay(50); - return 0; -} - -int tc358768_command_tx_more8bytes_hs(unsigned char type, unsigned char regs[], int n) { - - int i = 0; - unsigned int dbg_data = 0x00E80000, temp = 0; - unsigned int command[] = { - 0x05000080, //HS data 4 lane, EOT is added - 0x0502A300, - 0x00080001, - 0x00500000, //Data ID setting - 0x00220000, //Transmission byte count= byte - 0x00E08000, //Enable I2C/SPI write to VB - 0x00E20048, //Total word count = 0x48 (max 0xFFF). This value should be adjusted considering trade off between transmission time and transmission start/stop time delay - 0x00E4007F, //Vertical blank line = 0x7F - }; - - - command[3] |= type; //data type - command[4] |= n & 0xffff; //Transmission byte count - - tc358768_wr_regs_32bits(command); - - for(i = 0; i < (n + 1)/2; i++) { - temp = dbg_data | regs[i*2]; - if((i*2 + 1) < n) - temp |= (regs[i*2 + 1] << 8); - //dsi_debug("0x%08x\n", temp); - tc358768_wr_reg_32bits(temp); - } - if((n % 4 == 1) || (n % 4 == 2)) //4 bytes align - tc358768_wr_reg_32bits(dbg_data); - - tc358768_wr_reg_32bits(0x00E0C000); //Start command transmisison - tc358768_wr_reg_32bits(0x00E00000); //Stop command transmission. This setting should be done just after above setting to prevent multiple output - udelay(200); - //Re-Initialize - //tc358768_wr_regs_32bits(re_initialize); - return 0; -} - -//low power mode only for tc358768a -int tc358768_command_tx_more8bytes_lp(unsigned char type, unsigned char regs[], int n) { - - int i = 0; - unsigned int dbg_data = 0x00E80000, temp = 0; - unsigned int command[] = { - 0x00080001, - 0x00500000, //Data ID setting - 0x00220000, //Transmission byte count= byte - 0x00E08000, //Enable I2C/SPI write to VB - }; - - command[1] |= type; //data type - command[2] |= n & 0xffff; //Transmission byte count - - tc358768_wr_regs_32bits(command); - - for(i = 0; i < (n + 1)/2; i++) { - temp = dbg_data | regs[i*2]; - if((i*2 + 1) < n) - temp |= (regs[i*2 + 1] << 8); - //dsi_debug("0x%08x\n", temp); - tc358768_wr_reg_32bits(temp); - - } - if((n % 4 == 1) || (n % 4 == 2)) //4 bytes align - tc358768_wr_reg_32bits(dbg_data); - - tc358768_wr_reg_32bits(0x00E0E000); //Start command transmisison - udelay(1000); - tc358768_wr_reg_32bits(0x00E02000); //Keep Mask High to prevent short packets send out - tc358768_wr_reg_32bits(0x00E00000); //Stop command transmission. This setting should be done just after above setting to prevent multiple output - udelay(10); - return 0; -} - -int _tc358768_send_packet(unsigned char type, unsigned char regs[], int n) { - - if(n <= 8) { - tc358768_command_tx_less8bytes(type, regs, n); - } else { - //tc358768_command_tx_more8bytes_hs(type, regs, n); - tc358768_command_tx_more8bytes_lp(type, regs, n); - } - return 0; -} - -int tc358768_send_packet(unsigned char type, unsigned char regs[], int n) { - return _tc358768_send_packet(type, regs, n); -} - - -/* -The DCS is separated into two functional areas: the User Command Set and the Manufacturer Command -Set. Each command is an eight-bit code with 00h to AFh assigned to the User Command Set and all other -codes assigned to the Manufacturer Command Set. -*/ -int _mipi_dsi_send_dcs_packet(unsigned char regs[], int n) { - - unsigned char type = 0; - if(n == 1) { - type = DTYPE_DCS_SWRITE_0P; - } else if (n == 2) { - type = DTYPE_DCS_SWRITE_1P; - } else if (n > 2) { - type = DTYPE_DCS_LWRITE; - } - _tc358768_send_packet(type, regs, n); - return 0; -} - -int mipi_dsi_send_dcs_packet(unsigned char regs[], int n) { - return _mipi_dsi_send_dcs_packet(regs, n); -} - - -int _tc358768_rd_lcd_regs(unsigned char type, char comd, int size, unsigned char* buf) { - - unsigned char regs[8]; - u32 count = 0, data30, data32; - regs[0] = size; - regs[1] = 0; - tc358768_command_tx_less8bytes(0x37, regs, 2); - tc358768_wr_reg_32bits(0x05040010); - tc358768_wr_reg_32bits(0x05060000); - regs[0] = comd; - tc358768_command_tx_less8bytes(type, regs, 1); - - while (!(tc358768_rd_reg_32bits(0x0410) & 0x20)){ - printk("error 0x0410:%04x\n", tc358768_rd_reg_32bits(0x0410)); - msleep(1); - if(count++ > 10) { - break; - } - } - - data30 = tc358768_rd_reg_32bits(0x0430); //data id , word count[0:7] - //printk("0x0430:%04x\n", data30); - data32 = tc358768_rd_reg_32bits(0x0432); //word count[8:15] ECC - //printk("0x0432:%04x\n", data32); - - while(size > 0) { - data30 = tc358768_rd_reg_32bits(0x0430); - //printk("0x0430:%04x\n", data30); - data32 = tc358768_rd_reg_32bits(0x0432); - //printk("0x0432:%04x\n", data32); - - if(size-- > 0) - *buf++ = (u8)data30; - else - break; - if(size-- > 0) - *buf++ = (u8)(data30 >> 8); - else - break; - if(size-- > 0) { - *buf++ = (u8)data32; - if(size-- > 0) - *buf++ = (u8)(data32 >> 8); - } - } - - data30 = tc358768_rd_reg_32bits(0x0430); - //printk("0x0430:%04x\n", data30); - data32 = tc358768_rd_reg_32bits(0x0432); - //printk("0x0432:%04x\n", data32); - return 0; -} - -int mipi_dsi_read_dcs_packet(unsigned char *data, int n) { - //DCS READ - _tc358768_rd_lcd_regs(0x06, *data, n, data); - return 0; -} - -int tc358768_get_id(void) { - - int id = -1; - - tc358768_power_up(); - id = tc358768_rd_reg_32bits(0); - return id; -} - -static struct mipi_dsi_ops tc358768_ops = { - .id = 0x4401, - .name = "tc358768a", - .get_id = tc358768_get_id, - .dsi_set_regs = _tc358768_wr_regs_32bits, - .dsi_send_dcs_packet = mipi_dsi_send_dcs_packet, - .dsi_read_dcs_packet = mipi_dsi_read_dcs_packet, - .power_up = tc358768_power_up, - .power_down = tc358768_power_down, - -}; - -static int __init tc358768_module_init(void) -{ -#ifdef CONFIG_TC358768_I2C - i2c_add_driver(&tc358768_driver); - - if(!tc358768 || !tc358768_client) - return -1; -#endif - - register_dsi_ops(&tc358768_ops); - if(tc358768->id > 0) - tc358768_ops.id = tc358768->id; - return 0; -} - -static void __exit tc358768_module_exit(void) -{ - del_dsi_ops(&tc358768_ops); -#ifdef CONFIG_TC358768_I2C - i2c_del_driver(&tc358768_driver); -#endif -} - -subsys_initcall_sync(tc358768_module_init); -//module_exit(tc358768_module_init); -module_exit(tc358768_module_exit); diff --git a/drivers/video/display/tve/Kconfig b/drivers/video/display/tve/Kconfig deleted file mode 100644 index 68639bdd419b..000000000000 --- a/drivers/video/display/tve/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -config RK610_TVOUT - bool "RK610(Jetta) tvout support" - depends on MFD_RK610 - default y if MFD_RK610 - help - Support Jetta(RK610) to output YPbPr and CVBS. - -config RK610_TVOUT_YPbPr - bool "support YPbPr output" - depends on RK610_TVOUT -config RK610_TVOUT_CVBS - bool "support CVBS output" - depends on RK610_TVOUT diff --git a/drivers/video/display/tve/Makefile b/drivers/video/display/tve/Makefile deleted file mode 100644 index b7d457326d26..000000000000 --- a/drivers/video/display/tve/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# Makefile for the jetta tv control. -# -obj-$(CONFIG_RK610_TVOUT) += rk610_tv.o -obj-$(CONFIG_RK610_TVOUT_YPbPr) += rk610_tv_ypbpr.o -obj-$(CONFIG_RK610_TVOUT_CVBS) += rk610_tv_cvbs.o \ No newline at end of file diff --git a/drivers/video/display/tve/rk610_tv.c b/drivers/video/display/tve/rk610_tv.c deleted file mode 100644 index 03237ce4a410..000000000000 --- a/drivers/video/display/tve/rk610_tv.c +++ /dev/null @@ -1,246 +0,0 @@ -/* - * rk610_tv.c - * - * Driver for rockchip rk610 tv control - * Copyright (C) 2009 - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rk610_tv.h" -#include "../../rk29_fb.h" - -#define DRV_NAME "rk610_tvout" -#define RK610_I2C_RATE 100*1000 - -volatile int rk610_tv_output_status = RK610_TVOUT_DEAULT; -static struct i2c_client *rk610_tv_i2c_client = NULL; - -int rk610_tv_wirte_reg(u8 reg, u8 data) -{ - int ret; - if(rk610_tv_i2c_client == NULL) - return -1; - ret = i2c_master_reg8_send(rk610_tv_i2c_client, reg, &data, 1, RK610_I2C_RATE); - if (ret > 0) - ret = 0; - return ret; -} - -int rk610_switch_fb(const struct fb_videomode *modedb, int tv_mode) -{ - struct rk29fb_screen *screen; - - if(modedb == NULL) - return -1; - screen = kzalloc(sizeof(struct rk29fb_screen), GFP_KERNEL); - if(screen == NULL) - return -1; - - memset(screen, 0, sizeof(struct rk29fb_screen)); - /* screen type & face */ - screen->type = SCREEN_HDMI; - screen->mode = modedb->vmode; - screen->face = modedb->flag; - /* Screen size */ - screen->x_res = modedb->xres; - screen->y_res = modedb->yres; - - /* Timing */ - screen->pixclock = modedb->pixclock; - - screen->lcdc_aclk = 500000000; - screen->left_margin = modedb->left_margin; - screen->right_margin = modedb->right_margin; - screen->hsync_len = modedb->hsync_len; - screen->upper_margin = modedb->upper_margin; - screen->lower_margin = modedb->lower_margin; - screen->vsync_len = modedb->vsync_len; - - /* Pin polarity */ - if(FB_SYNC_HOR_HIGH_ACT & modedb->sync) - screen->pin_hsync = 1; - else - screen->pin_hsync = 0; - if(FB_SYNC_VERT_HIGH_ACT & modedb->sync) - screen->pin_vsync = 1; - else - screen->pin_vsync = 0; - screen->pin_den = 0; - screen->pin_dclk = 0; - - /* Swap rule */ - screen->swap_rb = 0; - screen->swap_rg = 0; - screen->swap_gb = 0; - screen->swap_delta = 0; - screen->swap_dumy = 0; - - /* Operation function*/ - screen->init = NULL; - screen->standby = NULL; - - switch(tv_mode) - { -#ifdef CONFIG_RK610_TVOUT_CVBS - case TVOUT_CVBS_NTSC: - case TVOUT_CVBS_PAL: - screen->init = rk610_tv_cvbs_init;; - break; -#endif - -#ifdef CONFIG_RK610_TVOUT_YPbPr - case TVOUT_YPbPr_720x480p_60: - case TVOUT_YPbPr_720x576p_50: - case TVOUT_YPbPr_1280x720p_50: - case TVOUT_YPbPr_1280x720p_60: - //case TVOUT_YPbPr_1920x1080i_50: - case TVOUT_YPbPr_1920x1080i_60: - case TVOUT_YPbPr_1920x1080p_50: - case TVOUT_YPbPr_1920x1080p_60: - screen->init = rk610_tv_ypbpr_init; - break; -#endif - default:{ - kfree(screen); - return -1; - } - break; - } - rk610_tv_output_status = tv_mode; - FB_Switch_Screen(screen, 1); - kfree(screen); - return 0; -} - -int rk610_tv_standby(int type) -{ - int ret; - - switch(type) - { - #ifdef CONFIG_RK610_TVOUT_CVBS - case RK610_TVOUT_CVBS: - if(rk610_cvbs_monspecs.enable == 0) - return 0; - #ifdef CONFIG_RK610_TVOUT_YPbPr - if(rk610_ypbpr_monspecs.enable == 1) - return 0; - #endif - break; - #endif - #ifdef CONFIG_RK610_TVOUT_YPbPr - case RK610_TVOUT_YPBPR: - if(rk610_ypbpr_monspecs.enable == 0) - return 0; - #ifdef CONFIG_RK610_TVOUT_CVBS - if(rk610_cvbs_monspecs.enable == 1) - return 0; - #endif - break; - #endif - default: - break; - } - - ret = rk610_tv_wirte_reg(TVE_POWERCR, 0); - if(ret < 0){ - printk("[%s] rk610_tv_wirte_reg err!\n", __FUNCTION__); - return ret; - } - - ret = rk610_control_send_byte(RK610_CONTROL_REG_TVE_CON, 0); - if(ret < 0){ - printk("[%s] rk610_control_send_byte err!\n", __FUNCTION__); - return ret; - } - return 0; -} - -static int rk610_tv_probe(struct i2c_client *client,const struct i2c_device_id *id) -{ - int rc = 0; - - if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { - rc = -ENODEV; - goto failout; - } - rk610_tv_i2c_client = client; - -#ifdef CONFIG_RK610_TVOUT_YPbPr - rk610_register_display_ypbpr(&client->dev); - if(rk610_tv_output_status > TVOUT_CVBS_PAL) - rk_display_device_enable(rk610_ypbpr_monspecs.ddev); -#endif - -#ifdef CONFIG_RK610_TVOUT_CVBS - rk610_register_display_cvbs(&client->dev); - if(rk610_tv_output_status < TVOUT_YPbPr_720x480p_60) - rk_display_device_enable(rk610_cvbs_monspecs.ddev); -#endif - - printk(KERN_INFO "rk610_tv ver 1.0 probe ok\n"); - return 0; -failout: - kfree(client); - return rc; -} - -static int rk610_tv_remove(struct i2c_client *client) -{ - return 0; -} - - -static const struct i2c_device_id rk610_tv_id[] = { - { DRV_NAME, 0 }, - { } -}; -MODULE_DEVICE_TABLE(i2c, rk610_tv_id); - -static struct i2c_driver rk610_tv_driver = { - .driver = { - .name = DRV_NAME, - }, - .id_table = rk610_tv_id, - .probe = rk610_tv_probe, - .remove = rk610_tv_remove, -}; - -static int __init rk610_tv_init(void) -{ - int ret = 0; - ret = i2c_add_driver(&rk610_tv_driver); - if(ret < 0){ - printk("i2c_add_driver err, ret = %d\n", ret); - } - return ret; -} - -static void __exit rk610_tv_exit(void) -{ - i2c_del_driver(&rk610_tv_driver); -} - -module_init(rk610_tv_init); -//late_initcall(rk610_tv_init); -module_exit(rk610_tv_exit); - -/* Module information */ -MODULE_DESCRIPTION("ROCKCHIP RK610 TV Output"); -MODULE_LICENSE("GPL"); - - diff --git a/drivers/video/display/tve/rk610_tv.h b/drivers/video/display/tve/rk610_tv.h deleted file mode 100644 index 422e8f25c83a..000000000000 --- a/drivers/video/display/tve/rk610_tv.h +++ /dev/null @@ -1,131 +0,0 @@ -#ifndef _RK610_TV_H -#define _RK610_TV_H -#include -#include -#include -#include -#ifdef CONFIG_ARCH_RK29 -#include -#endif -#include "../screen/screen.h" -#include "../../rk29_fb.h" -#include - -#define TVE_VFCR 0x00 - #define TVE_VFCR_ENABLE_SUBCARRIER_RESET 0 << 6 - #define TVE_VFCR_DISABLE_SUBCARRIER_RESET 1 << 6 - #define TVE_VFCR_VIN_RANGE_16_235 0 << 3 - #define TVE_VFCR_VIN_RANGE_1_254 1 << 3 - #define TVE_VFCR_BLACK_7_5_IRE 0 << 2 - #define TVE_VFCR_BLACK_0_IRE 1 << 2 - #define TVE_VFCR_NTSC 0 - #define TVE_VFCR_PAL_M 1 - #define TVE_VFCR_PAL_B_N 2 - #define TVE_VFCR_PAL_NC 3 - -#define TVE_VINCR 0x01 - #define TVE_VINCR_PIX_DATA_DELAY(n) (n << 5) - #define TVE_VINCR_H_SYNC_POLARITY_NEGTIVE 0 << 4 - #define TVE_VINCR_H_SYNC_POLARITY_POSITIVE 1 << 4 - #define TVE_VINCR_V_SYNC_POLARITY_NEGTIVE 0 << 3 - #define TVE_VINCR_V_SYNC_POLARITY_POSITIVE 1 << 3 -enum { - INPUT_FORMAT_BT601_SLAVE = 0, - INPUT_FORMAT_BT656, - INPUT_FORMAT_BT601_MASTER, - INPUT_FORMAT_INTERNAL_COLLOR_BAR -}; - #define TVE_VINCR_INPUT_FORMAT(n) (n << 1) - #define TVE_VINCR_VSYNC_FUNCTION_VSYNC 0 - #define TVE_VINCR_VSYNC_FUNCTION_FIELD 1 - -#define TVE_VOUTCR 0x02 - #define TVE_VOUTCR_OUTPUT_CVBS 0 << 6 - #define TVE_VOUTCR_OUTPUT_YPBPR 1 << 6 - #define TVE_VOUTCR_OUTPUT_ENABLE_BLUE 1 << 5 - #define TVE_VOUTCR_OUTPUT_ENABLE_BLACK 1 << 4 - #define TVE_VOUTCR_DISABLE_CVBS_COLOR 1 << 3 - #define TVE_VOUTCR_CVBS_Y2C_DELAY(n) (n << 0) - -#define TVE_POWERCR 0x03 - #define TVE_PIX_CLK_INVERSE_ENABLE 1 << 4 - #define TVE_DAC_CLK_INVERSE_DISABLE 1 << 3 - #define TVE_DAC_Y_ENABLE 1 << 2 - #define TVE_DAC_U_ENABLE 1 << 1 - #define TVE_DAC_V_ENABLE 1 << 0 - -#define TVE_HDTVCR 0x05 - #define TVE_RESET 1 << 7 - #define TVE_FILTER(n) (n << 5) - #define TVE_COLOR_CONVERT_REC601 0 << 4 - #define TVE_COLOR_CONVERT_REC709 1 << 4 - #define TVE_INPUT_DATA_RGB 0 << 3 - #define TVE_INPUT_DATA_YUV 1 << 3 - #define TVE_OUTPUT_50HZ 0 << 2 - #define TVE_OUTPUT_60HZ 1 << 2 - #define TVE_OUTPUT_MODE_PAL_NTSC 0 - #define TVE_OUTPUT_MODE_576P 1 - #define TVE_OUTPUT_MODE_480P 2 - #define TVE_OUTPUT_MODE_720P 3 - -#define TVE_YADJCR 0x06 - #define TVE_OUTPUT_MODE_1080P 1 << 6 - #define TVE_OUTPUT_MODE_1080I 1 << 5 - #define TVE_Y_ADJ_VALUE(n) n -#define TVE_YCBADJCR 0x07 -#define TVE_YCRADJCR 0x08 - -/******************* TVOUT OUTPUT TYPE **********************/ -struct rk610_monspecs { - struct rk_display_device *ddev; - unsigned int enable; - struct fb_videomode *mode; - struct list_head modelist; - unsigned int mode_set; -}; - -enum { - TVOUT_CVBS_NTSC = 1, - TVOUT_CVBS_PAL, - TVOUT_YPbPr_720x480p_60, - TVOUT_YPbPr_720x576p_50, - TVOUT_YPbPr_1280x720p_50, - TVOUT_YPbPr_1280x720p_60, - //TVOUT_YPbPr_1920x1080i_50, - TVOUT_YPbPr_1920x1080i_60, - TVOUT_YPbPr_1920x1080p_50, - TVOUT_YPbPr_1920x1080p_60 -}; - -#define RK610_TVOUT_DEAULT TVOUT_CVBS_NTSC - -enum { - RK610_TVOUT_CVBS = 0, - RK610_TVOUT_YC, - RK610_TVOUT_YPBPR, -}; - -extern volatile int rk610_tv_output_status; -extern struct rk_display_ops rk610_display_ops; - -extern int FB_Switch_Screen( struct rk29fb_screen *screen, u32 enable ); - -extern int rk610_tv_wirte_reg(u8 reg, u8 data); -extern int rk610_tv_standby(int type); -extern int rk610_switch_fb(const struct fb_videomode *modedb, int tv_mode); -extern int rk610_register_display(struct device *parent); - -#ifdef CONFIG_RK610_TVOUT_YPbPr -extern int rk610_tv_ypbpr_init(void); -extern int rk610_register_display_ypbpr(struct device *parent); -extern struct rk610_monspecs rk610_ypbpr_monspecs; -#endif - -#ifdef CONFIG_RK610_TVOUT_CVBS -extern int rk610_tv_cvbs_init(void); -extern int rk610_register_display_cvbs(struct device *parent); -extern struct rk610_monspecs rk610_cvbs_monspecs; -#endif - -#endif - diff --git a/drivers/video/display/tve/rk610_tv_cvbs.c b/drivers/video/display/tve/rk610_tv_cvbs.c deleted file mode 100644 index ea0fe8a0d79c..000000000000 --- a/drivers/video/display/tve/rk610_tv_cvbs.c +++ /dev/null @@ -1,209 +0,0 @@ -#include -#include -#include -#include "rk610_tv.h" - - -#ifdef CONFIG_DISPLAY_KEY_LED_CONTROL -#define RK610_LED_CVBS_PIN RK29_PIN4_PD3 -#else -#define RK610_LED_CVBS_PIN INVALID_GPIO -#endif - -#ifdef USE_RGB2CCIR -static const struct fb_videomode rk610_cvbs_mode [] = { - //name refresh xres yres pixclock h_bp h_fp v_bp v_fp h_pw v_pw polariry PorI flag - { "NTSC", 60, 720, 480, 27000000, 116, 16, 25, 14, 6, 6, 0, 1, OUT_P888 }, - { "PAL", 50, 720, 576, 27000000, 126, 12, 37, 6, 6, 6, 0, 1, OUT_P888 }, -}; -#else -static const struct fb_videomode rk610_cvbs_mode [] = { - //name refresh xres yres pixclock h_bp h_fp v_bp v_fp h_pw v_pw polariry PorI flag - { "NTSC", 60, 720, 480, 27000000, 116, 16, 16, 3, 6, 3, 0, 1, OUT_CCIR656 }, - { "PAL", 50, 720, 576, 27000000, 126, 12, 19, 2, 6, 3, 0, 1, OUT_CCIR656 }, -}; -#endif - -struct rk610_monspecs rk610_cvbs_monspecs; - - -int rk610_tv_cvbs_init(void) -{ - unsigned char TVE_Regs[9]; - unsigned char TVE_CON_Reg; - int ret, i; - - rk610_tv_wirte_reg(TVE_HDTVCR, TVE_RESET); - - memset(TVE_Regs, 0, 9); - TVE_CON_Reg = TVE_CONTROL_CVBS_3_CHANNEL_ENALBE; - TVE_Regs[TVE_VINCR] = TVE_VINCR_PIX_DATA_DELAY(0) | TVE_VINCR_H_SYNC_POLARITY_NEGTIVE | TVE_VINCR_V_SYNC_POLARITY_NEGTIVE | TVE_VINCR_VSYNC_FUNCTION_VSYNC; - TVE_Regs[TVE_POWERCR] = TVE_DAC_Y_ENABLE | TVE_DAC_U_ENABLE | TVE_DAC_V_ENABLE; - TVE_Regs[TVE_VOUTCR] = TVE_VOUTCR_OUTPUT_CVBS; - TVE_Regs[TVE_YADJCR] = 0x17; - TVE_Regs[TVE_YCBADJCR] = 0x10; - TVE_Regs[TVE_YCRADJCR] = 0x10; - - switch(rk610_tv_output_status) { - case TVOUT_CVBS_NTSC: - TVE_Regs[TVE_VFCR] = TVE_VFCR_ENABLE_SUBCARRIER_RESET | TVE_VFCR_VIN_RANGE_16_235 | TVE_VFCR_BLACK_7_5_IRE | TVE_VFCR_NTSC; - #ifdef USE_RGB2CCIR - TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT601_SLAVE); - TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_COLOR_CONVERT_REC601 | TVE_INPUT_DATA_RGB | TVE_OUTPUT_MODE_PAL_NTSC; - TVE_CON_Reg |= RGB2CCIR_INPUT_DATA_FORMAT(0) | RGB2CCIR_RGB_SWAP_DISABLE | RGB2CCIR_INPUT_PROGRESSIVE | RGB2CCIR_CVBS_NTSC | RGB2CCIR_ENABLE; - #else - TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT656); - TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_INPUT_DATA_YUV | TVE_OUTPUT_MODE_PAL_NTSC; - #endif - break; - case TVOUT_CVBS_PAL: - TVE_Regs[TVE_VFCR] = TVE_VFCR_ENABLE_SUBCARRIER_RESET | TVE_VFCR_VIN_RANGE_16_235 | TVE_VFCR_BLACK_0_IRE | TVE_VFCR_PAL_B_N; - #ifdef USE_RGB2CCIR - TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT601_SLAVE); - TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_COLOR_CONVERT_REC601 | TVE_INPUT_DATA_RGB | TVE_OUTPUT_MODE_PAL_NTSC; - TVE_CON_Reg |= RGB2CCIR_INPUT_DATA_FORMAT(0) | RGB2CCIR_RGB_SWAP_DISABLE | RGB2CCIR_INPUT_PROGRESSIVE | RGB2CCIR_CVBS_PAL | RGB2CCIR_ENABLE; - #else - TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT656); - TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_INPUT_DATA_YUV | TVE_OUTPUT_MODE_PAL_NTSC; - #endif - break; - default: - return -1; - } - - for(i = 0; i < sizeof(TVE_Regs); i++){ -// printk(KERN_ERR "reg[%d] = 0x%02x\n", i, TVE_Regs[i]); - ret = rk610_tv_wirte_reg(i, TVE_Regs[i]); - if(ret < 0){ - printk(KERN_ERR "rk610_tv_wirte_reg %d err!\n", i); - return ret; - } - } -// printk(KERN_ERR "TVE_CON_Reg = 0x%02x\n", TVE_CON_Reg); - rk610_control_send_byte(RK610_CONTROL_REG_TVE_CON, TVE_CON_Reg); - #ifdef USE_RGB2CCIR - rk610_control_send_byte(RK610_CONTROL_REG_CCIR_RESET, 0x01); - #endif - return 0; -} - -static int rk610_cvbs_set_enable(struct rk_display_device *device, int enable) -{ - if(rk610_cvbs_monspecs.enable != enable || rk610_cvbs_monspecs.mode_set != rk610_tv_output_status) - { - if(enable == 0) - { - rk610_tv_standby(RK610_TVOUT_CVBS); - rk610_cvbs_monspecs.enable = 0; - if(RK610_LED_CVBS_PIN != INVALID_GPIO) - gpio_direction_output(RK610_LED_CVBS_PIN, GPIO_HIGH); - } - else if(enable == 1) - { - rk610_switch_fb(rk610_cvbs_monspecs.mode, rk610_cvbs_monspecs.mode_set); - rk610_cvbs_monspecs.enable = 1; - if(RK610_LED_CVBS_PIN != INVALID_GPIO) - gpio_direction_output(RK610_LED_CVBS_PIN, GPIO_LOW); - } - } - return 0; -} - -static int rk610_cvbs_get_enable(struct rk_display_device *device) -{ - return rk610_cvbs_monspecs.enable; -} - -static int rk610_cvbs_get_status(struct rk_display_device *device) -{ - if(rk610_tv_output_status < TVOUT_YPbPr_720x480p_60) - return 1; - else - return 0; -} - -static int rk610_cvbs_get_modelist(struct rk_display_device *device, struct list_head **modelist) -{ - *modelist = &(rk610_cvbs_monspecs.modelist); - return 0; -} - -static int rk610_cvbs_set_mode(struct rk_display_device *device, struct fb_videomode *mode) -{ - int i; - - for(i = 0; i < ARRAY_SIZE(rk610_cvbs_mode); i++) - { - if(fb_mode_is_equal(&rk610_cvbs_mode[i], mode)) - { - if( ((i + 1) != rk610_tv_output_status) ) - { - rk610_cvbs_monspecs.mode_set = i + 1; - rk610_cvbs_monspecs.mode = (struct fb_videomode *)&rk610_cvbs_mode[i]; - } - return 0; - } - } - - return -1; -} - -static int rk610_cvbs_get_mode(struct rk_display_device *device, struct fb_videomode *mode) -{ - *mode = *(rk610_cvbs_monspecs.mode); - return 0; -} - -static struct rk_display_ops rk610_cvbs_display_ops = { - .setenable = rk610_cvbs_set_enable, - .getenable = rk610_cvbs_get_enable, - .getstatus = rk610_cvbs_get_status, - .getmodelist = rk610_cvbs_get_modelist, - .setmode = rk610_cvbs_set_mode, - .getmode = rk610_cvbs_get_mode, -}; - -static int rk610_display_cvbs_probe(struct rk_display_device *device, void *devdata) -{ - device->owner = THIS_MODULE; - strcpy(device->type, "TV"); - device->priority = DISPLAY_PRIORITY_TV; - device->priv_data = devdata; - device->ops = &rk610_cvbs_display_ops; - return 1; -} - -static struct rk_display_driver display_rk610_cvbs = { - .probe = rk610_display_cvbs_probe, -}; - -int rk610_register_display_cvbs(struct device *parent) -{ - int i; - - memset(&rk610_cvbs_monspecs, 0, sizeof(struct rk610_monspecs)); - INIT_LIST_HEAD(&rk610_cvbs_monspecs.modelist); - for(i = 0; i < ARRAY_SIZE(rk610_cvbs_mode); i++) - fb_add_videomode(&rk610_cvbs_mode[i], &rk610_cvbs_monspecs.modelist); - if(rk610_tv_output_status < TVOUT_YPbPr_720x480p_60) { - rk610_cvbs_monspecs.mode = (struct fb_videomode *)&(rk610_cvbs_mode[rk610_tv_output_status - 1]); - rk610_cvbs_monspecs.mode_set = rk610_tv_output_status; - } - else { - rk610_cvbs_monspecs.mode = (struct fb_videomode *)&(rk610_cvbs_mode[0]); - rk610_cvbs_monspecs.mode_set = TVOUT_CVBS_NTSC; - } - rk610_cvbs_monspecs.ddev = rk_display_device_register(&display_rk610_cvbs, parent, NULL); - if(RK610_LED_CVBS_PIN != INVALID_GPIO) - { - if(gpio_request(RK610_LED_CVBS_PIN, NULL) != 0) - { - gpio_free(RK610_LED_CVBS_PIN); - dev_err(rk610_cvbs_monspecs.ddev->dev, ">>>>>> RK610_LED_CVBS_PIN gpio_request err \n "); - return -1; - } - gpio_pull_updown(RK610_LED_CVBS_PIN,GPIOPullUp); - gpio_direction_output(RK610_LED_CVBS_PIN, GPIO_HIGH); - } - return 0; -} diff --git a/drivers/video/display/tve/rk610_tv_ypbpr.c b/drivers/video/display/tve/rk610_tv_ypbpr.c deleted file mode 100644 index af74126f7604..000000000000 --- a/drivers/video/display/tve/rk610_tv_ypbpr.c +++ /dev/null @@ -1,229 +0,0 @@ -#include -#include -#include -#include "rk610_tv.h" - - -#ifdef CONFIG_DISPLAY_KEY_LED_CONTROL -#define RK610_LED_YPbPr_PIN RK29_PIN4_PD5 -#else -#define RK610_LED_YPbPr_PIN INVALID_GPIO -#endif -#define E(fmt, arg...) printk("<3>!!!%s:%d: " fmt, __FILE__, __LINE__, ##arg) - -static const struct fb_videomode rk610_YPbPr_mode [] = { - //name refresh xres yres pixclock h_bp h_fp v_bp v_fp h_pw v_pw polariry PorI flag - { "YPbPr480p", 60, 720, 480, 27000000, 55, 19, 37, 5, 64, 5, 0, 0, OUT_P888 }, - { "YPbPr576p", 50, 720, 576, 27000000, 68, 12, 39, 5, 64, 5, 0, 0, OUT_P888 }, - { "YPbPr720p@50", 50, 1280, 720, 74250000, 600, 0, 20, 5, 100, 5, 0, 0, OUT_P888 }, - { "YPbPr720p@60", 60, 1280, 720, 74250000, 270, 0, 20, 5, 100, 5, 0, 0, OUT_P888 }, - //{ "YPbPr1080i@50", 50, 1920, 1080, 148500000, 620, 0, 15, 2, 100, 5, 0, 1, OUT_CCIR656 }, - { "YPbPr1080i@60", 60, 1920, 1080, 148500000, 180, 0, 15, 2, 100, 5, 0, 1, OUT_CCIR656 }, - { "YPbPr1080p@50", 50, 1920, 1080, 148500000, 620, 0, 36, 4, 100, 5, 0, 0, OUT_P888 }, - { "YPbPr1080p@60", 60, 1920, 1080, 148500000, 180, 0, 36, 4, 100, 5, 0, 0, OUT_P888 }, -}; - -struct rk610_monspecs rk610_ypbpr_monspecs; - -int rk610_tv_ypbpr_init(void) -{ - unsigned char TVE_Regs[9]; - unsigned char TVE_CON_Reg; - int i, ret; - - rk610_tv_wirte_reg(TVE_HDTVCR, TVE_RESET); - memset(TVE_Regs, 0, 9); - - TVE_CON_Reg = 0x00; - - TVE_Regs[TVE_VINCR] = TVE_VINCR_PIX_DATA_DELAY(0) | TVE_VINCR_H_SYNC_POLARITY_NEGTIVE | TVE_VINCR_V_SYNC_POLARITY_NEGTIVE | TVE_VINCR_VSYNC_FUNCTION_VSYNC; - TVE_Regs[TVE_POWERCR] = TVE_DAC_CLK_INVERSE_DISABLE | TVE_DAC_Y_ENABLE | TVE_DAC_U_ENABLE | TVE_DAC_V_ENABLE; - TVE_Regs[TVE_VOUTCR] = TVE_VOUTCR_OUTPUT_YPBPR; - TVE_Regs[TVE_YADJCR] = 0x17; - TVE_Regs[TVE_YCBADJCR] = 0x10; - TVE_Regs[TVE_YCRADJCR] = 0x10; - - switch(rk610_tv_output_status) - { - case TVOUT_YPbPr_720x480p_60: - TVE_Regs[TVE_VFCR] = TVE_VFCR_BLACK_0_IRE; - TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT601_SLAVE); - TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_COLOR_CONVERT_REC601 | TVE_INPUT_DATA_RGB | TVE_OUTPUT_60HZ | TVE_OUTPUT_MODE_480P; - break; - case TVOUT_YPbPr_720x576p_50: - TVE_Regs[TVE_VFCR] = TVE_VFCR_BLACK_0_IRE | TVE_VFCR_PAL_NC; - TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT601_SLAVE); - TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_COLOR_CONVERT_REC601 | TVE_INPUT_DATA_RGB | TVE_OUTPUT_50HZ | TVE_OUTPUT_MODE_576P; - break; - case TVOUT_YPbPr_1280x720p_50: - TVE_Regs[TVE_VFCR] = TVE_VFCR_BLACK_0_IRE | TVE_VFCR_PAL_NC; - TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT601_SLAVE); - TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_COLOR_CONVERT_REC709 | TVE_INPUT_DATA_RGB | TVE_OUTPUT_50HZ | TVE_OUTPUT_MODE_720P; - break; - case TVOUT_YPbPr_1280x720p_60: - TVE_Regs[TVE_VFCR] = TVE_VFCR_BLACK_0_IRE | TVE_VFCR_PAL_NC; - TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT601_SLAVE); - TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_COLOR_CONVERT_REC709 | TVE_INPUT_DATA_RGB | TVE_OUTPUT_60HZ | TVE_OUTPUT_MODE_720P; - break; - /*case TVOUT_YPbPr_1920x1080i_50: - TVE_Regs[TVE_VFCR] = TVE_VFCR_BLACK_0_IRE | TVE_VFCR_PAL_NC; - TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT656); - TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_INPUT_DATA_YUV | TVE_OUTPUT_50HZ; - TVE_Regs[TVE_YADJCR] |= TVE_OUTPUT_MODE_1080I; - break; - */ - case TVOUT_YPbPr_1920x1080i_60: - TVE_Regs[TVE_VFCR] = TVE_VFCR_BLACK_0_IRE | TVE_VFCR_PAL_NC; - TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT656); - TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_INPUT_DATA_YUV | TVE_OUTPUT_60HZ; - TVE_Regs[TVE_YADJCR] |= TVE_OUTPUT_MODE_1080I; - break; - case TVOUT_YPbPr_1920x1080p_50: - TVE_Regs[TVE_VFCR] = TVE_VFCR_BLACK_0_IRE | TVE_VFCR_PAL_NC; - TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT601_SLAVE); - TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_COLOR_CONVERT_REC709 | TVE_INPUT_DATA_RGB | TVE_OUTPUT_50HZ; - TVE_Regs[TVE_YADJCR] |= TVE_OUTPUT_MODE_1080P; - break; - case TVOUT_YPbPr_1920x1080p_60: - TVE_Regs[TVE_VFCR] = TVE_VFCR_BLACK_0_IRE | TVE_VFCR_PAL_NC; - TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT601_SLAVE); - TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_COLOR_CONVERT_REC709 | TVE_INPUT_DATA_RGB | TVE_OUTPUT_60HZ; - TVE_Regs[TVE_YADJCR] |= TVE_OUTPUT_MODE_1080P; - break; - default: - return -1; - } - - rk610_control_send_byte(RK610_CONTROL_REG_TVE_CON, TVE_CON_Reg); - - for(i = 0; i < sizeof(TVE_Regs); i++){ -// printk(KERN_ERR "reg[%d] = 0x%02x\n", i, TVE_Regs[i]); - ret = rk610_tv_wirte_reg(i, TVE_Regs[i]); - if(ret < 0){ - E("rk610_tv_wirte_reg %d err!\n", i); - return ret; - } - } - return 0; -} - -static int rk610_ypbpr_set_enable(struct rk_display_device *device, int enable) -{ - if(rk610_ypbpr_monspecs.enable != enable || rk610_ypbpr_monspecs.mode_set != rk610_tv_output_status) - { - if(enable == 0) - { - rk610_tv_standby(RK610_TVOUT_YPBPR); - rk610_ypbpr_monspecs.enable = 0; - if(RK610_LED_YPbPr_PIN != INVALID_GPIO) - gpio_direction_output(RK610_LED_YPbPr_PIN, GPIO_HIGH); - } - else if(enable == 1) - { - rk610_switch_fb(rk610_ypbpr_monspecs.mode, rk610_ypbpr_monspecs.mode_set); - rk610_ypbpr_monspecs.enable = 1; - if(RK610_LED_YPbPr_PIN != INVALID_GPIO) - gpio_direction_output(RK610_LED_YPbPr_PIN, GPIO_LOW); - } - } - return 0; -} - -static int rk610_ypbpr_get_enable(struct rk_display_device *device) -{ - return rk610_ypbpr_monspecs.enable; -} - -static int rk610_ypbpr_get_status(struct rk_display_device *device) -{ - if(rk610_tv_output_status > TVOUT_CVBS_PAL) - return 1; - else - return 0; -} - -static int rk610_ypbpr_get_modelist(struct rk_display_device *device, struct list_head **modelist) -{ - *modelist = &(rk610_ypbpr_monspecs.modelist); - return 0; -} - -static int rk610_ypbpr_set_mode(struct rk_display_device *device, struct fb_videomode *mode) -{ - int i; - - for(i = 0; i < ARRAY_SIZE(rk610_YPbPr_mode); i++) - { - if(fb_mode_is_equal(&rk610_YPbPr_mode[i], mode)) - { - if( (i + 3) != rk610_tv_output_status ) - { - rk610_ypbpr_monspecs.mode_set = i + 3; - rk610_ypbpr_monspecs.mode = (struct fb_videomode *)&rk610_YPbPr_mode[i]; - } - return 0; - } - } - - return -1; -} - -static int rk610_ypbpr_get_mode(struct rk_display_device *device, struct fb_videomode *mode) -{ - *mode = *(rk610_ypbpr_monspecs.mode); - return 0; -} - -static struct rk_display_ops rk610_ypbpr_display_ops = { - .setenable = rk610_ypbpr_set_enable, - .getenable = rk610_ypbpr_get_enable, - .getstatus = rk610_ypbpr_get_status, - .getmodelist = rk610_ypbpr_get_modelist, - .setmode = rk610_ypbpr_set_mode, - .getmode = rk610_ypbpr_get_mode, -}; - -static int rk610_display_YPbPr_probe(struct rk_display_device *device, void *devdata) -{ - device->owner = THIS_MODULE; - strcpy(device->type, "YPbPr"); - device->priority = DISPLAY_PRIORITY_YPbPr; - device->priv_data = devdata; - device->ops = &rk610_ypbpr_display_ops; - return 1; -} - -static struct rk_display_driver display_rk610_YPbPr = { - .probe = rk610_display_YPbPr_probe, -}; - -int rk610_register_display_ypbpr(struct device *parent) -{ - int i; - - memset(&rk610_ypbpr_monspecs, 0, sizeof(struct rk610_monspecs)); - INIT_LIST_HEAD(&rk610_ypbpr_monspecs.modelist); - for(i = 0; i < ARRAY_SIZE(rk610_YPbPr_mode); i++) - fb_add_videomode(&rk610_YPbPr_mode[i], &rk610_ypbpr_monspecs.modelist); - if(rk610_tv_output_status > TVOUT_CVBS_PAL) { - rk610_ypbpr_monspecs.mode = (struct fb_videomode *)&(rk610_YPbPr_mode[rk610_tv_output_status - 3]); - rk610_ypbpr_monspecs.mode_set = rk610_tv_output_status; - } - else { - rk610_ypbpr_monspecs.mode = (struct fb_videomode *)&(rk610_YPbPr_mode[3]); - rk610_ypbpr_monspecs.mode_set = TVOUT_YPbPr_1280x720p_60; - } - rk610_ypbpr_monspecs.ddev = rk_display_device_register(&display_rk610_YPbPr, parent, NULL); - if(RK610_LED_YPbPr_PIN != INVALID_GPIO) - { - if(gpio_request(RK610_LED_YPbPr_PIN, NULL) != 0) - { - gpio_free(RK610_LED_YPbPr_PIN); - dev_err(rk610_ypbpr_monspecs.ddev->dev, ">>>>>> RK610_LED_YPbPr_PIN gpio_request err \n "); - return -1; - } - gpio_pull_updown(RK610_LED_YPbPr_PIN,GPIOPullUp); - gpio_direction_output(RK610_LED_YPbPr_PIN, GPIO_HIGH); - } - return 0; -} diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig index e8be339e241e..bdfea2b473ef 100755 --- a/drivers/video/rockchip/Kconfig +++ b/drivers/video/rockchip/Kconfig @@ -58,6 +58,9 @@ config THREE_FB_BUFFER source "drivers/video/rockchip/lcdc/Kconfig" +source "drivers/video/rockchip/screen/Kconfig" +source "drivers/video/rockchip/transmitter/Kconfig" source "drivers/video/rockchip/hdmi/Kconfig" +source "drivers/video/rockchip/tve/Kconfig" source "drivers/video/rockchip/rga/Kconfig" -source "drivers/video/rockchip/lvds/Kconfig" + diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile index f20c306deedf..dc250b75fc78 100755 --- a/drivers/video/rockchip/Makefile +++ b/drivers/video/rockchip/Makefile @@ -1,4 +1,4 @@ -obj-$(CONFIG_FB_ROCKCHIP) += rk_fb.o rkfb_sysfs.o lcdc/ +obj-$(CONFIG_FB_ROCKCHIP) += rk_fb.o rkfb_sysfs.o lcdc/ screen/ +obj-$(CONFIG_RK_TRSM) += transmitter/ obj-$(CONFIG_RGA_RK30) += rga/ obj-$(CONFIG_RK_HDMI) += hdmi/ -obj-$(CONFIG_RK_LVDS) += lvds/ diff --git a/drivers/video/rockchip/lvds/Kconfig b/drivers/video/rockchip/lvds/Kconfig deleted file mode 100755 index 1577242cb924..000000000000 --- a/drivers/video/rockchip/lvds/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config RK_LVDS - bool "RK_LVDS support" diff --git a/drivers/video/rockchip/lvds/Makefile b/drivers/video/rockchip/lvds/Makefile deleted file mode 100755 index f410fda78ee1..000000000000 --- a/drivers/video/rockchip/lvds/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# Makefile for LVDS linux kernel module. -# - - -obj-$(CONFIG_RK_LVDS) += rk_lvds.o diff --git a/drivers/video/rockchip/lvds/rk_lvds.c b/drivers/video/rockchip/lvds/rk_lvds.c deleted file mode 100644 index 1c130cea26ea..000000000000 --- a/drivers/video/rockchip/lvds/rk_lvds.c +++ /dev/null @@ -1,63 +0,0 @@ -#include -#include -#include -#include -#include -#include "rk_lvds.h" - -static void rk_output_lvds(rk_screen *screen) -{ - LVDSWrReg(m_PDN_CBG(1)|m_PD_PLL(0)|m_PDN(1)|m_OEN(0) \ - |m_DS(DS_10PF)|m_MSBSEL(DATA_D0_MSB) \ - |m_OUT_FORMAT(screen->hw_format) \ - |m_LCDC_SEL(screen->lcdc_id)); - - printk("%s>>connect to lcdc output interface%d\n",__func__,screen->lcdc_id); -} - -static void rk_output_lvttl(rk_screen *screen) -{ - LVDSWrReg(m_PDN_CBG(0)|m_PD_PLL(1)|m_PDN(0)|m_OEN(1) \ - |m_DS(DS_10PF)|m_MSBSEL(DATA_D0_MSB) \ - |m_OUT_FORMAT(screen->hw_format) \ - |m_LCDC_SEL(screen->lcdc_id)); - printk("%s>>connect to lcdc output interface%d\n",__func__,screen->lcdc_id); -} - -static void rk_output_disable(void) -{ - LVDSWrReg(m_PDN_CBG(0)|m_PD_PLL(1)|m_PDN(0)|m_OEN(0)); - printk("%s: reg = 0x%x\n", __func__, LVDSRdReg()); -} - -static int rk_lvds_set_param(rk_screen *screen,bool enable ) -{ - if(OUT_ENABLE == enable){ - switch(screen->type){ - case SCREEN_LVDS: - rk_output_lvds(screen); - - break; - case SCREEN_RGB: - rk_output_lvttl(screen); - break; - default: - printk("%s>>>>LVDS not support this screen type %d,power down LVDS\n",__func__,screen->type); - rk_output_disable(); - break; - } - }else{ - rk_output_disable(); - } - return 0; -} - -int rk_lvds_register(rk_screen *screen) -{ - if(screen->sscreen_set == NULL) - screen->sscreen_set = rk_lvds_set_param; - - rk_lvds_set_param(screen , OUT_ENABLE); - - return 0; -} diff --git a/drivers/video/rockchip/lvds/rk_lvds.h b/drivers/video/rockchip/lvds/rk_lvds.h deleted file mode 100644 index 6cd2f889afd6..000000000000 --- a/drivers/video/rockchip/lvds/rk_lvds.h +++ /dev/null @@ -1,49 +0,0 @@ -#ifndef RK_LVDS_H_ -#define RK_LVDS_H - -#define LVDS_CON0_OFFSET 0x150 -#define LVDS_CON0_REG (RK2928_GRF_BASE + LVDS_CON0_OFFSET) - -#define LVDSRdReg() __raw_readl(LVDS_CON0_REG) -#define LVDSWrReg(val) __raw_writel( val ,LVDS_CON0_REG) - -#define m_value(x,offset,mask) \ - ((mask<<(offset+16)) | (x&mask)< +#include +#include "../../rk29_fb.h" +#include +#include +#include +#include "screen.h" + + +/* Base */ +#define OUT_TYPE SCREEN_RGB + +#if defined(CONFIG_MACH_RK29SDK)||defined(CONFIG_MACH_RK29FIH) +#define OUT_FACE OUT_D888_P666 +#else +#define OUT_FACE OUT_D888_P666 +#endif +#define OUT_CLK 58500000 // 65000000 +#define LCDC_ACLK 500000000//312000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 10 +#define H_BP 100 +#define H_VD 1024 +#define H_FP 210 + +#define V_PW 10 +#define V_BP 10 +#define V_VD 600 +#define V_FP 18 + +#define LCD_WIDTH 202 +#define LCD_HEIGHT 152 +/* Other */ +#define DCLK_POL 0 +#if defined(CONFIG_MACH_RK29SDK)||defined(CONFIG_MACH_RK29FIH) +#define SWAP_RB 0 +#else +#define SWAP_RB 0 +#endif + +void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) +{ + /* screen type & face */ + screen->type = OUT_TYPE; + screen->face = OUT_FACE; + + /* Screen size */ + screen->x_res = H_VD; + screen->y_res = V_VD; + + screen->width = LCD_WIDTH; + screen->height = LCD_HEIGHT; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK; + screen->pixclock = OUT_CLK; + screen->left_margin = H_BP; + screen->right_margin = H_FP; + screen->hsync_len = H_PW; + screen->upper_margin = V_BP; + screen->lower_margin = V_FP; + screen->vsync_len = V_PW; + + /* Pin polarity */ + screen->pin_hsync = 0; + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = DCLK_POL; + + /* Swap rule */ + screen->swap_rb = SWAP_RB; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = NULL; + screen->standby = NULL; +} + + + diff --git a/drivers/video/rockchip/screen/lcd_AUO_A080SN03.c b/drivers/video/rockchip/screen/lcd_AUO_A080SN03.c new file mode 100644 index 000000000000..216e7bd91456 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_AUO_A080SN03.c @@ -0,0 +1,42 @@ +/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */ + +#ifndef __LCD_AUO__ +#define __LCD_AUO__ + + + + +/* Base */ +#define SCREEN_TYPE SCREEN_RGB +#define LVDS_FORMAT LVDS_8BIT_1 +#define OUT_FACE OUT_P888//OUT_P666 +#define DCLK 40000000 +#define LCDC_ACLK 500000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 1//30//48 //10 +#define H_BP 46//10//40 //100 +#define H_VD 800 //1024 +#define H_FP 210// //210 + +#define V_PW 3// 2// 3//13//10 +#define V_BP 23// 18 // 23//10// //10 +#define V_VD 600//480 //768 +#define V_FP 2// 8// 12//22 //18 + +/* Other */ +#define DCLK_POL 1 +#define SWAP_RB 0 +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_RG 0 +#define SWAP_GB 0 + + +#define LCD_WIDTH 162//154 //need modify +#define LCD_HEIGHT 121//85 +#endif + diff --git a/drivers/video/rockchip/screen/lcd_B101AW06.c b/drivers/video/rockchip/screen/lcd_B101AW06.c new file mode 100644 index 000000000000..e0000cacba2c --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_B101AW06.c @@ -0,0 +1,76 @@ +#include +#include +#include "../../rk29_fb.h" +#include +#include +#include +#include "screen.h" + + +/* Base */ +#define OUT_TYPE SCREEN_RGB +#define OUT_FACE OUT_D888_P666 +#define OUT_CLK 45000000 +#define LCDC_ACLK 312000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 10 +#define H_BP 80 +#define H_VD 1024 +#define H_FP 100 + +#define V_PW 10 +#define V_BP 10 +#define V_VD 600 +#define V_FP 18 + +#define LCD_WIDTH 202 +#define LCD_HEIGHT 152 +/* Other */ +#define DCLK_POL 0 +#define SWAP_RB 0 + + +void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) +{ + /* screen type & face */ + screen->type = OUT_TYPE; + screen->face = OUT_FACE; + + /* Screen size */ + screen->x_res = H_VD; + screen->y_res = V_VD; + + screen->width = LCD_WIDTH; + screen->height = LCD_HEIGHT; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK; + screen->pixclock = OUT_CLK; + screen->left_margin = H_BP; + screen->right_margin = H_FP; + screen->hsync_len = H_PW; + screen->upper_margin = V_BP; + screen->lower_margin = V_FP; + screen->vsync_len = V_PW; + + /* Pin polarity */ + screen->pin_hsync = 0; + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = DCLK_POL; + + /* Swap rule */ + screen->swap_rb = SWAP_RB; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = NULL; + screen->standby = NULL; +} + + + diff --git a/drivers/video/rockchip/screen/lcd_CPTclaa038la31xe.c b/drivers/video/rockchip/screen/lcd_CPTclaa038la31xe.c new file mode 100644 index 000000000000..2b896ba81746 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_CPTclaa038la31xe.c @@ -0,0 +1,327 @@ +/* + * Copyright (C) 2011 ROCKCHIP, Inc. + * + * author: hhb@rock-chips.com + * creat date: 2011-03-22 + * route:drivers/video/display/screen/lcd_ls035y8dx02a.c - driver for rk29 phone sdk + * declaration: This program driver have been tested in rk29_phonesdk hardware platform at 2011.03.31. + * about migration: you need just 3 interface functions,such as lcd_init(void),lcd_standby(u8 enable), + * set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include +#include +#include "../../rk29_fb.h" +#include +#include +#include +#include "screen.h" + +/* Base */ +#define OUT_TYPE SCREEN_RGB +#define OUT_FACE OUT_P666 +#define OUT_CLK (26*1000000) //***27 uint Hz +#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ�� + +/* Timing */ +#define H_PW 10//8 //16 +#define H_BP 10//24 +#define H_VD 480//320 +#define H_FP 10//60//16 + +#define V_PW 3 +#define V_BP 3 +#define V_VD 800//480 +#define V_FP 3 + +#define LCD_WIDTH 800 //need modify +#define LCD_HEIGHT 480 + +/* Other */ +#define DCLK_POL 0 //0 +#define SWAP_RB 0 + +static struct rk29lcd_info *gLcd_info = NULL; +int lcd_init(void); +int lcd_standby(u8 enable); + +#define RXD_PORT RK29_PIN2_PC7 +#define TXD_PORT gLcd_info->txd_pin +#define CLK_PORT gLcd_info->clk_pin +#define CS_PORT gLcd_info->cs_pin +#define RESET_PORT RK29_PIN6_PC6 + +#define CS_OUT() gpio_direction_output(CS_PORT, 1) +#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) +#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) +#define CLK_OUT() gpio_direction_output(CLK_PORT, 0) +#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) +#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) +#define TXD_OUT() gpio_direction_output(TXD_PORT, 1) +#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) +#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) +#define RXD_IN() gpio_direction_input(RXD_PORT) +#define RXD_GET() gpio_get_value(RXD_PORT) + +#define DRVDelayUs(i) udelay(i*4) +#define DRVDelayMs(i) mdelay(i*4) + +/*---------------------------------------------------------------------- +Name : Claa0381a31RegSet +Desc : IO模拟SPI对屏寄存器进行设置 +Params : Reg 寄存器地址 + Data 数据 +Return : +Notes : 设置前需要调用SetIOSpiMode(1)进入IO模式 + 设置后需要调用SetIOSpiMode(0)退出IO模式 +----------------------------------------------------------------------*/ +void Claa0381a31Cmd(u32 data) +{ + u32 i; + TXD_OUT(); + CLK_OUT(); + CS_OUT(); + DRVDelayUs(2); + + CS_SET(); + TXD_SET(); + CLK_SET(); + DRVDelayUs(2); + + if(data) + { + CS_CLR(); + DRVDelayUs(2); + + TXD_CLR(); //wr 0 + CLK_CLR(); + DRVDelayUs(2); + CLK_SET(); + DRVDelayUs(2); + + for(i = 0; i < 8; i++) //reg + { + if(data &(1<<(7-i))) + TXD_SET(); + else + TXD_CLR(); + + // 模拟CLK + CLK_CLR(); + DRVDelayUs(2); + CLK_SET(); + DRVDelayUs(2); + } + } +} + +void Claa0381a31Data(u32 data) +{ + u32 i; + + TXD_SET(); + CLK_CLR(); + DRVDelayUs(2); + CLK_SET(); + DRVDelayUs(2); + + for(i = 0; i < 8; i++) //reg + { + if(data &(1<<(7-i))) + TXD_SET(); + else + TXD_CLR(); + + // 模拟CLK + CLK_CLR(); + DRVDelayUs(2); + CLK_SET(); + DRVDelayUs(2); + } + +} + + +void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) +{ + /* screen type & face */ + screen->type = OUT_TYPE; + screen->face = OUT_FACE; + + /* Screen size */ + screen->x_res = H_VD; + screen->y_res = V_VD; + screen->width = LCD_WIDTH; + screen->height = LCD_HEIGHT; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK; + screen->pixclock = OUT_CLK; + screen->left_margin = H_BP; /*>2*/ + screen->right_margin = H_FP; /*>2*/ + screen->hsync_len = H_PW; /*>2*/ //***all > 326, 4upper_margin = V_BP; /*>2*/ + screen->lower_margin = V_FP; /*>2*/ + screen->vsync_len = V_PW; /*>6*/ + + /* Pin polarity */ + screen->pin_hsync = 0; + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = DCLK_POL; + + /* Swap rule */ + screen->swap_rb = SWAP_RB; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = lcd_init; + screen->standby = lcd_standby; + if(lcd_info) + gLcd_info = lcd_info; +} + +int lcd_init(void) +{ + volatile u32 data; + if(gLcd_info){ + gLcd_info->io_init(); + } + + /* reset lcd to start init lcd by software if there is no hardware reset circuit for the lcd */ +#ifdef RESET_PORT + gpio_request(RESET_PORT, NULL); + gpio_direction_output(RESET_PORT, 0); + mdelay(2); + gpio_set_value(RESET_PORT, 1); + mdelay(10); + gpio_free(RESET_PORT); +#endif + + printk("lcd init...\n"); + + Claa0381a31Cmd(0xb9); + Claa0381a31Data(0xff); + Claa0381a31Data(0x83); + Claa0381a31Data(0x63); + Claa0381a31Cmd(0); + + Claa0381a31Cmd(0xb1); + Claa0381a31Data(0x81); + Claa0381a31Data(0x30); + Claa0381a31Data(0x03); + Claa0381a31Data(0x34); + Claa0381a31Data(0x02); + Claa0381a31Data(0x13); + Claa0381a31Data(0x11); + Claa0381a31Data(0x00); + Claa0381a31Data(0x35); + Claa0381a31Data(0x3e); + Claa0381a31Data(0x16); + Claa0381a31Data(0x16); + Claa0381a31Cmd(0); + + Claa0381a31Cmd(0x11); + Claa0381a31Cmd(0); + + DRVDelayMs(150); + + Claa0381a31Cmd(0xb6); + Claa0381a31Data(0x42); + Claa0381a31Cmd(0); + + Claa0381a31Cmd(0xb3); + Claa0381a31Data(0x01); + Claa0381a31Cmd(0); + + Claa0381a31Cmd(0xb4); + Claa0381a31Data(0x04); + Claa0381a31Cmd(0); + + Claa0381a31Cmd(0xe0); + Claa0381a31Data(0x00); + Claa0381a31Data(0x1e); + Claa0381a31Data(0x23); + Claa0381a31Data(0x2d); + Claa0381a31Data(0x2d); + Claa0381a31Data(0x3f); + Claa0381a31Data(0x08); + Claa0381a31Data(0xcc); + Claa0381a31Data(0x8c); + Claa0381a31Data(0xcf); + Claa0381a31Data(0x51); + Claa0381a31Data(0x12); + Claa0381a31Data(0x52); + Claa0381a31Data(0x92); + Claa0381a31Data(0x1E); + Claa0381a31Data(0x00); + Claa0381a31Data(0x1e); + Claa0381a31Data(0x23); + Claa0381a31Data(0x2d); + Claa0381a31Data(0x2d); + Claa0381a31Data(0x3f); + Claa0381a31Data(0x08); + Claa0381a31Data(0xcc); + Claa0381a31Data(0x8c); + Claa0381a31Data(0xcf); + Claa0381a31Data(0x51); + Claa0381a31Data(0x12); + Claa0381a31Data(0x52); + Claa0381a31Data(0x92); + Claa0381a31Data(0x1E); + Claa0381a31Cmd(0); + + Claa0381a31Cmd(0xcc); + Claa0381a31Data(0x0b); + Claa0381a31Cmd(0); + + Claa0381a31Cmd(0x3a); + Claa0381a31Data(0x60); + Claa0381a31Cmd(0); + + DRVDelayMs(20); + + Claa0381a31Cmd(0x29); + Claa0381a31Cmd(0); + + if(gLcd_info) + gLcd_info->io_deinit(); + + return 0; +} + +int lcd_standby(u8 enable) //***enable =1 means suspend, 0 means resume +{ + + if(gLcd_info) + gLcd_info->io_init(); + printk("lcd standby\n"); + if(enable) { + printk("lcd standby...enable =1 means suspend\n"); + //spi_screenreg_set(0x10, 0xffff, 0xffff); + //mdelay(120); + //spi_screenreg_set(0x28, 0xffff, 0xffff); + } else { + printk("lcd standby...0 means resume\n"); + //spi_screenreg_set(0x29, 0xffff, 0xffff); + //spi_screenreg_set(0x11, 0xffff, 0xffff); + //mdelay(150); + } + + if(gLcd_info) + gLcd_info->io_deinit(); + return 0; +} + diff --git a/drivers/video/rockchip/screen/lcd_E242868_rk3168_86v.c b/drivers/video/rockchip/screen/lcd_E242868_rk3168_86v.c new file mode 100644 index 000000000000..3b38065f42be --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_E242868_rk3168_86v.c @@ -0,0 +1,34 @@ +#ifndef __LCD_E242868__ +#define __LCD_E242868__ +/* Base */ +#define SCREEN_TYPE SCREEN_RGB +#define LVDS_FORMAT LVDS_8BIT_1 +#define OUT_FACE OUT_P888 +#define DCLK 50000000 +#define LCDC_ACLK 500000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 30 +#define H_BP 10 +#define H_VD 1024 +#define H_FP 210 + +#define V_PW 13 +#define V_BP 10 +#define V_VD 600 +#define V_FP 22 + +#define LCD_WIDTH 154 +#define LCD_HEIGHT 85 + +/* Other */ +#define DCLK_POL 0 +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_RG 0 +#define SWAP_GB 0 + +#endif diff --git a/drivers/video/rockchip/screen/lcd_I30_800x480.c b/drivers/video/rockchip/screen/lcd_I30_800x480.c new file mode 100644 index 000000000000..5b70c8a4ad13 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_I30_800x480.c @@ -0,0 +1,62 @@ +#ifndef __LCD_I30__ +#define __LCD_I30__ +/* Base */ +#define LCD_WIDTH 154 //need modify +#define LCD_HEIGHT 85 + +#define SCREEN_TYPE SCREEN_RGB +#define LVDS_FORMAT LVDS_8BIT_1 +#define OUT_FACE OUT_P666 +#define DCLK 30000000 +#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 48 //10 +#define H_BP 88 //100 +#define H_VD 800 +#define H_FP 40 //210 + +#define V_PW 3 //10 +#define V_BP 32 //10 +#define V_VD 480 +#define V_FP 13 //18 + +/* Other */ +#define DCLK_POL 1 +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_RG 0 +#define SWAP_GB 0 + +#define RK_SCREEN_INIT +static struct rk29lcd_info *gLcd_info = NULL; + +static int rk_lcd_init(void) +{ + int ret = 0; + + if(gLcd_info && gLcd_info->io_init) + gLcd_info->io_init(); + + return 0; +} + +static int rk_lcd_standby(u8 enable) +{ + if(!enable) + { + if(gLcd_info && gLcd_info->io_enable) + gLcd_info->io_enable(); + } + else + { + if(gLcd_info && gLcd_info->io_disable) + gLcd_info->io_disable(); + } + return 0; +} + +#endif diff --git a/drivers/video/rockchip/screen/lcd_LG_LP097X02.c b/drivers/video/rockchip/screen/lcd_LG_LP097X02.c new file mode 100644 index 000000000000..220092b0b275 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_LG_LP097X02.c @@ -0,0 +1,33 @@ +#ifndef __LCD_LG097X02__ +#define __LCD_LG097X02__ + +/* Base */ +#define SCREEN_TYPE SCREEN_RGB +#define LVDS_FORMAT LVDS_8BIT_1 +#define OUT_FACE OUT_D888_P666 +#define DCLK 100000000 +#define LCDC_ACLK 500000000 +/* Timing */ +#define H_PW 320 +#define H_BP 480 +#define H_VD 1024 +#define H_FP 260 + +#define V_PW 10 +#define V_BP 6 +#define V_VD 768 +#define V_FP 16 + +#define LCD_WIDTH 196// 142 // 202 +#define LCD_HEIGHT 147 //106// 152 +/* Other */ +#define DCLK_POL 1 // +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_RG 0 +#define SWAP_GB 0 + +#endif diff --git a/drivers/video/rockchip/screen/lcd_LP097QX1.c b/drivers/video/rockchip/screen/lcd_LP097QX1.c new file mode 100644 index 000000000000..50a5e0c5b5ed --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_LP097QX1.c @@ -0,0 +1,77 @@ +#ifndef __LCD_LP097QX1__ +#define __LCD_LP097QX1__ + +/* Base */ +#define SCREEN_TYPE SCREEN_RGB +#define LVDS_FORMAT LVDS_8BIT_1 +#define OUT_FACE OUT_P666 +#define DCLK 205000000 //160000000//205000000 +#define LCDC_ACLK 300000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 5 +#define H_BP 500 + +#if defined(CONFIG_ARCH_RK3066B) +#define H_VD 2047 +#else +#define H_VD 2048 +#endif + + +#define H_FP 15 + +#define V_PW 1 +#define V_BP 9 +#define V_VD 1536 +#define V_FP 3 + +#define LCD_WIDTH 216 +#define LCD_HEIGHT 135 +/* Other */ +#define DCLK_POL 1 +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_DUMMY 0 +#define SWAP_GB 0 +#define SWAP_RG 0 + +int dsp_lut[256] ={ + 0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707, + 0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f, + 0x00101010, 0x00111111, 0x00121212, 0x00131313, 0x00141414, 0x00151515, 0x00161616, 0x00171717, + 0x00181818, 0x00191919, 0x001a1a1a, 0x001b1b1b, 0x001c1c1c, 0x001d1d1d, 0x001e1e1e, 0x001f1f1f, + 0x00202020, 0x00212121, 0x00222222, 0x00232323, 0x00242424, 0x00252525, 0x00262626, 0x00272727, + 0x00282828, 0x00292929, 0x002a2a2a, 0x002b2b2b, 0x002c2c2c, 0x002d2d2d, 0x002e2e2e, 0x002f2f2f, + 0x00303030, 0x00313131, 0x00323232, 0x00333333, 0x00343434, 0x00353535, 0x00363636, 0x00373737, + 0x00383838, 0x00393939, 0x003a3a3a, 0x003b3b3b, 0x003c3c3c, 0x003d3d3d, 0x003e3e3e, 0x003f3f3f, + 0x00404040, 0x00414141, 0x00424242, 0x00434343, 0x00444444, 0x00454545, 0x00464646, 0x00474747, + 0x00484848, 0x00494949, 0x004a4a4a, 0x004b4b4b, 0x004c4c4c, 0x004d4d4d, 0x004e4e4e, 0x004f4f4f, + 0x00505050, 0x00515151, 0x00525252, 0x00535353, 0x00545454, 0x00555555, 0x00565656, 0x00575757, + 0x00585858, 0x00595959, 0x005a5a5a, 0x005b5b5b, 0x005c5c5c, 0x005d5d5d, 0x005e5e5e, 0x005f5f5f, + 0x00606060, 0x00616161, 0x00626262, 0x00636363, 0x00646464, 0x00656565, 0x00666666, 0x00676767, + 0x00686868, 0x00696969, 0x006a6a6a, 0x006b6b6b, 0x006c6c6c, 0x006d6d6d, 0x006e6e6e, 0x006f6f6f, + 0x00707070, 0x00717171, 0x00727272, 0x00737373, 0x00747474, 0x00757575, 0x00767676, 0x00777777, + 0x00787878, 0x00797979, 0x007a7a7a, 0x007b7b7b, 0x007c7c7c, 0x007d7d7d, 0x007e7e7e, 0x007f7f7f, + 0x00808080, 0x00818181, 0x00828282, 0x00838383, 0x00848484, 0x00858585, 0x00868686, 0x00878787, + 0x00888888, 0x00898989, 0x008a8a8a, 0x008b8b8b, 0x008c8c8c, 0x008d8d8d, 0x008e8e8e, 0x008f8f8f, + 0x00909090, 0x00919191, 0x00929292, 0x00939393, 0x00949494, 0x00959595, 0x00969696, 0x00979797, + 0x00989898, 0x00999999, 0x009a9a9a, 0x009b9b9b, 0x009c9c9c, 0x009d9d9d, 0x009e9e9e, 0x009f9f9f, + 0x00a0a0a0, 0x00a1a1a1, 0x00a2a2a2, 0x00a3a3a3, 0x00a4a4a4, 0x00a5a5a5, 0x00a6a6a6, 0x00a7a7a7, + 0x00a8a8a8, 0x00a9a9a9, 0x00aaaaaa, 0x00ababab, 0x00acacac, 0x00adadad, 0x00aeaeae, 0x00afafaf, + 0x00b0b0b0, 0x00b1b1b1, 0x00b2b2b2, 0x00b3b3b3, 0x00b4b4b4, 0x00b5b5b5, 0x00b6b6b6, 0x00b7b7b7, + 0x00b8b8b8, 0x00b9b9b9, 0x00bababa, 0x00bbbbbb, 0x00bcbcbc, 0x00bdbdbd, 0x00bebebe, 0x00bfbfbf, + 0x00c0c0c0, 0x00c1c1c1, 0x00c2c2c2, 0x00c3c3c3, 0x00c4c4c4, 0x00c5c5c5, 0x00c6c6c6, 0x00c7c7c7, + 0x00c8c8c8, 0x00c9c9c9, 0x00cacaca, 0x00cbcbcb, 0x00cccccc, 0x00cdcdcd, 0x00cecece, 0x00cfcfcf, + 0x00d0d0d0, 0x00d1d1d1, 0x00d2d2d2, 0x00d3d3d3, 0x00d4d4d4, 0x00d5d5d5, 0x00d6d6d6, 0x00d7d7d7, + 0x00d8d8d8, 0x00d9d9d9, 0x00dadada, 0x00dbdbdb, 0x00dcdcdc, 0x00dddddd, 0x00dedede, 0x00dfdfdf, + 0x00e0e0e0, 0x00e1e1e1, 0x00e2e2e2, 0x00e3e3e3, 0x00e4e4e4, 0x00e5e5e5, 0x00e6e6e6, 0x00e7e7e7, + 0x00e8e8e8, 0x00e9e9e9, 0x00eaeaea, 0x00ebebeb, 0x00ececec, 0x00ededed, 0x00eeeeee, 0x00efefef, + 0x00f0f0f0, 0x00f1f1f1, 0x00f2f2f2, 0x00f3f3f3, 0x00f4f4f4, 0x00f5f5f5, 0x00f6f6f6, 0x00f7f7f7, + 0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff, +}; + +#endif diff --git a/drivers/video/rockchip/screen/lcd_YQ70CPT9160.c b/drivers/video/rockchip/screen/lcd_YQ70CPT9160.c new file mode 100644 index 000000000000..c8854b36fcbf --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_YQ70CPT9160.c @@ -0,0 +1,38 @@ +/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */ + + +#ifndef __LCD_YQ70CPT__ +#define __LCD_YQ70CPT__ +/* Base */ +#define SCREEN_TYPE SCREEN_RGB +#define LVDS_FORMAT LVDS_8BIT_1 +#define OUT_FACE OUT_P666 +#define DCLK 33000000 +#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 30//48 //10 +#define H_BP 10//40 //100 +#define H_VD 800 //1024 +#define H_FP 210// //210 + +#define V_PW 13//10 +#define V_BP 10// //10 +#define V_VD 480 //768 +#define V_FP 22 //18 + +/* Other */ +#define DCLK_POL 1 +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_RG 0 +#define SWAP_GB 0 + + +#define LCD_WIDTH 154 //need modify +#define LCD_HEIGHT 85 + +#endif diff --git a/drivers/video/rockchip/screen/lcd_YQ70CPT9160_rk3168_86v.c b/drivers/video/rockchip/screen/lcd_YQ70CPT9160_rk3168_86v.c new file mode 100644 index 000000000000..c835cbaa2857 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_YQ70CPT9160_rk3168_86v.c @@ -0,0 +1,36 @@ +/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */ + +#ifndef __LCD_YQ70CPT__ +#define __LCD_YQ70CPT__ +/* Base */ +#define SCREEN_TYPE SCREEN_RGB +#define OUT_FACE OUT_P888 +#define DCLK 33000000 +#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 30//48 //10 +#define H_BP 10//40 //100 +#define H_VD 800 //1024 +#define H_FP 210// //210 + +#define V_PW 13//10 +#define V_BP 10// //10 +#define V_VD 480 //768 +#define V_FP 22 //18 + +#define LCD_WIDTH 154 +#define LCD_HEIGHT 85 + +/* Other */ +#define DCLK_POL 0 + +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_RG 0 +#define SWAP_GB 0 + +#endif diff --git a/drivers/video/rockchip/screen/lcd_YQ70CPT9160_v86.c b/drivers/video/rockchip/screen/lcd_YQ70CPT9160_v86.c new file mode 100644 index 000000000000..530133e821e2 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_YQ70CPT9160_v86.c @@ -0,0 +1,40 @@ +/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */ +#ifndef __LCD_YQ70CPT__ +#define __LCD_YQ70CPT__ + + +/* Base */ +#define SCREEN_TYPE SCREEN_RGB +#define LVDS_FORMAT LVDS_8BIT_1 +#define OUT_FACE OUT_P666 +#define DCLK 33000000 +#define LCDC_ACLK 50000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 30//48 //10 +#define H_BP 10//40 //100 +#define H_VD 800 //1024 +#define H_FP 210// //210 + +#define V_PW 13//10 +#define V_BP 10// //10 +#define V_VD 480 //768 +#define V_FP 22 //18 + +/* Other */ +#define DCLK_POL 0 +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_DUMMY 0 +#define SWAP_GB 0 +#define SWAP_RG 0 + + + +#define LCD_WIDTH 154 //need modify +#define LCD_HEIGHT 85 + +#endif diff --git a/drivers/video/rockchip/screen/lcd_a060se02.c b/drivers/video/rockchip/screen/lcd_a060se02.c new file mode 100644 index 000000000000..1cb426f43550 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_a060se02.c @@ -0,0 +1,168 @@ +#include +#include +#include "../../rk29_fb.h" +#include +#include +#include "screen.h" + +/* Base */ +#define OUT_TYPE SCREEN_MCU +#define OUT_FACE OUT_P16BPP4 + +#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 1 +#define H_BP 1 +#define H_VD 600 +#define H_FP 5 + +#define V_PW 1 +#define V_BP 1 +#define V_VD 800 +#define V_FP 1 + +#define P_WR 200 + +/* Other */ +#define DCLK_POL 0 +#define SWAP_RB 0 + +#define LCD_WIDTH 600 //need modify +#define LCD_HEIGHT 800 + + +int lcd_init(void) +{ + mcu_ioctl(MCU_SETBYPASS, 1); + + // init set + mcu_ioctl(MCU_WRCMD, 0x0000); + mcu_ioctl(MCU_WRDATA, 0x0001); + + // start display + mcu_ioctl(MCU_WRCMD, 0x1001); + mcu_ioctl(MCU_WRDATA, 0x0001); + mcu_ioctl(MCU_WRDATA, 0x0001); + mcu_ioctl(MCU_WRDATA, 0x0320); + mcu_ioctl(MCU_WRDATA, 0x0258); + + // ³õʼ»¯Í¼Ïó + int i=0, j=0; + while(0) + { + mcu_ioctl(MCU_WRCMD, 0x1001); + mcu_ioctl(MCU_WRDATA, 0x0001); + mcu_ioctl(MCU_WRDATA, 0x0001); + mcu_ioctl(MCU_WRDATA, 0x0320); + mcu_ioctl(MCU_WRDATA, 0x0258); + + for(i=0; i<800*100; i++) + mcu_ioctl(MCU_WRDATA, j%2 ? 0xffff : 0x0000); + for(i=0; i<800*100; i++) + mcu_ioctl(MCU_WRDATA, j%2 ? 0x0000 : 0xffff); + j++; + + mcu_ioctl(MCU_WRCMD, 0x1002); + msleep(2000); + printk(">>>>>> lcd_init : send test image! \n"); + } + + mcu_ioctl(MCU_SETBYPASS, 0); + return 0; +} + +int lcd_standby(u8 enable) +{ + return 0; +} + +int lcd_refresh(u8 arg) +{ + mcu_ioctl(MCU_SETBYPASS, 1); + + switch(arg) + { + case REFRESH_PRE: //DMA´«ËÍÇ°×¼±¸ + #if 0 + mcu_ioctl(MCU_WRCMD, 0x1001); + mcu_ioctl(MCU_WRDATA, 0x0001); + mcu_ioctl(MCU_WRDATA, 0x0001); + mcu_ioctl(MCU_WRDATA, 0x0320); + mcu_ioctl(MCU_WRDATA, 0x0258); + printk(">>>>>> lcd_refresh : REFRESH_PRE! \n"); + #else + // init set + mcu_ioctl(MCU_WRCMD, 0x0000); + mcu_ioctl(MCU_WRDATA, 0x0001); + // start display + mcu_ioctl(MCU_WRCMD, 0x1001); + mcu_ioctl(MCU_WRDATA, 0x0001); + mcu_ioctl(MCU_WRDATA, 0x0001); + mcu_ioctl(MCU_WRDATA, 0x0320); + mcu_ioctl(MCU_WRDATA, 0x0258); + printk(">>>>>> lcd_refresh : REFRESH_PRE!!! \n"); + #endif + break; + + case REFRESH_END: //DMA´«ËͽáÊøºó + mcu_ioctl(MCU_WRCMD, 0x1002); + printk(">>>>>> lcd_refresh : REFRESH_END! \n"); + break; + + default: + break; + } + + mcu_ioctl(MCU_SETBYPASS, 0); + + return 0; +} + + + +void set_lcd_info(struct rk29fb_screen *screen) +{ + /* screen type & face */ + screen->type = OUT_TYPE; + screen->face = OUT_FACE; + + /* Screen size */ + screen->x_res = H_VD; + screen->y_res = V_VD; + + screen->width = LCD_WIDTH; + screen->height = LCD_HEIGHT; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK; + screen->left_margin = H_BP; + screen->right_margin = H_FP; + screen->hsync_len = H_PW; + screen->upper_margin = V_BP; + screen->lower_margin = V_FP; + screen->vsync_len = V_PW; + screen->mcu_wrperiod = P_WR; + + /* Pin polarity */ + screen->pin_hsync = 0; + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = DCLK_POL; + + /* Swap rule */ + screen->swap_rb = SWAP_RB; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = lcd_init; + screen->standby = lcd_standby; + screen->refresh = lcd_refresh; +} + + + + diff --git a/drivers/video/rockchip/screen/lcd_at070tn93.c b/drivers/video/rockchip/screen/lcd_at070tn93.c new file mode 100644 index 000000000000..614f9f79b30b --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_at070tn93.c @@ -0,0 +1,76 @@ +#include +#include +#include "../../rk29_fb.h" +#include +#include +#include +#include "screen.h" + + +/* Base */ +#define OUT_TYPE SCREEN_RGB + +#define OUT_FACE OUT_P888 +#define OUT_CLK 46800000//33300000//50000000 +#define LCDC_ACLK 500000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 10 +#define H_BP 36 +#define H_VD 800 +#define H_FP 210 + +#define V_PW 10 +#define V_BP 13 +#define V_VD 480 +#define V_FP 22 + +#define LCD_WIDTH 154 +#define LCD_HEIGHT 86 +/* Other */ +#define DCLK_POL 0 +#define SWAP_RB 0 + +void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) +{ + /* screen type & face */ + screen->type = OUT_TYPE; + screen->face = OUT_FACE; + + /* Screen size */ + screen->x_res = H_VD; + screen->y_res = V_VD; + + screen->width = LCD_WIDTH; + screen->height = LCD_HEIGHT; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK; + screen->pixclock = OUT_CLK; + screen->left_margin = H_BP; + screen->right_margin = H_FP; + screen->hsync_len = H_PW; + screen->upper_margin = V_BP; + screen->lower_margin = V_FP; + screen->vsync_len = V_PW; + + /* Pin polarity */ + screen->pin_hsync = 0; + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = DCLK_POL; + + /* Swap rule */ + screen->swap_rb = SWAP_RB; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = NULL; + screen->standby = NULL; +} + + + diff --git a/drivers/video/rockchip/screen/lcd_auto.c b/drivers/video/rockchip/screen/lcd_auto.c new file mode 100644 index 000000000000..79c4ec56b59b --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_auto.c @@ -0,0 +1,474 @@ + +#ifndef __LCD_AUTO__ +#define __LCD_AUTO__ + +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_HAS_EARLYSUSPEND) +#include +#endif +#include +#include + + +//FOR ID0 +/* Base */ +#define SCREEN_TYPE_ID0 SCREEN_RGB + +#define OUT_FACE_ID0 OUT_P888 +#define DCLK_ID0 71000000 +#define LCDC_ACLK_ID0 500000000//312000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW_ID0 100 +#define H_BP_ID0 100 +#define H_VD_ID0 1024 +#define H_FP_ID0 120 + +#define V_PW_ID0 10 +#define V_BP_ID0 10 +#define V_VD_ID0 600 +#define V_FP_ID0 15 + +#define LCD_WIDTH_ID0 202 +#define LCD_HEIGHT_ID0 152 +/* Other */ +#define DCLK_POL_ID0 0 +#define DEN_POL_ID0 0 +#define VSYNC_POL_ID0 0 +#define HSYNC_POL_ID0 0 + +#define SWAP_RB_ID0 0 +#define SWAP_DUMMY_ID0 0 +#define SWAP_GB_ID0 0 +#define SWAP_RG_ID0 0 + + + +//FOR ID1 +/* Base */ +#define SCREEN_TYPE_ID1 SCREEN_RGB +#define OUT_FACE_ID1 OUT_P888 +#define DCLK_ID1 71000000 +#define LCDC_ACLK_ID1 500000000 + +/* Timing */ +#define H_PW_ID1 10 +#define H_BP_ID1 160 +#define H_VD_ID1 1024 +#define H_FP_ID1 16 + +#define V_PW_ID1 3 +#define V_BP_ID1 23 +#define V_VD_ID1 768 +#define V_FP_ID1 12 + + +/* Other */ +#define DCLK_POL_ID1 0 +#define DEN_POL_ID1 0 +#define VSYNC_POL_ID1 0 +#define HSYNC_POL_ID1 0 + +#define SWAP_RB_ID1 0 +#define SWAP_DUMMY_ID1 0 +#define SWAP_GB_ID1 0 +#define SWAP_RG_ID1 0 + + +#define LCD_WIDTH_ID1 270 +#define LCD_HEIGHT_ID1 202 + + + +//FOR ID2 +#define SCREEN_TYPE_ID2 SCREEN_RGB + +#define OUT_FACE_ID2 OUT_P888 +#define DCLK_ID2 65000000 +#define LCDC_ACLK_ID2 500000000 + +/* Timing */ +#define H_PW_ID2 100 +#define H_BP_ID2 100 +#define H_VD_ID2 1024 +#define H_FP_ID2 120 + +#define V_PW_ID2 10 +#define V_BP_ID2 10 +#define V_VD_ID2 768 +#define V_FP_ID2 15 + +#define LCD_WIDTH_ID2 216 +#define LCD_HEIGHT_ID2 162 +/* Other */ +#define DCLK_POL_ID2 0 +#define DEN_POL_ID2 0 +#define VSYNC_POL_ID2 0 +#define HSYNC_POL_ID2 0 + +#define SWAP_RB_ID2 0 +#define SWAP_DUMMY_ID2 0 +#define SWAP_GB_ID2 0 +#define SWAP_RG_ID2 0 + + +//FOR ID3 +/* Base */ +#define SCREEN_TYPE_ID3 SCREEN_RGB +#define OUT_FACE_ID3 OUT_P888 +#define DCLK_ID3 71000000 +#define LCDC_ACLK_ID3 500000000 + +/* Timing */ +#define H_PW_ID3 10 +#define H_BP_ID3 160 +#define H_VD_ID3 1280 +#define H_FP_ID3 16 + +#define V_PW_ID3 3 +#define V_BP_ID3 23 +#define V_VD_ID3 800 +#define V_FP_ID3 12 + + +/* Other */ +#define DCLK_POL_ID3 0 +#define DEN_POL_ID3 0 +#define VSYNC_POL_ID3 0 +#define HSYNC_POL_ID3 0 + +#define SWAP_RB_ID3 0 +#define SWAP_DUMMY_ID3 0 +#define SWAP_GB_ID3 0 +#define SWAP_RG_ID3 0 + + +#define LCD_WIDTH_ID3 270 +#define LCD_HEIGHT_ID3 202 + + +//FOR ID4 +/* Base */ +#define SCREEN_TYPE_ID4 SCREEN_RGB +#define OUT_FACE_ID4 OUT_P888 +#define DCLK_ID4 71000000 +#define LCDC_ACLK_ID4 300000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW_ID4 10 +#define H_BP_ID4 64 +#define H_VD_ID4 800 +#define H_FP_ID4 16 + +#define V_PW_ID4 3 +#define V_BP_ID4 8 +#define V_VD_ID4 1280 +#define V_FP_ID4 10 + + +/* Other */ +#define DCLK_POL_ID4 0 +#define DEN_POL_ID4 0 +#define VSYNC_POL_ID4 0 +#define HSYNC_POL_ID4 0 + +#define SWAP_RB_ID4 0 +#define SWAP_DUMMY_ID4 0 +#define SWAP_GB_ID4 0 +#define SWAP_RG_ID4 0 + + +#define LCD_WIDTH_ID4 152 +#define LCD_HEIGHT_ID4 202 + + +#define H_VD 1280 +#define V_VD 800 +#if defined(CONFIG_TS_AUTO) +extern struct ts_private_data *g_ts; +#else +static struct ts_private_data *g_ts = NULL; +#endif + +#if defined(CONFIG_RK_BOARD_ID) +extern enum rk_board_id rk_get_board_id(void); +#else +static enum rk_board_id rk_get_board_id(void) +{ + return -1; +} +#endif +static int lcd_get_id(void) +{ + int id = -1; + int ts_id = -1; + +#if defined(CONFIG_RK_BOARD_ID) + id = rk_get_board_id(); +#elif defined(CONFIG_TS_AUTO) + if(!g_ts) + return -1; + + ts_id = g_ts->ops->ts_id; + + switch(ts_id) + { + case TS_ID_FT5306: + id = BOARD_ID_C8003; + break; + case TS_ID_GT8110: + id = BOARD_ID_C1014; + break; + case TS_ID_GT828: + id = BOARD_ID_C7018; + break; + case TS_ID_GT8005: + id = BOARD_ID_C8002; + break; + case TS_ID_CT360: + id = BOARD_ID_DS763; + break; + default: + break; + } + +#endif + return id; +} + +#define RK_USE_SCREEN_ID + +#if defined(RK_USE_SCREEN_ID) +void set_lcd_info_by_id(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) +{ + int id; + id = lcd_get_id(); + + switch(id) + { + case BOARD_ID_DS763: + + /* screen type & face */ + screen->type = SCREEN_TYPE_ID0; + screen->face = OUT_FACE_ID0; + + /* Screen size */ + screen->x_res = H_VD_ID0; + screen->y_res = V_VD_ID0; + + screen->width = LCD_WIDTH_ID0; + screen->height = LCD_HEIGHT_ID0; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK_ID0; + screen->pixclock = DCLK_ID0; + screen->left_margin = H_BP_ID0; + screen->right_margin = H_FP_ID0; + screen->hsync_len = H_PW_ID0; + screen->upper_margin = V_BP_ID0; + screen->lower_margin = V_FP_ID0; + screen->vsync_len = V_PW_ID0; + + /* Pin polarity */ + screen->pin_hsync = HSYNC_POL_ID0; + screen->pin_vsync = VSYNC_POL_ID0; + screen->pin_den = DEN_POL_ID0; + screen->pin_dclk = DCLK_POL_ID0; + + /* Swap rule */ + screen->swap_rb = SWAP_RB_ID0; + screen->swap_rg = SWAP_RG_ID0; + screen->swap_gb = SWAP_GB_ID0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = NULL; + screen->standby = NULL; + + break; + + case BOARD_ID_C8002: + + /* screen type & face */ + screen->type = SCREEN_TYPE_ID1; + screen->face = OUT_FACE_ID1; + + /* Screen size */ + screen->x_res = H_VD_ID1; + screen->y_res = V_VD_ID1; + + screen->width = LCD_WIDTH_ID1; + screen->height = LCD_HEIGHT_ID1; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK_ID1; + screen->pixclock = DCLK_ID1; + screen->left_margin = H_BP_ID1; + screen->right_margin = H_FP_ID1; + screen->hsync_len = H_PW_ID1; + screen->upper_margin = V_BP_ID1; + screen->lower_margin = V_FP_ID1; + screen->vsync_len = V_PW_ID1; + + /* Pin polarity */ + screen->pin_hsync = HSYNC_POL_ID1; + screen->pin_vsync = VSYNC_POL_ID1; + screen->pin_den = DEN_POL_ID1; + screen->pin_dclk = DCLK_POL_ID1; + + /* Swap rule */ + screen->swap_rb = SWAP_RB_ID1; + screen->swap_rg = SWAP_RG_ID1; + screen->swap_gb = SWAP_GB_ID1; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = NULL; + screen->standby = NULL; + break; + + case BOARD_ID_C8003: + + /* screen type & face */ + screen->type = SCREEN_TYPE_ID2; + screen->face = OUT_FACE_ID2; + + /* Screen size */ + screen->x_res = H_VD_ID2; + screen->y_res = V_VD_ID2; + + screen->width = LCD_WIDTH_ID2; + screen->height = LCD_HEIGHT_ID2; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK_ID2; + screen->pixclock = DCLK_ID2; + screen->left_margin = H_BP_ID2; + screen->right_margin = H_FP_ID2; + screen->hsync_len = H_PW_ID2; + screen->upper_margin = V_BP_ID2; + screen->lower_margin = V_FP_ID2; + screen->vsync_len = V_PW_ID2; + + /* Pin polarity */ + screen->pin_hsync = HSYNC_POL_ID2; + screen->pin_vsync = VSYNC_POL_ID2; + screen->pin_den = DEN_POL_ID2; + screen->pin_dclk = DCLK_POL_ID2; + + /* Swap rule */ + screen->swap_rb = SWAP_RB_ID2; + screen->swap_rg = SWAP_RG_ID2; + screen->swap_gb = SWAP_GB_ID2; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = NULL; + screen->standby = NULL; + + break; + + case BOARD_ID_C1014: + default: + + /* screen type & face */ + screen->type = SCREEN_TYPE_ID3; + screen->face = OUT_FACE_ID3; + + /* Screen size */ + screen->x_res = H_VD_ID3; + screen->y_res = V_VD_ID3; + + screen->width = LCD_WIDTH_ID3; + screen->height = LCD_HEIGHT_ID3; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK_ID3; + screen->pixclock = DCLK_ID3; + screen->left_margin = H_BP_ID3; + screen->right_margin = H_FP_ID3; + screen->hsync_len = H_PW_ID3; + screen->upper_margin = V_BP_ID3; + screen->lower_margin = V_FP_ID3; + screen->vsync_len = V_PW_ID3; + + /* Pin polarity */ + screen->pin_hsync = HSYNC_POL_ID3; + screen->pin_vsync = VSYNC_POL_ID3; + screen->pin_den = DEN_POL_ID3; + screen->pin_dclk = DCLK_POL_ID3; + + /* Swap rule */ + screen->swap_rb = SWAP_RB_ID3; + screen->swap_rg = SWAP_RG_ID3; + screen->swap_gb = SWAP_GB_ID3; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = NULL; + screen->standby = NULL; + + break; + + case BOARD_ID_C7018: + + /* screen type & face */ + screen->type = SCREEN_TYPE_ID4; + screen->face = OUT_FACE_ID4; + + /* Screen size */ + screen->x_res = H_VD_ID4; + screen->y_res = V_VD_ID4; + + screen->width = LCD_WIDTH_ID4; + screen->height = LCD_HEIGHT_ID4; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK_ID4; + screen->pixclock = DCLK_ID4; + screen->left_margin = H_BP_ID4; + screen->right_margin = H_FP_ID4; + screen->hsync_len = H_PW_ID4; + screen->upper_margin = V_BP_ID4; + screen->lower_margin = V_FP_ID4; + screen->vsync_len = V_PW_ID4; + + /* Pin polarity */ + screen->pin_hsync = HSYNC_POL_ID4; + screen->pin_vsync = VSYNC_POL_ID4; + screen->pin_den = DEN_POL_ID4; + screen->pin_dclk = DCLK_POL_ID4; + + /* Swap rule */ + screen->swap_rb = SWAP_RB_ID4; + screen->swap_rg = SWAP_RG_ID4; + screen->swap_gb = SWAP_GB_ID4; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = NULL; + screen->standby = NULL; + + break; + + + } + + + printk("%s:board_id=%d\n",__func__,id); + +} + +#endif + +#endif diff --git a/drivers/video/rockchip/screen/lcd_b101ew05.c b/drivers/video/rockchip/screen/lcd_b101ew05.c new file mode 100644 index 000000000000..984a8a857657 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_b101ew05.c @@ -0,0 +1,251 @@ +#ifndef __LCD_B101EW05__ +#define __LCD_B101EW05__ + +#if defined(CONFIG_RK610_LVDS) +#include "../transmitter/rk610_lcd.h" +#endif + +#if defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS) +#define SCREEN_TYPE SCREEN_LVDS +#else +#define SCREEN_TYPE SCREEN_RGB +#endif +#define LVDS_FORMAT LVDS_8BIT_2 +#define OUT_FACE OUT_D888_P666 + + +#define DCLK 71000000 +#define LCDC_ACLK 300000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 10 +#define H_BP 100 +#define H_VD 1280 +#define H_FP 18 + +#define V_PW 2 +#define V_BP 8 +#define V_VD 800 +#define V_FP 6 + +#define LCD_WIDTH 216 +#define LCD_HEIGHT 135 +/* Other */ +#if defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS) +#define DCLK_POL 1 +#else +#define DCLK_POL 0 +#endif +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_RG 0 +#define SWAP_GB 0 + +#define USE_RK_DSP_LUT +int dsp_lut[256] ={ + 0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707, + 0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f, + 0x00101010, 0x00111111, 0x00121212, 0x00131313, 0x00141414, 0x00151515, 0x00161616, 0x00171717, + 0x00181818, 0x00191919, 0x001a1a1a, 0x001b1b1b, 0x001c1c1c, 0x001d1d1d, 0x001e1e1e, 0x001f1f1f, + 0x00202020, 0x00212121, 0x00222222, 0x00232323, 0x00242424, 0x00252525, 0x00262626, 0x00272727, + 0x00282828, 0x00292929, 0x002a2a2a, 0x002b2b2b, 0x002c2c2c, 0x002d2d2d, 0x002e2e2e, 0x002f2f2f, + 0x00303030, 0x00313131, 0x00323232, 0x00333333, 0x00343434, 0x00353535, 0x00363636, 0x00373737, + 0x00383838, 0x00393939, 0x003a3a3a, 0x003b3b3b, 0x003c3c3c, 0x003d3d3d, 0x003e3e3e, 0x003f3f3f, + 0x00404040, 0x00414141, 0x00424242, 0x00434343, 0x00444444, 0x00454545, 0x00464646, 0x00474747, + 0x00484848, 0x00494949, 0x004a4a4a, 0x004b4b4b, 0x004c4c4c, 0x004d4d4d, 0x004e4e4e, 0x004f4f4f, + 0x00505050, 0x00515151, 0x00525252, 0x00535353, 0x00545454, 0x00555555, 0x00565656, 0x00575757, + 0x00585858, 0x00595959, 0x005a5a5a, 0x005b5b5b, 0x005c5c5c, 0x005d5d5d, 0x005e5e5e, 0x005f5f5f, + 0x00606060, 0x00616161, 0x00626262, 0x00636363, 0x00646464, 0x00656565, 0x00666666, 0x00676767, + 0x00686868, 0x00696969, 0x006a6a6a, 0x006b6b6b, 0x006c6c6c, 0x006d6d6d, 0x006e6e6e, 0x006f6f6f, + 0x00707070, 0x00717171, 0x00727272, 0x00737373, 0x00747474, 0x00757575, 0x00767676, 0x00777777, + 0x00787878, 0x00797979, 0x007a7a7a, 0x007b7b7b, 0x007c7c7c, 0x007d7d7d, 0x007e7e7e, 0x007f7f7f, + 0x00808080, 0x00818181, 0x00828282, 0x00838383, 0x00848484, 0x00858585, 0x00868686, 0x00878787, + 0x00888888, 0x00898989, 0x008a8a8a, 0x008b8b8b, 0x008c8c8c, 0x008d8d8d, 0x008e8e8e, 0x008f8f8f, + 0x00909090, 0x00919191, 0x00929292, 0x00939393, 0x00949494, 0x00959595, 0x00969696, 0x00979797, + 0x00989898, 0x00999999, 0x009a9a9a, 0x009b9b9b, 0x009c9c9c, 0x009d9d9d, 0x009e9e9e, 0x009f9f9f, + 0x00a0a0a0, 0x00a1a1a1, 0x00a2a2a2, 0x00a3a3a3, 0x00a4a4a4, 0x00a5a5a5, 0x00a6a6a6, 0x00a7a7a7, + 0x00a8a8a8, 0x00a9a9a9, 0x00aaaaaa, 0x00ababab, 0x00acacac, 0x00adadad, 0x00aeaeae, 0x00afafaf, + 0x00b0b0b0, 0x00b1b1b1, 0x00b2b2b2, 0x00b3b3b3, 0x00b4b4b4, 0x00b5b5b5, 0x00b6b6b6, 0x00b7b7b7, + 0x00b8b8b8, 0x00b9b9b9, 0x00bababa, 0x00bbbbbb, 0x00bcbcbc, 0x00bdbdbd, 0x00bebebe, 0x00bfbfbf, + 0x00c0c0c0, 0x00c1c1c1, 0x00c2c2c2, 0x00c3c3c3, 0x00c4c4c4, 0x00c5c5c5, 0x00c6c6c6, 0x00c7c7c7, + 0x00c8c8c8, 0x00c9c9c9, 0x00cacaca, 0x00cbcbcb, 0x00cccccc, 0x00cdcdcd, 0x00cecece, 0x00cfcfcf, + 0x00d0d0d0, 0x00d1d1d1, 0x00d2d2d2, 0x00d3d3d3, 0x00d4d4d4, 0x00d5d5d5, 0x00d6d6d6, 0x00d7d7d7, + 0x00d8d8d8, 0x00d9d9d9, 0x00dadada, 0x00dbdbdb, 0x00dcdcdc, 0x00dddddd, 0x00dedede, 0x00dfdfdf, + 0x00e0e0e0, 0x00e1e1e1, 0x00e2e2e2, 0x00e3e3e3, 0x00e4e4e4, 0x00e5e5e5, 0x00e6e6e6, 0x00e7e7e7, + 0x00e8e8e8, 0x00e9e9e9, 0x00eaeaea, 0x00ebebeb, 0x00ececec, 0x00ededed, 0x00eeeeee, 0x00efefef, + 0x00f0f0f0, 0x00f1f1f1, 0x00f2f2f2, 0x00f3f3f3, 0x00f4f4f4, 0x00f5f5f5, 0x00f6f6f6, 0x00f7f7f7, + 0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff, +}; + + +// if we use one lcdc with jetta for dual display,we need these configration +#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF) + +/* scaler Timing */ +//1920*1080*60 + +#if defined(CONFIG_RK610_LVDS) +#define S_DCLK_POL 1 +#define S_OUT_CLK SCALE_RATE(148500000,74250000) //m=16 n=9 no=4 +#define S_H_PW 48 +#define S_H_BP 98 +#define S_H_VD 1280 +#define S_H_FP 59 + +#define S_V_PW 6 +#define S_V_BP 25 +#define S_V_VD 800 +#define S_V_FP 2 + +#define S_H_ST 495 +#define S_V_ST 2 +#endif + + +#if defined(CONFIG_RK616_LVDS) +#define S_PLL_CFG_VAL 0x01842016 +#define S_FRAC 0xc16c2d +#define S_SCL_VST 0x25 +#define S_SCL_HST 0x4ba +#define S_VIF_VST 0x1 +#define S_VIF_HST 0xca +#endif + +//1920*1080*50 +#if defined(CONFIG_RK610_LVDS) +#define S1_OUT_CLK SCALE_RATE(148500000,57375000) //m=17 n=11 no=4 +#define S1_H_PW 10 +#define S1_H_BP 10 +#define S1_H_VD 1280 +#define S1_H_FP 77 + +#define S1_V_PW 10 +#define S1_V_BP 10 +#define S1_V_VD 800 +#define S1_V_FP 13 + +#define S1_H_ST 459 +#define S1_V_ST 13 +#endif + +#if defined(CONFIG_RK616_LVDS) +#define S1_PLL_CFG_VAL 0x01c42016 +#define S1_FRAC 0x1f9ad4 +#define S1_SCL_VST 0x25 +#define S1_SCL_HST 0x5ab +#define S1_VIF_VST 0x1 +#define S1_VIF_HST 0xca +#endif + +//1280*720*60 +#if defined(CONFIG_RK610_LVDS) +#define S2_OUT_CLK SCALE_RATE(74250000,74250000) //m=32 n=9 no=4 +#define S2_H_PW 48 +#define S2_H_BP 98 +#define S2_H_VD 1280 +#define S2_H_FP 59 + +#define S2_V_PW 6 +#define S2_V_BP 25 +#define S2_V_VD 800 +#define S2_V_FP 2 + +#define S2_H_ST 495 +#define S2_V_ST 5 +#endif + +//bellow are for jettaB +#if defined(CONFIG_RK616_LVDS) +#define S2_PLL_CFG_VAL 0x01822016 +#define S2_FRAC 0xc16c2d +#define S2_SCL_VST 0x19 +#define S2_SCL_HST 0x483 +#define S2_VIF_VST 0x1 +#define S2_VIF_HST 0xcf +#endif + +//1280*720*50 +#if defined(CONFIG_RK610_LVDS) +#define S3_OUT_CLK SCALE_RATE(74250000,67500000) // m=34 n=11 no=4 +#define S3_H_PW 48 +#define S3_H_BP 233 +#define S3_H_VD 1280 +#define S3_H_FP 59 + +#define S3_V_PW 6 +#define S3_V_BP 25 +#define S3_V_VD 800 +#define S3_V_FP 2 + +#define S3_H_ST 540 +#define S3_V_ST 3 +#endif + +#if defined(CONFIG_RK616_LVDS) +#define S3_PLL_CFG_VAL 0x01c22016 +#define S3_FRAC 0x1f9ad4 +#define S3_SCL_VST 0x19 +#define S3_SCL_HST 0x569 +#define S3_VIF_VST 0x1 +#define S3_VIF_HST 0xcf +#endif + +//720*576*50 +#if defined(CONFIG_RK610_LVDS) +#define S4_OUT_CLK SCALE_RATE(27000000,70312500) //m=75 n=4 no=8 +#define S4_H_PW 48 +#define S4_H_BP 233 +#define S4_H_VD 1280 +#define S4_H_FP 59 + +#define S4_V_PW 9 +#define S4_V_BP 57 +#define S4_V_VD 800 +#define S4_V_FP 2 + +#define S4_H_ST 90 +#define S4_V_ST 2 +#endif + +#if defined(CONFIG_RK616_LVDS) +#define S4_PLL_CFG_VAL 0x01412016 +#define S4_FRAC 0xa23d09 +#define S4_SCL_VST 0x2d +#define S4_SCL_HST 0x33d +#define S4_VIF_VST 0x1 +#define S4_VIF_HST 0xc1 +#endif + +//720*480*60 +#if defined(CONFIG_RK610_LVDS) +#define S5_OUT_CLK SCALE_RATE(27000000,75000000) //m=100 n=9 no=4 +#define S5_H_PW 48 +#define S5_H_BP 86 +#define S5_H_VD 1280 +#define S5_H_FP 16 + +#define S5_V_PW 9 +#define S5_V_BP 35 +#define S5_V_VD 800 +#define S5_V_FP 30 + +#define S5_H_ST 476 +#define S5_V_ST 12 +#endif +#if defined(CONFIG_RK616_LVDS) + +#define S5_PLL_CFG_VAL 0x01c11013 +#define S5_FRAC 0x25325e +#define S5_SCL_VST 0x26 +#define S5_SCL_HST 0x2ae +#define S5_VIF_VST 0x1 +#define S5_VIF_HST 0xc1 +#endif + +#endif +#endif + + diff --git a/drivers/video/rockchip/screen/lcd_b101uano_1920x1200.c b/drivers/video/rockchip/screen/lcd_b101uano_1920x1200.c new file mode 100644 index 000000000000..04919bc74ab6 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_b101uano_1920x1200.c @@ -0,0 +1,138 @@ + +#ifndef __LCD_B101UANO__ +#define __LCD_B101UANO__ + +/* Base */ +#if defined(CONFIG_RK616_LVDS) +#define SCREEN_TYPE SCREEN_LVDS +#else +#define SCREEN_TYPE SCREEN_RGB +#endif +#define LVDS_FORMAT LVDS_8BIT_1 + +#define OUT_FACE OUT_P888 + + +#define DCLK 160000000 +#define LCDC_ACLK 500000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 1 +#define H_BP 90 +#define H_VD 1920 +#define H_FP 1 + +#define V_PW 1 +#define V_BP 12 +#define V_VD 1200 +#define V_FP 1 + +#define LCD_WIDTH 217 +#define LCD_HEIGHT 136 +/* Other */ +#if defined(CONFIG_RK616_LVDS) +#define DCLK_POL 1 +#else +#define DCLK_POL 0 +#endif +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_RG 0 +#define SWAP_GB 0 + +#define USE_RK_DSP_LUT +int dsp_lut[256] ={ + 0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707, + 0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f, + 0x00101010, 0x00111111, 0x00121212, 0x00131313, 0x00141414, 0x00151515, 0x00161616, 0x00171717, + 0x00181818, 0x00191919, 0x001a1a1a, 0x001b1b1b, 0x001c1c1c, 0x001d1d1d, 0x001e1e1e, 0x001f1f1f, + 0x00202020, 0x00212121, 0x00222222, 0x00232323, 0x00242424, 0x00252525, 0x00262626, 0x00272727, + 0x00282828, 0x00292929, 0x002a2a2a, 0x002b2b2b, 0x002c2c2c, 0x002d2d2d, 0x002e2e2e, 0x002f2f2f, + 0x00303030, 0x00313131, 0x00323232, 0x00333333, 0x00343434, 0x00353535, 0x00363636, 0x00373737, + 0x00383838, 0x00393939, 0x003a3a3a, 0x003b3b3b, 0x003c3c3c, 0x003d3d3d, 0x003e3e3e, 0x003f3f3f, + 0x00404040, 0x00414141, 0x00424242, 0x00434343, 0x00444444, 0x00454545, 0x00464646, 0x00474747, + 0x00484848, 0x00494949, 0x004a4a4a, 0x004b4b4b, 0x004c4c4c, 0x004d4d4d, 0x004e4e4e, 0x004f4f4f, + 0x00505050, 0x00515151, 0x00525252, 0x00535353, 0x00545454, 0x00555555, 0x00565656, 0x00575757, + 0x00585858, 0x00595959, 0x005a5a5a, 0x005b5b5b, 0x005c5c5c, 0x005d5d5d, 0x005e5e5e, 0x005f5f5f, + 0x00606060, 0x00616161, 0x00626262, 0x00636363, 0x00646464, 0x00656565, 0x00666666, 0x00676767, + 0x00686868, 0x00696969, 0x006a6a6a, 0x006b6b6b, 0x006c6c6c, 0x006d6d6d, 0x006e6e6e, 0x006f6f6f, + 0x00707070, 0x00717171, 0x00727272, 0x00737373, 0x00747474, 0x00757575, 0x00767676, 0x00777777, + 0x00787878, 0x00797979, 0x007a7a7a, 0x007b7b7b, 0x007c7c7c, 0x007d7d7d, 0x007e7e7e, 0x007f7f7f, + 0x00808080, 0x00818181, 0x00828282, 0x00838383, 0x00848484, 0x00858585, 0x00868686, 0x00878787, + 0x00888888, 0x00898989, 0x008a8a8a, 0x008b8b8b, 0x008c8c8c, 0x008d8d8d, 0x008e8e8e, 0x008f8f8f, + 0x00909090, 0x00919191, 0x00929292, 0x00939393, 0x00949494, 0x00959595, 0x00969696, 0x00979797, + 0x00989898, 0x00999999, 0x009a9a9a, 0x009b9b9b, 0x009c9c9c, 0x009d9d9d, 0x009e9e9e, 0x009f9f9f, + 0x00a0a0a0, 0x00a1a1a1, 0x00a2a2a2, 0x00a3a3a3, 0x00a4a4a4, 0x00a5a5a5, 0x00a6a6a6, 0x00a7a7a7, + 0x00a8a8a8, 0x00a9a9a9, 0x00aaaaaa, 0x00ababab, 0x00acacac, 0x00adadad, 0x00aeaeae, 0x00afafaf, + 0x00b0b0b0, 0x00b1b1b1, 0x00b2b2b2, 0x00b3b3b3, 0x00b4b4b4, 0x00b5b5b5, 0x00b6b6b6, 0x00b7b7b7, + 0x00b8b8b8, 0x00b9b9b9, 0x00bababa, 0x00bbbbbb, 0x00bcbcbc, 0x00bdbdbd, 0x00bebebe, 0x00bfbfbf, + 0x00c0c0c0, 0x00c1c1c1, 0x00c2c2c2, 0x00c3c3c3, 0x00c4c4c4, 0x00c5c5c5, 0x00c6c6c6, 0x00c7c7c7, + 0x00c8c8c8, 0x00c9c9c9, 0x00cacaca, 0x00cbcbcb, 0x00cccccc, 0x00cdcdcd, 0x00cecece, 0x00cfcfcf, + 0x00d0d0d0, 0x00d1d1d1, 0x00d2d2d2, 0x00d3d3d3, 0x00d4d4d4, 0x00d5d5d5, 0x00d6d6d6, 0x00d7d7d7, + 0x00d8d8d8, 0x00d9d9d9, 0x00dadada, 0x00dbdbdb, 0x00dcdcdc, 0x00dddddd, 0x00dedede, 0x00dfdfdf, + 0x00e0e0e0, 0x00e1e1e1, 0x00e2e2e2, 0x00e3e3e3, 0x00e4e4e4, 0x00e5e5e5, 0x00e6e6e6, 0x00e7e7e7, + 0x00e8e8e8, 0x00e9e9e9, 0x00eaeaea, 0x00ebebeb, 0x00ececec, 0x00ededed, 0x00eeeeee, 0x00efefef, + 0x00f0f0f0, 0x00f1f1f1, 0x00f2f2f2, 0x00f3f3f3, 0x00f4f4f4, 0x00f5f5f5, 0x00f6f6f6, 0x00f7f7f7, + 0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff, +}; + +#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK616_LVDS) + +#define S_PLL_CFG_VAL 0x01842016 +#define S_FRAC 0xc16c2d +#define S_SCL_VST 0x25 +#define S_SCL_HST 0x4ba +#define S_VIF_VST 0x1 +#define S_VIF_HST 0xca + +//1920*1080*50 + + +#define S1_PLL_CFG_VAL 0x01c42016 +#define S1_FRAC 0x1f9ad4 +#define S1_SCL_VST 0x25 +#define S1_SCL_HST 0x5ab +#define S1_VIF_VST 0x1 +#define S1_VIF_HST 0xca + + +//1280*720*60 +//bellow are for jettaB +#define S2_PLL_CFG_VAL 0x01822016 +#define S2_FRAC 0xc16c2d +#define S2_SCL_VST 0x19 +#define S2_SCL_HST 0x483 +#define S2_VIF_VST 0x1 +#define S2_VIF_HST 0xcf + + +//1280*720*50 +#define S3_PLL_CFG_VAL 0x01c22016 +#define S3_FRAC 0x1f9ad4 +#define S3_SCL_VST 0x19 +#define S3_SCL_HST 0x569 +#define S3_VIF_VST 0x1 +#define S3_VIF_HST 0xcf + +//720*576*50 +#define S4_PLL_CFG_VAL 0x01412016 +#define S4_FRAC 0xa23d09 +#define S4_SCL_VST 0x2d +#define S4_SCL_HST 0x33d +#define S4_VIF_VST 0x1 +#define S4_VIF_HST 0xc1 + + +//720*480*60 + +#define S5_PLL_CFG_VAL 0x01c11013 +#define S5_FRAC 0x25325e +#define S5_SCL_VST 0x26 +#define S5_SCL_HST 0x2ae +#define S5_VIF_VST 0x1 +#define S5_VIF_HST 0xc1 +#endif +#endif diff --git a/drivers/video/rockchip/screen/lcd_byd1024x600.c b/drivers/video/rockchip/screen/lcd_byd1024x600.c new file mode 100644 index 000000000000..d00901890d11 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_byd1024x600.c @@ -0,0 +1,111 @@ +/* + * This Lcd Driver is for BYD 5' LCD BM800480-8545FTGE. + * written by Michael Lin, 2010-06-18 + */ + +#include +#include +#include "../../rk29_fb.h" +#include +#include +#include +#include "screen.h" + + +/* Base */ +#define OUT_TYPE SCREEN_RGB +#define OUT_FACE OUT_P888 +//tcl miaozh modify +//#define OUT_CLK 50000000 +#define OUT_CLK 47000000 +//#define OUT_CLK 42000000 +#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 10 +#define H_BP 160 +#define H_VD 1024 +#define H_FP 119 + +#define V_PW 3 +#define V_BP 23 +#define V_VD 600 +#define V_FP 9 + +/* Other */ +#define DCLK_POL 0 +#define SWAP_RB 0 + +//tcl miaozh modify +//#define LCD_WIDTH 1024 //need modify +//#define LCD_HEIGHT 600 +#define LCD_WIDTH 153 //need modify +#define LCD_HEIGHT 90 + +static struct rk29lcd_info *gLcd_info = NULL; + +#define DRVDelayUs(i) udelay(i*2) + +static int init(void); +static int standby(u8 enable); + +void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) +{ + /* screen type & face */ + screen->type = OUT_TYPE; + screen->face = OUT_FACE; + + /* Screen size */ + screen->x_res = H_VD; + screen->y_res = V_VD; + screen->width = LCD_WIDTH; + screen->height = LCD_HEIGHT; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK; + screen->pixclock = OUT_CLK; + screen->left_margin = H_BP; + screen->right_margin = H_FP; + screen->hsync_len = H_PW; + screen->upper_margin = V_BP; + screen->lower_margin = V_FP; + screen->vsync_len = V_PW; + + /* Pin polarity */ + screen->pin_hsync = 0; + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = DCLK_POL; + + /* Swap rule */ + screen->swap_rb = SWAP_RB; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + /*screen->init = init;*/ + screen->init = NULL; + screen->standby = standby; +} + + +static int standby(u8 enable) +{ + printk(KERN_INFO "byd1024x600 lcd standby, enable=%d\n", enable); + if (enable) + { + //rockchip_mux_api_set(LED_CON_IOMUX_PINNAME, LED_CON_IOMUX_PINDIR); + //GPIOSetPinDirection(LED_CON_IOPIN,GPIO_OUT); + //GPIOSetPinLevel(LED_CON_IOPIN,GPIO_HIGH); +// gpio_set_value(LCD_DISP_ON_IOPIN, GPIO_LOW); + } + else + { + //rockchip_mux_api_set(LED_CON_IOMUX_PINNAME, 1); +// gpio_set_value(LCD_DISP_ON_IOPIN, GPIO_HIGH); + } + return 0; +} + diff --git a/drivers/video/rockchip/screen/lcd_common.c b/drivers/video/rockchip/screen/lcd_common.c new file mode 100644 index 000000000000..4d18e7b442aa --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_common.c @@ -0,0 +1,79 @@ +#include +#include +#include "../../rk29_fb.h" +#include +#include +#include +#include "screen.h" + +/* Base */ +#define OUT_TYPE SCREEN_RGB + +#define OUT_FACE OUT_D888_P666 + + +#define OUT_CLK 71000000 +#define LCDC_ACLK 300000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 10 +#define H_BP 100 +#define H_VD 1280 +#define H_FP 18 + +#define V_PW 2 +#define V_BP 8 +#define V_VD 800 +#define V_FP 6 + +#define LCD_WIDTH 216 +#define LCD_HEIGHT 135 +/* Other */ +#define DCLK_POL 0 +#define SWAP_RB 0 + + +u32 lcdpamara[]={0x4B434F52,0x64636C5F,0x61746164,SCREEN_RGB,OUT_D888_P666,71000000,300000000,10,100,1280,18,2,8,800,6,216,135,0,0}; + +void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) +{ + /* screen type & face */ + screen->type = lcdpamara[3]; + screen->face = lcdpamara[4]; + + /* Screen size */ + screen->x_res = lcdpamara[9]; + screen->y_res = lcdpamara[13]; + + screen->width = lcdpamara[15]; + screen->height = lcdpamara[16]; + + /* Timing */ + screen->lcdc_aclk = lcdpamara[6]; + screen->pixclock = lcdpamara[5]; + screen->left_margin = lcdpamara[8]; + screen->right_margin = lcdpamara[10]; + screen->hsync_len = lcdpamara[7]; + screen->upper_margin = lcdpamara[12]; + screen->lower_margin = lcdpamara[14]; + screen->vsync_len = lcdpamara[11]; + + /* Pin polarity */ + screen->pin_hsync = 0; + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = lcdpamara[17]; + + /* Swap rule */ + screen->swap_rb = lcdpamara[18]; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = NULL; + screen->standby = NULL; + +} + diff --git a/drivers/video/rockchip/screen/lcd_ds1006h.c b/drivers/video/rockchip/screen/lcd_ds1006h.c new file mode 100644 index 000000000000..3f65f37743d1 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_ds1006h.c @@ -0,0 +1,187 @@ +#ifndef __LCD_DS1006H__ +#define __LCD_DS1006H__ + +#ifdef CONFIG_RK610_LVDS +#include "../transmitter/rk610_lcd.h" +#endif + + +/* Base */ +#ifdef CONFIG_RK610_LVDS +#define SCREEN_TYPE SCREEN_LVDS +#else +#define SCREEN_TYPE SCREEN_RGB +#endif +#define LVDS_FORMAT LVDS_8BIT_1 + +#define OUT_FACE OUT_P888 + + +#define DCLK 71000000 +#define LCDC_ACLK 500000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 1 +#define H_BP 1 +#define H_VD 1280 +#define H_FP 158 + +#define V_PW 1 +#define V_BP 1 +#define V_VD 800 +#define V_FP 21 + +#define LCD_WIDTH 216 +#define LCD_HEIGHT 135 +/* Other */ +#ifdef CONFIG_RK610_LVDS +#define DCLK_POL 1 +#else +#define DCLK_POL 0 +#endif + +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_RG 0 +#define SWAP_GB 0 + + +int dsp_lut[256] ={ + 0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707, + 0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f, + 0x00101010, 0x00111111, 0x00121212, 0x00131313, 0x00141414, 0x00151515, 0x00161616, 0x00171717, + 0x00181818, 0x00191919, 0x001a1a1a, 0x001b1b1b, 0x001c1c1c, 0x001d1d1d, 0x001e1e1e, 0x001f1f1f, + 0x00202020, 0x00212121, 0x00222222, 0x00232323, 0x00242424, 0x00252525, 0x00262626, 0x00272727, + 0x00282828, 0x00292929, 0x002a2a2a, 0x002b2b2b, 0x002c2c2c, 0x002d2d2d, 0x002e2e2e, 0x002f2f2f, + 0x00303030, 0x00313131, 0x00323232, 0x00333333, 0x00343434, 0x00353535, 0x00363636, 0x00373737, + 0x00383838, 0x00393939, 0x003a3a3a, 0x003b3b3b, 0x003c3c3c, 0x003d3d3d, 0x003e3e3e, 0x003f3f3f, + 0x00404040, 0x00414141, 0x00424242, 0x00434343, 0x00444444, 0x00454545, 0x00464646, 0x00474747, + 0x00484848, 0x00494949, 0x004a4a4a, 0x004b4b4b, 0x004c4c4c, 0x004d4d4d, 0x004e4e4e, 0x004f4f4f, + 0x00505050, 0x00515151, 0x00525252, 0x00535353, 0x00545454, 0x00555555, 0x00565656, 0x00575757, + 0x00585858, 0x00595959, 0x005a5a5a, 0x005b5b5b, 0x005c5c5c, 0x005d5d5d, 0x005e5e5e, 0x005f5f5f, + 0x00606060, 0x00616161, 0x00626262, 0x00636363, 0x00646464, 0x00656565, 0x00666666, 0x00676767, + 0x00686868, 0x00696969, 0x006a6a6a, 0x006b6b6b, 0x006c6c6c, 0x006d6d6d, 0x006e6e6e, 0x006f6f6f, + 0x00707070, 0x00717171, 0x00727272, 0x00737373, 0x00747474, 0x00757575, 0x00767676, 0x00777777, + 0x00787878, 0x00797979, 0x007a7a7a, 0x007b7b7b, 0x007c7c7c, 0x007d7d7d, 0x007e7e7e, 0x007f7f7f, + 0x00808080, 0x00818181, 0x00828282, 0x00838383, 0x00848484, 0x00858585, 0x00868686, 0x00878787, + 0x00888888, 0x00898989, 0x008a8a8a, 0x008b8b8b, 0x008c8c8c, 0x008d8d8d, 0x008e8e8e, 0x008f8f8f, + 0x00909090, 0x00919191, 0x00929292, 0x00939393, 0x00949494, 0x00959595, 0x00969696, 0x00979797, + 0x00989898, 0x00999999, 0x009a9a9a, 0x009b9b9b, 0x009c9c9c, 0x009d9d9d, 0x009e9e9e, 0x009f9f9f, + 0x00a0a0a0, 0x00a1a1a1, 0x00a2a2a2, 0x00a3a3a3, 0x00a4a4a4, 0x00a5a5a5, 0x00a6a6a6, 0x00a7a7a7, + 0x00a8a8a8, 0x00a9a9a9, 0x00aaaaaa, 0x00ababab, 0x00acacac, 0x00adadad, 0x00aeaeae, 0x00afafaf, + 0x00b0b0b0, 0x00b1b1b1, 0x00b2b2b2, 0x00b3b3b3, 0x00b4b4b4, 0x00b5b5b5, 0x00b6b6b6, 0x00b7b7b7, + 0x00b8b8b8, 0x00b9b9b9, 0x00bababa, 0x00bbbbbb, 0x00bcbcbc, 0x00bdbdbd, 0x00bebebe, 0x00bfbfbf, + 0x00c0c0c0, 0x00c1c1c1, 0x00c2c2c2, 0x00c3c3c3, 0x00c4c4c4, 0x00c5c5c5, 0x00c6c6c6, 0x00c7c7c7, + 0x00c8c8c8, 0x00c9c9c9, 0x00cacaca, 0x00cbcbcb, 0x00cccccc, 0x00cdcdcd, 0x00cecece, 0x00cfcfcf, + 0x00d0d0d0, 0x00d1d1d1, 0x00d2d2d2, 0x00d3d3d3, 0x00d4d4d4, 0x00d5d5d5, 0x00d6d6d6, 0x00d7d7d7, + 0x00d8d8d8, 0x00d9d9d9, 0x00dadada, 0x00dbdbdb, 0x00dcdcdc, 0x00dddddd, 0x00dedede, 0x00dfdfdf, + 0x00e0e0e0, 0x00e1e1e1, 0x00e2e2e2, 0x00e3e3e3, 0x00e4e4e4, 0x00e5e5e5, 0x00e6e6e6, 0x00e7e7e7, + 0x00e8e8e8, 0x00e9e9e9, 0x00eaeaea, 0x00ebebeb, 0x00ececec, 0x00ededed, 0x00eeeeee, 0x00efefef, + 0x00f0f0f0, 0x00f1f1f1, 0x00f2f2f2, 0x00f3f3f3, 0x00f4f4f4, 0x00f5f5f5, 0x00f6f6f6, 0x00f7f7f7, + 0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff, +}; + +#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS) + +/* scaler Timing */ +//1920*1080*60 + +#define S_OUT_CLK SCALE_RATE(148500000,74250000) //m=16 n=9 no=4 +#define S_H_PW 48 +#define S_H_BP 98 +#define S_H_VD 1280 +#define S_H_FP 59 + +#define S_V_PW 6 +#define S_V_BP 25 +#define S_V_VD 800 +#define S_V_FP 2 + +#define S_H_ST 495 +#define S_V_ST 2 + +//1920*1080*50 +#define S1_OUT_CLK SCALE_RATE(148500000,57375000) //m=17 n=11 no=4 +#define S1_H_PW 10 +#define S1_H_BP 10 +#define S1_H_VD 1280 +#define S1_H_FP 77 + +#define S1_V_PW 10 +#define S1_V_BP 10 +#define S1_V_VD 800 +#define S1_V_FP 13 + +#define S1_H_ST 459 +#define S1_V_ST 13 + +//1280*720*60 +#define S2_OUT_CLK SCALE_RATE(74250000,74250000) //m=32 n=9 no=4 +#define S2_H_PW 48 +#define S2_H_BP 98 +#define S2_H_VD 1280 +#define S2_H_FP 59 + +#define S2_V_PW 6 +#define S2_V_BP 5 +#define S2_V_VD 800 +#define S2_V_FP 2 + +#define S2_H_ST 495 +#define S2_V_ST 15 + +//1280*720*50 + +#define S3_OUT_CLK SCALE_RATE(74250000,67500000) // m=34 n=11 no=4 +#define S3_H_PW 48 +#define S3_H_BP 233 +#define S3_H_VD 1280 +#define S3_H_FP 59 + +#define S3_V_PW 6 +#define S3_V_BP 5 +#define S3_V_VD 800 +#define S3_V_FP 2 + +#define S3_H_ST 540 +#define S3_V_ST 14 + +//720*576*50 +#define S4_OUT_CLK SCALE_RATE(27000000,70312500) //m=75 n=4 no=8 +#define S4_H_PW 48 +#define S4_H_BP 233 +#define S4_H_VD 1280 +#define S4_H_FP 59 + +#define S4_V_PW 9 +#define S4_V_BP 57 +#define S4_V_VD 800 +#define S4_V_FP 2 + +#define S4_H_ST 90 +#define S4_V_ST 2 + +//720*480*60 +#define S5_OUT_CLK SCALE_RATE(27000000,75000000) //m=100 n=9 no=4 +#define S5_H_PW 48 +#define S5_H_BP 86 +#define S5_H_VD 1280 +#define S5_H_FP 16 + +#define S5_V_PW 9 +#define S5_V_BP 35 +#define S5_V_VD 800 +#define S5_V_FP 30 + +#define S5_H_ST 476 +#define S5_V_ST 12 + +#define S_DCLK_POL 1 +#endif + + +#endif + diff --git a/drivers/video/rockchip/screen/lcd_hdmi_1024x600.c b/drivers/video/rockchip/screen/lcd_hdmi_1024x600.c new file mode 100644 index 000000000000..c73631e481c4 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_hdmi_1024x600.c @@ -0,0 +1,182 @@ +#ifndef __LCD_HDMI_1024x600__ +#define __LCD_HDMI_1024x600__ + +#ifdef CONFIG_RK610_LVDS +#include "../transmitter/rk610_lcd.h" +#endif + + +/* Base */ +#ifdef CONFIG_RK610_LVDS +#define SCREEN_TYPE SCREEN_LVDS +#else +#define SCREEN_TYPE SCREEN_RGB +#endif +#define LVDS_FORMAT LVDS_8BIT_1 + +#define OUT_FACE OUT_P888 +#define DCLK 50000000 // 65000000 +#define LCDC_ACLK 312000000//312000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 20 +#define H_BP 20 +#define H_VD 1024 +#define H_FP 280 + +#define V_PW 2 +#define V_BP 2 +#define V_VD 600 +#define V_FP 34 + +#define LCD_WIDTH 154//1024 +#define LCD_HEIGHT 91//600 +/* Other */ +#ifdef CONFIG_RK610_LVDS +#define DCLK_POL 1 +#else +#define DCLK_POL 0 +#endif + +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_RG 0 +#define SWAP_GB 0 + +int dsp_lut[256] ={ + 0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707, + 0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f, + 0x00101010, 0x00111111, 0x00121212, 0x00131313, 0x00141414, 0x00151515, 0x00161616, 0x00171717, + 0x00181818, 0x00191919, 0x001a1a1a, 0x001b1b1b, 0x001c1c1c, 0x001d1d1d, 0x001e1e1e, 0x001f1f1f, + 0x00202020, 0x00212121, 0x00222222, 0x00232323, 0x00242424, 0x00252525, 0x00262626, 0x00272727, + 0x00282828, 0x00292929, 0x002a2a2a, 0x002b2b2b, 0x002c2c2c, 0x002d2d2d, 0x002e2e2e, 0x002f2f2f, + 0x00303030, 0x00313131, 0x00323232, 0x00333333, 0x00343434, 0x00353535, 0x00363636, 0x00373737, + 0x00383838, 0x00393939, 0x003a3a3a, 0x003b3b3b, 0x003c3c3c, 0x003d3d3d, 0x003e3e3e, 0x003f3f3f, + 0x00404040, 0x00414141, 0x00424242, 0x00434343, 0x00444444, 0x00454545, 0x00464646, 0x00474747, + 0x00484848, 0x00494949, 0x004a4a4a, 0x004b4b4b, 0x004c4c4c, 0x004d4d4d, 0x004e4e4e, 0x004f4f4f, + 0x00505050, 0x00515151, 0x00525252, 0x00535353, 0x00545454, 0x00555555, 0x00565656, 0x00575757, + 0x00585858, 0x00595959, 0x005a5a5a, 0x005b5b5b, 0x005c5c5c, 0x005d5d5d, 0x005e5e5e, 0x005f5f5f, + 0x00606060, 0x00616161, 0x00626262, 0x00636363, 0x00646464, 0x00656565, 0x00666666, 0x00676767, + 0x00686868, 0x00696969, 0x006a6a6a, 0x006b6b6b, 0x006c6c6c, 0x006d6d6d, 0x006e6e6e, 0x006f6f6f, + 0x00707070, 0x00717171, 0x00727272, 0x00737373, 0x00747474, 0x00757575, 0x00767676, 0x00777777, + 0x00787878, 0x00797979, 0x007a7a7a, 0x007b7b7b, 0x007c7c7c, 0x007d7d7d, 0x007e7e7e, 0x007f7f7f, + 0x00808080, 0x00818181, 0x00828282, 0x00838383, 0x00848484, 0x00858585, 0x00868686, 0x00878787, + 0x00888888, 0x00898989, 0x008a8a8a, 0x008b8b8b, 0x008c8c8c, 0x008d8d8d, 0x008e8e8e, 0x008f8f8f, + 0x00909090, 0x00919191, 0x00929292, 0x00939393, 0x00949494, 0x00959595, 0x00969696, 0x00979797, + 0x00989898, 0x00999999, 0x009a9a9a, 0x009b9b9b, 0x009c9c9c, 0x009d9d9d, 0x009e9e9e, 0x009f9f9f, + 0x00a0a0a0, 0x00a1a1a1, 0x00a2a2a2, 0x00a3a3a3, 0x00a4a4a4, 0x00a5a5a5, 0x00a6a6a6, 0x00a7a7a7, + 0x00a8a8a8, 0x00a9a9a9, 0x00aaaaaa, 0x00ababab, 0x00acacac, 0x00adadad, 0x00aeaeae, 0x00afafaf, + 0x00b0b0b0, 0x00b1b1b1, 0x00b2b2b2, 0x00b3b3b3, 0x00b4b4b4, 0x00b5b5b5, 0x00b6b6b6, 0x00b7b7b7, + 0x00b8b8b8, 0x00b9b9b9, 0x00bababa, 0x00bbbbbb, 0x00bcbcbc, 0x00bdbdbd, 0x00bebebe, 0x00bfbfbf, + 0x00c0c0c0, 0x00c1c1c1, 0x00c2c2c2, 0x00c3c3c3, 0x00c4c4c4, 0x00c5c5c5, 0x00c6c6c6, 0x00c7c7c7, + 0x00c8c8c8, 0x00c9c9c9, 0x00cacaca, 0x00cbcbcb, 0x00cccccc, 0x00cdcdcd, 0x00cecece, 0x00cfcfcf, + 0x00d0d0d0, 0x00d1d1d1, 0x00d2d2d2, 0x00d3d3d3, 0x00d4d4d4, 0x00d5d5d5, 0x00d6d6d6, 0x00d7d7d7, + 0x00d8d8d8, 0x00d9d9d9, 0x00dadada, 0x00dbdbdb, 0x00dcdcdc, 0x00dddddd, 0x00dedede, 0x00dfdfdf, + 0x00e0e0e0, 0x00e1e1e1, 0x00e2e2e2, 0x00e3e3e3, 0x00e4e4e4, 0x00e5e5e5, 0x00e6e6e6, 0x00e7e7e7, + 0x00e8e8e8, 0x00e9e9e9, 0x00eaeaea, 0x00ebebeb, 0x00ececec, 0x00ededed, 0x00eeeeee, 0x00efefef, + 0x00f0f0f0, 0x00f1f1f1, 0x00f2f2f2, 0x00f3f3f3, 0x00f4f4f4, 0x00f5f5f5, 0x00f6f6f6, 0x00f7f7f7, + 0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff, +}; + +#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS) + +/* scaler Timing */ +//1920*1080*60 + +#define S_OUT_CLK SCALE_RATE(148500000,50625000) +#define S_H_PW 10 +#define S_H_BP 10 +#define S_H_VD 1024 +#define S_H_FP 306 + +#define S_V_PW 10 +#define S_V_BP 10 +#define S_V_VD 600 +#define S_V_FP 5 + +#define S_H_ST 0 +#define S_V_ST 5 + +//1920*1080*50 +#define S1_OUT_CLK SCALE_RATE(148500000,45375000) +#define S1_H_PW 10 +#define S1_H_BP 10 +#define S1_H_VD 1024 +#define S1_H_FP 408 + +#define S1_V_PW 10 +#define S1_V_BP 10 +#define S1_V_VD 600 +#define S1_V_FP 5 + +#define S1_H_ST 0 +#define S1_V_ST 5 + +//1280*720*60 +#define S2_OUT_CLK SCALE_RATE(74250000,50625000) +#define S2_H_PW 10 +#define S2_H_BP 10 +#define S2_H_VD 1024 +#define S2_H_FP 306 + +#define S2_V_PW 10 +#define S2_V_BP 10 +#define S2_V_VD 600 +#define S2_V_FP 5 + +#define S2_H_ST 0 +#define S2_V_ST 3 + +//1280*720*50 + +#define S3_OUT_CLK SCALE_RATE(74250000,44343750) +#define S3_H_PW 10 +#define S3_H_BP 10 +#define S3_H_VD 1024 +#define S3_H_FP 375 + +#define S3_V_PW 10 +#define S3_V_BP 10 +#define S3_V_VD 600 +#define S3_V_FP 3 + +#define S3_H_ST 0 +#define S3_V_ST 3 + +//720*576*50 +#define S4_OUT_CLK SCALE_RATE(27000000,46875000) +#define S4_H_PW 10 +#define S4_H_BP 10 +#define S4_H_VD 1024 +#define S4_H_FP 396 + +#define S4_V_PW 10 +#define S4_V_BP 10 +#define S4_V_VD 600 +#define S4_V_FP 31 + +#define S4_H_ST 0 +#define S4_V_ST 28 + +//720*480*60 +#define S5_OUT_CLK SCALE_RATE(27000000,56250000) //m=100 n=9 no=4 +#define S5_H_PW 10 +#define S5_H_BP 10 +#define S5_H_VD 1024 +#define S5_H_FP 386 + +#define S5_V_PW 10 +#define S5_V_BP 10 +#define S5_V_VD 600 +#define S5_V_FP 35 + +#define S5_H_ST 0 +#define S5_V_ST 22 + +#define S_DCLK_POL 1 +#endif + +#endif diff --git a/drivers/video/rockchip/screen/lcd_hdmi_1024x768.c b/drivers/video/rockchip/screen/lcd_hdmi_1024x768.c new file mode 100644 index 000000000000..600baf76fc2f --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_hdmi_1024x768.c @@ -0,0 +1,138 @@ + +#ifndef __LCD_HDMI_1024x768__ +#define __LCD_HDMI_1024x768__ + +#ifdef CONFIG_RK610_LVDS +#include "../transmitter/rk610_lcd.h" +#endif + + +/* Base */ +#define SCREEN_TYPE SCREEN_LVDS +#define LVDS_FORMAT LVDS_8BIT_2 +#define OUT_FACE OUT_D888_P666 +#define DCLK 65000000 +#define LCDC_ACLK 500000000//312000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 10 +#define H_BP 100 +#define H_VD 1024 +#define H_FP 210 + +#define V_PW 10 +#define V_BP 10 +#define V_VD 768 +#define V_FP 18 + +#define LCD_WIDTH 202 +#define LCD_HEIGHT 152 +#define DCLK_POL 1 + +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_RG 0 +#define SWAP_GB 0 + + +#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS) + +/* scaler Timing */ +//1920*1080*60 +#define S_OUT_CLK SCALE_RATE(148500000,66000000) //m=16 n=9 no=4 +#define S_H_PW 100 +#define S_H_BP 100 +#define S_H_VD 1024 +#define S_H_FP 151 + +#define S_V_PW 5 +#define S_V_BP 15 +#define S_V_VD 768 +#define S_V_FP 12 + +#define S_H_ST 1757 +#define S_V_ST 14 + +//1920*1080*50 +#define S1_OUT_CLK SCALE_RATE(148500000,54000000) //m=16 n=11 no=4 +#define S1_H_PW 100 +#define S1_H_BP 100 +#define S1_H_VD 1024 +#define S1_H_FP 126 + +#define S1_V_PW 5 +#define S1_V_BP 15 +#define S1_V_VD 768 +#define S1_V_FP 12 + +#define S1_H_ST 1757 +#define S1_V_ST 14 + +//1280*720*60 +#define S2_OUT_CLK SCALE_RATE(74250000,66000000) //m=32 n=9 no=4 +#define S2_H_PW 100 +#define S2_H_BP 100 +#define S2_H_VD 1024 +#define S2_H_FP 151 + +#define S2_V_PW 5 +#define S2_V_BP 15 +#define S2_V_VD 768 +#define S2_V_FP 12 + +#define S2_H_ST 0 +#define S2_V_ST 12 +//1280*720*50 + +#define S3_OUT_CLK SCALE_RATE(74250000,54000000) // m=32 n=11 no=4 +#define S3_H_PW 100 +#define S3_H_BP 100 +#define S3_H_VD 1024 +#define S3_H_FP 151 + +#define S3_V_PW 5 +#define S3_V_BP 15 +#define S3_V_VD 768 +#define S3_V_FP 12 + +#define S3_H_ST 0 +#define S3_V_ST 12 + +//720*576*50 +#define S4_OUT_CLK SCALE_RATE(27000000,54375000) //m=145 n=9 no=8 +#define S4_H_PW 100 +#define S4_H_BP 100 +#define S4_H_VD 1024 +#define S4_H_FP 81 + +#define S4_V_PW 5 +#define S4_V_BP 15 +#define S4_V_VD 768 +#define S4_V_FP 45 + + +#define S4_H_ST 435 +#define S4_V_ST 45 +//720*480*60 +#define S5_OUT_CLK SCALE_RATE(27000000,72000000) //m=32 n=3 no=4 +#define S5_H_PW 100 +#define S5_H_BP 100 +#define S5_H_VD 1024 +#define S5_H_FP 81 + +#define S5_V_PW 5 +#define S5_V_BP 15 +#define S5_V_VD 768 +#define S5_V_FP 51 + +#define S5_H_ST 858 +#define S5_V_ST 45 + +#define S_DCLK_POL 0 + +#endif + +#endif diff --git a/drivers/video/rockchip/screen/lcd_hdmi_1280x800.c b/drivers/video/rockchip/screen/lcd_hdmi_1280x800.c new file mode 100644 index 000000000000..cdf15f3dc5bb --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_hdmi_1280x800.c @@ -0,0 +1,141 @@ + +#ifndef __LCD_HDMI_1280x800__ +#define __LCD_HDMI_1280x800__ + +#ifdef CONFIG_RK610_LVDS +#include "../transmitter/rk610_lcd.h" +#endif + + + +/* Base */ +#define SCREEN_TYPE SCREEN_LVDS +#define LVDS_FORMAT LVDS_8BIT_2 +#define OUT_FACE OUT_D888_P666 +#define DCLK 65000000 +#define LCDC_ACLK 500000000//312000000 //29 lcdc axi DMA ƵÂÊ + + +/* Timing */ +#define H_PW 10 +#define H_BP 10 +#define H_VD 1280 +#define H_FP 20 + +#define V_PW 10 +#define V_BP 10 +#define V_VD 800 +#define V_FP 13 + +#define LCD_WIDTH 202 +#define LCD_HEIGHT 152 +#define DCLK_POL 1 +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_RG 0 +#define SWAP_GB 0 + + +#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS) + +/* scaler Timing */ +//1920*1080*60 + +#define S_OUT_CLK SCALE_RATE(148500000,66000000) //m=16 n=9 no=4 +#define S_H_PW 10 +#define S_H_BP 10 +#define S_H_VD 1280 +#define S_H_FP 20 + +#define S_V_PW 10 +#define S_V_BP 10 +#define S_V_VD 800 +#define S_V_FP 13 + +#define S_H_ST 440 +#define S_V_ST 13 + +//1920*1080*50 +#define S1_OUT_CLK SCALE_RATE(148500000,57375000) //m=17 n=11 no=4 +#define S1_H_PW 10 +#define S1_H_BP 10 +#define S1_H_VD 1280 +#define S1_H_FP 77 + +#define S1_V_PW 10 +#define S1_V_BP 10 +#define S1_V_VD 800 +#define S1_V_FP 13 + +#define S1_H_ST 459 +#define S1_V_ST 13 + +//1280*720*60 +#define S2_OUT_CLK SCALE_RATE(74250000,66000000) //m=32 n=9 no=4 +#define S2_H_PW 10 +#define S2_H_BP 10 +#define S2_H_VD 1280 +#define S2_H_FP 20 + +#define S2_V_PW 10 +#define S2_V_BP 10 +#define S2_V_VD 800 +#define S2_V_FP 13 + +#define S2_H_ST 440 +#define S2_V_ST 13 + +//1280*720*50 + +#define S3_OUT_CLK SCALE_RATE(74250000,57375000) // m=34 n=11 no=4 +#define S3_H_PW 10 +#define S3_H_BP 10 +#define S3_H_VD 1280 +#define S3_H_FP 77 + +#define S3_V_PW 10 +#define S3_V_BP 10 +#define S3_V_VD 800 +#define S3_V_FP 13 + +#define S3_H_ST 459 +#define S3_V_ST 13 + +//720*576*50 +#define S4_OUT_CLK SCALE_RATE(27000000,63281250) //m=75 n=4 no=8 +#define S4_H_PW 10 +#define S4_H_BP 10 +#define S4_H_VD 1280 +#define S4_H_FP 185 + +#define S4_V_PW 10 +#define S4_V_BP 10 +#define S4_V_VD 800 +#define S4_V_FP 48 + +#define S4_H_ST 81 +#define S4_V_ST 48 + +//720*480*60 +#define S5_OUT_CLK SCALE_RATE(27000000,75000000) //m=100 n=9 no=4 +#define S5_H_PW 10 +#define S5_H_BP 10 +#define S5_H_VD 1280 +#define S5_H_FP 130 + +#define S5_V_PW 10 +#define S5_V_BP 10 +#define S5_V_VD 800 +#define S5_V_FP 54 + +#define S5_H_ST 476 +#define S5_V_ST 48 + +#define S_DCLK_POL 0 + +#endif + +#endif diff --git a/drivers/video/rockchip/screen/lcd_hdmi_1366x768.c b/drivers/video/rockchip/screen/lcd_hdmi_1366x768.c new file mode 100644 index 000000000000..c295e2ae5de8 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_hdmi_1366x768.c @@ -0,0 +1,178 @@ + +#ifndef __LCD_HDMI_1366x768__ +#define __LCD_HDMI_1366x768__ + +#ifdef CONFIG_RK610_LVDS +#include "../transmitter/rk610_lcd.h" +#endif + +/* Base */ +#define SCREEN_TYPE SCREEN_LVDS +#define LVDS_FORMAT LVDS_8BIT_1 +#define OUT_FACE OUT_D888_P666 +#define DCLK 95000000 // 1280x800x1.13x60(hz) +#define LCDC_ACLK 500000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 34 +#define H_BP 120 +#define H_VD 1366 +#define H_FP 80 + +#define V_PW 8 +#define V_BP 50 +#define V_VD 768 +#define V_FP 12 + +#define DCLK_POL 1 +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_RG 0 +#define SWAP_GB 0 + + +#define LCD_WIDTH 1366 +#define LCD_HEIGHT 768 + +int dsp_lut[256] ={ + 0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707, + 0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f, + 0x00101010, 0x00111111, 0x00121212, 0x00131313, 0x00141414, 0x00151515, 0x00161616, 0x00171717, + 0x00181818, 0x00191919, 0x001a1a1a, 0x001b1b1b, 0x001c1c1c, 0x001d1d1d, 0x001e1e1e, 0x001f1f1f, + 0x00202020, 0x00212121, 0x00222222, 0x00232323, 0x00242424, 0x00252525, 0x00262626, 0x00272727, + 0x00282828, 0x00292929, 0x002a2a2a, 0x002b2b2b, 0x002c2c2c, 0x002d2d2d, 0x002e2e2e, 0x002f2f2f, + 0x00303030, 0x00313131, 0x00323232, 0x00333333, 0x00343434, 0x00353535, 0x00363636, 0x00373737, + 0x00383838, 0x00393939, 0x003a3a3a, 0x003b3b3b, 0x003c3c3c, 0x003d3d3d, 0x003e3e3e, 0x003f3f3f, + 0x00404040, 0x00414141, 0x00424242, 0x00434343, 0x00444444, 0x00454545, 0x00464646, 0x00474747, + 0x00484848, 0x00494949, 0x004a4a4a, 0x004b4b4b, 0x004c4c4c, 0x004d4d4d, 0x004e4e4e, 0x004f4f4f, + 0x00505050, 0x00515151, 0x00525252, 0x00535353, 0x00545454, 0x00555555, 0x00565656, 0x00575757, + 0x00585858, 0x00595959, 0x005a5a5a, 0x005b5b5b, 0x005c5c5c, 0x005d5d5d, 0x005e5e5e, 0x005f5f5f, + 0x00606060, 0x00616161, 0x00626262, 0x00636363, 0x00646464, 0x00656565, 0x00666666, 0x00676767, + 0x00686868, 0x00696969, 0x006a6a6a, 0x006b6b6b, 0x006c6c6c, 0x006d6d6d, 0x006e6e6e, 0x006f6f6f, + 0x00707070, 0x00717171, 0x00727272, 0x00737373, 0x00747474, 0x00757575, 0x00767676, 0x00777777, + 0x00787878, 0x00797979, 0x007a7a7a, 0x007b7b7b, 0x007c7c7c, 0x007d7d7d, 0x007e7e7e, 0x007f7f7f, + 0x00808080, 0x00818181, 0x00828282, 0x00838383, 0x00848484, 0x00858585, 0x00868686, 0x00878787, + 0x00888888, 0x00898989, 0x008a8a8a, 0x008b8b8b, 0x008c8c8c, 0x008d8d8d, 0x008e8e8e, 0x008f8f8f, + 0x00909090, 0x00919191, 0x00929292, 0x00939393, 0x00949494, 0x00959595, 0x00969696, 0x00979797, + 0x00989898, 0x00999999, 0x009a9a9a, 0x009b9b9b, 0x009c9c9c, 0x009d9d9d, 0x009e9e9e, 0x009f9f9f, + 0x00a0a0a0, 0x00a1a1a1, 0x00a2a2a2, 0x00a3a3a3, 0x00a4a4a4, 0x00a5a5a5, 0x00a6a6a6, 0x00a7a7a7, + 0x00a8a8a8, 0x00a9a9a9, 0x00aaaaaa, 0x00ababab, 0x00acacac, 0x00adadad, 0x00aeaeae, 0x00afafaf, + 0x00b0b0b0, 0x00b1b1b1, 0x00b2b2b2, 0x00b3b3b3, 0x00b4b4b4, 0x00b5b5b5, 0x00b6b6b6, 0x00b7b7b7, + 0x00b8b8b8, 0x00b9b9b9, 0x00bababa, 0x00bbbbbb, 0x00bcbcbc, 0x00bdbdbd, 0x00bebebe, 0x00bfbfbf, + 0x00c0c0c0, 0x00c1c1c1, 0x00c2c2c2, 0x00c3c3c3, 0x00c4c4c4, 0x00c5c5c5, 0x00c6c6c6, 0x00c7c7c7, + 0x00c8c8c8, 0x00c9c9c9, 0x00cacaca, 0x00cbcbcb, 0x00cccccc, 0x00cdcdcd, 0x00cecece, 0x00cfcfcf, + 0x00d0d0d0, 0x00d1d1d1, 0x00d2d2d2, 0x00d3d3d3, 0x00d4d4d4, 0x00d5d5d5, 0x00d6d6d6, 0x00d7d7d7, + 0x00d8d8d8, 0x00d9d9d9, 0x00dadada, 0x00dbdbdb, 0x00dcdcdc, 0x00dddddd, 0x00dedede, 0x00dfdfdf, + 0x00e0e0e0, 0x00e1e1e1, 0x00e2e2e2, 0x00e3e3e3, 0x00e4e4e4, 0x00e5e5e5, 0x00e6e6e6, 0x00e7e7e7, + 0x00e8e8e8, 0x00e9e9e9, 0x00eaeaea, 0x00ebebeb, 0x00ececec, 0x00ededed, 0x00eeeeee, 0x00efefef, + 0x00f0f0f0, 0x00f1f1f1, 0x00f2f2f2, 0x00f3f3f3, 0x00f4f4f4, 0x00f5f5f5, 0x00f6f6f6, 0x00f7f7f7, + 0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff, +}; + +#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS) + +/* scaler Timing */ +//1920*1080*60 + +#define S_OUT_CLK SCALE_RATE(148500000,79199997) //m=32 n=15 no=4 +#define S_H_PW 34 +#define S_H_BP 120 +#define S_H_VD 1366 +#define S_H_FP 130 + +#define S_V_PW 8 +#define S_V_BP 10 +#define S_V_VD 768 +#define S_V_FP 13 + +#define S_H_ST 0 +#define S_V_ST 15 + +//1920*1080*50 +#define S1_OUT_CLK SCALE_RATE(148500000,66000000) //m=16 n=9 no=4 +#define S1_H_PW 34 +#define S1_H_BP 120 +#define S1_H_VD 1366 +#define S1_H_FP 130 + +#define S1_V_PW 8 +#define S1_V_BP 10 +#define S1_V_VD 768 +#define S1_V_FP 14 + +#define S1_H_ST 0 +#define S1_V_ST 15 + + +//1280*720p 60HZ +#define S2_OUT_CLK SCALE_RATE(74250000,79199997) //m=64 n=15 no=4 +#define S2_H_PW 34 +#define S2_H_BP 120 +#define S2_H_VD 1366 +#define S2_H_FP 130 + +#define S2_V_PW 8 +#define S2_V_BP 10 +#define S2_V_VD 768 +#define S2_V_FP 13 + +#define S2_H_ST 0 +#define S2_V_ST 8 + +//1280*720*50 + +#define S3_OUT_CLK SCALE_RATE(74250000,66000000) // m=16 n=5 no=4 +#define S3_H_PW 34 +#define S3_H_BP 120 +#define S3_H_VD 1366 +#define S3_H_FP 130 + +#define S3_V_PW 8 +#define S3_V_BP 10 +#define S3_V_VD 768 +#define S3_V_FP 14 + +#define S3_H_ST 0 +#define S3_V_ST 8 + + +//720*576*50 //run +#define S4_OUT_CLK SCALE_RATE(27000000,60000000) //m=91 n=9 no=4 +#define S4_H_PW 34 +#define S4_H_BP 20 +#define S4_H_VD 1366 +#define S4_H_FP 20 + +#define S4_V_PW 8 +#define S4_V_BP 10 +#define S4_V_VD 768 +#define S4_V_FP 47 + +#define S4_H_ST 0 +#define S4_V_ST 33 + +//720*480*60 +#define S5_OUT_CLK SCALE_RATE(27000000,72000000) //m=79 n=7 no=4 +#define S5_H_PW 34 +#define S5_H_BP 20 +#define S5_H_VD 1366 +#define S5_H_FP 10 + +#define S5_V_PW 8 +#define S5_V_BP 10 +#define S5_V_VD 768 +#define S5_V_FP 53 + +#define S5_H_ST 0 +#define S5_V_ST 29 + +#define S_DCLK_POL 1 + +/* Other */ + +#endif + +#endif diff --git a/drivers/video/rockchip/screen/lcd_hdmi_800x480.c b/drivers/video/rockchip/screen/lcd_hdmi_800x480.c new file mode 100644 index 000000000000..2511959f21f3 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_hdmi_800x480.c @@ -0,0 +1,138 @@ + +#ifndef __LCD_HDMI_800x480__ +#define __LCD_HDMI_800x480__ + +#ifdef CONFIG_RK610_LVDS +#include "../transmitter/rk610_lcd.h" +#endif + + +/* Base */ +#define SCREEN_TYPE SCREEN_RGB +#define LVDS_FORMAT LVDS_8BIT_1 +#define OUT_FACE OUT_P888 +#define DCLK 33000000 +#define LCDC_ACLK 150000000//312000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 1 +#define H_BP 88 +#define H_VD 800 +#define H_FP 40 + +#define V_PW 3 +#define V_BP 29 +#define V_VD 480 +#define V_FP 13 + +#define LCD_WIDTH 154 +#define LCD_HEIGHT 85 + +/* Other */ +#define DCLK_POL 0 +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_RG 0 +#define SWAP_GB 0 + + +#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS) + +/* scaler Timing */ +//1920*1080*60 + +#define S_OUT_CLK SCALE_RATE(148500000,33000000) +#define S_H_PW 1 +#define S_H_BP 88 +#define S_H_VD 800 +#define S_H_FP 211 + +#define S_V_PW 3 +#define S_V_BP 10 +#define S_V_VD 480 +#define S_V_FP 7 + +#define S_H_ST 244 +#define S_V_ST 11 + +//1920*1080*50 +#define S1_OUT_CLK SCALE_RATE(148500000,30375000) +#define S1_H_PW 1 +#define S1_H_BP 88 +#define S1_H_VD 800 +#define S1_H_FP 326 + +#define S1_V_PW 3 +#define S1_V_BP 9 +#define S1_V_VD 480 +#define S1_V_FP 8 + +#define S1_H_ST 270 +#define S1_V_ST 13 +//1280*720*60 +#define S2_OUT_CLK SCALE_RATE(74250000,33000000) +#define S2_H_PW 1 +#define S2_H_BP 88 +#define S2_H_VD 800 +#define S2_H_FP 211 + +#define S2_V_PW 3 +#define S2_V_BP 9 +#define S2_V_VD 480 +#define S2_V_FP 8 + +#define S2_H_ST 0 +#define S2_V_ST 8 +//1280*720*50 + +#define S3_OUT_CLK SCALE_RATE(74250000,30375000) +#define S3_H_PW 1 +#define S3_H_BP 88 +#define S3_H_VD 800 +#define S3_H_FP 326 + +#define S3_V_PW 3 +#define S3_V_BP 9 +#define S3_V_VD 480 +#define S3_V_FP 8 + +#define S3_H_ST 0 +#define S3_V_ST 8 + +//720*576*50 +#define S4_OUT_CLK SCALE_RATE(27000000,30000000) +#define S4_H_PW 1 +#define S4_H_BP 88 +#define S4_H_VD 800 +#define S4_H_FP 263 + +#define S4_V_PW 3 +#define S4_V_BP 9 +#define S4_V_VD 480 +#define S4_V_FP 28 + +#define S4_H_ST 0 +#define S4_V_ST 33 +//720*480*60 +#define S5_OUT_CLK SCALE_RATE(27000000,31500000) +#define S5_H_PW 1 +#define S5_H_BP 88 +#define S5_H_VD 800 +#define S5_H_FP 112 + +#define S5_V_PW 3 +#define S5_V_BP 9 +#define S5_V_VD 480 +#define S5_V_FP 28 + +#define S5_H_ST 0 +#define S5_V_ST 29 + +#define S_DCLK_POL 0 + +#endif + +#endif diff --git a/drivers/video/rockchip/screen/lcd_hdmi_rk3168m_b101ew05.c b/drivers/video/rockchip/screen/lcd_hdmi_rk3168m_b101ew05.c new file mode 100644 index 000000000000..0d99a4d4a0a0 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_hdmi_rk3168m_b101ew05.c @@ -0,0 +1,85 @@ +#ifndef __LCD_RK3168M__ +#define __LCD_RK3168M__ + +#ifdef CONFIG_RK610_LVDS +#include "../transmitter/rk610_lcd.h" +#endif + + +/* Base */ +#ifdef CONFIG_RK610_LVDS +#define SCREEN_TYPE SCREEN_LVDS +#else +#define SCREEN_TYPE SCREEN_RGB +#endif + +#define LVDS_FORMAT LVDS_8BIT_2 +#define OUT_FACE OUT_D888_P666 + + +#define DCLK 71000000 +#define LCDC_ACLK 300000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 10 +#define H_BP 100 +#define H_VD 1280 +#define H_FP 18 + +#define V_PW 2 +#define V_BP 8 +#define V_VD 800 +#define V_FP 6 + +#define LCD_WIDTH 216 +#define LCD_HEIGHT 135 +/* Other */ +#ifdef CONFIG_RK610_LVDS +#define DCLK_POL 1 +#else +#define DCLK_POL 0 +#endif +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_RG 0 +#define SWAP_GB 0 + +int dsp_lut[256] ={ + 0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707, + 0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f, + 0x00101010, 0x00111111, 0x00121212, 0x00131313, 0x00141414, 0x00151515, 0x00161616, 0x00171717, + 0x00181818, 0x00191919, 0x001a1a1a, 0x001b1b1b, 0x001c1c1c, 0x001d1d1d, 0x001e1e1e, 0x001f1f1f, + 0x00202020, 0x00212121, 0x00222222, 0x00232323, 0x00242424, 0x00252525, 0x00262626, 0x00272727, + 0x00282828, 0x00292929, 0x002a2a2a, 0x002b2b2b, 0x002c2c2c, 0x002d2d2d, 0x002e2e2e, 0x002f2f2f, + 0x00303030, 0x00313131, 0x00323232, 0x00333333, 0x00343434, 0x00353535, 0x00363636, 0x00373737, + 0x00383838, 0x00393939, 0x003a3a3a, 0x003b3b3b, 0x003c3c3c, 0x003d3d3d, 0x003e3e3e, 0x003f3f3f, + 0x00404040, 0x00414141, 0x00424242, 0x00434343, 0x00444444, 0x00454545, 0x00464646, 0x00474747, + 0x00484848, 0x00494949, 0x004a4a4a, 0x004b4b4b, 0x004c4c4c, 0x004d4d4d, 0x004e4e4e, 0x004f4f4f, + 0x00505050, 0x00515151, 0x00525252, 0x00535353, 0x00545454, 0x00555555, 0x00565656, 0x00575757, + 0x00585858, 0x00595959, 0x005a5a5a, 0x005b5b5b, 0x005c5c5c, 0x005d5d5d, 0x005e5e5e, 0x005f5f5f, + 0x00606060, 0x00616161, 0x00626262, 0x00636363, 0x00646464, 0x00656565, 0x00666666, 0x00676767, + 0x00686868, 0x00696969, 0x006a6a6a, 0x006b6b6b, 0x006c6c6c, 0x006d6d6d, 0x006e6e6e, 0x006f6f6f, + 0x00707070, 0x00717171, 0x00727272, 0x00737373, 0x00747474, 0x00757575, 0x00767676, 0x00777777, + 0x00787878, 0x00797979, 0x007a7a7a, 0x007b7b7b, 0x007c7c7c, 0x007d7d7d, 0x007e7e7e, 0x007f7f7f, + 0x00808080, 0x00818181, 0x00828282, 0x00838383, 0x00848484, 0x00858585, 0x00868686, 0x00878787, + 0x00888888, 0x00898989, 0x008a8a8a, 0x008b8b8b, 0x008c8c8c, 0x008d8d8d, 0x008e8e8e, 0x008f8f8f, + 0x00909090, 0x00919191, 0x00929292, 0x00939393, 0x00949494, 0x00959595, 0x00969696, 0x00979797, + 0x00989898, 0x00999999, 0x009a9a9a, 0x009b9b9b, 0x009c9c9c, 0x009d9d9d, 0x009e9e9e, 0x009f9f9f, + 0x00a0a0a0, 0x00a1a1a1, 0x00a2a2a2, 0x00a3a3a3, 0x00a4a4a4, 0x00a5a5a5, 0x00a6a6a6, 0x00a7a7a7, + 0x00a8a8a8, 0x00a9a9a9, 0x00aaaaaa, 0x00ababab, 0x00acacac, 0x00adadad, 0x00aeaeae, 0x00afafaf, + 0x00b0b0b0, 0x00b1b1b1, 0x00b2b2b2, 0x00b3b3b3, 0x00b4b4b4, 0x00b5b5b5, 0x00b6b6b6, 0x00b7b7b7, + 0x00b8b8b8, 0x00b9b9b9, 0x00bababa, 0x00bbbbbb, 0x00bcbcbc, 0x00bdbdbd, 0x00bebebe, 0x00bfbfbf, + 0x00c0c0c0, 0x00c1c1c1, 0x00c2c2c2, 0x00c3c3c3, 0x00c4c4c4, 0x00c5c5c5, 0x00c6c6c6, 0x00c7c7c7, + 0x00c8c8c8, 0x00c9c9c9, 0x00cacaca, 0x00cbcbcb, 0x00cccccc, 0x00cdcdcd, 0x00cecece, 0x00cfcfcf, + 0x00d0d0d0, 0x00d1d1d1, 0x00d2d2d2, 0x00d3d3d3, 0x00d4d4d4, 0x00d5d5d5, 0x00d6d6d6, 0x00d7d7d7, + 0x00d8d8d8, 0x00d9d9d9, 0x00dadada, 0x00dbdbdb, 0x00dcdcdc, 0x00dddddd, 0x00dedede, 0x00dfdfdf, + 0x00e0e0e0, 0x00e1e1e1, 0x00e2e2e2, 0x00e3e3e3, 0x00e4e4e4, 0x00e5e5e5, 0x00e6e6e6, 0x00e7e7e7, + 0x00e8e8e8, 0x00e9e9e9, 0x00eaeaea, 0x00ebebeb, 0x00ececec, 0x00ededed, 0x00eeeeee, 0x00efefef, + 0x00f0f0f0, 0x00f1f1f1, 0x00f2f2f2, 0x00f3f3f3, 0x00f4f4f4, 0x00f5f5f5, 0x00f6f6f6, 0x00f7f7f7, + 0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff, +}; + +#endif diff --git a/drivers/video/rockchip/screen/lcd_hh070d_lvds.c b/drivers/video/rockchip/screen/lcd_hh070d_lvds.c new file mode 100644 index 000000000000..9e8683593751 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_hh070d_lvds.c @@ -0,0 +1,77 @@ +#include +#include +#include "../../rk29_fb.h" +#include +#include +#include +#include "screen.h" + +/* Base */ +#define OUT_TYPE SCREEN_LVDS +#define OUT_FORMAT 1//LVDS_8BIT_2 + +#define OUT_FACE OUT_D888_P666 +#define OUT_CLK 60000000 +#define LCDC_ACLK 300000000//500000000//312000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 100 +#define H_BP 100 +#define H_VD 1024 +#define H_FP 120 + +#define V_PW 10 +#define V_BP 10 +#define V_VD 600 +#define V_FP 150 + +#define LCD_WIDTH 202 +#define LCD_HEIGHT 152 +/* Other */ +#define DCLK_POL 1 +#define SWAP_RB 0 + +void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) +{ + /* screen type & face */ + screen->type = OUT_TYPE; + screen->face = OUT_FACE; + + /* Screen size */ + screen->x_res = H_VD; + screen->y_res = V_VD; + + screen->width = LCD_WIDTH; + screen->height = LCD_HEIGHT; + screen->hw_format = OUT_FORMAT; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK; + screen->pixclock = OUT_CLK; + screen->left_margin = H_BP; + screen->right_margin = H_FP; + screen->hsync_len = H_PW; + screen->upper_margin = V_BP; + screen->lower_margin = V_FP; + screen->vsync_len = V_PW; + + /* Pin polarity */ + screen->pin_hsync = 0; + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = DCLK_POL; + + /* Swap rule */ + screen->swap_rb = SWAP_RB; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = NULL; + screen->standby = NULL; +} + + + diff --git a/drivers/video/rockchip/screen/lcd_hj050na_06a.c b/drivers/video/rockchip/screen/lcd_hj050na_06a.c new file mode 100644 index 000000000000..84e35c309d60 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_hj050na_06a.c @@ -0,0 +1,378 @@ +/* + * Copyright (C) 2012 ROCKCHIP, Inc. + * + * author: hhb@rock-chips.com + * creat date: 2012-04-19 + * route:drivers/video/display/screen/lcd_hj050na_06a.c + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __LCD_HJ050NA__ +#define __LCD_HJ050NA__ + +#include +#include +#include +#include + + +/* Base */ +#define SCREEN_TYPE SCREEN_RGB +#define LVDS_FORMAT LVDS_8BIT_2 +#define OUT_FACE OUT_D888_P666// OUT_D888_P666 //OUT_P888 +#define DCLK 50000000 //50MHz +#define LCDC_ACLK 300000000 //29 lcdc axi DMA + +/* Timing */ +#define H_PW 5 +#define H_BP 50 +#define H_VD 640 +#define H_FP 130 + +#define V_PW 3 +#define V_BP 20//23 +#define V_VD 960 +#define V_FP 12 + +#define LCD_WIDTH 71 //uint mm the lenth of lcd active area +#define LCD_HEIGHT 106 +/* Other */ +#define DCLK_POL 0 +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_RG 0 +#define SWAP_GB 0 + + + +#define RK_SCREEN_INIT //this screen need to init + +#define CONFIG_DEEP_STANDBY_MODE 0 + + +/* define spi write command and data interface function */ + +#define SIMULATION_SPI 1 +#ifdef SIMULATION_SPI + + #define TXD_PORT gLcd_info->txd_pin + #define CLK_PORT gLcd_info->clk_pin + #define CS_PORT gLcd_info->cs_pin + #define LCD_RST_PORT gLcd_info->reset_pin + + #define CS_OUT() gpio_direction_output(CS_PORT, 0) + #define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) + #define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) + #define CLK_OUT() gpio_direction_output(CLK_PORT, 0) + #define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) + #define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) + #define TXD_OUT() gpio_direction_output(TXD_PORT, 0) + #define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) + #define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) + #define LCD_RST_OUT() gpio_direction_output(LCD_RST_PORT, 0) + #define LCD_RST(i) gpio_set_value(LCD_RST_PORT, i) + + #define bits_9 + #ifdef bits_9 //9bits + #define Write_ADDR(cmd) spi_write_9bit(0, cmd) + #define Write_DATA(dat) spi_write_9bit(0x100, dat) + #else //16bits + #define Write_ADDR(cmd) spi_write_16bit(0, cmd) + #define Write_DATA(dat) spi_write_16bit(1, dat) + #endif + #define Lcd_EnvidOnOff(i) + +#else + + #define bits_9 1 + #ifdef bits_9 //9bits + #define LCDSPI_InitCMD(cmd) + #define LCDSPI_InitDAT(dat) + #else //16bits + #define LCDSPI_InitCMD(cmd) + #define LCDSPI_InitDAT(dat) + #endif + +#endif + + +static struct rk29lcd_info *gLcd_info = NULL; +int rk_lcd_init(void); +int rk_lcd_standby(u8 enable); + + +/* spi write a data frame,type mean command or data */ +int spi_write_9bit(u32 type, u32 value) +{ +// if(type != 0 && type != 1) +// return -1; + /*make a data frame of 9 bits,the 8th bit 0:mean command,1:mean data*/ + value &= 0xff; + value |= type; + type = 9; + CS_CLR(); + //udelay(2); + while(type--) { + CLK_CLR(); + if(value & 0x100) + TXD_SET(); + else + TXD_CLR(); + value <<= 1; + //udelay(2); + CLK_SET(); + //udelay(2); + } + CS_SET(); + TXD_SET(); + + return 0; +} + + +int rk_lcd_init(void) +{ + if(gLcd_info) + gLcd_info->io_init(); + + printk("lcd hj050a_06a...\n"); +#if 1 + gpio_direction_output(LCD_RST_PORT, 0); + usleep_range(2*1000, 3*1000); + gpio_set_value(LCD_RST_PORT, 1); + usleep_range(7*1000, 7*1000); +#endif + + Write_ADDR(0x0001); // Software Reset + msleep(10); + + Write_ADDR(0x0011); // Sleep Out + msleep(60); + +//<<<<<<<<<<<<<<>>>>>>>>>>>>>> + Write_ADDR(0x00B0); //Manufacture Command Access Protect + Write_DATA(0x0004); + +//<<<<<<<<<<<>>>>>>>>>>>> + Write_ADDR(0x00B3); //Number of Source outputs & Pixel Format setting + Write_DATA(0x0000); //PSEL[2:0] = 640 RGB + +//<<<<<<<<<<<>>>>>>>>>>>>>>>> + Write_ADDR(0x00B6); + Write_DATA(0x0052); + Write_DATA(0x0083); + Write_DATA(0x0045); + Write_DATA(0x0000); + +//<<<<<<<<<<<>>>>>>>>>>> + Write_ADDR(0x00B8); //Back Light Control(1) + Write_DATA(0x0000); //P1: CABCON = 0; + Write_DATA(0x001A); //P2: SSD_THRE = 1A; + Write_DATA(0x0018); //P3: SD_THRE = 18; + Write_DATA(0x0002); //P4: IPK_INTPO = 02; + Write_DATA(0x0040); //P5: IPK_TRANS = 40; + + Write_ADDR(0x00BB); //Back Light Control(1) + Write_DATA(0x0000); //LEDPWME[3] = 1,PWMWM[1] = 0,PWMON[0] = 0; + Write_DATA(0x00FF); //BDCV = FF; + Write_DATA(0x0001); //PWMDIC=1 + +//<<<<<<<<<<<>>>>>>>>>>> + Write_ADDR(0x00C0); //PANEL DRIVING SETTING 1 (36h=00) + Write_DATA(0x000B); //BLREV[5:4];REV[3];UD[2]=0:forward;BGR[1]=1:RGB->BGR;SS=1:S1920->S1 + Write_DATA(0x00BF); //NL[7:0] NL = 3BF : 960 Line + Write_DATA(0x0003); //NL[10:8] + Write_DATA(0x0011); //VBP[5:0] Vertical back porch + Write_DATA(0x0002); //DIV[3:0] + Write_DATA(0x0009); //PCDIVL[4:0] PCLKD Low Period + Write_DATA(0x0009); //PCDIVH[4:0] PCLKD High Period + + Write_ADDR(0x00C1); //PANEL DRIVING SETTING 2 + Write_DATA(0x0000); //GDS_MODE = 0 : GIP Ctrl(single scan) + Write_DATA(0x0010); //LINEINV[6:4]:2 Line inversion; MFPOL[1]:No Phase inversion; PNSER[0]:Spatial mode1 + Write_DATA(0x0004); //SEQMODE[7]:Source Pre-charge Mode; SEQGND[3:0]: GND Pre-charge 3clk + Write_DATA(0x0088); //SEQVN[7:4]:VCL pre-charge 2clk ;SEQVP[3:0]:VCL pre-charge 2clk + Write_DATA(0x001B); //DPM[7:6]: ;GEQ2W[5:3]/GEQ1W[2:0]:Gate pre-charge + Write_DATA(0x0001); //SDT[5:0] = 8 : Source output delay + Write_DATA(0x0060); //PSEUDO_EN = 0; + Write_DATA(0x0001); //GEM + + Write_ADDR(0x00C3); //PANEL DRIVING SETTING 4 + Write_DATA(0x0000); //GIPPAT[6:4]:Pattern-1 ; GIPMOD[2:0]: GIP mode 1 + Write_DATA(0x0000); //STPEOFF:normal ; FWBWOFF:normal ; T_GALH:normal + Write_DATA(0x0021); //GSPF[5:0]: 33clk + Write_DATA(0x0021); //GSPS[5:0]: 33clk + Write_DATA(0x0000); //VFSTEN[7]: NO END Pulse ; VFST[4:0]: 0 line + Write_DATA(0x0060); //FL1[6]: ; GLOL[5:4]: ; VGSET[3]: ; GIPSIDE=0:Single drive mode ; GOVERSEL=0:Overlap ; GIPSEL=0:8-phase clk + Write_DATA(0x0003); //VBPEX[6]: ; STVG[5:3]: ; STVGA[2:0]: + Write_DATA(0x0000); //ACBF[7:6]: ; ACF[5:4]: ; ACBR[3:2]: ; ACR[1:0]: + Write_DATA(0x0000); //ACBF2[7:6]: ; ACF2[5:4]: ; ACBR2[3:2]: ; ACR2[1:0]: + Write_DATA(0x0090); //9xH ACCYC[3:2]: ; ACFIX[1;0]: + Write_DATA(0x001D); //GOFF_L[7:0] + Write_DATA(0x00FE); //GOFF_L[15:8] + Write_DATA(0x0003); //GOFF_L[17:16] + Write_DATA(0x001D); //GOFF_R[7:0] + Write_DATA(0x00FE); //GOFF_R[15:8] + Write_DATA(0x0003); //GOFF_R[17:16] + +//<<<<<<<<<>>>>>>>>> + Write_ADDR(0x00C7); //TCON Unusual Operation Setting + Write_DATA(0x0000); //P1: + Write_DATA(0x0000); //P2: + Write_DATA(0x0000); //P3: + Write_DATA(0x0000); //P4: + Write_DATA(0x0000); //P5: + Write_DATA(0x0000); //P6: + Write_DATA(0x0000); //P7: + Write_DATA(0x0000); //P8: + Write_DATA(0x0000); //P9: + Write_DATA(0x0000); //P10: + Write_DATA(0x0000); //P11: + Write_DATA(0x0000); //P12: + Write_DATA(0x0000); //P13: + Write_DATA(0x0000); //P14: + +//<<<<<<<<<>>>>>>>>> + Write_ADDR(0x00C8); //Gamma Setting + Write_DATA(0x0003); + Write_DATA(0x000F); + Write_DATA(0x0015); + Write_DATA(0x0018); + Write_DATA(0x001A); + Write_DATA(0x0023); + Write_DATA(0x0025); + Write_DATA(0x0024); + Write_DATA(0x0021); + Write_DATA(0x001E); + Write_DATA(0x0015); + Write_DATA(0x000A); + + Write_DATA(0x0003); + Write_DATA(0x000F); + Write_DATA(0x0015); + Write_DATA(0x0018); + Write_DATA(0x001A); + Write_DATA(0x0023); + Write_DATA(0x0025); + Write_DATA(0x0024); + Write_DATA(0x0021); + Write_DATA(0x001E); + Write_DATA(0x0015); + Write_DATA(0x000A); + +//<<<<<<<<<>>>>>>>>> + Write_ADDR(0x00C9); //COLOR ENHANCEMENT SETTING + Write_DATA(0x0000); //CE_ON = 0; + Write_DATA(0x0080); + Write_DATA(0x0080); + Write_DATA(0x0080); + Write_DATA(0x0080); + Write_DATA(0x0080); + Write_DATA(0x0080); + Write_DATA(0x0080); + Write_DATA(0x0080); + Write_DATA(0x0000); + Write_DATA(0x0000); + Write_DATA(0x0002); + Write_DATA(0x0080); + +//<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>> + Write_ADDR(0x00D0); //POWER SETTING(CHARGE PUMP) + Write_DATA(0x0054); //P1:VC1 = 7; DC23 = 4 + Write_DATA(0x0019); //P2:BT3 = 2; BT2 = 1 09 + Write_DATA(0x00DD); //P3:VLMT1M = D; VLMT1 = D + Write_DATA(0x0016); //P4:VC3 = B; VC2 =B 3B + Write_DATA(0x0092); //P5:VLMT2B = 0; VLMT2 = 0A + Write_DATA(0x00A1); //P6:VLMT3B = 0; VLMT3 = 0F A1 + Write_DATA(0x0000); //P7:VBSON = 0; VBS = 00 + Write_DATA(0x00C0); //P8:VGGON = 0; LVGLON = 0; VC6 = 0 + Write_DATA(0x00CC); //P9:DC56 = ? + + Write_ADDR(0x00D1); //POWER SETTING(SWITCHING REGULATOR) + Write_DATA(0x004D); //P1:VDF1 = 4; VDF0 = D + Write_DATA(0x0024); //P2:DC1CLKEN = 0; DC1MCLKEN = 0; VDF2 =4 + Write_DATA(0x0034); //P3:VDWS2 = 3; VDWS1 = 4 + Write_DATA(0x0055); //P4:VDW12 = 5; VDW11 = 5 + Write_DATA(0x0055); //P5:VDW14 = 5; VDW13 = 5 + Write_DATA(0x0077); //P6:VDW22 = 7; VDW21 = 7 + Write_DATA(0x0077); //P7:VDW24 = 7; VDW23 = 7 + Write_DATA(0x0006); //P8:LSWPH = 6 + +//<<<<<<<<<<<<<<>>>>>>>>>>>>>> + Write_ADDR(0x00D5); //VPLVL/VNLVL SETTING + Write_DATA(0x0020); //P1:PVH = 24 + Write_DATA(0x0020); //P2:NVH = 24 + +//<<<<<<<<<<<<<<>>>>>>>>>>>>>>> + Write_ADDR(0x00D6); + Write_DATA(0x00A8); + +//<<<<<<<<<<<<<<>>>>>>>>>>>>>> + Write_ADDR(0x00DE); //VCOMDC SETTING + Write_DATA(0x0003); //P1:WCVDCB.[1] = 1; WCVDCF.[0] = 1 + Write_DATA(0x005A); //P2:VDCF.[7:0] = ? //57 + Write_DATA(0x005A); //P3:VDCB.[7:0] = ? //57 + + +//<<<<<<<<<<<<<<>>>>>>>>>>>>>> + Write_ADDR(0x00B0); //MANUFACTURE COMMAND ACCESS PROTECT + Write_DATA(0x0003); // + msleep(17); + + Write_ADDR(0x0036); // + Write_DATA(0x0000); // + msleep(17); + Write_ADDR(0x003A); // + Write_DATA(0x0060); // + msleep(17); + Write_ADDR(0x0029); // + + if(gLcd_info) + gLcd_info->io_deinit(); + + return 0; + +} + + + +int rk_lcd_standby(u8 enable) +{ + if(enable) { + if(gLcd_info) + gLcd_info->io_init(); + printk("lcd_standby...\n"); + Write_ADDR(0x0028); //set Display Off + Write_ADDR(0x0010); //enter sleep mode + msleep(50); //wait at least 3 frames time +#if 1 + Write_ADDR(0x00b0); + Write_DATA(0x0004); + Write_ADDR(0x00b1); + Write_DATA(0x0001); + msleep(1); //wait at least 1ms + gpio_direction_output(LCD_RST_PORT, 0); +#endif + + if(gLcd_info) + gLcd_info->io_deinit(); + + } else { + rk_lcd_init(); + } + + return 0; +} + +#endif + diff --git a/drivers/video/rockchip/screen/lcd_hj080na.c b/drivers/video/rockchip/screen/lcd_hj080na.c new file mode 100644 index 000000000000..329d3307aa73 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_hj080na.c @@ -0,0 +1,76 @@ +#include +#include +#include "../../rk29_fb.h" +#include +#include +#include +#include "screen.h" + + +/* Base */ +#define OUT_TYPE SCREEN_RGB +#define LVDS_FORMAT LVDS_8BIT_2 +#define OUT_FACE OUT_P888 +#define OUT_CLK 65000000 +#define LCDC_ACLK 500000000//312000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 100 +#define H_BP 100 +#define H_VD 1024 +#define H_FP 120 + +#define V_PW 10 +#define V_BP 10 +#define V_VD 768 +#define V_FP 15 + +#define LCD_WIDTH 216 +#define LCD_HEIGHT 162 +/* Other */ +#define DCLK_POL 0 +#define SWAP_RB 0 + +void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) +{ + /* screen type & face */ + screen->type = OUT_TYPE; + screen->face = OUT_FACE; + + /* Screen size */ + screen->x_res = H_VD; + screen->y_res = V_VD; + + screen->width = LCD_WIDTH; + screen->height = LCD_HEIGHT; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK; + screen->pixclock = OUT_CLK; + screen->left_margin = H_BP; + screen->right_margin = H_FP; + screen->hsync_len = H_PW; + screen->upper_margin = V_BP; + screen->lower_margin = V_FP; + screen->vsync_len = V_PW; + + /* Pin polarity */ + screen->pin_hsync = 0; + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = DCLK_POL; + + /* Swap rule */ + screen->swap_rb = SWAP_RB; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = NULL; + screen->standby = NULL; +} + + + diff --git a/drivers/video/rockchip/screen/lcd_hj101na.c b/drivers/video/rockchip/screen/lcd_hj101na.c new file mode 100644 index 000000000000..41e04b957d3f --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_hj101na.c @@ -0,0 +1,42 @@ +/* + * This Lcd Driver is for BYD 5' LCD BM800480-8545FTGE. + * written by Michael Lin, 2010-06-18 + */ + +#ifndef __LCD_HJ101NA__ +#define __LCD_HJ101NA__ + + +/* Base */ +#define SCREEN_TYPE SCREEN_RGB +#define OUT_FACE OUT_P888 +#define DCLK 71000000 +#define LCDC_ACLK 300000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 10 +#define H_BP 160 +#define H_VD 1280 +#define H_FP 16 + +#define V_PW 3 +#define V_BP 23 +#define V_VD 800 +#define V_FP 12 + + +/* Other */ +#define DCLK_POL 0 +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_RG 0 +#define SWAP_GB 0 + + +#define LCD_WIDTH 216 //need modify +#define LCD_HEIGHT 135 + +#endif diff --git a/drivers/video/rockchip/screen/lcd_hl070vm4.c b/drivers/video/rockchip/screen/lcd_hl070vm4.c new file mode 100644 index 000000000000..6c2953395517 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_hl070vm4.c @@ -0,0 +1,206 @@ + +#include +#include +#include +#include +#include + + +/* Base */ +#define OUT_TYPE SCREEN_RGB +#define OUT_FACE OUT_P888 +#define OUT_CLK 27000000 +#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 10 +#define H_BP 206 +#define H_VD 800 +#define H_FP 40 + +#define V_PW 10 +#define V_BP 25 +#define V_VD 480 +#define V_FP 10 + + +#define LCD_WIDTH 800 //need modify +#define LCD_HEIGHT 480 + +/* Other */ +#define DCLK_POL 1 ///0 +#define SWAP_RB 0 + +#define TXD_PORT gLcd_info->txd_pin +#define CLK_PORT gLcd_info->clk_pin +#define CS_PORT gLcd_info->cs_pin + +#define CS_OUT() gpio_direction_output(CS_PORT, 0) +#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) +#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) +#define CLK_OUT() gpio_direction_output(CLK_PORT, 0) +#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) +#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) +#define TXD_OUT() gpio_direction_output(TXD_PORT, 0) +#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) +#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) + +static struct rk29lcd_info *gLcd_info = NULL; + +#define DRVDelayUs(i) udelay(i*2) + +int init(void); +int standby(u8 enable); + +void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) +{ + /* screen type & face */ + screen->type = OUT_TYPE; + screen->face = OUT_FACE; + + /* Screen size */ + screen->x_res = H_VD; + screen->y_res = V_VD; + + screen->width = LCD_WIDTH; + screen->height = LCD_HEIGHT; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK; + screen->pixclock = OUT_CLK; + screen->left_margin = H_BP; + screen->right_margin = H_FP; + screen->hsync_len = H_PW; + screen->upper_margin = V_BP; + screen->lower_margin = V_FP; + screen->vsync_len = V_PW; + + /* Pin polarity */ + screen->pin_hsync = 0; + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = DCLK_POL; + + /* Swap rule */ + screen->swap_rb = SWAP_RB; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = init; + screen->standby = standby; + if(lcd_info) + gLcd_info = lcd_info; +} + + +//void spi_screenreg_set(uint32 Addr, uint32 Data) +void spi_screenreg_set(u32 Data) +{ + u32 i; + TXD_OUT(); + CLK_OUT(); + CS_OUT(); + DRVDelayUs(2); + DRVDelayUs(2); + + CS_SET(); + TXD_SET(); + CLK_SET(); + DRVDelayUs(2); + + CS_CLR(); + for(i = 0; i < 16; i++) //reg + { + if(Data &(1<<(15-i))) + TXD_SET(); + else + TXD_CLR(); + + // \u6a21\u62dfCLK + CLK_CLR(); + DRVDelayUs(2); + CLK_SET(); + DRVDelayUs(2); + } + +/* + TXD_CLR(); //write + + // \u6a21\u62dfCLK + CLK_CLR(); + DRVDelayUs(2); + CLK_SET(); + DRVDelayUs(2); + + TXD_SET(); //highz + + // \u6a21\u62dfCLK + CLK_CLR(); + DRVDelayUs(2); + CLK_SET(); + DRVDelayUs(2); + + + //for(i = 0; i < 8; i++) //data + for(i = 0; i < 16; i++) + { + if(Data &(1<<(15-i))) + TXD_SET(); + else + TXD_CLR(); + + // \u6a21\u62dfCLK + CLK_CLR(); + DRVDelayUs(2); + CLK_SET(); + DRVDelayUs(2); + } +*/ + CS_SET(); + CLK_CLR(); + TXD_CLR(); + DRVDelayUs(2); + +} + + +int init(void) +{ + if(gLcd_info) + gLcd_info->io_init(); +/* +r0 00000010 11011011 +r1 00010001 01101111 +r2 00100000 10000000 +r3 00110000 00001000 +r4 01000001 10010000-->>01000001 10011111 +r5 01100001 11001110 +*/ + spi_screenreg_set(0x02db); + spi_screenreg_set(0x116f); + spi_screenreg_set(0x2080); + spi_screenreg_set(0x3008); + spi_screenreg_set(0x419f); + spi_screenreg_set(0x61ce); + if(gLcd_info) + gLcd_info->io_deinit(); + return 0; +} + +int standby(u8 enable) +{ + if(gLcd_info) + gLcd_info->io_init(); + if(!enable) { + init(); + } //else { +// spi_screenreg_set(0x03, 0x5f); +// } + if(gLcd_info) + gLcd_info->io_deinit(); + return 0; +} + diff --git a/drivers/video/rockchip/screen/lcd_hsd100pxn.c b/drivers/video/rockchip/screen/lcd_hsd100pxn.c new file mode 100644 index 000000000000..7e0485ca9541 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_hsd100pxn.c @@ -0,0 +1,130 @@ + +#ifndef __LCD_HSD100PXN__ +#define __LCD_HSD100PXN__ +/* Base */ +#define SCREEN_TYPE SCREEN_LVDS +#define LVDS_FORMAT LVDS_8BIT_2 +#define OUT_FACE OUT_D888_P666 +#define DCLK 65000000 +#define LCDC_ACLK 300000000//312000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 10 +#define H_BP 100 +#define H_VD 1024 +#define H_FP 210 + +#define V_PW 10 +#define V_BP 10 +#define V_VD 768 +#define V_FP 18 + +#define LCD_WIDTH 202 +#define LCD_HEIGHT 152 +/* Other */ +#define DCLK_POL 1 +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_RG 0 +#define SWAP_GB 0 + + +#ifdef CONFIG_ONE_LCDC_DUAL_OUTPUT_INF +/* scaler Timing */ +//1920*1080*60 + +#define S_OUT_CLK 64512000 +#define S_H_PW 114 +#define S_H_BP 210 +#define S_H_VD 1024 +#define S_H_FP 0 + +#define S_V_PW 4 +#define S_V_BP 10 +#define S_V_VD 768 +#define S_V_FP 0 + +#define S_H_ST 0 +#define S_V_ST 23 + +//1920*1080*50 +#define S1_OUT_CLK 53760000 +#define S1_H_PW 114 +#define S1_H_BP 210 +#define S1_H_VD 1024 +#define S1_H_FP 0 + +#define S1_V_PW 4 +#define S1_V_BP 10 +#define S1_V_VD 768 +#define S1_V_FP 0 + +#define S1_H_ST 0 +#define S1_V_ST 23 +//1280*720*60 +#define S2_OUT_CLK 64512000 +#define S2_H_PW 114 +#define S2_H_BP 210 +#define S2_H_VD 1024 +#define S2_H_FP 0 + +#define S2_V_PW 4 +#define S2_V_BP 10 +#define S2_V_VD 768 +#define S2_V_FP 0 + +#define S2_H_ST 0 +#define S2_V_ST 23 +//1280*720*50 + +#define S3_OUT_CLK 53760000 +#define S3_H_PW 114 +#define S3_H_BP 210 +#define S3_H_VD 1024 +#define S3_H_FP 0 + +#define S3_V_PW 4 +#define S3_V_BP 10 +#define S3_V_VD 768 +#define S3_V_FP 0 + +#define S3_H_ST 0 +#define S3_V_ST 23 + +//720*576*50 +#define S4_OUT_CLK 30000000 +#define S4_H_PW 1 +#define S4_H_BP 88 +#define S4_H_VD 800 +#define S4_H_FP 263 + +#define S4_V_PW 3 +#define S4_V_BP 9 +#define S4_V_VD 480 +#define S4_V_FP 28 + +#define S4_H_ST 0 +#define S4_V_ST 33 +//720*480*60 +#define S5_OUT_CLK 30000000 +#define S5_H_PW 1 +#define S5_H_BP 88 +#define S5_H_VD 800 +#define S5_H_FP 112 + +#define S5_V_PW 3 +#define S5_V_BP 9 +#define S5_V_VD 480 +#define S5_V_FP 28 + +#define S5_H_ST 0 +#define S5_V_ST 29 + +#define S_DCLK_POL 1 + +#endif + +#endif diff --git a/drivers/video/rockchip/screen/lcd_hsd100pxn_for_tdw851.c b/drivers/video/rockchip/screen/lcd_hsd100pxn_for_tdw851.c new file mode 100644 index 000000000000..87563c0ddf44 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_hsd100pxn_for_tdw851.c @@ -0,0 +1,284 @@ +/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */ +#include +#include +#include +#include + +/* Base */ +#define SCREEN_TYPE SCREEN_RGB +#define LVDS_FORMAT LVDS_8BIT_2 +#define OUT_FACE OUT_P888//OUT_D888_P666 //OUT_D888_P565 +#define DCLK 24000000 +#define LCDC_ACLK 456000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 10 +#define H_BP 10 +#define H_VD 480 +#define H_FP 12 + +#define V_PW 4 +#define V_BP 4 +#define V_VD 800 +#define V_FP 8 + +/* Other */ +#define DCLK_POL 1 +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_RG 0 +#define SWAP_GB 0 + + +#define LCD_WIDTH 68//800 //need modify +#define LCD_HEIGHT 112//480 + +static struct rk29lcd_info *gLcd_info = NULL; + +#define RK_SCREEN_INIT //this screen need to init + +#define TXD_PORT gLcd_info->txd_pin +#define CLK_PORT gLcd_info->clk_pin +#define CS_PORT gLcd_info->cs_pin +#define RST_PORT gLcd_info->reset_pin + + +#define CS_OUT() gpio_direction_output(CS_PORT, 1) +#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) +#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) + +#define CLK_OUT() gpio_direction_output(CLK_PORT, 0) +#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) +#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) + +#define TXD_OUT() gpio_direction_output(TXD_PORT, 1) +#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) +#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) + +#define RST_OUT() gpio_direction_output(RST_PORT, 1) +#define RST_SET() gpio_set_value(RST_PORT, GPIO_HIGH) +#define RST_CLR() gpio_set_value(RST_PORT, GPIO_LOW) + +#define UDELAY_TIME 1 +#define MDELAY_TIME 120 +void Spi_Write_index(unsigned char index) +{ + int j; + CS_CLR(); + TXD_CLR(); //0 + udelay(UDELAY_TIME); + + CLK_CLR(); + udelay(3);// + + CLK_SET(); + udelay(UDELAY_TIME); + + TXD_CLR(); + CLK_CLR(); + + for(j=0;j<8;j++) + { + if(index&0x80) + { + TXD_SET(); + } + else + { + TXD_CLR(); + } + index<<=1; + + CLK_CLR(); + udelay(UDELAY_TIME); + CLK_SET(); + udelay(UDELAY_TIME); + } + CS_SET(); +} + +void Spi_Write_data(unsigned char data) +{ + int j; + CS_CLR(); + TXD_SET(); + udelay(UDELAY_TIME); + + CLK_CLR(); + udelay(3); + + CLK_SET(); + udelay(UDELAY_TIME); + + TXD_CLR(); + CLK_CLR(); + + for(j=0;j<8;j++) + { + if(data&0x80) + { + TXD_SET(); + } + else + { + TXD_CLR(); + } + data<<=1; + + CLK_CLR(); + udelay(UDELAY_TIME); + CLK_SET(); + udelay(UDELAY_TIME); + } + CS_SET(); +} + +void Lcd_WriteSpi_initial3(void) //HX8363A+IVO 20111128 canshu +{ + //FOR IVO5.2 + HX8363-A + //Set_EXTC + printk("Lcd_WriteSpi_initial3-------------\n"); + Spi_Write_index(0xB9); + Spi_Write_data(0xFF); + Spi_Write_data(0x83); + Spi_Write_data(0x63); + + //Set_VCOM + Spi_Write_index(0xB6); + Spi_Write_data(0x27);//09 + + + //Set_POWER + Spi_Write_index(0xB1); + Spi_Write_data(0x81); + Spi_Write_data(0x30); + Spi_Write_data(0x07);//04 + Spi_Write_data(0x33); + Spi_Write_data(0x02); + Spi_Write_data(0x13); + Spi_Write_data(0x11); + Spi_Write_data(0x00); + Spi_Write_data(0x24); + Spi_Write_data(0x2B); + Spi_Write_data(0x3F); + Spi_Write_data(0x3F); + + Spi_Write_index(0xBf); // + Spi_Write_data(0x00); + Spi_Write_data(0x10); + + //Sleep Out + Spi_Write_index(0x11); + mdelay(MDELAY_TIME); + + + //Set COLMOD + Spi_Write_index(0x3A); + Spi_Write_data(0x70); + + + //Set_RGBIF + Spi_Write_index(0xB3); + Spi_Write_data(0x01); + + + //Set_CYC + Spi_Write_index(0xB4); + Spi_Write_data(0x08); + Spi_Write_data(0x16); + Spi_Write_data(0x5C); + Spi_Write_data(0x0B); + Spi_Write_data(0x01); + Spi_Write_data(0x1E); + Spi_Write_data(0x7B); + Spi_Write_data(0x01); + Spi_Write_data(0x4D); + + //Set_PANEL + Spi_Write_index(0xCC); + //Spi_Write_data(0x01); + Spi_Write_data(0x09); + mdelay(5); + + + //Set Gamma 2.2 + Spi_Write_index(0xE0); + Spi_Write_data(0x00); + Spi_Write_data(0x1E); + Spi_Write_data(0x63); + Spi_Write_data(0x15); + Spi_Write_data(0x11); + Spi_Write_data(0x30); + Spi_Write_data(0x0C); + Spi_Write_data(0x8F); + Spi_Write_data(0x8F); + Spi_Write_data(0x15); + Spi_Write_data(0x17); + Spi_Write_data(0xD5); + Spi_Write_data(0x56); + Spi_Write_data(0x0e); + Spi_Write_data(0x15); + Spi_Write_data(0x00); + Spi_Write_data(0x1E); + Spi_Write_data(0x63); + Spi_Write_data(0x15); + Spi_Write_data(0x11); + Spi_Write_data(0x30); + Spi_Write_data(0x0C); + Spi_Write_data(0x8F); + Spi_Write_data(0x8F); + Spi_Write_data(0x15); + Spi_Write_data(0x17); + Spi_Write_data(0xD5); + Spi_Write_data(0x56); + Spi_Write_data(0x0e); + Spi_Write_data(0x15); + mdelay(5); + + //Display On + Spi_Write_index(0x29); + Spi_Write_index(0x2c); +} + + +static int rk_lcd_init(void) +{ + if(gLcd_info) + gLcd_info->io_init(); + + TXD_OUT(); + CLK_OUT(); + CS_OUT(); + + RST_CLR(); + CS_SET(); + CLK_SET(); + + mdelay(5); + RST_SET(); + mdelay(2); + + Lcd_WriteSpi_initial3(); + + return 0; +} +static int deinit(void) +{ + Spi_Write_index(0x10); + if(gLcd_info) + gLcd_info->io_deinit(); + return 0; + +} +static int rk_lcd_standby(u8 enable) +{ + if(!enable) + rk_lcd_init(); + else + deinit(); + return 0; +} + diff --git a/drivers/video/rockchip/screen/lcd_hsd800x480.c b/drivers/video/rockchip/screen/lcd_hsd800x480.c new file mode 100644 index 000000000000..b55cd3fb707e --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_hsd800x480.c @@ -0,0 +1,246 @@ +/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */ +#include +#include +#include "../../rk29_fb.h" +#include +#include +#include +#include "screen.h" + + +/* Base */ +#define OUT_TYPE SCREEN_RGB +#define OUT_FACE OUT_P888 +#define OUT_CLK 33000000 +#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 8 //10 +#define H_BP 88 //100 +#define H_VD 800 //1024 +#define H_FP 40 //210 + +#define V_PW 3 //10 +#define V_BP 10 //10 +#define V_VD 480 //768 +#define V_FP 32 //18 + +/* Other */ +#define DCLK_POL 0 +#define SWAP_RB 0 + +#define LCD_WIDTH 154 //need modify +#define LCD_HEIGHT 85 + +#define TXD_PORT gLcd_info->txd_pin +#define CLK_PORT gLcd_info->clk_pin +#define CS_PORT gLcd_info->cs_pin + +#define CS_OUT() gpio_direction_output(CS_PORT, 0) +#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) +#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) +#define CLK_OUT() gpio_direction_output(CLK_PORT, 0) +#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) +#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) +#define TXD_OUT() gpio_direction_output(TXD_PORT, 0) +#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) +#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) + +static struct rk29lcd_info *gLcd_info = NULL; + +#define DRVDelayUs(i) udelay(i*2) + +int init(void); +int standby(u8 enable); + +void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) +{ + /* screen type & face */ + screen->type = OUT_TYPE; + screen->face = OUT_FACE; + + /* Screen size */ + screen->x_res = H_VD; + screen->y_res = V_VD; + + screen->width = LCD_WIDTH; + screen->height = LCD_HEIGHT; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK; + screen->pixclock = OUT_CLK; + screen->left_margin = H_BP; + screen->right_margin = H_FP; + screen->hsync_len = H_PW; + screen->upper_margin = V_BP; + screen->lower_margin = V_FP; + screen->vsync_len = V_PW; + + /* Pin polarity */ + screen->pin_hsync = 0; + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = DCLK_POL; + + /* Swap rule */ + screen->swap_rb = SWAP_RB; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + /*screen->init = init;*/ + screen->init = NULL; + screen->standby = standby; + if(lcd_info) + gLcd_info = lcd_info; +} +//cannot need init,so set screen->init = null at rk29_fb.c file + +void spi_screenreg_set(u32 Addr, u32 Data) +{ + u32 i; + + TXD_OUT(); + CLK_OUT(); + CS_OUT(); + DRVDelayUs(2); + DRVDelayUs(2); + + CS_SET(); + TXD_SET(); + CLK_SET(); + DRVDelayUs(2); + + CS_CLR(); + for(i = 0; i < 6; i++) //reg + { + if(Addr &(1<<(5-i))) + TXD_SET(); + else + TXD_CLR(); + + // \u6a21\u62dfCLK + CLK_CLR(); + DRVDelayUs(2); + CLK_SET(); + DRVDelayUs(2); + } + + TXD_CLR(); //write + + // \u6a21\u62dfCLK + CLK_CLR(); + DRVDelayUs(2); + CLK_SET(); + DRVDelayUs(2); + + TXD_SET(); //highz + + // \u6a21\u62dfCLK + CLK_CLR(); + DRVDelayUs(2); + CLK_SET(); + DRVDelayUs(2); + + + for(i = 0; i < 8; i++) //data + { + if(Data &(1<<(7-i))) + TXD_SET(); + else + TXD_CLR(); + + // \u6a21\u62dfCLK + CLK_CLR(); + DRVDelayUs(2); + CLK_SET(); + DRVDelayUs(2); + } + + CS_SET(); + CLK_CLR(); + TXD_CLR(); + DRVDelayUs(2); + +} + + +int init(void) +{ + if(gLcd_info) + gLcd_info->io_init(); + + spi_screenreg_set(0x02, 0x07); + spi_screenreg_set(0x03, 0x5f); + spi_screenreg_set(0x04, 0x17); + spi_screenreg_set(0x05, 0x20); + spi_screenreg_set(0x06, 0x08); + spi_screenreg_set(0x07, 0x20); + spi_screenreg_set(0x08, 0x20); + spi_screenreg_set(0x09, 0x20); + spi_screenreg_set(0x0a, 0x20); + spi_screenreg_set(0x0b, 0x22); + spi_screenreg_set(0x0c, 0x22); + spi_screenreg_set(0x0d, 0x22); + spi_screenreg_set(0x0e, 0x10); + spi_screenreg_set(0x0f, 0x10); + spi_screenreg_set(0x10, 0x10); + + spi_screenreg_set(0x11, 0x15); + spi_screenreg_set(0x12, 0xAA); + spi_screenreg_set(0x13, 0xFF); + spi_screenreg_set(0x14, 0xb0); + spi_screenreg_set(0x15, 0x8e); + spi_screenreg_set(0x16, 0xd6); + spi_screenreg_set(0x17, 0xfe); + spi_screenreg_set(0x18, 0x28); + spi_screenreg_set(0x19, 0x52); + spi_screenreg_set(0x1A, 0x7c); + + spi_screenreg_set(0x1B, 0xe9); + spi_screenreg_set(0x1C, 0x42); + spi_screenreg_set(0x1D, 0x88); + spi_screenreg_set(0x1E, 0xb8); + spi_screenreg_set(0x1F, 0xFF); + spi_screenreg_set(0x20, 0xF0); + spi_screenreg_set(0x21, 0xF0); + spi_screenreg_set(0x22, 0x09); + + if(gLcd_info) + gLcd_info->io_deinit(); + return 0; +} + +int standby(u8 enable) +{ +#if 1 + if(gLcd_info) + gLcd_info->io_init(); + if(enable) { + spi_screenreg_set(0x03, 0xde); + } else { + spi_screenreg_set(0x03, 0x5f); + } + if(gLcd_info) + gLcd_info->io_deinit(); +#else + + GPIOSetPinDirection(GPIOPortB_Pin3, GPIO_OUT); + GPIOSetPinDirection(GPIOPortB_Pin2, GPIO_OUT); + + if(enable) + { + GPIOSetPinLevel(GPIOPortB_Pin3, GPIO_LOW); + GPIOSetPinLevel(GPIOPortB_Pin2, GPIO_HIGH); + } + else + { + GPIOSetPinLevel(GPIOPortB_Pin3, GPIO_HIGH); + GPIOSetPinLevel(GPIOPortB_Pin2, GPIO_LOW); + } +#endif + return 0; +} + diff --git a/drivers/video/rockchip/screen/lcd_hv070wsa.c b/drivers/video/rockchip/screen/lcd_hv070wsa.c new file mode 100644 index 000000000000..b8e670933591 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_hv070wsa.c @@ -0,0 +1,36 @@ +#ifndef __LCD_HV070WSA__ +#define __LCD_HV070WSA__ + + +/* Base */ +#define SCREEN_TYPE SCREEN_RGB +#define LVDS_FORMAT LVDS_8BIT_2 +#define OUT_FACE OUT_P888 +#define DCLK 50000000 +#define LCDC_ACLK 500000000//312000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 100 +#define H_BP 100 +#define H_VD 1024 +#define H_FP 120 + +#define V_PW 10 +#define V_BP 10 +#define V_VD 600 +#define V_FP 15 + +#define LCD_WIDTH 202 +#define LCD_HEIGHT 152 +/* Other */ +#define DCLK_POL 0 +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_RG 0 +#define SWAP_GB 0 + + +#endif diff --git a/drivers/video/rockchip/screen/lcd_hx8357.c b/drivers/video/rockchip/screen/lcd_hx8357.c new file mode 100644 index 000000000000..463ae0b5552a --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_hx8357.c @@ -0,0 +1,401 @@ +#include +#include +#include "../../rk29_fb.h" +#include +#include +#include +#include "screen.h" + + +/* Base */ +#define OUT_TYPE SCREEN_RGB +#define OUT_FACE OUT_P666 /*OUT_P888*/ +#define OUT_CLK 10000000 //***27 +#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 8 +#define H_BP 6 +#define H_VD 320 //***800 +#define H_FP 60 + +#define V_PW 12 +#define V_BP 4 +#define V_VD 480 //***480 +#define V_FP 40 + +#define LCD_WIDTH 320 //need modify +#define LCD_HEIGHT 480 + +/* Other */ +#define DCLK_POL 0 +#define SWAP_RB 0 + +static struct rk29lcd_info *gLcd_info = NULL; +int init(void); +int standby(u8 enable); + + +#define TXD_PORT gLcd_info->txd_pin +#define CLK_PORT gLcd_info->clk_pin +#define CS_PORT gLcd_info->cs_pin + +#define CS_OUT() gpio_direction_output(CS_PORT, 0) +#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) +#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) +#define CLK_OUT() gpio_direction_output(CLK_PORT, 0) +#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) +#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) +#define TXD_OUT() gpio_direction_output(TXD_PORT, 0) +#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) +#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) + +#if 0 +static void screen_set_iomux(u8 enable) +{ + int ret=-1; + if(enable) + { + rk29_mux_api_set(GPIOH6_IQ_SEL_NAME, 0); + ret = gpio_request(RK29_PIN_PH6, NULL); + if(0)//(ret != 0) + { + gpio_free(RK29_PIN_PH6); + printk(">>>>>> lcd cs gpio_request err \n "); + goto pin_err; + } + + rk29_mux_api_set(GPIOE_I2C0_SEL_NAME, 1); + + ret = gpio_request(RK29_PIN_PE5, NULL); + if(0)//(ret != 0) + { + gpio_free(RK29_PIN_PE5); + printk(">>>>>> lcd clk gpio_request err \n "); + goto pin_err; + } + + ret = gpio_request(RK29_PIN_PE4, NULL); + if(0)//(ret != 0) + { + gpio_free(RK29_PIN_PE4); + printk(">>>>>> lcd txd gpio_request err \n "); + goto pin_err; + } + } + else + { + gpio_free(RK29_PIN_PH6); + // rk29_mux_api_set(CXGPIO_HSADC_SEL_NAME, 1); + + gpio_free(RK29_PIN_PE5); + gpio_free(RK29_PIN_PE4); + rk29_mux_api_set(GPIOE_I2C0_SEL_NAME, 0); + } + return ; +pin_err: + return ; + +} +#endif + +void spi_screenreg_set(u32 Addr, u32 Data) +{ +#define DRVDelayUs(i) udelay(i*2) + + u32 i; + u32 control_bit; + + + TXD_OUT(); + CLK_OUT(); + CS_OUT(); + DRVDelayUs(2); + DRVDelayUs(2); + + CS_SET(); + TXD_SET(); + CLK_SET(); + DRVDelayUs(2); + + CS_CLR(); + control_bit = 0x70<<8; + Addr = (control_bit | Addr); + //printk("addr is 0x%x \n", Addr); + for(i = 0; i < 16; i++) //reg + { + if(Addr &(1<<(15-i))) + TXD_SET(); + else + TXD_CLR(); + + // \u6a21\u62dfCLK + CLK_CLR(); + DRVDelayUs(2); + CLK_SET(); + DRVDelayUs(2); + } + + CS_SET(); + TXD_SET(); + CLK_SET(); + DRVDelayUs(2); + CS_CLR(); + + control_bit = 0x72<<8; + Data = (control_bit | Data); + //printk("data is 0x%x \n", Data); + for(i = 0; i < 16; i++) //data + { + if(Data &(1<<(15-i))) + TXD_SET(); + else + TXD_CLR(); + + // \u6a21\u62dfCLK + CLK_CLR(); + DRVDelayUs(2); + CLK_SET(); + DRVDelayUs(2); + } + + CS_SET(); + CLK_CLR(); + TXD_CLR(); + DRVDelayUs(2); +} + +void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) +{ + //printk("lcd_hx8357 set_lcd_info \n"); + /* screen type & face */ + screen->type = OUT_TYPE; + screen->face = OUT_FACE; + + /* Screen size */ + screen->x_res = H_VD; + screen->y_res = V_VD; + + screen->width = LCD_WIDTH; + screen->height = LCD_HEIGHT; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK; + screen->pixclock = OUT_CLK; + screen->left_margin = H_BP; /*>2*/ + screen->right_margin = H_FP; /*>2*/ + screen->hsync_len = H_PW; /*>2*/ //***all > 326, 4upper_margin = V_BP; /*>2*/ + screen->lower_margin = V_FP; /*>2*/ + screen->vsync_len = V_PW; /*>6*/ + + /* Pin polarity */ + screen->pin_hsync = 0; + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = DCLK_POL; + + /* Swap rule */ + screen->swap_rb = SWAP_RB; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = init; + screen->standby = standby; + if(lcd_info) + gLcd_info = lcd_info; +} + +int init(void) +{ + + if(gLcd_info) + gLcd_info->io_init(); + +#if 0 //***Õâ¾ä´úÂëÊDz»ÊÇд´íÁË + spi_screenreg_set(0x02, 0x07); + spi_screenreg_set(0x03, 0x5f); + spi_screenreg_set(0x04, 0x17); + spi_screenreg_set(0x05, 0x20); + spi_screenreg_set(0x06, 0x08); + spi_screenreg_set(0x07, 0x20); + spi_screenreg_set(0x08, 0x20); + spi_screenreg_set(0x09, 0x20); + spi_screenreg_set(0x0a, 0x20); + spi_screenreg_set(0x0b, 0x22); + spi_screenreg_set(0x0c, 0x22); + spi_screenreg_set(0x0d, 0x22); + spi_screenreg_set(0x0e, 0x10); + spi_screenreg_set(0x0f, 0x10); + spi_screenreg_set(0x10, 0x10); + + spi_screenreg_set(0x11, 0x15); + spi_screenreg_set(0x12, 0xAA); + spi_screenreg_set(0x13, 0xFF); + spi_screenreg_set(0x14, 0xb0); + spi_screenreg_set(0x15, 0x8e); + spi_screenreg_set(0x16, 0xd6); + spi_screenreg_set(0x17, 0xfe); + spi_screenreg_set(0x18, 0x28); + spi_screenreg_set(0x19, 0x52); + spi_screenreg_set(0x1A, 0x7c); + + spi_screenreg_set(0x1B, 0xe9); + spi_screenreg_set(0x1C, 0x42); + spi_screenreg_set(0x1D, 0x88); + spi_screenreg_set(0x1E, 0xb8); + spi_screenreg_set(0x1F, 0xFF); + spi_screenreg_set(0x20, 0xF0); + spi_screenreg_set(0x21, 0xF0); + spi_screenreg_set(0x22, 0x09); +#else + spi_screenreg_set(0xff, 0x00); + spi_screenreg_set(0x16, 0x08); + spi_screenreg_set(0x01, 0x02); + spi_screenreg_set(0xe2, 0x00); + spi_screenreg_set(0xe3, 0x00); + spi_screenreg_set(0xf2, 0x00); + spi_screenreg_set(0xe4, 0x1c); + spi_screenreg_set(0xe5, 0x1c); + spi_screenreg_set(0xe6, 0x00); + spi_screenreg_set(0xe7, 0x1c); + + spi_screenreg_set(0x19, 0x01); + mdelay(10); + spi_screenreg_set(0x2a, 0x00); + spi_screenreg_set(0x2b, 0x13); + spi_screenreg_set(0x2f, 0x01); + spi_screenreg_set(0x02, 0x00); + spi_screenreg_set(0x03, 0x00); + spi_screenreg_set(0x04, 0x01); + spi_screenreg_set(0x05, 0x3f); + spi_screenreg_set(0x06, 0x00); + spi_screenreg_set(0x07, 0x00); + + spi_screenreg_set(0x08, 0x01); + spi_screenreg_set(0x09, 0xdf); + spi_screenreg_set(0x24, 0x91); + spi_screenreg_set(0x25, 0x8a); + spi_screenreg_set(0x29, 0x01); + spi_screenreg_set(0x18, 0x22); + spi_screenreg_set(0x1b, 0x30); + mdelay(10); + spi_screenreg_set(0x1d, 0x22); + mdelay(10); + spi_screenreg_set(0x40, 0x00); + spi_screenreg_set(0x41, 0x3c); + spi_screenreg_set(0x42, 0x38); + spi_screenreg_set(0x43, 0x34); + spi_screenreg_set(0x44, 0x2e); + spi_screenreg_set(0x45, 0x2f); + spi_screenreg_set(0x46, 0x41); + spi_screenreg_set(0x47, 0x7d); + spi_screenreg_set(0x48, 0x0b); + spi_screenreg_set(0x49, 0x05); + spi_screenreg_set(0x4a, 0x06); + spi_screenreg_set(0x4b, 0x12); + spi_screenreg_set(0x4c, 0x16); + spi_screenreg_set(0x50, 0x10); + spi_screenreg_set(0x51, 0x11); + spi_screenreg_set(0x52, 0x0b); + spi_screenreg_set(0x53, 0x07); + spi_screenreg_set(0x54, 0x03); + spi_screenreg_set(0x55, 0x3f); + spi_screenreg_set(0x56, 0x02); + spi_screenreg_set(0x57, 0x3e); + spi_screenreg_set(0x58, 0x09); + spi_screenreg_set(0x59, 0x0d); + spi_screenreg_set(0x5a, 0x19); + spi_screenreg_set(0x5b, 0x1a); + spi_screenreg_set(0x5c, 0x14); + spi_screenreg_set(0x5d, 0xc0); + spi_screenreg_set(0x1a, 0x05); + mdelay(10); + + spi_screenreg_set(0x1c, 0x03); + mdelay(10); + spi_screenreg_set(0x1f, 0x90); + mdelay(10); + spi_screenreg_set(0x1f, 0xd2); + mdelay(10); + spi_screenreg_set(0x28, 0x04); + mdelay(40); + spi_screenreg_set(0x28, 0x38); + mdelay(40); + spi_screenreg_set(0x28, 0x3c); + mdelay(40); + spi_screenreg_set(0x80, 0x00); + spi_screenreg_set(0x81, 0x00); + spi_screenreg_set(0x82, 0x00); + spi_screenreg_set(0x83, 0x00); + + spi_screenreg_set(0x60, 0x08); + spi_screenreg_set(0x31, 0x02); + spi_screenreg_set(0x32, 0x08 /*0x00*/); + spi_screenreg_set(0x17, 0x60); //***RGB666 + spi_screenreg_set(0x2d, 0x1f); + spi_screenreg_set(0xe8, 0x90); +#endif + if(gLcd_info) + gLcd_info->io_deinit(); + + return 0; +} + +int standby(u8 enable) //***enable =1 means suspend, 0 means resume +{ + + if(gLcd_info) + gLcd_info->io_init(); + if(enable) { + //printk("---------hx8357 screen suspend--------------\n"); + #if 0 + spi_screenreg_set(0x03, 0xde); + #else + //modify by robert + #if 0 + spi_screenreg_set(0x1f, 0x91); + spi_screenreg_set(0x19, 0x00); + #else + spi_screenreg_set(0x28, 0x38); + msleep(10); + spi_screenreg_set(0x28, 0x24); + msleep(10); + spi_screenreg_set(0x28, 0x04); + #endif + //modify end + #endif + } else { + //printk("--------- hx8357 screen resume--------------\n "); + #if 0 + spi_screenreg_set(0x03, 0x5f); + #else + //modify by robert + #if 0 + spi_screenreg_set(0x19, 0x01); + spi_screenreg_set(0x1f, 0x90); + mdelay(10); + spi_screenreg_set(0x1f, 0xd2); + #else + spi_screenreg_set(0x28, 0x38); + msleep(10); + spi_screenreg_set(0x28, 0x3c); + msleep(10); + spi_screenreg_set(0x80, 0x00); + spi_screenreg_set(0x81, 0x00); + spi_screenreg_set(0x82, 0x00); + spi_screenreg_set(0x83, 0x00); + + #endif + //modify end + #endif + } + + if(gLcd_info) + gLcd_info->io_deinit(); + return 0; +} + diff --git a/drivers/video/rockchip/screen/lcd_ili9803_cpt4_3.c b/drivers/video/rockchip/screen/lcd_ili9803_cpt4_3.c new file mode 100644 index 000000000000..aba60562dbc3 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_ili9803_cpt4_3.c @@ -0,0 +1,380 @@ +/* + * Copyright (C) 2011 ROCKCHIP, Inc. + * + * author: hhb@rock-chips.com + * creat date: 2011-05-14 + * route:drivers/video/display/screen/lcd_ili9803_cpt4_3.c - driver for rk29 phone sdk or rk29 a22 + * station:haven been tested in a22 hardware platform + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + + + +#include +#include +#include "../../rk29_fb.h" +#include +#include +#include +#include "screen.h" + + +/* Base */ +#define OUT_TYPE SCREEN_RGB +#define OUT_FACE OUT_P666 +#define OUT_CLK 26000000 +#define LCDC_ACLK 150000000 //29 lcdc axi DMA + +/* Timing */ +#define H_PW 8 +#define H_BP 6 +#define H_VD 480 +#define H_FP 60 + +#define V_PW 2 +#define V_BP 12 +#define V_VD 800 +#define V_FP 4 + + +#define LCD_WIDTH 480 //need modify +#define LCD_HEIGHT 800 + +/* Other */ +#define DCLK_POL 1 +#define SWAP_RB 0 + + +/* define spi write command and data interface function */ + +#define SIMULATION_SPI 1 +#ifdef SIMULATION_SPI + + #define TXD_PORT gLcd_info->txd_pin + #define CLK_PORT gLcd_info->clk_pin + #define CS_PORT gLcd_info->cs_pin + #define LCD_RST_PORT RK29_PIN6_PC6 + + #define CS_OUT() gpio_direction_output(CS_PORT, 0) + #define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) + #define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) + #define CLK_OUT() gpio_direction_output(CLK_PORT, 0) + #define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) + #define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) + #define TXD_OUT() gpio_direction_output(TXD_PORT, 0) + #define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) + #define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) + #define LCD_RST_OUT() gpio_direction_output(LCD_RST_PORT, 0) + #define LCD_RST(i) gpio_set_value(LCD_RST_PORT, i) + + #define bits_9 + #ifdef bits_9 //9bits + + #define LCD_ILI9803_CMD(cmd) spi_write_9bit(0, cmd) + #define LCD_ILI9803_Parameter(dat) spi_write_9bit(1, dat) + #else //16bits + #define LCD_ILI9803_CMD(cmd) spi_write_16bit(0, cmd) + #define LCD_ILI9803_Parameter(dat) spi_write_16bit(1, dat) + #endif + #define Lcd_EnvidOnOff(i) + +#else + + #define bits_9 1 + #ifdef bits_9 //9bits + #define LCD_ILI9803_CMD(cmd) + #define LCD_ILI9803_Parameter(dat) + #else //16bits + #define LCD_ILI9803_CMD(cmd) + #define LCD_ILI9803_Parameter(dat) + #endif + +#endif + + +/* define lcd command */ +#define ENTER_SLEEP_MODE 0x10 +#define EXIT_SLEEP_MODE 0x11 +#define SET_COLUMN_ADDRESS 0x2a +#define SET_PAGE_ADDRESS 0x2b +#define WRITE_MEMORY_START 0x2c +#define SET_DISPLAY_ON 0x29 +#define SET_DISPLAY_OFF 0x28 +#define SET_ADDRESS_MODE 0x36 +#define SET_PIXEL_FORMAT 0x3a + + +#define DRVDelayUs(i) udelay(i*2) + +static struct rk29lcd_info *gLcd_info = NULL; +int lcd_init(void); +int lcd_standby(u8 enable); + + +/* spi write a data frame,type mean command or data */ +int spi_write_9bit(u32 type, u32 value) +{ + u32 i = 0; + + if(type != 0 && type != 1) + { + return -1; + } + /*make a data frame of 9 bits,the 8th bit 0:mean command,1:mean data*/ + value &= 0xff; + value |= (type << 8); +// if(0 == type){ + TXD_OUT(); + CLK_OUT(); + CS_OUT(); + DRVDelayUs(2); + DRVDelayUs(2); + CS_SET(); + TXD_SET(); + CLK_SET(); + DRVDelayUs(2); + CS_CLR(); +// } + + for(i = 0; i < 9; i++) //reg + { + + CLK_CLR(); + DRVDelayUs(2); + if(value & (1 << (8-i))) + { + TXD_SET(); + } + else + { + TXD_CLR(); + } + CLK_SET(); + DRVDelayUs(2); + } + +// if(0 == type){ + CS_SET(); + CLK_CLR(); + TXD_CLR(); +// } + + DRVDelayUs(2); + return 0; +} + + +int lcd_init(void) +{ + if(gLcd_info) + gLcd_info->io_init(); + printk("*****lcd_init...*****\n"); +/* reset lcd to start init lcd by software if there is no hardware reset circuit for the lcd */ +#ifdef LCD_RST_PORT + gpio_request(LCD_RST_PORT, NULL); + LCD_RST_OUT(); + LCD_RST(1); + msleep(1); + LCD_RST(0); + msleep(10); + LCD_RST(1); + msleep(120); + +#endif + + TXD_OUT(); + CLK_OUT(); + CS_OUT(); + CS_SET(); + TXD_SET(); + CLK_SET(); + + LCD_ILI9803_CMD(0xB1); + LCD_ILI9803_Parameter(0x00); + LCD_ILI9803_CMD(0xB2); + LCD_ILI9803_Parameter(0x10); + LCD_ILI9803_Parameter(0xC7); + LCD_ILI9803_CMD(0xB3); + LCD_ILI9803_Parameter(0x00); + LCD_ILI9803_CMD(0xB4); + LCD_ILI9803_Parameter(0x00); + LCD_ILI9803_CMD(0xB9); + LCD_ILI9803_Parameter(0x00); + LCD_ILI9803_CMD(0xC3); + LCD_ILI9803_Parameter(0x07); + LCD_ILI9803_CMD(0xB2); + LCD_ILI9803_Parameter(0x04); + LCD_ILI9803_Parameter(0x0B); + LCD_ILI9803_Parameter(0x0B); + LCD_ILI9803_Parameter(0x00); + LCD_ILI9803_Parameter(0x07); + LCD_ILI9803_Parameter(0x04); + LCD_ILI9803_CMD(0xC5); + LCD_ILI9803_Parameter(0x6E); + LCD_ILI9803_CMD(0xC2); + LCD_ILI9803_Parameter(0x20); + LCD_ILI9803_Parameter(0x00); + LCD_ILI9803_Parameter(0x10); + msleep(20); + LCD_ILI9803_CMD(0xC8); + LCD_ILI9803_Parameter(0xA3); + LCD_ILI9803_CMD(0xC9); + LCD_ILI9803_Parameter(0x32); + LCD_ILI9803_Parameter(0x06); + LCD_ILI9803_CMD(0xD7); + LCD_ILI9803_Parameter(0x03); + LCD_ILI9803_Parameter(0x00); + LCD_ILI9803_Parameter(0x0F); + LCD_ILI9803_Parameter(0x0F); + LCD_ILI9803_CMD(0xCF); + LCD_ILI9803_Parameter(0x00); + LCD_ILI9803_Parameter(0x08); + LCD_ILI9803_CMD(0xB6); + LCD_ILI9803_Parameter(0x20); + LCD_ILI9803_Parameter(0xC2); + LCD_ILI9803_Parameter(0xFF); + LCD_ILI9803_Parameter(0x04); + LCD_ILI9803_CMD(0xEA); + LCD_ILI9803_Parameter(0x00); + LCD_ILI9803_CMD(0x2A); + LCD_ILI9803_Parameter(0x00); + LCD_ILI9803_Parameter(0x00); + LCD_ILI9803_Parameter(0x01); + LCD_ILI9803_Parameter(0xDF); + LCD_ILI9803_CMD(0x2B); + LCD_ILI9803_Parameter(0x00); + LCD_ILI9803_Parameter(0x00); + LCD_ILI9803_Parameter(0x03); + LCD_ILI9803_Parameter(0xEF); + LCD_ILI9803_CMD(0xB0); + LCD_ILI9803_Parameter(0x01); + LCD_ILI9803_CMD(0x0C); + LCD_ILI9803_Parameter(0x50); + LCD_ILI9803_CMD(0x36); + LCD_ILI9803_Parameter(0x48); + LCD_ILI9803_CMD(0x3A); + LCD_ILI9803_Parameter(0x66); + LCD_ILI9803_CMD(0xE0); + LCD_ILI9803_Parameter(0x05); + LCD_ILI9803_Parameter(0x07); + LCD_ILI9803_Parameter(0x0B); + LCD_ILI9803_Parameter(0x14); + LCD_ILI9803_Parameter(0x11); + LCD_ILI9803_Parameter(0x14); + LCD_ILI9803_Parameter(0x0A); + LCD_ILI9803_Parameter(0x07); + LCD_ILI9803_Parameter(0x04); + LCD_ILI9803_Parameter(0x0B); + LCD_ILI9803_Parameter(0x02); + LCD_ILI9803_Parameter(0x00); + LCD_ILI9803_Parameter(0x04); + LCD_ILI9803_Parameter(0x33); + LCD_ILI9803_Parameter(0x36); + LCD_ILI9803_Parameter(0x1F); + LCD_ILI9803_CMD(0xE1); + LCD_ILI9803_Parameter(0x1F); + LCD_ILI9803_Parameter(0x36); + LCD_ILI9803_Parameter(0x33); + LCD_ILI9803_Parameter(0x04); + LCD_ILI9803_Parameter(0x00); + LCD_ILI9803_Parameter(0x02); + LCD_ILI9803_Parameter(0x0B); + LCD_ILI9803_Parameter(0x04); + LCD_ILI9803_Parameter(0x07); + LCD_ILI9803_Parameter(0x0A); + LCD_ILI9803_Parameter(0x14); + LCD_ILI9803_Parameter(0x11); + LCD_ILI9803_Parameter(0x14); + LCD_ILI9803_Parameter(0x0B); + LCD_ILI9803_Parameter(0x07); + LCD_ILI9803_Parameter(0x05); + LCD_ILI9803_CMD(EXIT_SLEEP_MODE); + msleep(70); + LCD_ILI9803_CMD(SET_DISPLAY_ON); + msleep(10); + LCD_ILI9803_CMD(WRITE_MEMORY_START); + + if(gLcd_info) + gLcd_info->io_deinit(); + + return 0; +} + +extern void rk29_lcd_spim_spin_lock(void); +extern void rk29_lcd_spim_spin_unlock(void); +int lcd_standby(u8 enable) +{ + rk29_lcd_spim_spin_lock(); + if(gLcd_info) + gLcd_info->io_init(); + + if(enable) { + LCD_ILI9803_CMD(ENTER_SLEEP_MODE); + msleep(150); + printk("lcd enter sleep mode\n"); + } else { + LCD_ILI9803_CMD(EXIT_SLEEP_MODE); + msleep(150); + printk("lcd exit sleep mode\n"); + } + + if(gLcd_info) + gLcd_info->io_deinit(); + rk29_lcd_spim_spin_unlock(); + + return 0; +} + +void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) +{ + /* screen type & face */ + screen->type = OUT_TYPE; + screen->face = OUT_FACE; + + /* Screen size */ + screen->x_res = H_VD; + screen->y_res = V_VD; + + screen->width = LCD_WIDTH; + screen->height = LCD_HEIGHT; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK; + screen->pixclock = OUT_CLK; + screen->left_margin = H_BP; + screen->right_margin = H_FP; + screen->hsync_len = H_PW; + screen->upper_margin = V_BP; + screen->lower_margin = V_FP; + screen->vsync_len = V_PW; + + /* Pin polarity */ + screen->pin_hsync = 0; + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = DCLK_POL; + + /* Swap rule */ + screen->swap_rb = SWAP_RB; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = lcd_init; + screen->standby = lcd_standby; + if(lcd_info) + gLcd_info = lcd_info; +} + + + diff --git a/drivers/video/rockchip/screen/lcd_ips1p5680_v1_e.c b/drivers/video/rockchip/screen/lcd_ips1p5680_v1_e.c new file mode 100644 index 000000000000..4dafd4d5db69 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_ips1p5680_v1_e.c @@ -0,0 +1,239 @@ +/* + * Copyright (C) 2011 ROCKCHIP, Inc. + * + * author: hhb@rock-chips.com + * creat date: 2011-03-07 + * route:drivers/video/display/screen/lcd_ips1p5680_v1_e.c - driver for rk29 phone sdk + * station:haven't been tested in any hardware platform + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include +#include +#include "../../rk29_fb.h" +#include +#include +#include "screen.h" + +/* Base */ +#define OUT_TYPE SCREEN_MCU +#define OUT_FACE OUT_P565 + +/* Timing */ +#define H_PW 1 +#define H_BP 1 +#define H_VD 320 +#define H_FP 5 + +#define V_PW 1 +#define V_BP 1 +#define V_VD 480 +#define V_FP 1 + +#define LCD_WIDTH 320 //need modify +#define LCD_HEIGHT 480 + +#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ + +#define P_WR 27 +#define USE_FMARK 0 //2 ÊÇ·ñʹÓÃFMK (0:²»Ö§³Ö 1:ºáÆÁÖ§³Ö 2:ºáÊúÆÁ¶ŒÖ§³Ö) +#define FRMRATE 60 //MCUÆÁµÄË¢ÐÂÂÊ (FMKÓÐЧʱÓÃ) + + +/* Other */ +#define DCLK_POL 0 +#define SWAP_RB 0 + + +/* define lcd command */ +#define ENTER_SLEEP_MODE 0x10 +#define EXIT_SLEEP_MODE 0x11 +#define SET_COLUMN_ADDRESS 0x2a +#define SET_PAGE_ADDRESS 0x2b +#define WRITE_MEMORY_START 0x2c +#define SET_DISPLAY_ON 0x29 +#define SET_DISPLAY_OFF 0x28 +#define SET_ADDRESS_MODE 0x36 +#define SET_PIXEL_FORMAT 0x3a + + +/* initialize the lcd registers to make it function noamally*/ + +int lcd_init(void) +{ + int i =0; + mcu_ioctl(MCU_SETBYPASS, 1); + msleep(5); + mcu_ioctl(MCU_WRCMD, SET_ADDRESS_MODE); //set address normal mode + mcu_ioctl(MCU_WRDATA, 0); + mcu_ioctl(MCU_WRCMD, SET_PIXEL_FORMAT); //set 16 bits per pixel + mcu_ioctl(MCU_WRDATA, 0x55); + mcu_ioctl(MCU_WRCMD, EXIT_SLEEP_MODE); //set lcd exit sleep mode,because the lcd is in sleep mode when power on + msleep(1000*6 / FRMRATE + 10); //wait for about 6 frames' time + mcu_ioctl(MCU_WRCMD, SET_DISPLAY_ON); //set display on + msleep(1000/FRMRATE); + + /*init lcd internal ram,so lcd won't display randomly*/ + mcu_ioctl(MCU_WRCMD, SET_COLUMN_ADDRESS); + mcu_ioctl(MCU_WRDATA, 0); + mcu_ioctl(MCU_WRDATA, 0); + mcu_ioctl(MCU_WRDATA, (LCD_WIDTH >> 8) & 0x0003); + mcu_ioctl(MCU_WRDATA, LCD_WIDTH & 0x00ff); + msleep(10); + mcu_ioctl(MCU_WRCMD, SET_PAGE_ADDRESS); + mcu_ioctl(MCU_WRDATA, 0); + mcu_ioctl(MCU_WRDATA, 0); + mcu_ioctl(MCU_WRDATA, (LCD_HEIGHT >> 8) & 0x0003); + mcu_ioctl(MCU_WRDATA, LCD_HEIGHT & 0x00ff); + msleep(10); + mcu_ioctl(MCU_WRCMD, WRITE_MEMORY_START); + + for(i = 0; i < LCD_WIDTH*LCD_HEIGHT; i++) + { + mcu_ioctl(MCU_WRDATA, 0x00000000); + } + + mcu_ioctl(MCU_SETBYPASS, 0); + return 0; +} + +/* set lcd to sleep mode or not */ + +int lcd_standby(u8 enable) +{ + mcu_ioctl(MCU_SETBYPASS, 1); + + if(enable) { + mcu_ioctl(MCU_WRCMD, ENTER_SLEEP_MODE); + } else { + mcu_ioctl(MCU_WRCMD, EXIT_SLEEP_MODE); + } + + mcu_ioctl(MCU_SETBYPASS, 0); + + return 0; +} + +/* set lcd to write memory mode, so the lcdc of RK29xx can send the fb content to the lcd internal ram in hold mode*/ + +int lcd_refresh(u8 arg) +{ + mcu_ioctl(MCU_SETBYPASS, 1); + + switch(arg) + { + case REFRESH_PRE: //start to write the image data to lcd ram + mcu_ioctl(MCU_WRCMD, SET_COLUMN_ADDRESS); //set + mcu_ioctl(MCU_WRDATA, 0); + mcu_ioctl(MCU_WRDATA, 0); + mcu_ioctl(MCU_WRDATA, (LCD_WIDTH >> 8) & 0x0003); + mcu_ioctl(MCU_WRDATA, LCD_WIDTH & 0x00ff); + msleep(10); + mcu_ioctl(MCU_WRCMD, SET_PAGE_ADDRESS); + mcu_ioctl(MCU_WRDATA, 0); + mcu_ioctl(MCU_WRDATA, 0); + mcu_ioctl(MCU_WRDATA, (LCD_HEIGHT >> 8) & 0x0003); + mcu_ioctl(MCU_WRDATA, LCD_HEIGHT & 0x00ff); + msleep(10); + mcu_ioctl(MCU_WRCMD, WRITE_MEMORY_START); + break; + + case REFRESH_END: //set display on + mcu_ioctl(MCU_WRCMD, SET_DISPLAY_ON); + break; + + default: + break; + } + + mcu_ioctl(MCU_SETBYPASS, 0); + + return 0; +} + + +/* not used */ + +int lcd_scandir(u16 dir) +{ + mcu_ioctl(MCU_SETBYPASS, 1); + +// mcu_ioctl(MCU_WRCMD, SET_DISPLAY_OFF); + + mcu_ioctl(MCU_SETBYPASS, 0); + return 0; +} + + +/* not used */ + +int lcd_disparea(u8 area) +{ + mcu_ioctl(MCU_SETBYPASS, 1); + mcu_ioctl(MCU_SETBYPASS, 0); + return (0); +} + + +/* set real information about lcd which we use in this harware platform */ + +void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info) +{ + /* screen type & face */ + screen->type = OUT_TYPE; + screen->face = OUT_FACE; + + /* Screen size */ + screen->x_res = H_VD; + screen->y_res = V_VD; + + screen->width = LCD_WIDTH; + screen->height = LCD_HEIGHT; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK; + screen->left_margin = H_BP; + screen->right_margin = H_FP; + screen->hsync_len = H_PW; + screen->upper_margin = V_BP; + screen->lower_margin = V_FP; + screen->vsync_len = V_PW; + + screen->mcu_wrperiod = P_WR; + screen->mcu_usefmk = USE_FMARK; + screen->mcu_frmrate = FRMRATE; + + /* Pin polarity */ + screen->pin_hsync = 0; + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = DCLK_POL; + + /* Swap rule */ + screen->swap_rb = SWAP_RB; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = lcd_init; + screen->standby = lcd_standby; + screen->scandir = lcd_scandir; + screen->refresh = lcd_refresh; + screen->disparea = lcd_disparea; +} + + + + + + diff --git a/drivers/video/rockchip/screen/lcd_mcu_tft480800_25_e.c b/drivers/video/rockchip/screen/lcd_mcu_tft480800_25_e.c new file mode 100644 index 000000000000..f88c493a184f --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_mcu_tft480800_25_e.c @@ -0,0 +1,556 @@ +/* + * Copyright (C) 2011 ROCKCHIP, Inc. + * + * author: hhb@rock-chips.com + * creat date: 2011-03-11 + * route:drivers/video/display/screen/lcd_mcu_tft480800_25_e.c - driver for rk29 phone sdk + * station:haven't been tested in any hardware platform + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include +#include +#include "../../rk29_fb.h" +#include +#include +#include "screen.h" + +/* Base */ +#define OUT_TYPE SCREEN_MCU +#define OUT_FACE OUT_P888 + +/* Timing */ +#define H_PW 1 +#define H_BP 1 +#define H_VD 480 +#define H_FP 5 + +#define V_PW 1 +#define V_BP 1 +#define V_VD 800 +#define V_FP 1 + +#define LCD_WIDTH 480 //need modify +#define LCD_HEIGHT 800 + +#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ + +#define P_WR 27 +#define USE_FMARK 0 //2 ÊÇ·ñʹÓÃFMK (0:²»Ö§³Ö 1:ºáÆÁÖ§³Ö 2:ºáÊúÆÁ¶ŒÖ§³Ö) +#define FRMRATE 60 //MCUÆÁµÄË¢ÐÂÂÊ (FMKÓÐЧʱÓÃ) + + +/* Other */ +#define DCLK_POL 0 +#define SWAP_RB 0 + + +/* define lcd command */ +#define ENTER_SLEEP_MODE 0x10 +#define EXIT_SLEEP_MODE 0x11 +#define SET_COLUMN_ADDRESS 0x2a +#define SET_PAGE_ADDRESS 0x2b +#define WRITE_MEMORY_START 0x2c +#define SET_DISPLAY_ON 0x29 +#define SET_DISPLAY_OFF 0x28 +#define SET_ADDRESS_MODE 0x36 +#define SET_PIXEL_FORMAT 0x3a + + +#define WMLCDCOM(command) mcu_ioctl(MCU_WRCMD,command) +#define WMLCDDATA(data) mcu_ioctl(MCU_WRDATA,data) + + + + +/* initialize the lcd registers to make it function noamally*/ + +int lcd_init(void) +{ + int k = 0; + mcu_ioctl(MCU_SETBYPASS, 1); + +#if 1 //HX8369-A + + WMLCDCOM(0xB9); // SET password + WMLCDDATA(0xFF); + WMLCDDATA(0x83); + WMLCDDATA(0x69); + + WMLCDCOM(0xB0); //Enable internal oscillator + WMLCDDATA(0x01); + WMLCDDATA(0x0B); + + + WMLCDCOM(0xB1); //Set Power + WMLCDDATA(0x85); + WMLCDDATA(0x00); + WMLCDDATA(0x34); + WMLCDDATA(0x0A); + WMLCDDATA(0x00); + WMLCDDATA(0x0F); + WMLCDDATA(0x0F); + WMLCDDATA(0x2A); + WMLCDDATA(0x32); + WMLCDDATA(0x3F); + WMLCDDATA(0x3F); + WMLCDDATA(0x01); //update VBIAS + WMLCDDATA(0x23); + WMLCDDATA(0x01); + WMLCDDATA(0xE6); + WMLCDDATA(0xE6); + WMLCDDATA(0xE6); + WMLCDDATA(0xE6); + WMLCDDATA(0xE6); + + + WMLCDCOM(0xB2); // SET Display 480x800 + WMLCDDATA(0x00); + WMLCDDATA(0x20); + WMLCDDATA(0x05); + WMLCDDATA(0x05); + WMLCDDATA(0x70); //70 + WMLCDDATA(0x00); //00 + WMLCDDATA(0xFF); //FF + WMLCDDATA(0x00); + WMLCDDATA(0x00); + WMLCDDATA(0x00); + WMLCDDATA(0x00); //1 + WMLCDDATA(0x03); + WMLCDDATA(0x03); + WMLCDDATA(0x00); + WMLCDDATA(0x01); + + + + WMLCDCOM(0xB4); // SET Display 480x800 + WMLCDDATA(0x00); //00 + WMLCDDATA(0x18); //18 + WMLCDDATA(0x80); //80 + WMLCDDATA(0x06); + WMLCDDATA(0x02); + + WMLCDCOM(0xB6); // SET VCOM + WMLCDDATA(0x3A); // Update VCOM + WMLCDDATA(0x3A); + + + /************CABC test ***************/ + + WMLCDCOM(0X51);//Write Display Brightness + WMLCDDATA(0Xff);//DBV[7:0]=0XE4 + msleep(20); + + /* + WMLCDCOM(0XC9);//SETCABC + WMLCDDATA(0X5F);//PWM_DIV="110" PWM_CLK 64·ÖƵ INVPULS="1" + WMLCDDATA(0X7F);//WMLCDDATA(0X7F); + WMLCDDATA(0X20);//PWM_EPERIOD + WMLCDDATA(0X00);//SAVEPOWER[6:0] + WMLCDDATA(0X20);//DIM_FRAM[6:0] + WMLCDDATA(0X00);// + WMLCDDATA(0X03);//CABC_FLM + WMLCDDATA(0X20);// + msleep(20); + */ + + WMLCDCOM(0X53);//WRITE CTRL DISPLAY + WMLCDDATA(0X24);//WMLCDDATA(0X26) BCTRL="1" BL="1" DD="1"/"0" + msleep(20); + + WMLCDCOM(0X55); + WMLCDDATA(0X02);//STILL PICTURE + msleep(20); + + //WMLCDCOM(0X5E);//Write CABC minimum brightness (5Eh) + //WMLCDDATA(0X00);//CMB[7:0=0X00 + //msleep(20); + + + /***************************************/ + + WMLCDCOM(0x2A); //set window + WMLCDDATA(0x00); + WMLCDDATA(0x00); + WMLCDDATA(0x0); + WMLCDDATA(0xF0); + + WMLCDCOM(0x2B); + WMLCDDATA(0x00); + WMLCDDATA(0x00); + WMLCDDATA(0x01); + WMLCDDATA(0x40); + + WMLCDCOM(0xD5); //Set GIP + WMLCDDATA(0x00); + WMLCDDATA(0x04); + WMLCDDATA(0x03); + WMLCDDATA(0x00); + WMLCDDATA(0x01); + WMLCDDATA(0x05); + WMLCDDATA(0x28); + WMLCDDATA(0x70); + WMLCDDATA(0x01); + WMLCDDATA(0x03); + WMLCDDATA(0x00); + WMLCDDATA(0x00); + WMLCDDATA(0x40); + WMLCDDATA(0x06); + WMLCDDATA(0x51); + WMLCDDATA(0x07); + WMLCDDATA(0x00); + WMLCDDATA(0x00); + WMLCDDATA(0x41); + WMLCDDATA(0x06); + WMLCDDATA(0x50); + WMLCDDATA(0x07); + WMLCDDATA(0x07); + WMLCDDATA(0x0F); + WMLCDDATA(0x04); + WMLCDDATA(0x00); + + + //Gamma2.2 + WMLCDCOM(0xE0); + WMLCDDATA(0x00); + WMLCDDATA(0x13); + WMLCDDATA(0x19); + WMLCDDATA(0x38); + WMLCDDATA(0x3D); + WMLCDDATA(0x3F); + WMLCDDATA(0x28); + WMLCDDATA(0x46); + WMLCDDATA(0x07); + WMLCDDATA(0x0D); + WMLCDDATA(0x0E); + WMLCDDATA(0x12); + WMLCDDATA(0x15); + WMLCDDATA(0x12); + WMLCDDATA(0x14); + WMLCDDATA(0x0F); + WMLCDDATA(0x17); + WMLCDDATA(0x00); + WMLCDDATA(0x13); + WMLCDDATA(0x19); + WMLCDDATA(0x38); + WMLCDDATA(0x3D); + WMLCDDATA(0x3F); + WMLCDDATA(0x28); + WMLCDDATA(0x46); + WMLCDDATA(0x07); + WMLCDDATA(0x0D); + WMLCDDATA(0x0E); + WMLCDDATA(0x12); + WMLCDDATA(0x15); + WMLCDDATA(0x12); + WMLCDDATA(0x14); + WMLCDDATA(0x0F); + WMLCDDATA(0x17); + msleep(10); + + //DGC Setting + WMLCDCOM(0xC1); + WMLCDDATA(0x01); + + //R + WMLCDDATA(0x00); + WMLCDDATA(0x04); + WMLCDDATA(0x11); + WMLCDDATA(0x19); + WMLCDDATA(0x20); + WMLCDDATA(0x29); + WMLCDDATA(0x30); + WMLCDDATA(0x37); + WMLCDDATA(0x40); + WMLCDDATA(0x4A); + WMLCDDATA(0x52); + WMLCDDATA(0x59); + WMLCDDATA(0x60); + WMLCDDATA(0x68); + WMLCDDATA(0x70); + WMLCDDATA(0x79); + WMLCDDATA(0x81); + WMLCDDATA(0x89); + WMLCDDATA(0x91); + WMLCDDATA(0x99); + WMLCDDATA(0xA1); + WMLCDDATA(0xA8); + WMLCDDATA(0xB0); + WMLCDDATA(0xB8); + WMLCDDATA(0xC1); + WMLCDDATA(0xC9); + WMLCDDATA(0xD0); + WMLCDDATA(0xD8); + WMLCDDATA(0xE1); + WMLCDDATA(0xE8); + WMLCDDATA(0xF1); + WMLCDDATA(0xF8); + WMLCDDATA(0xFF); + WMLCDDATA(0x31); + WMLCDDATA(0x9C); + WMLCDDATA(0x57); + WMLCDDATA(0xED); + WMLCDDATA(0x57); + WMLCDDATA(0x7F); + WMLCDDATA(0x61); + WMLCDDATA(0xAD); + WMLCDDATA(0xC0); +//G + WMLCDDATA(0x00); + WMLCDDATA(0x04); + WMLCDDATA(0x11); + WMLCDDATA(0x19); + WMLCDDATA(0x20); + WMLCDDATA(0x29); + WMLCDDATA(0x30); + WMLCDDATA(0x37); + WMLCDDATA(0x40); + WMLCDDATA(0x4A); + WMLCDDATA(0x52); + WMLCDDATA(0x59); + WMLCDDATA(0x60); + WMLCDDATA(0x68); + WMLCDDATA(0x70); + WMLCDDATA(0x79); + WMLCDDATA(0x81); + WMLCDDATA(0x89); + WMLCDDATA(0x91); + WMLCDDATA(0x99); + WMLCDDATA(0xA1); + WMLCDDATA(0xA8); + WMLCDDATA(0xB0); + WMLCDDATA(0xB8); + WMLCDDATA(0xC1); + WMLCDDATA(0xC9); + WMLCDDATA(0xD0); + WMLCDDATA(0xD8); + WMLCDDATA(0xE1); + WMLCDDATA(0xE8); + WMLCDDATA(0xF1); + WMLCDDATA(0xF8); + WMLCDDATA(0xFF); + WMLCDDATA(0x31); + WMLCDDATA(0x9C); + WMLCDDATA(0x57); + WMLCDDATA(0xED); + WMLCDDATA(0x57); + WMLCDDATA(0x7F); + WMLCDDATA(0x61); + WMLCDDATA(0xAD); + WMLCDDATA(0xC0); + //B + WMLCDDATA(0x00); + WMLCDDATA(0x04); + WMLCDDATA(0x11); + WMLCDDATA(0x19); + WMLCDDATA(0x20); + WMLCDDATA(0x29); + WMLCDDATA(0x30); + WMLCDDATA(0x37); + WMLCDDATA(0x40); + WMLCDDATA(0x4A); + WMLCDDATA(0x52); + WMLCDDATA(0x59); + WMLCDDATA(0x60); + WMLCDDATA(0x68); + WMLCDDATA(0x70); + WMLCDDATA(0x79); + WMLCDDATA(0x81); + WMLCDDATA(0x89); + WMLCDDATA(0x91); + WMLCDDATA(0x99); + WMLCDDATA(0xA1); + WMLCDDATA(0xA8); + WMLCDDATA(0xB0); + WMLCDDATA(0xB8); + WMLCDDATA(0xC1); + WMLCDDATA(0xC9); + WMLCDDATA(0xD0); + WMLCDDATA(0xD8); + WMLCDDATA(0xE1); + WMLCDDATA(0xE8); + WMLCDDATA(0xF1); + WMLCDDATA(0xF8); + WMLCDDATA(0xFF); + WMLCDDATA(0x31); + WMLCDDATA(0x9C); + WMLCDDATA(0x57); + WMLCDDATA(0xED); + WMLCDDATA(0x57); + WMLCDDATA(0x7F); + WMLCDDATA(0x61); + WMLCDDATA(0xAD); + WMLCDDATA(0xC0); + WMLCDCOM(0x2D);//Look up table + + for(k = 0; k < 64; k++) //RED + { + WMLCDDATA(8*k); + } + for(k = 0; k < 64; k++) //GREEN + { + WMLCDDATA(4*k); + } + for(k = 0; k < 64; k++) //BLUE + { + WMLCDDATA(8*k); + } + + msleep(10); + WMLCDCOM(SET_PIXEL_FORMAT); //pixel format setting + WMLCDDATA(0x77); + + WMLCDCOM(EXIT_SLEEP_MODE); + msleep(120); + + WMLCDCOM(SET_DISPLAY_ON); //Display on + WMLCDCOM(WRITE_MEMORY_START); + +#endif + + mcu_ioctl(MCU_SETBYPASS, 0); + return 0; +} + +/* set lcd to sleep mode or not */ + +int lcd_standby(u8 enable) +{ + mcu_ioctl(MCU_SETBYPASS, 1); + + if(enable) { + mcu_ioctl(MCU_WRCMD, ENTER_SLEEP_MODE); + msleep(10); + } else { + mcu_ioctl(MCU_WRCMD, EXIT_SLEEP_MODE); + msleep(20); + } + + mcu_ioctl(MCU_SETBYPASS, 0); + + return 0; +} + +/* set lcd to write memory mode, so the lcdc of RK29xx can send the fb content to the lcd internal ram in hold mode*/ + +int lcd_refresh(u8 arg) +{ + mcu_ioctl(MCU_SETBYPASS, 1); + + switch(arg) + { + case REFRESH_PRE: //start to write the image data to lcd ram + mcu_ioctl(MCU_WRCMD, SET_COLUMN_ADDRESS); //set + mcu_ioctl(MCU_WRDATA, 0); + mcu_ioctl(MCU_WRDATA, 0); + mcu_ioctl(MCU_WRDATA, (LCD_WIDTH >> 8) & 0x00ff); + mcu_ioctl(MCU_WRDATA, LCD_WIDTH & 0x00ff); + msleep(1); + mcu_ioctl(MCU_WRCMD, SET_PAGE_ADDRESS); + mcu_ioctl(MCU_WRDATA, 0); + mcu_ioctl(MCU_WRDATA, 0); + mcu_ioctl(MCU_WRDATA, (LCD_HEIGHT >> 8) & 0x00ff); + mcu_ioctl(MCU_WRDATA, LCD_HEIGHT & 0x00ff); + msleep(1); + mcu_ioctl(MCU_WRCMD, WRITE_MEMORY_START); + break; + + case REFRESH_END: //set display on + mcu_ioctl(MCU_WRCMD, SET_DISPLAY_ON); + break; + + default: + break; + } + + mcu_ioctl(MCU_SETBYPASS, 0); + + return 0; +} + + +/* not used */ + +int lcd_scandir(u16 dir) +{ + mcu_ioctl(MCU_SETBYPASS, 1); + +// mcu_ioctl(MCU_WRCMD, SET_DISPLAY_OFF); + + mcu_ioctl(MCU_SETBYPASS, 0); + return 0; +} + + +/* not used */ + +int lcd_disparea(u8 area) +{ + mcu_ioctl(MCU_SETBYPASS, 1); + mcu_ioctl(MCU_SETBYPASS, 0); + return (0); +} + + +/* set real information about lcd which we use in this harware platform */ + +void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info) +{ + /* screen type & face */ + screen->type = OUT_TYPE; + screen->face = OUT_FACE; + + /* Screen size */ + screen->x_res = H_VD; + screen->y_res = V_VD; + + screen->width = LCD_WIDTH; + screen->height = LCD_HEIGHT; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK; + screen->left_margin = H_BP; + screen->right_margin = H_FP; + screen->hsync_len = H_PW; + screen->upper_margin = V_BP; + screen->lower_margin = V_FP; + screen->vsync_len = V_PW; + + screen->mcu_wrperiod = P_WR; + screen->mcu_usefmk = USE_FMARK; + screen->mcu_frmrate = FRMRATE; + + /* Pin polarity */ + screen->pin_hsync = 0; + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = DCLK_POL; + + /* Swap rule */ + screen->swap_rb = SWAP_RB; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = lcd_init; + screen->standby = lcd_standby; + screen->scandir = lcd_scandir; + screen->refresh = lcd_refresh; + screen->disparea = lcd_disparea; +} + + + + + + diff --git a/drivers/video/rockchip/screen/lcd_mq0801d.c b/drivers/video/rockchip/screen/lcd_mq0801d.c new file mode 100644 index 000000000000..5ddaadc1b38f --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_mq0801d.c @@ -0,0 +1,186 @@ + +#ifndef __LCD_H__ +#define __LCD_H__ + +#if defined(CONFIG_RK610_LVDS) +#include "../transmitter/rk610_lcd.h" +#endif + + +#ifdef CONFIG_RK610_LVDS +#define SCREEN_TYPE SCREEN_LVDS +#else +#define SCREEN_TYPE SCREEN_RGB +#endif +#define LVDS_FORMAT LVDS_8BIT_1 + +#define OUT_FACE OUT_P888 +#define DCLK 67000000 // 65000000 +#define LCDC_ACLK 312000000//312000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 10 +#define H_BP 10 +#define H_VD 1024 +#define H_FP 300 + +#define V_PW 4 +#define V_BP 4 +#define V_VD 768 +#define V_FP 30 + +#define LCD_WIDTH 162 +#define LCD_HEIGHT 121 +/* Other */ +#ifdef CONFIG_RK610_LVDS +#define DCLK_POL 1 +#else +#define DCLK_POL 0 +#endif + +#define SWAP_RB 0 + +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_RG 0 +#define SWAP_GB 0 + +#define USE_RK_DSP_LUT +int dsp_lut[256] ={ + 0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707, + 0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f, + 0x00101010, 0x00111111, 0x00121212, 0x00131313, 0x00141414, 0x00151515, 0x00161616, 0x00171717, + 0x00181818, 0x00191919, 0x001a1a1a, 0x001b1b1b, 0x001c1c1c, 0x001d1d1d, 0x001e1e1e, 0x001f1f1f, + 0x00202020, 0x00212121, 0x00222222, 0x00232323, 0x00242424, 0x00252525, 0x00262626, 0x00272727, + 0x00282828, 0x00292929, 0x002a2a2a, 0x002b2b2b, 0x002c2c2c, 0x002d2d2d, 0x002e2e2e, 0x002f2f2f, + 0x00303030, 0x00313131, 0x00323232, 0x00333333, 0x00343434, 0x00353535, 0x00363636, 0x00373737, + 0x00383838, 0x00393939, 0x003a3a3a, 0x003b3b3b, 0x003c3c3c, 0x003d3d3d, 0x003e3e3e, 0x003f3f3f, + 0x00404040, 0x00414141, 0x00424242, 0x00434343, 0x00444444, 0x00454545, 0x00464646, 0x00474747, + 0x00484848, 0x00494949, 0x004a4a4a, 0x004b4b4b, 0x004c4c4c, 0x004d4d4d, 0x004e4e4e, 0x004f4f4f, + 0x00505050, 0x00515151, 0x00525252, 0x00535353, 0x00545454, 0x00555555, 0x00565656, 0x00575757, + 0x00585858, 0x00595959, 0x005a5a5a, 0x005b5b5b, 0x005c5c5c, 0x005d5d5d, 0x005e5e5e, 0x005f5f5f, + 0x00606060, 0x00616161, 0x00626262, 0x00636363, 0x00646464, 0x00656565, 0x00666666, 0x00676767, + 0x00686868, 0x00696969, 0x006a6a6a, 0x006b6b6b, 0x006c6c6c, 0x006d6d6d, 0x006e6e6e, 0x006f6f6f, + 0x00707070, 0x00717171, 0x00727272, 0x00737373, 0x00747474, 0x00757575, 0x00767676, 0x00777777, + 0x00787878, 0x00797979, 0x007a7a7a, 0x007b7b7b, 0x007c7c7c, 0x007d7d7d, 0x007e7e7e, 0x007f7f7f, + 0x00808080, 0x00818181, 0x00828282, 0x00838383, 0x00848484, 0x00858585, 0x00868686, 0x00878787, + 0x00888888, 0x00898989, 0x008a8a8a, 0x008b8b8b, 0x008c8c8c, 0x008d8d8d, 0x008e8e8e, 0x008f8f8f, + 0x00909090, 0x00919191, 0x00929292, 0x00939393, 0x00949494, 0x00959595, 0x00969696, 0x00979797, + 0x00989898, 0x00999999, 0x009a9a9a, 0x009b9b9b, 0x009c9c9c, 0x009d9d9d, 0x009e9e9e, 0x009f9f9f, + 0x00a0a0a0, 0x00a1a1a1, 0x00a2a2a2, 0x00a3a3a3, 0x00a4a4a4, 0x00a5a5a5, 0x00a6a6a6, 0x00a7a7a7, + 0x00a8a8a8, 0x00a9a9a9, 0x00aaaaaa, 0x00ababab, 0x00acacac, 0x00adadad, 0x00aeaeae, 0x00afafaf, + 0x00b0b0b0, 0x00b1b1b1, 0x00b2b2b2, 0x00b3b3b3, 0x00b4b4b4, 0x00b5b5b5, 0x00b6b6b6, 0x00b7b7b7, + 0x00b8b8b8, 0x00b9b9b9, 0x00bababa, 0x00bbbbbb, 0x00bcbcbc, 0x00bdbdbd, 0x00bebebe, 0x00bfbfbf, + 0x00c0c0c0, 0x00c1c1c1, 0x00c2c2c2, 0x00c3c3c3, 0x00c4c4c4, 0x00c5c5c5, 0x00c6c6c6, 0x00c7c7c7, + 0x00c8c8c8, 0x00c9c9c9, 0x00cacaca, 0x00cbcbcb, 0x00cccccc, 0x00cdcdcd, 0x00cecece, 0x00cfcfcf, + 0x00d0d0d0, 0x00d1d1d1, 0x00d2d2d2, 0x00d3d3d3, 0x00d4d4d4, 0x00d5d5d5, 0x00d6d6d6, 0x00d7d7d7, + 0x00d8d8d8, 0x00d9d9d9, 0x00dadada, 0x00dbdbdb, 0x00dcdcdc, 0x00dddddd, 0x00dedede, 0x00dfdfdf, + 0x00e0e0e0, 0x00e1e1e1, 0x00e2e2e2, 0x00e3e3e3, 0x00e4e4e4, 0x00e5e5e5, 0x00e6e6e6, 0x00e7e7e7, + 0x00e8e8e8, 0x00e9e9e9, 0x00eaeaea, 0x00ebebeb, 0x00ececec, 0x00ededed, 0x00eeeeee, 0x00efefef, + 0x00f0f0f0, 0x00f1f1f1, 0x00f2f2f2, 0x00f3f3f3, 0x00f4f4f4, 0x00f5f5f5, 0x00f6f6f6, 0x00f7f7f7, + 0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff, +}; + +#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS) + +/* scaler Timing */ +//1920*1080*60 + +#define S_OUT_CLK SCALE_RATE(148500000,54000000) +#define S_H_PW 20 +#define S_H_BP 20 +#define S_H_VD 1024 +#define S_H_FP 61 + +#define S_V_PW 10 +#define S_V_BP 10 +#define S_V_VD 768 +#define S_V_FP 12 + +#define S_H_ST 0 +#define S_V_ST 12 + +//1920*1080*50 +#define S1_OUT_CLK SCALE_RATE(148500000,53035713) +#define S1_H_PW 10 +#define S1_H_BP 10 +#define S1_H_VD 1024 +#define S1_H_FP 282 + +#define S1_V_PW 10 +#define S1_V_BP 10 +#define S1_V_VD 768 +#define S1_V_FP 11 + +#define S1_H_ST 1145 +#define S1_V_ST 11 + +//1280*720*60 +#define S2_OUT_CLK SCALE_RATE(74250000,54000000) +#define S2_H_PW 10 +#define S2_H_BP 10 +#define S2_H_VD 1024 +#define S2_H_FP 81 + +#define S2_V_PW 8 +#define S2_V_BP 7 +#define S2_V_VD 768 +#define S2_V_FP 15 + +#define S2_H_ST 0 +#define S2_V_ST 12 + +//1280*720*50 + +#define S3_OUT_CLK SCALE_RATE(74250000,52117790) +#define S3_H_PW 10 +#define S3_H_BP 10 +#define S3_H_VD 1024 +#define S3_H_FP 259 + +#define S3_V_PW 10 +#define S3_V_BP 10 +#define S3_V_VD 768 +#define S3_V_FP 8 + +#define S3_H_ST 1040 +#define S3_V_ST 7 + +//720*576*50 +#define S4_OUT_CLK SCALE_RATE(27000000,52125000) +#define S4_H_PW 10 +#define S4_H_BP 10 +#define S4_H_VD 1024 +#define S4_H_FP 207 + +#define S4_V_PW 15 +#define S4_V_BP 12 +#define S4_V_VD 768 +#define S4_V_FP 10 + +#define S4_H_ST 417 +#define S4_V_ST 25 + +//720*480*60 +#define S5_OUT_CLK SCALE_RATE(27000000,58153847) //m=100 n=9 no=4 +#define S5_H_PW 10 +#define S5_H_BP 10 +#define S5_H_VD 1024 +#define S5_H_FP 111 + +#define S5_V_PW 4 +#define S5_V_BP 3 +#define S5_V_VD 768 +#define S5_V_FP 31 + +#define S5_H_ST 693 +#define S5_V_ST 35 + +#define S_DCLK_POL 1 + +#endif + +#endif diff --git a/drivers/video/rockchip/screen/lcd_nt35510.c b/drivers/video/rockchip/screen/lcd_nt35510.c new file mode 100644 index 000000000000..95f5f06248bb --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_nt35510.c @@ -0,0 +1,1600 @@ + +#ifndef __LCD_NT35510__ +#define __LCD_NT35510__ + +#include +#include +#include +#include +#include + +/* Base */ +#define SCREEN_TYPE SCREEN_RGB +#define OUT_FACE OUT_P888 +#define LVDS_FORMAT LVDS_8BIT_1 +#define DCLK 26*1000*1000 //***27 +#define LCDC_ACLK 300000000 //29 lcdc axi DMA Ƶ�� //rk29 + +/* Timing */ +#define H_PW 4 //8Ç°ÏûÓ° +#define H_BP 8//6 +#define H_VD 480//320 //***800 +#define H_FP 8//60 + +#define V_PW 4//12 +#define V_BP 8// 4 +#define V_VD 800//480 //***480 +#define V_FP 8//40 + +#define LCD_WIDTH 57 //lcd size *mm +#define LCD_HEIGHT 94 + +/* Other */ +#define DCLK_POL 1//0 +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_RG 0 +#define SWAP_GB 0 + + +static struct rk29lcd_info *gLcd_info = NULL; + +int rk_lcd_init(void); +int rk_lcd_standby(u8 enable); + +#define TXD_PORT gLcd_info->txd_pin +#define CLK_PORT gLcd_info->clk_pin +#define CS_PORT gLcd_info->cs_pin + +#define CS_OUT() gpio_direction_output(CS_PORT, 1) +#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) +#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) +#define CLK_OUT() gpio_direction_output(CLK_PORT, 0) +#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) +#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) +#define TXD_OUT() gpio_direction_output(TXD_PORT, 1) +#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) +#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) + + +#define DRVDelayUs(i) udelay(i*4) +#if 0 +void spi_screenreg_cmd(u8 Addr) +{ + u32 i; + u32 control_bit; + + TXD_OUT(); + CLK_OUT(); + CS_OUT(); + DRVDelayUs(2); + DRVDelayUs(2); + + CS_SET(); + TXD_SET(); + CLK_CLR(); + DRVDelayUs(30); + + CS_CLR(); + control_bit = 0x0000; + Addr = (control_bit | Addr);//spi_screenreg_set(0x36, 0x0000, 0xffff); + //printk("addr is 0x%x \n", Addr); + for(i = 0; i < 9; i++) //reg + { + if(Addr &(1<<(8-i))) + TXD_SET(); + else + TXD_CLR(); + + // \u6a21\u62dfCLK + CLK_SET(); + DRVDelayUs(2); + CLK_CLR(); + DRVDelayUs(2); + } + + CS_SET(); + TXD_SET(); + CLK_CLR(); + DRVDelayUs(10); +} + + +void spi_screenreg_param(u8 Param) +{ + + u32 i; + u32 control_bit; + + CS_CLR(); + + control_bit = 0x0100; + Param = (control_bit | Param); + //printk("data0 is 0x%x \n", Data); + for(i = 0; i < 9; i++) //data + { + if(Param &(1<<(8-i))) + TXD_SET(); + else + TXD_CLR(); + + // \u6a21\u62dfCLK + CLK_SET(); + DRVDelayUs(2); + CLK_CLR(); + DRVDelayUs(2); + } + + CS_SET(); + CLK_CLR(); + TXD_CLR(); + DRVDelayUs(10); +} +#endif + + + +void WriteCommand( int Command) +{ + unsigned char i,count1, count2,count3,count4; + count1= Command>>8; + count2= Command; + count3=0x20;//00100000 //дÃüÁî¸ßλ + count4=0x00;//00000000 //дÃüÁîµÍλ======¾ßÌåÇë¿´ICµÄDatasheet + CS_CLR(); + for(i=0;i<8;i++) + { + CLK_CLR(); + if (count3 & 0x80) TXD_SET(); + else TXD_CLR(); + CLK_SET(); + count3<<=1; + } + + for(i=0;i<8;i++) + { + CLK_CLR(); + if (count1 & 0x80) TXD_SET(); + else TXD_CLR(); + CLK_SET(); + count1<<=1; + } + + for(i=0;i<8;i++) + { + CLK_CLR(); + if (count4 & 0x80) TXD_SET(); + else TXD_CLR(); + CLK_SET(); + count4<<=1; + } + + for(i=0;i<8;i++) + { + CLK_CLR(); + if (count2 & 0x80) TXD_SET(); + else TXD_CLR(); + CLK_SET(); + count2<<=1; + } + + CS_SET(); + +} + + + +void WriteParameter(char DH) +{ + unsigned char i, count1, count2,count3,count4; + count1=DH>>8; + count2=DH; + count3=0x60;//дÊý¾Ý¸ßλ + count4=0x40;//дÊý¾ÝµÍλ + + CS_CLR(); + /* + TXD_CLR(); CLK_CLR(); CLK_SET(); //WRITE + TXD_SET(); CLK_CLR(); CLK_SET(); //DATA + TXD_SET(); CLK_CLR(); CLK_SET(); //HIGH BYTE + TXD_CLR(); CLK_CLR(); CLK_SET(); + TXD_CLR(); CLK_CLR(); CLK_SET(); + TXD_CLR(); CLK_CLR(); CLK_SET(); + TXD_CLR(); CLK_CLR(); CLK_SET(); + TXD_CLR(); CLK_CLR(); CLK_SET(); + */ + /* + //ÒòΪÊý¾ÝµÄ¸ßλ»ù±¾ÊDz»Óõģ¬¿ÉÒÔ²»´«¸ßλ£¬Ö±½Ó´«µÍλ + for(i=0;i<8;i++) + { + CLK_CLR(); + if (count3 & 0x80) TXD_SET(); + else TXD_CLR(); + CLK_SET(); + count3<<=1; + } + + for(i=0;i<8;i++) + { + CLK_CLR(); + if (count1 & 0x80) TXD_SET(); + else TXD_CLR(); + CLK_SET(); + count1<<=1; + } + */ + + + for(i=0;i<8;i++) + { + CLK_CLR(); + if (count4 & 0x80) TXD_SET(); + else TXD_CLR(); + CLK_SET(); + count4<<=1; + } + + for(i=0;i<8;i++) + { + CLK_CLR(); + if (count2 & 0x80) TXD_SET(); + else TXD_CLR(); + CLK_SET(); + count2<<=1; + } + + CS_SET(); + +} + + +void init_nt35510(void) +{ + WriteCommand(0X1100); + usleep_range(10*1000, 10*1000); + + WriteCommand(0X1300); + + WriteCommand(0XF000); + WriteParameter(0x55); + + WriteCommand(0XF001); + WriteParameter(0xAA); + + WriteCommand(0XF002); + WriteParameter(0x52); + + WriteCommand(0XF003); + WriteParameter(0x08); + + WriteCommand(0XF004); + WriteParameter(0x01); + + //Gamma setting Red + WriteCommand(0XD100); + WriteParameter(0x00); + + WriteCommand(0XD101); + WriteParameter(0x20); + + WriteCommand(0XD102); + WriteParameter(0x00); + + WriteCommand(0XD103); + WriteParameter(0x2B); + + WriteCommand(0XD104); + WriteParameter(0x00); + + WriteCommand(0XD105); + WriteParameter(0x3C); + + WriteCommand(0XD106); + WriteParameter(0x00); + + WriteCommand(0XD107); + WriteParameter(0x56); + + WriteCommand(0XD108); + WriteParameter(0x00); + + WriteCommand(0XD109); + WriteParameter(0x68); + + WriteCommand(0XD10a); + WriteParameter(0x00); + + WriteCommand(0XD10b); + WriteParameter(0x87); + + WriteCommand(0XD10c); + WriteParameter(0x00); + + WriteCommand(0XD10d); + WriteParameter(0x9E); + + WriteCommand(0XD10e); + WriteParameter(0x00); + + WriteCommand(0XD10f); + WriteParameter(0xC6); + + WriteCommand(0XD110); + WriteParameter(0x00); + + WriteCommand(0XD111); + WriteParameter(0xE4); + + WriteCommand(0XD112); + WriteParameter(0x01); + + WriteCommand(0XD113); + WriteParameter(0x12); + + WriteCommand(0XD114); + WriteParameter(0x01); + + WriteCommand(0XD115); + WriteParameter(0x37); + + WriteCommand(0XD116); + WriteParameter(0x01); + + WriteCommand(0XD117); + WriteParameter(0x75); + + WriteCommand(0XD118); + WriteParameter(0x01); + + WriteCommand(0XD119); + WriteParameter(0xA5); + + WriteCommand(0XD11a); + WriteParameter(0x01); + + WriteCommand(0XD11b); + WriteParameter(0xA6); + + WriteCommand(0XD11c); + WriteParameter(0x01); + + WriteCommand(0XD11d); + WriteParameter(0xD0); + + WriteCommand(0XD11e); + WriteParameter(0x01); + + WriteCommand(0XD11f); + WriteParameter(0xF5); + + WriteCommand(0XD120); + WriteParameter(0x02); + + WriteCommand(0XD121); + WriteParameter(0x0A); + + WriteCommand(0XD122); + WriteParameter(0x02); + + WriteCommand(0XD123); + WriteParameter(0x26); + + WriteCommand(0XD124); + WriteParameter(0x02); + + WriteCommand(0XD125); + WriteParameter(0x3B); + + WriteCommand(0XD126); + WriteParameter(0x02); + + WriteCommand(0XD127); + WriteParameter(0x6B); + + WriteCommand(0XD128); + WriteParameter(0x02); + + WriteCommand(0XD129); + WriteParameter(0x99); + + WriteCommand(0XD12a); + WriteParameter(0x02); + + WriteCommand(0XD12b); + WriteParameter(0xDD); + + WriteCommand(0XD12C); + WriteParameter(0x03); + + WriteCommand(0XD12D); + WriteParameter(0x10); + + WriteCommand(0XD12E); + WriteParameter(0x03); + + WriteCommand(0XD12F); + WriteParameter(0x26); + + WriteCommand(0XD130); + WriteParameter(0x03); + + WriteCommand(0XD131); + WriteParameter(0x32); + + WriteCommand(0XD132); + WriteParameter(0x03); + + WriteCommand(0XD133); + WriteParameter(0x9A); + + //Gamma setting Green + WriteCommand(0XD200); + WriteParameter(0x00); + + WriteCommand(0XD201); + WriteParameter(0xa0); + + WriteCommand(0XD202); + WriteParameter(0x00); + + WriteCommand(0XD203); + WriteParameter(0xa9); + + WriteCommand(0XD204); + WriteParameter(0x00); + + WriteCommand(0XD205); + WriteParameter(0xb5); + + WriteCommand(0XD206); + WriteParameter(0x00); + + WriteCommand(0XD207); + WriteParameter(0xbf); + + WriteCommand(0XD208); + WriteParameter(0x00); + + WriteCommand(0XD209); + WriteParameter(0xc9); + + WriteCommand(0XD20a); + WriteParameter(0x00); + + WriteCommand(0XD20b); + WriteParameter(0xdc); + + WriteCommand(0XD20c); + WriteParameter(0x00); + + WriteCommand(0XD20d); + WriteParameter(0xEE); + + WriteCommand(0XD20e); + WriteParameter(0x01); + + WriteCommand(0XD20f); + WriteParameter(0x0A); + + WriteCommand(0XD210); + WriteParameter(0x01); + + WriteCommand(0XD211); + WriteParameter(0x21); + + WriteCommand(0XD212); + WriteParameter(0x01); + + WriteCommand(0XD213); + WriteParameter(0x48); + + WriteCommand(0XD214); + WriteParameter(0x01); + + WriteCommand(0XD215); + WriteParameter(0x67); + + WriteCommand(0XD216); + WriteParameter(0x01); + + WriteCommand(0XD217); + WriteParameter(0x97); + + WriteCommand(0XD218); + WriteParameter(0x01); + + WriteCommand(0XD219); + WriteParameter(0xBE); + + WriteCommand(0XD21a); + WriteParameter(0x01); + + WriteCommand(0XD21b); + WriteParameter(0xC0); + + WriteCommand(0XD21c); + WriteParameter(0x01); + + WriteCommand(0XD21d); + WriteParameter(0xE1); + + WriteCommand(0XD21e); + WriteParameter(0x02); + + WriteCommand(0XD21f); + WriteParameter(0x04); + + WriteCommand(0XD220); + WriteParameter(0x02); + + WriteCommand(0XD221); + WriteParameter(0x17); + + WriteCommand(0XD222); + WriteParameter(0x02); + + WriteCommand(0XD223); + WriteParameter(0x36); + + WriteCommand(0XD224); + WriteParameter(0x02); + + WriteCommand(0XD225); + WriteParameter(0x50); + + WriteCommand(0XD226); + WriteParameter(0x02); + + WriteCommand(0XD227); + WriteParameter(0x7E); + + WriteCommand(0XD228); + WriteParameter(0x02); + + WriteCommand(0XD229); + WriteParameter(0xAC); + + WriteCommand(0XD22a); + WriteParameter(0x02); + + WriteCommand(0XD22b); + WriteParameter(0xF1); + + WriteCommand(0XD22C); + WriteParameter(0x03); + + WriteCommand(0XD22D); + WriteParameter(0x20); + + WriteCommand(0XD22E); + WriteParameter(0x03); + + WriteCommand(0XD22F); + WriteParameter(0x38); + + WriteCommand(0XD230); + WriteParameter(0x03); + + WriteCommand(0XD231); + WriteParameter(0x43); + + WriteCommand(0XD232); + WriteParameter(0x03); + + WriteCommand(0XD233); + WriteParameter(0x9A); + + + //Gamma setting Blue + WriteCommand(0XD300); + WriteParameter(0x00); + + WriteCommand(0XD301); + WriteParameter(0x50); + + WriteCommand(0XD302); + WriteParameter(0x00); + + WriteCommand(0XD303); + WriteParameter(0x53); + + WriteCommand(0XD304); + WriteParameter(0x00); + + WriteCommand(0XD305); + WriteParameter(0x73); + + WriteCommand(0XD306); + WriteParameter(0x00); + + WriteCommand(0XD307); + WriteParameter(0x89); + + WriteCommand(0XD308); + WriteParameter(0x00); + + WriteCommand(0XD309); + WriteParameter(0x9f); + + WriteCommand(0XD30a); + WriteParameter(0x00); + + WriteCommand(0XD30b); + WriteParameter(0xc1); + + WriteCommand(0XD30c); + WriteParameter(0x00); + + WriteCommand(0XD30d); + WriteParameter(0xda); + + WriteCommand(0XD30e); + WriteParameter(0x01); + + WriteCommand(0XD30f); + WriteParameter(0x02); + + WriteCommand(0XD310); + WriteParameter(0x01); + + WriteCommand(0XD311); + WriteParameter(0x23); + + WriteCommand(0XD312); + WriteParameter(0x01); + + WriteCommand(0XD313); + WriteParameter(0x50); + + WriteCommand(0XD314); + WriteParameter(0x01); + + WriteCommand(0XD315); + WriteParameter(0x6f); + + WriteCommand(0XD316); + WriteParameter(0x01); + + WriteCommand(0XD317); + WriteParameter(0x9f); + + WriteCommand(0XD318); + WriteParameter(0x01); + + WriteCommand(0XD319); + WriteParameter(0xc5); + + WriteCommand(0XD31a); + WriteParameter(0x01); + + WriteCommand(0XD31b); + WriteParameter(0xC6); + + WriteCommand(0XD31c); + WriteParameter(0x01); + + WriteCommand(0XD31d); + WriteParameter(0xE3); + + WriteCommand(0XD31e); + WriteParameter(0x02); + + WriteCommand(0XD31f); + WriteParameter(0x08); + + WriteCommand(0XD320); + WriteParameter(0x02); + + WriteCommand(0XD321); + WriteParameter(0x16); + + WriteCommand(0XD322); + WriteParameter(0x02); + + WriteCommand(0XD323); + WriteParameter(0x2b); + + WriteCommand(0XD324); + WriteParameter(0x02); + + WriteCommand(0XD325); + WriteParameter(0x4d); + + WriteCommand(0XD326); + WriteParameter(0x02); + + WriteCommand(0XD327); + WriteParameter(0x6f); + + WriteCommand(0XD328); + WriteParameter(0x02); + + WriteCommand(0XD329); + WriteParameter(0x8C); + + WriteCommand(0XD32a); + WriteParameter(0x02); + + WriteCommand(0XD32b); + WriteParameter(0xd6); + + WriteCommand(0XD32C); + WriteParameter(0x03); + + WriteCommand(0XD32D); + WriteParameter(0x12); + + WriteCommand(0XD32E); + WriteParameter(0x03); + + WriteCommand(0XD32F); + WriteParameter(0x28); + + WriteCommand(0XD330); + WriteParameter(0x03); + + WriteCommand(0XD331); + WriteParameter(0x3e); + + WriteCommand(0XD332); + WriteParameter(0x03); + + WriteCommand(0XD333); + WriteParameter(0x9A); + + //Gamma setting Red + WriteCommand(0XD400); + WriteParameter(0x00); + + WriteCommand(0XD401); + WriteParameter(0x20); + + WriteCommand(0XD402); + WriteParameter(0x00); + + WriteCommand(0XD403); + WriteParameter(0x2b); + + WriteCommand(0XD404); + WriteParameter(0x00); + + WriteCommand(0XD405); + WriteParameter(0x3c); + + WriteCommand(0XD406); + WriteParameter(0x00); + + WriteCommand(0XD407); + WriteParameter(0x56); + + WriteCommand(0XD408); + WriteParameter(0x00); + + WriteCommand(0XD409); + WriteParameter(0x68); + + WriteCommand(0XD40a); + WriteParameter(0x00); + + WriteCommand(0XD40b); + WriteParameter(0x87); + + WriteCommand(0XD40c); + WriteParameter(0x00); + + WriteCommand(0XD40d); + WriteParameter(0x9e); + + WriteCommand(0XD40e); + WriteParameter(0x00); + + WriteCommand(0XD40f); + WriteParameter(0xc6); + + WriteCommand(0XD410); + WriteParameter(0x00); + + WriteCommand(0XD411); + WriteParameter(0xe4); + + WriteCommand(0XD412); + WriteParameter(0x01); + + WriteCommand(0XD413); + WriteParameter(0x12); + + WriteCommand(0XD414); + WriteParameter(0x01); + + WriteCommand(0XD415); + WriteParameter(0x37); + + WriteCommand(0XD416); + WriteParameter(0x01); + + WriteCommand(0XD417); + WriteParameter(0x75); + + WriteCommand(0XD418); + WriteParameter(0x01); + + WriteCommand(0XD419); + WriteParameter(0xa5); + + WriteCommand(0XD41a); + WriteParameter(0x01); + + WriteCommand(0XD41b); + WriteParameter(0xa6); + + WriteCommand(0XD41c); + WriteParameter(0x01); + + WriteCommand(0XD41d); + WriteParameter(0xd0); + + WriteCommand(0XD41e); + WriteParameter(0x01); + + WriteCommand(0XD41f); + WriteParameter(0xf5); + + WriteCommand(0XD420); + WriteParameter(0x02); + + WriteCommand(0XD421); + WriteParameter(0x0a); + + WriteCommand(0XD422); + WriteParameter(0x02); + + WriteCommand(0XD423); + WriteParameter(0x26); + + WriteCommand(0XD424); + WriteParameter(0x02); + + WriteCommand(0XD425); + WriteParameter(0x3b); + + WriteCommand(0XD426); + WriteParameter(0x02); + + WriteCommand(0XD427); + WriteParameter(0x6b); + + WriteCommand(0XD428); + WriteParameter(0x02); + + WriteCommand(0XD429); + WriteParameter(0x99); + + WriteCommand(0XD42a); + WriteParameter(0x02); + + WriteCommand(0XD42b); + WriteParameter(0xdd); + + WriteCommand(0XD42C); + WriteParameter(0x03); + + WriteCommand(0XD42D); + WriteParameter(0x10); + + WriteCommand(0XD42E); + WriteParameter(0x03); + + WriteCommand(0XD42F); + WriteParameter(0x26); + + WriteCommand(0XD430); + WriteParameter(0x03); + + WriteCommand(0XD431); + WriteParameter(0x32); + + WriteCommand(0XD432); + WriteParameter(0x03); + + WriteCommand(0XD433); + WriteParameter(0x9A); + + //Gamma setting Green + WriteCommand(0XD500); + WriteParameter(0x00); + + WriteCommand(0XD501); + WriteParameter(0xa0); + + WriteCommand(0XD502); + WriteParameter(0x00); + + WriteCommand(0XD503); + WriteParameter(0xa9); + + WriteCommand(0XD504); + WriteParameter(0x00); + + WriteCommand(0XD505); + WriteParameter(0xb5); + + WriteCommand(0XD506); + WriteParameter(0x00); + + WriteCommand(0XD507); + WriteParameter(0xbf); + + WriteCommand(0XD508); + WriteParameter(0x00); + + WriteCommand(0XD509); + WriteParameter(0xc9); + + WriteCommand(0XD50a); + WriteParameter(0x00); + + WriteCommand(0XD50b); + WriteParameter(0xdc); + + WriteCommand(0XD50c); + WriteParameter(0x00); + + WriteCommand(0XD50d); + WriteParameter(0xee); + + WriteCommand(0XD50e); + WriteParameter(0x01); + + WriteCommand(0XD50f); + WriteParameter(0x0a); + + WriteCommand(0XD510); + WriteParameter(0x01); + + WriteCommand(0XD511); + WriteParameter(0x21); + + WriteCommand(0XD512); + WriteParameter(0x01); + + WriteCommand(0XD513); + WriteParameter(0x48); + + WriteCommand(0XD514); + WriteParameter(0x01); + + WriteCommand(0XD515); + WriteParameter(0x67); + + WriteCommand(0XD516); + WriteParameter(0x01); + + WriteCommand(0XD517); + WriteParameter(0x97); + + WriteCommand(0XD518); + WriteParameter(0x01); + + WriteCommand(0XD519); + WriteParameter(0xbe); + + WriteCommand(0XD51a); + WriteParameter(0x01); + + WriteCommand(0XD51b); + WriteParameter(0xc0); + + WriteCommand(0XD51c); + WriteParameter(0x01); + + WriteCommand(0XD51d); + WriteParameter(0xe1); + + WriteCommand(0XD51e); + WriteParameter(0x02); + + WriteCommand(0XD51f); + WriteParameter(0x04); + + WriteCommand(0XD520); + WriteParameter(0x02); + + WriteCommand(0XD521); + WriteParameter(0x17); + + WriteCommand(0XD522); + WriteParameter(0x02); + + WriteCommand(0XD523); + WriteParameter(0x36); + + WriteCommand(0XD524); + WriteParameter(0x02); + + WriteCommand(0XD525); + WriteParameter(0x50); + + WriteCommand(0XD526); + WriteParameter(0x02); + + WriteCommand(0XD527); + WriteParameter(0x7e); + + WriteCommand(0XD528); + WriteParameter(0x02); + + WriteCommand(0XD529); + WriteParameter(0xac); + + WriteCommand(0XD52a); + WriteParameter(0x02); + + WriteCommand(0XD52b); + WriteParameter(0xf1); + + WriteCommand(0XD52C); + WriteParameter(0x03); + + WriteCommand(0XD52D); + WriteParameter(0x20); + + WriteCommand(0XD52E); + WriteParameter(0x03); + + WriteCommand(0XD52F); + WriteParameter(0x38); + + WriteCommand(0XD530); + WriteParameter(0x03); + + WriteCommand(0XD531); + WriteParameter(0x43); + + WriteCommand(0XD532); + WriteParameter(0x03); + + WriteCommand(0XD533); + WriteParameter(0x9A); + + //Gamma setting Blue + WriteCommand(0XD600); + WriteParameter(0x00); + + WriteCommand(0XD601); + WriteParameter(0x50); + + WriteCommand(0XD602); + WriteParameter(0x00); + + WriteCommand(0XD603); + WriteParameter(0x53); + + WriteCommand(0XD604); + WriteParameter(0x00); + + WriteCommand(0XD605); + WriteParameter(0x73); + + WriteCommand(0XD606); + WriteParameter(0x00); + + WriteCommand(0XD607); + WriteParameter(0x89); + + WriteCommand(0XD608); + WriteParameter(0x00); + + WriteCommand(0XD609); + WriteParameter(0x9f); + + WriteCommand(0XD60a); + WriteParameter(0x00); + + WriteCommand(0XD60b); + WriteParameter(0xc1); + + WriteCommand(0XD60c); + WriteParameter(0x00); + + WriteCommand(0XD60d); + WriteParameter(0xda); + + WriteCommand(0XD60e); + WriteParameter(0x01); + + WriteCommand(0XD60f); + WriteParameter(0x02); + + WriteCommand(0XD610); + WriteParameter(0x01); + + WriteCommand(0XD611); + WriteParameter(0x23); + + WriteCommand(0XD612); + WriteParameter(0x01); + + WriteCommand(0XD613); + WriteParameter(0x50); + + WriteCommand(0XD614); + WriteParameter(0x01); + + WriteCommand(0XD615); + WriteParameter(0x6f); + + WriteCommand(0XD616); + WriteParameter(0x01); + + WriteCommand(0XD617); + WriteParameter(0x9f); + + WriteCommand(0XD618); + WriteParameter(0x01); + + WriteCommand(0XD619); + WriteParameter(0xc5); + + WriteCommand(0XD61a); + WriteParameter(0x01); + + WriteCommand(0XD61b); + WriteParameter(0xc6); + + WriteCommand(0XD61c); + WriteParameter(0x01); + + WriteCommand(0XD61d); + WriteParameter(0xe3); + + WriteCommand(0XD61e); + WriteParameter(0x02); + + WriteCommand(0XD61f); + WriteParameter(0x08); + + WriteCommand(0XD620); + WriteParameter(0x02); + + WriteCommand(0XD621); + WriteParameter(0x16); + + WriteCommand(0XD622); + WriteParameter(0x02); + + WriteCommand(0XD623); + WriteParameter(0x2b); + + WriteCommand(0XD624); + WriteParameter(0x02); + + WriteCommand(0XD625); + WriteParameter(0x4d); + + WriteCommand(0XD626); + WriteParameter(0x02); + + WriteCommand(0XD627); + WriteParameter(0x6f); + + WriteCommand(0XD628); + WriteParameter(0x02); + + WriteCommand(0XD629); + WriteParameter(0x8c); + + WriteCommand(0XD62a); + WriteParameter(0x02); + + WriteCommand(0XD62b); + WriteParameter(0xd6); + + WriteCommand(0XD62C); + WriteParameter(0x03); + + WriteCommand(0XD62D); + WriteParameter(0x12); + + WriteCommand(0XD62E); + WriteParameter(0x03); + + WriteCommand(0XD62F); + WriteParameter(0x28); + + WriteCommand(0XD630); + WriteParameter(0x03); + + WriteCommand(0XD631); + WriteParameter(0x3e); + + WriteCommand(0XD632); + WriteParameter(0x03); + + WriteCommand(0XD633); + WriteParameter(0x9A); + + WriteCommand(0XBA00); + WriteParameter(0x14); + + WriteCommand(0XBA01); + WriteParameter(0x14); + + WriteCommand(0XBA02); + WriteParameter(0x14); + + WriteCommand(0XBF00); + WriteParameter(0x01); + + WriteCommand(0XB300); + WriteParameter(0x07); + + WriteCommand(0XB301); + WriteParameter(0x07); + + WriteCommand(0XB302); + WriteParameter(0x07); + + WriteCommand(0XB900); + WriteParameter(0x25); + + WriteCommand(0XB901); + WriteParameter(0x25); + + WriteCommand(0XB902); + WriteParameter(0x25); + + + + WriteCommand(0XBC01); + WriteParameter(0xA0); + + WriteCommand(0XBC02); + WriteParameter(0x00); + + WriteCommand(0XBD01); + WriteParameter(0xA0); + + WriteCommand(0XBD02); + WriteParameter(0x00); + + + WriteCommand(0XF000); + WriteParameter(0x55); + + WriteCommand(0XF001); + WriteParameter(0xAA); + + WriteCommand(0XF002); + WriteParameter(0x52); + + WriteCommand(0XF003); + WriteParameter(0x08); + + WriteCommand(0XF004); + WriteParameter(0x00); + + WriteCommand(0XB100); + WriteParameter(0xCC); + + WriteCommand(0XBC00); + WriteParameter(0x05); + + WriteCommand(0XBC01); + WriteParameter(0x05); + + WriteCommand(0XBC02); + WriteParameter(0x05); + + + WriteCommand(0XBD02); + WriteParameter(0x07); + WriteCommand(0XBD03); + WriteParameter(0x31); + + WriteCommand(0XBE02); + WriteParameter(0x07); + WriteCommand(0XBE03); + WriteParameter(0x31); + + WriteCommand(0XBF02); + WriteParameter(0x07); + WriteCommand(0XBF03); + WriteParameter(0x31); +/* + WriteCommand(0XFF00); + WriteParameter(0xAA); + WriteCommand(0XFF01); + WriteParameter(0x55); + WriteCommand(0XFF02); + WriteParameter(0x25); + WriteCommand(0XFF03); + WriteParameter(0x01); +*/ +/*****************************************************************/ + WriteCommand(0XF000);WriteParameter(0x55);//ENABLE High Mode + WriteCommand(0XF001);WriteParameter(0xAA); + WriteCommand(0XF002);WriteParameter(0x52); + WriteCommand(0XF003);WriteParameter(0x08); + WriteCommand(0XF004);WriteParameter(0x00); + + WriteCommand(0XB400);WriteParameter(0x10); + + WriteCommand(0XFF00);WriteParameter(0xAA);//ENABLE LV3 + WriteCommand(0XFF01);WriteParameter(0x55); + WriteCommand(0XFF02);WriteParameter(0x25); + WriteCommand(0XFF03);WriteParameter(0x01); + + WriteCommand(0XF900);WriteParameter(0x14);//ÖеÈÔöÑÞÏÔʾЧ¹û + WriteCommand(0XF901);WriteParameter(0x00); + WriteCommand(0XF902);WriteParameter(0x0A); + WriteCommand(0XF903);WriteParameter(0x11); + WriteCommand(0XF904);WriteParameter(0x17); + WriteCommand(0XF905);WriteParameter(0x1D); + WriteCommand(0XF906);WriteParameter(0x24); + WriteCommand(0XF907);WriteParameter(0x2A); + WriteCommand(0XF908);WriteParameter(0x31); + WriteCommand(0XF909);WriteParameter(0x37); + WriteCommand(0XF90A);WriteParameter(0x3D); +/* + WriteCommand(0XF900);WriteParameter(0x14);//¸ßµÈÔöÑÞÏÔʾЧ¹û + WriteCommand(0XF901);WriteParameter(0x00); + WriteCommand(0XF902);WriteParameter(0x0D); + WriteCommand(0XF903);WriteParameter(0x1A); + WriteCommand(0XF904);WriteParameter(0x26); + WriteCommand(0XF905);WriteParameter(0x33); + WriteCommand(0XF906);WriteParameter(0x40); + WriteCommand(0XF907);WriteParameter(0x4D); + WriteCommand(0XF908);WriteParameter(0x5A); + WriteCommand(0XF909);WriteParameter(0x66); + WriteCommand(0XF90A);WriteParameter(0x73); +*/ +/******************************************************************/ + WriteCommand(0X3500); + WriteParameter(0x00); + + WriteCommand(0X3a00); + +if(OUT_FACE == OUT_P888) + WriteParameter(0x70); //24bit +else if(OUT_FACE == OUT_P666) + WriteParameter(0x60);//18bit + + WriteCommand(0X3600); + WriteParameter(0x00);//R<->B + + WriteCommand(0X2000); // + + WriteCommand(0X1100); + usleep_range(120*1000, 120*1000); + + WriteCommand(0X2900); + + usleep_range(100*1000, 100*1000); + WriteCommand(0X2C00); +} + + +void resume_nt35510(void) +{ + WriteCommand(0X1100); + msleep(120); + + WriteCommand(0X1300); + + WriteCommand(0XF000); + WriteParameter(0x55); + + WriteCommand(0XF001); + WriteParameter(0xAA); + + WriteCommand(0XF002); + WriteParameter(0x52); + + WriteCommand(0XF003); + WriteParameter(0x08); + + WriteCommand(0XF004); + WriteParameter(0x01); + + + /**************/ + WriteCommand(0XBA00); + WriteParameter(0x14); + + WriteCommand(0XBA01); + WriteParameter(0x14); + + WriteCommand(0XBA02); + WriteParameter(0x14); + + WriteCommand(0XBF00); + WriteParameter(0x01); + + WriteCommand(0XB300); + WriteParameter(0x07); + + WriteCommand(0XB301); + WriteParameter(0x07); + + WriteCommand(0XB302); + WriteParameter(0x07); + + WriteCommand(0XB900); + WriteParameter(0x25); + + WriteCommand(0XB901); + WriteParameter(0x25); + + WriteCommand(0XB902); + WriteParameter(0x25); + + + + WriteCommand(0XBC01); + WriteParameter(0xA0); + + WriteCommand(0XBC02); + WriteParameter(0x00); + + WriteCommand(0XBD01); + WriteParameter(0xA0); + + WriteCommand(0XBD02); + WriteParameter(0x00); + + + WriteCommand(0XF000); + WriteParameter(0x55); + + WriteCommand(0XF001); + WriteParameter(0xAA); + + WriteCommand(0XF002); + WriteParameter(0x52); + + WriteCommand(0XF003); + WriteParameter(0x08); + + WriteCommand(0XF004); + WriteParameter(0x00); + + WriteCommand(0XB100); + WriteParameter(0xCC); + + WriteCommand(0XBC00); + WriteParameter(0x05); + + WriteCommand(0XBC01); + WriteParameter(0x05); + + WriteCommand(0XBC02); + WriteParameter(0x05); + + + WriteCommand(0XBD02); + WriteParameter(0x07); + WriteCommand(0XBD03); + WriteParameter(0x31); + + WriteCommand(0XBE02); + WriteParameter(0x07); + WriteCommand(0XBE03); + WriteParameter(0x31); + + WriteCommand(0XBF02); + WriteParameter(0x07); + WriteCommand(0XBF03); + WriteParameter(0x31); + + WriteCommand(0XFF00); + WriteParameter(0xAA); + WriteCommand(0XFF01); + WriteParameter(0x55); + WriteCommand(0XFF02); + WriteParameter(0x25); + WriteCommand(0XFF03); + WriteParameter(0x01); + + + WriteCommand(0X3500); + WriteParameter(0x00); + + WriteCommand(0X3a00); + +if(OUT_FACE == OUT_P888) + WriteParameter(0x70); //24bit +else if(OUT_FACE == OUT_P666) + WriteParameter(0x60);//18bit + + WriteCommand(0X3600); + WriteParameter(0x00);//R<->B + + WriteCommand(0X2000); // + + WriteCommand(0X1100); + msleep(120); + + WriteCommand(0X2900); + + msleep(100); + WriteCommand(0X2C00); +} + +static DEFINE_MUTEX(lcd_mutex); +extern void rk29_lcd_spim_spin_lock(void); +extern void rk29_lcd_spim_spin_unlock(void); + +static void lcd_resume(struct work_struct *work) +{ + mutex_lock(&lcd_mutex); + rk29_lcd_spim_spin_lock(); + if(gLcd_info) + gLcd_info->io_init(); + init_nt35510(); + //resume_nt35510();//may be fail to wake up LCD some time,so change to init lcd again + printk(KERN_DEBUG "%s\n",__FUNCTION__); + + if(gLcd_info) + gLcd_info->io_deinit(); + + rk29_lcd_spim_spin_unlock(); + mutex_unlock(&lcd_mutex); +} + +static DECLARE_WORK(lcd_resume_work, lcd_resume); +static struct workqueue_struct *lcd_resume_wq; + +static void lcd_late_resume(struct early_suspend *h) +{ + queue_work(lcd_resume_wq, &lcd_resume_work); +} + +static struct early_suspend lcd_early_suspend_desc = { + .level = EARLY_SUSPEND_LEVEL_DISABLE_FB + 1, // before fb resume + .resume = lcd_late_resume, +}; + +int rk_lcd_init(void) +{ + volatile u32 data; + printk("lcd init...\n"); + if(gLcd_info) + gLcd_info->io_init(); + init_nt35510(); + + if(gLcd_info) + gLcd_info->io_deinit(); + + lcd_resume_wq = create_singlethread_workqueue("lcd"); + register_early_suspend(&lcd_early_suspend_desc); + return 0; +} + +int rk_lcd_standby(u8 enable) //***enable =1 means suspend, 0 means resume +{ + if (enable) { + mutex_lock(&lcd_mutex); + rk29_lcd_spim_spin_lock(); + if(gLcd_info) + gLcd_info->io_init(); + + WriteCommand(0X2800); + WriteCommand(0X1100); + msleep(5); + WriteCommand(0X4f00); + WriteParameter(0x01); + if(gLcd_info) + gLcd_info->io_deinit(); + + rk29_lcd_spim_spin_unlock(); + mutex_unlock(&lcd_mutex); + } else { + flush_workqueue(lcd_resume_wq); + } + return 0; +} + +#endif diff --git a/drivers/video/rockchip/screen/lcd_nt35580.c b/drivers/video/rockchip/screen/lcd_nt35580.c new file mode 100644 index 000000000000..8fb8b8350f36 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_nt35580.c @@ -0,0 +1,472 @@ +#include +#include +#include "../../rk29_fb.h" +#include +#include +#include +#include "screen.h" + + +/* Base */ +#define OUT_TYPE SCREEN_RGB +#define OUT_FACE OUT_P888 +#define OUT_CLK 24000000 +#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 1 +#define H_BP 1 +#define H_VD 480 +#define H_FP 2 + +#define V_PW 1 +#define V_BP 4 +#define V_VD 800 +#define V_FP 2 + +#define LCD_WIDTH 480 //need modify +#define LCD_HEIGHT 800 + +/* Other */ +#define DCLK_POL 0 +#define SWAP_RB 0 + +#define TXD_PORT gLcd_info->txd_pin +#define CLK_PORT gLcd_info->clk_pin +#define CS_PORT gLcd_info->cs_pin + +#define CS_OUT() gpio_direction_output(CS_PORT, 0) +#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) +#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) +#define CLK_OUT() gpio_direction_output(CLK_PORT, 0) +#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) +#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) +#define TXD_OUT() gpio_direction_output(TXD_PORT, 0) +#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) +#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) +#define TXD_IN() gpio_direction_input(TXD_PORT) +#define TXD_GET() gpio_get_value(TXD_PORT) + + +#define delay_us(i) udelay(i) +static struct rk29lcd_info *gLcd_info = NULL; + +u32 spi_screenreg_get(u32 Addr) +{ + u32 i; + u8 addr_h = (Addr>>8) & 0x000000ff; + u8 addr_l = Addr & 0x000000ff; + u8 cmd1 = 0x20; //0010 0000 + u8 cmd2 = 0x00; //0000 0000 + u8 cmd3 = 0x00; //0000 0000 + + u8 data_l = 0; + u8 tmp; + + TXD_OUT(); + CLK_OUT(); + CS_OUT(); + delay_us(8); + + CS_SET(); + CLK_CLR(); + TXD_CLR(); + delay_us(4); + + // first transmit + CS_CLR(); + delay_us(4); + for(i = 0; i < 8; i++) + { + if(cmd1 &(1<<(7-i))) + TXD_SET(); + else + TXD_CLR(); + + CLK_CLR(); + delay_us(4); + CLK_SET(); + delay_us(4); + } + for(i = 0; i < 8; i++) + { + if(addr_h &(1<<(7-i))) + TXD_SET(); + else + TXD_CLR(); + + CLK_CLR(); + delay_us(4); + CLK_SET(); + delay_us(4); + } + CLK_CLR(); + TXD_CLR(); + delay_us(4); + CS_SET(); + delay_us(8); + + // second transmit + CS_CLR(); + delay_us(4); + for(i = 0; i < 8; i++) + { + if(cmd2 &(1<<(7-i))) + TXD_SET(); + else + TXD_CLR(); + + CLK_CLR(); + delay_us(4); + CLK_SET(); + delay_us(4); + } + for(i = 0; i < 8; i++) + { + if(addr_l &(1<<(7-i))) + TXD_SET(); + else + TXD_CLR(); + + CLK_CLR(); + delay_us(4); + CLK_SET(); + delay_us(4); + } + CLK_CLR(); + TXD_CLR(); + delay_us(4); + CS_SET(); + delay_us(8); + + // third transmit + CS_CLR(); + delay_us(4); + for(i = 0; i < 8; i++) + { + if(cmd3 &(1<<(7-i))) + TXD_SET(); + else + TXD_CLR(); + + CLK_CLR(); + delay_us(4); + CLK_SET(); + delay_us(4); + } + TXD_CLR(); + TXD_IN(); + for(i = 0; i < 8; i++) + { + CLK_CLR(); + delay_us(4); + CLK_SET(); + + tmp = TXD_GET(); + data_l += (tmp<<(7-i)); + + delay_us(4); + } + CLK_CLR(); + TXD_CLR(); + delay_us(4); + CS_SET(); + delay_us(8); + + return data_l; +} + + +void spi_screenreg_set(u32 Addr, u32 Data) +{ + u32 i; + u8 addr_h = (Addr>>8) & 0x000000ff; + u8 addr_l = Addr & 0x000000ff; + u8 data_l = Data & 0x000000ff; + u8 cmd1 = 0x20; //0010 0000 + u8 cmd2 = 0x00; //0000 0000 + u8 cmd3 = 0x40; //0100 0000 + + TXD_OUT(); + CLK_OUT(); + CS_OUT(); + delay_us(8); + + CS_SET(); + CLK_CLR(); + TXD_CLR(); + delay_us(4); + + // first transmit + CS_CLR(); + delay_us(4); + for(i = 0; i < 8; i++) + { + if(cmd1 &(1<<(7-i))) + TXD_SET(); + else + TXD_CLR(); + + CLK_CLR(); + delay_us(4); + CLK_SET(); + delay_us(4); + } + for(i = 0; i < 8; i++) + { + if(addr_h &(1<<(7-i))) + TXD_SET(); + else + TXD_CLR(); + + CLK_CLR(); + delay_us(4); + CLK_SET(); + delay_us(4); + } + CLK_CLR(); + TXD_CLR(); + delay_us(4); + CS_SET(); + delay_us(8); + + // second transmit + CS_CLR(); + delay_us(4); + for(i = 0; i < 8; i++) + { + if(cmd2 &(1<<(7-i))) + TXD_SET(); + else + TXD_CLR(); + + CLK_CLR(); + delay_us(4); + CLK_SET(); + delay_us(4); + } + for(i = 0; i < 8; i++) + { + if(addr_l &(1<<(7-i))) + TXD_SET(); + else + TXD_CLR(); + + CLK_CLR(); + delay_us(4); + CLK_SET(); + delay_us(4); + } + CLK_CLR(); + TXD_CLR(); + delay_us(4); + CS_SET(); + delay_us(8); + + // third transmit + CS_CLR(); + delay_us(4); + for(i = 0; i < 8; i++) + { + if(cmd3 &(1<<(7-i))) + TXD_SET(); + else + TXD_CLR(); + + CLK_CLR(); + delay_us(4); + CLK_SET(); + delay_us(4); + } + for(i = 0; i < 8; i++) + { + if(data_l &(1<<(7-i))) + TXD_SET(); + else + TXD_CLR(); + + CLK_CLR(); + delay_us(4); + CLK_SET(); + delay_us(4); + } + CLK_CLR(); + TXD_CLR(); + delay_us(4); + CS_SET(); + delay_us(8); + + //printk("Addr=0x%04x, WData=0x%02x, RData=0x%02x \n", Addr, Data, spi_screenreg_get(Addr)); + +} + + + + + +int lcd_init(void) +{ + +#if 0 + GPIO_SetPinDirection(reset_pin, GPIO_OUT); + GPIO_SetPinLevel(reset_pin,GPIO_HIGH); + DelayMs_nops(100); + GPIO_SetPinLevel(reset_pin,GPIO_LOW); + DelayMs_nops(100); + GPIO_SetPinLevel(reset_pin,GPIO_HIGH); +#endif + + if(gLcd_info) + gLcd_info->io_init(); + + spi_screenreg_set(0x2E80, 0x0001); + spi_screenreg_set(0x0680, 0x002D); + spi_screenreg_set(0xD380, 0x0004); + spi_screenreg_set(0xD480, 0x0060); + spi_screenreg_set(0xD580, 0x0007); + spi_screenreg_set(0xD680, 0x005A); + spi_screenreg_set(0xD080, 0x000F); + spi_screenreg_set(0xD180, 0x0016); + spi_screenreg_set(0xD280, 0x0004); + spi_screenreg_set(0xDC80, 0x0004); + spi_screenreg_set(0xD780, 0x0001); + + spi_screenreg_set(0x2280, 0x000F); + spi_screenreg_set(0x2480, 0x0068); + spi_screenreg_set(0x2580, 0x0000); + spi_screenreg_set(0x2780, 0x00AF); + + spi_screenreg_set(0x3A00, 0x0060); + spi_screenreg_set(0x3B00, 0x0003); + spi_screenreg_set(0x3B02, 0x0005); + spi_screenreg_set(0x3B03, 0x0002); + spi_screenreg_set(0x3B04, 0x0002); + spi_screenreg_set(0x3B05, 0x0002); + + spi_screenreg_set(0x0180, 0x0000); + spi_screenreg_set(0x4080, 0x0051); + spi_screenreg_set(0x4180, 0x0055); + spi_screenreg_set(0x4280, 0x0058); + spi_screenreg_set(0x4380, 0x0064); + spi_screenreg_set(0x4480, 0x001A); + spi_screenreg_set(0x4580, 0x002E); + spi_screenreg_set(0x4680, 0x005F); + spi_screenreg_set(0x4780, 0x0021); + spi_screenreg_set(0x4880, 0x001C); + spi_screenreg_set(0x4980, 0x0022); + spi_screenreg_set(0x4A80, 0x005D); + spi_screenreg_set(0x4B80, 0x0019); + spi_screenreg_set(0x4C80, 0x0046); + spi_screenreg_set(0x4D80, 0x0062); + spi_screenreg_set(0x4E80, 0x0048); + spi_screenreg_set(0x4F80, 0x005B); + + spi_screenreg_set(0x5080, 0x002F); + spi_screenreg_set(0x5180, 0x005E); + spi_screenreg_set(0x5880, 0x002E); + spi_screenreg_set(0x5980, 0x003B); + spi_screenreg_set(0x5A80, 0x008D); + spi_screenreg_set(0x5B80, 0x00A7); + spi_screenreg_set(0x5C80, 0x0027); + spi_screenreg_set(0x5D80, 0x0039); + spi_screenreg_set(0x5E80, 0x0065); + spi_screenreg_set(0x5F80, 0x0055); + + spi_screenreg_set(0x6080, 0x001A); + spi_screenreg_set(0x6180, 0x0021); + spi_screenreg_set(0x6280, 0x008F); + spi_screenreg_set(0x6380, 0x0022); + spi_screenreg_set(0x6480, 0x0053); + spi_screenreg_set(0x6580, 0x0066); + spi_screenreg_set(0x6680, 0x008A); + spi_screenreg_set(0x6780, 0x0097); + spi_screenreg_set(0x6880, 0x001F); + spi_screenreg_set(0x6980, 0x0026); + + spi_screenreg_set(0x1100, 0x0000); + msleep(150); + spi_screenreg_set(0x2900, 0x0000); + +#if 0 + printk("spi_screenreg_set(0x5555, 0x0055)... \n"); + while(1) { + spi_screenreg_set(0x5555, 0x0055); + msleep(1); + } +#endif + +#if 0 + while(1) { + int i = 0; + for(i=0; i<400*480; i++) + mcu_ioctl(MCU_WRDATA, 0xffffffff); + for(i=0; i<400*480; i++) + mcu_ioctl(MCU_WRDATA, 0x00000000); + msleep(1000); + printk(">>>>> MCU_WRDATA ...\n"); + + for(i=0; i<400*480; i++) + mcu_ioctl(MCU_WRDATA, 0x00000000); + for(i=0; i<400*480; i++) + mcu_ioctl(MCU_WRDATA, 0xffffffff); + msleep(1000); + printk(">>>>> MCU_WRDATA ...\n"); + } +#endif + + if(gLcd_info) + gLcd_info->io_deinit(); + return 0; +} + + +int lcd_standby(u8 enable) +{ + return 0; +} + + +void set_lcd_info(struct rk29fb_screen *screen, struct rk2918lcd_info *lcd_info ) +{ + /* screen type & face */ + screen->type = OUT_TYPE; + screen->face = OUT_FACE; + + /* Screen size */ + screen->x_res = H_VD; + screen->y_res = V_VD; + + screen->width = LCD_WIDTH; + screen->height = LCD_HEIGHT; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK; + screen->pixclock = OUT_CLK; + screen->left_margin = H_BP; + screen->right_margin = H_FP; + screen->hsync_len = H_PW; + screen->upper_margin = V_BP; + screen->lower_margin = V_FP; + screen->vsync_len = V_PW; + + /* Pin polarity */ + screen->pin_hsync = 0; + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = DCLK_POL; + + /* Swap rule */ + screen->swap_rb = SWAP_RB; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = lcd_init; + screen->standby = lcd_standby; + if(lcd_info) + gLcd_info = lcd_info; +} + + diff --git a/drivers/video/rockchip/screen/lcd_nt35582.c b/drivers/video/rockchip/screen/lcd_nt35582.c new file mode 100644 index 000000000000..8835a2187a65 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_nt35582.c @@ -0,0 +1,436 @@ +#include +#include +#include "../../rk29_fb.h" +#include +#include +#include "screen.h" + +/* Base */ +#define OUT_TYPE SCREEN_MCU +#define OUT_FACE OUT_P888 + +/* Timing */ +#define H_PW 1 +#define H_BP 1 +#define H_VD 480 +#define H_FP 5 + +#define V_PW 1 +#define V_BP 1 +#define V_VD 800 +#define V_FP 1 + +#define LCD_WIDTH 480 //need modify +#define LCD_HEIGHT 800 + +#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ + +#define P_WR 27 +#define USE_FMARK 0 //2 //ÊÇ·ñʹÓÃFMK (0:²»Ö§³Ö 1:ºáÆÁÖ§³Ö 2:ºáÊúÆÁ¶¼Ö§³Ö) +#define FRMRATE 60 //MCUÆÁµÄË¢ÐÂÂÊ (FMKÓÐЧʱÓÃ) + + +/* Other */ +#define DCLK_POL 0 +#define SWAP_RB 0 + +void Set_LCD_8B_REG(unsigned char regh,unsigned char regl, u32 data) +{ + u32 cmd; + cmd = (regh<<8) + regl; + if(-1==data) { + mcu_ioctl(MCU_WRCMD,cmd); + } else { + mcu_ioctl(MCU_WRCMD,cmd); + mcu_ioctl(MCU_WRDATA,data); + } +} + +int lcd_init(void) +{ + int i = 0; + +#if 0 + GPIO_SetPinDirection(reset_pin, GPIO_OUT); + GPIO_SetPinLevel(reset_pin,GPIO_HIGH); + DelayMs_nops(100); + GPIO_SetPinLevel(reset_pin,GPIO_LOW); + DelayMs_nops(100); + GPIO_SetPinLevel(reset_pin,GPIO_HIGH); +#endif + + mcu_ioctl(MCU_SETBYPASS, 1); + + + + Set_LCD_8B_REG(0xC0,0X00,0x86); + + Set_LCD_8B_REG(0xC0,0X01,0x00); + Set_LCD_8B_REG(0xC0,0X02,0x86); + Set_LCD_8B_REG(0xC0,0X03,0x00); + + Set_LCD_8B_REG(0xC1,0X00,0x60); //0x004f + Set_LCD_8B_REG(0xC2,0X00,0x21); + Set_LCD_8B_REG(0xC2,0X02,0x70); //0x0202 + + Set_LCD_8B_REG(0xB6,0x00,0x10); //0x0030 + Set_LCD_8B_REG(0xB6,0x02,0x30); + + Set_LCD_8B_REG(0xC7,0X00,0x6F); + + Set_LCD_8B_REG(0xE0,0X00,0X0E); + Set_LCD_8B_REG(0xE0,0X01,0X14); + Set_LCD_8B_REG(0xE0,0X02,0X29); + Set_LCD_8B_REG(0xE0,0X03,0X3A); + Set_LCD_8B_REG(0xE0,0X04,0X1D); + Set_LCD_8B_REG(0xE0,0X05,0X30); + Set_LCD_8B_REG(0xE0,0X06,0X61); + Set_LCD_8B_REG(0xE0,0X07,0X3D); + Set_LCD_8B_REG(0xE0,0X08,0X22); + Set_LCD_8B_REG(0xE0,0X09,0X2A); + Set_LCD_8B_REG(0xE0,0X0A,0X87); + Set_LCD_8B_REG(0xE0,0X0B,0X16); + Set_LCD_8B_REG(0xE0,0X0C,0X3B); + Set_LCD_8B_REG(0xE0,0X0D,0X4C); + Set_LCD_8B_REG(0xE0,0X0E,0X78); + Set_LCD_8B_REG(0xE0,0X0F,0X96); + Set_LCD_8B_REG(0xE0,0X10,0X4A); + Set_LCD_8B_REG(0xE0,0X11,0X4D); + + Set_LCD_8B_REG(0xE1,0X00,0X0E); + Set_LCD_8B_REG(0xE1,0X01,0X14); + Set_LCD_8B_REG(0xE1,0X02,0X29); + Set_LCD_8B_REG(0xE1,0X03,0X3A); + Set_LCD_8B_REG(0xE1,0X04,0X1D); + Set_LCD_8B_REG(0xE1,0X05,0X30); + Set_LCD_8B_REG(0xE1,0X06,0X61); + Set_LCD_8B_REG(0xE1,0X07,0X3F); + Set_LCD_8B_REG(0xE1,0X08,0X20); + Set_LCD_8B_REG(0xE1,0X09,0X26); + Set_LCD_8B_REG(0xE1,0X0A,0X83); + Set_LCD_8B_REG(0xE1,0X0B,0X16); + Set_LCD_8B_REG(0xE1,0X0C,0X3B); + Set_LCD_8B_REG(0xE1,0X0D,0X4C); + Set_LCD_8B_REG(0xE1,0X0E,0X78); + Set_LCD_8B_REG(0xE1,0X0F,0X96); + Set_LCD_8B_REG(0xE1,0X10,0X4A); + Set_LCD_8B_REG(0xE1,0X11,0X4D); + + Set_LCD_8B_REG(0xE2,0X00,0X0E); + Set_LCD_8B_REG(0xE2,0X01,0X14); + Set_LCD_8B_REG(0xE2,0X02,0X29); + Set_LCD_8B_REG(0xE2,0X03,0X3A); + Set_LCD_8B_REG(0xE2,0X04,0X1D); + Set_LCD_8B_REG(0xE2,0X05,0X30); + Set_LCD_8B_REG(0xE2,0X06,0X61); + Set_LCD_8B_REG(0xE2,0X07,0X3D); + Set_LCD_8B_REG(0xE2,0X08,0X22); + Set_LCD_8B_REG(0xE2,0X09,0X2A); + Set_LCD_8B_REG(0xE2,0X0A,0X87); + Set_LCD_8B_REG(0xE2,0X0B,0X16); + Set_LCD_8B_REG(0xE2,0X0C,0X3B); + Set_LCD_8B_REG(0xE2,0X0D,0X4C); + Set_LCD_8B_REG(0xE2,0X0E,0X78); + Set_LCD_8B_REG(0xE2,0X0F,0X96); + Set_LCD_8B_REG(0xE2,0X10,0X4A); + Set_LCD_8B_REG(0xE2,0X11,0X4D); + + Set_LCD_8B_REG(0xE3,0X00,0X0E); + Set_LCD_8B_REG(0xE3,0X01,0X14); + Set_LCD_8B_REG(0xE3,0X02,0X29); + Set_LCD_8B_REG(0xE3,0X03,0X3A); + Set_LCD_8B_REG(0xE3,0X04,0X1D); + Set_LCD_8B_REG(0xE3,0X05,0X30); + Set_LCD_8B_REG(0xE3,0X06,0X61); + Set_LCD_8B_REG(0xE3,0X07,0X3F); + Set_LCD_8B_REG(0xE3,0X08,0X20); + Set_LCD_8B_REG(0xE3,0X09,0X26); + Set_LCD_8B_REG(0xE3,0X0A,0X83); + Set_LCD_8B_REG(0xE3,0X0B,0X16); + Set_LCD_8B_REG(0xE3,0X0C,0X3B); + Set_LCD_8B_REG(0xE3,0X0D,0X4C); + Set_LCD_8B_REG(0xE3,0X0E,0X78); + Set_LCD_8B_REG(0xE3,0X0F,0X96); + Set_LCD_8B_REG(0xE3,0X10,0X4A); + Set_LCD_8B_REG(0xE3,0X11,0X4D); + + Set_LCD_8B_REG(0xE4,0X00,0X0E); + Set_LCD_8B_REG(0xE4,0X01,0X14); + Set_LCD_8B_REG(0xE4,0X02,0X29); + Set_LCD_8B_REG(0xE4,0X03,0X3A); + Set_LCD_8B_REG(0xE4,0X04,0X1D); + Set_LCD_8B_REG(0xE4,0X05,0X30); + Set_LCD_8B_REG(0xE4,0X06,0X61); + Set_LCD_8B_REG(0xE4,0X07,0X3D); + Set_LCD_8B_REG(0xE4,0X08,0X22); + Set_LCD_8B_REG(0xE4,0X09,0X2A); + Set_LCD_8B_REG(0xE4,0X0A,0X87); + Set_LCD_8B_REG(0xE4,0X0B,0X16); + Set_LCD_8B_REG(0xE4,0X0C,0X3B); + Set_LCD_8B_REG(0xE4,0X0D,0X4C); + Set_LCD_8B_REG(0xE4,0X0E,0X78); + Set_LCD_8B_REG(0xE4,0X0F,0X96); + Set_LCD_8B_REG(0xE4,0X10,0X4A); + Set_LCD_8B_REG(0xE4,0X11,0X4D); + + Set_LCD_8B_REG(0xE5,0X00,0X0E); + Set_LCD_8B_REG(0xE5,0X01,0X14); + Set_LCD_8B_REG(0xE5,0X02,0X29); + Set_LCD_8B_REG(0xE5,0X03,0X3A); + Set_LCD_8B_REG(0xE5,0X04,0X1D); + Set_LCD_8B_REG(0xE5,0X05,0X30); + Set_LCD_8B_REG(0xE5,0X06,0X61); + Set_LCD_8B_REG(0xE5,0X07,0X3F); + Set_LCD_8B_REG(0xE5,0X08,0X20); + Set_LCD_8B_REG(0xE5,0X09,0X26); + Set_LCD_8B_REG(0xE5,0X0A,0X83); + Set_LCD_8B_REG(0xE5,0X0B,0X16); + Set_LCD_8B_REG(0xE5,0X0C,0X3B); + Set_LCD_8B_REG(0xE5,0X0D,0X4C); + Set_LCD_8B_REG(0xE5,0X0E,0X78); + Set_LCD_8B_REG(0xE5,0X0F,0X96); + Set_LCD_8B_REG(0xE5,0X10,0X4A); + Set_LCD_8B_REG(0xE5,0X11,0X4D); + + Set_LCD_8B_REG(0x36,0X01,0X01); + + Set_LCD_8B_REG(0x11,0X00,0X00); + msleep(100); + Set_LCD_8B_REG(0x29,0X00,0X00); + msleep(100); + + + Set_LCD_8B_REG(0x2a,0X00,0X00); + Set_LCD_8B_REG(0x2a,0X01,0X00); + Set_LCD_8B_REG(0x2a,0X02,0X01); + Set_LCD_8B_REG(0x2a,0X03,0Xdf); + msleep(100); + Set_LCD_8B_REG(0x2b,0X00,0X00); + Set_LCD_8B_REG(0x2b,0X01,0X00); + Set_LCD_8B_REG(0x2b,0X02,0X03); + Set_LCD_8B_REG(0x2b,0X03,0X1f); + msleep(100); + { + u32 fte = 0; + Set_LCD_8B_REG(0x44,0x00,(fte>>8)&0xff); + Set_LCD_8B_REG(0x44,0x01,(fte)&0xff); + } + Set_LCD_8B_REG(0x0E,0X00,0X80); + Set_LCD_8B_REG(0x35,0X00,0X80); + +#if (480==H_VD) + Set_LCD_8B_REG(0x36,0X00,0x00); +#else + Set_LCD_8B_REG(0x36,0X00,0x22); +#endif + Set_LCD_8B_REG(0x2c,0X00,-1); + + for(i=0; i<480*800; i++) { + mcu_ioctl(MCU_WRDATA, 0x00000000); + } + +#if 0 + // for test + while(1) { + int i = 0; + for(i=0; i<400*480; i++) + mcu_ioctl(MCU_WRDATA, 0xffffffff); + for(i=0; i<400*480; i++) + mcu_ioctl(MCU_WRDATA, 0x00000000); + msleep(1000); + printk(">>>>> MCU_WRDATA ...\n"); + + for(i=0; i<400*480; i++) + mcu_ioctl(MCU_WRDATA, 0x00000000); + for(i=0; i<400*480; i++) + mcu_ioctl(MCU_WRDATA, 0xffffffff); + msleep(1000); + printk(">>>>> MCU_WRDATA ...\n"); + } +#endif + + mcu_ioctl(MCU_SETBYPASS, 0); + return 0; +} + + +int lcd_standby(u8 enable) +{ + mcu_ioctl(MCU_SETBYPASS, 1); + if(enable) { + Set_LCD_8B_REG(0x10,0X00,-1); + } else { + Set_LCD_8B_REG(0x11,0X00,-1); + } + mcu_ioctl(MCU_SETBYPASS, 0); + return 0; +} + + +int lcd_refresh(u8 arg) +{ + switch(arg) + { + case REFRESH_PRE: //DMA´«ËÍÇ°×¼±¸ + mcu_ioctl(MCU_SETBYPASS, 1); + Set_LCD_8B_REG(0x2c,0X00,-1); + mcu_ioctl(MCU_SETBYPASS, 0); + break; + + case REFRESH_END: //DMA´«ËͽáÊøºó + mcu_ioctl(MCU_SETBYPASS, 1); + Set_LCD_8B_REG(0x29,0X00,-1); + mcu_ioctl(MCU_SETBYPASS, 0); + break; + + default: + break; + } + + return 0; +} + + +int lcd_scandir(u16 dir) +{ + mcu_ioctl(MCU_SETBYPASS, 1); + + // ÔÝʱ¹Ø±ÕMCUÏÔʾ,ÔÚlcd_refreshµÄcase REFRESH_ENDÔÙ´ò¿ª + // ·ñÔò»­Ãæ»áÒì³£ + Set_LCD_8B_REG(0x28,0X00,-1); + + Set_LCD_8B_REG(0x2a,0X00,0X00); + Set_LCD_8B_REG(0x2a,0X01,0X00); + Set_LCD_8B_REG(0x2a,0X02,0X01); + Set_LCD_8B_REG(0x2a,0X03,0Xdf); + Set_LCD_8B_REG(0x2b,0X00,0X00); + Set_LCD_8B_REG(0x2b,0X01,0X00); + Set_LCD_8B_REG(0x2b,0X02,0X03); + Set_LCD_8B_REG(0x2b,0X03,0X1f); + + switch(dir) + { + case 0: + Set_LCD_8B_REG(0x36,0X00,0x00); + break; + case 90: + Set_LCD_8B_REG(0x36,0X00,0x22); + break; + case 180: + Set_LCD_8B_REG(0x36,0X00,0x03); + break; + case 270: + Set_LCD_8B_REG(0x36,0X00,0x21); + break; + default: + break; + } + + mcu_ioctl(MCU_SETBYPASS, 0); + return 0; +} + + +int lcd_disparea(u8 area) +{ + u32 x0, y0, x1, y1, fte; + + mcu_ioctl(MCU_SETBYPASS, 1); + + switch(area) + { + case 0: + fte = 0; + x0 = 0; + y0 = 0; + x1 = 399; + y1 = 479; + break; + + case 2: + x0 = 0; + y0 = 0; + x1 = 799; + y1 = 479; + break; + + case 1: + default: + fte = 400; + x0 = 400; + y0 = 0; + x1 = 799; + y1 = 479; + break; + } + + //Set_LCD_8B_REG(0x44,0x00,(fte>>8)&0xff); + //Set_LCD_8B_REG(0x44,0x01,(fte)&0xff); + Set_LCD_8B_REG(0x2a,0X00,(y0>>8)&0xff); + Set_LCD_8B_REG(0x2a,0X01,y0&0xff); + Set_LCD_8B_REG(0x2a,0X02,(y1>>8)&0xff); + Set_LCD_8B_REG(0x2a,0X03,y1&0xff); + + Set_LCD_8B_REG(0x2b,0X00,(x0>>8)&0xff); + Set_LCD_8B_REG(0x2b,0X01,x0&0xff); + Set_LCD_8B_REG(0x2b,0X02,(x1>>8)&0xff); + Set_LCD_8B_REG(0x2b,0X03,x1&0xff); + Set_LCD_8B_REG(0x2c,0X00,-1); + + mcu_ioctl(MCU_SETBYPASS, 0); + + return (0); + +} + +void set_lcd_info(struct rk29fb_screen *screen) +{ + /* screen type & face */ + screen->type = OUT_TYPE; + screen->face = OUT_FACE; + + /* Screen size */ + screen->x_res = H_VD; + screen->y_res = V_VD; + + screen->width = LCD_WIDTH; + screen->height = LCD_HEIGHT; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK; + screen->left_margin = H_BP; + screen->right_margin = H_FP; + screen->hsync_len = H_PW; + screen->upper_margin = V_BP; + screen->lower_margin = V_FP; + screen->vsync_len = V_PW; + + screen->mcu_wrperiod = P_WR; + screen->mcu_usefmk = USE_FMARK; + screen->mcu_frmrate = FRMRATE; + + /* Pin polarity */ + screen->pin_hsync = 0; + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = DCLK_POL; + + /* Swap rule */ + screen->swap_rb = SWAP_RB; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = lcd_init; + screen->standby = lcd_standby; + screen->scandir = lcd_scandir; + screen->refresh = lcd_refresh; + screen->disparea = lcd_disparea; +} + + + + + diff --git a/drivers/video/rockchip/screen/lcd_null.c b/drivers/video/rockchip/screen/lcd_null.c new file mode 100644 index 000000000000..ea289c617a6a --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_null.c @@ -0,0 +1,41 @@ + +#ifndef __LCD_NULL__ +#define __LCD_NULL__ + + +/* Base */ +#define SCREEN_TYPE SCREEN_NULL +#define LVDS_FORMAT LVDS_8BIT_1 +#define OUT_FACE 0 +#define DCLK 0 +#define LCDC_ACLK 0 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 0 +#define H_BP 0 +#define H_VD 0 +#define H_FP 0 + +#define V_PW 0 +#define V_BP 0 +#define V_VD 0 +#define V_FP 0 + +#define LCD_WIDTH 0 //need modify +#define LCD_HEIGHT 0 + +/* Other */ +#define DCLK_POL 0 +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_DUMMY 0 +#define SWAP_GB 0 +#define SWAP_RG 0 + + + +#endif + diff --git a/drivers/video/rockchip/screen/lcd_rgb_tft480800_25_e.c b/drivers/video/rockchip/screen/lcd_rgb_tft480800_25_e.c new file mode 100644 index 000000000000..1591300955c0 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_rgb_tft480800_25_e.c @@ -0,0 +1,603 @@ +/* + * Copyright (C) 2011 ROCKCHIP, Inc. + * + * author: hhb@rock-chips.com + * creat date: 2011-03-11 + * route:drivers/video/display/screen/lcd_rgb_tft480800_25_e.c - driver for rk29 phone sdk + * station:haven't been tested in any hardware platform + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + + + +#include +#include +#include "../../rk29_fb.h" +#include +#include +#include +#include "screen.h" + + +/* Base */ +#define OUT_TYPE SCREEN_RGB +#define OUT_FACE OUT_P888 +#define OUT_CLK 26000000 +#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ�� + +/* Timing */ +#define H_PW 8 +#define H_BP 6 +#define H_VD 480 +#define H_FP 60 + +#define V_PW 2 +#define V_BP 12 +#define V_VD 800 +#define V_FP 4 + + +#define LCD_WIDTH 800 //need modify +#define LCD_HEIGHT 480 + +/* Other */ +#define DCLK_POL 1 +#define SWAP_RB 0 + + +/* define spi write command and data interface function */ + +#define SIMULATION_SPI 1 +#ifdef SIMULATION_SPI + + #define TXD_PORT gLcd_info->txd_pin + #define CLK_PORT gLcd_info->clk_pin + #define CS_PORT gLcd_info->cs_pin + #define LCD_RST_PORT RK29_PIN6_PC6 + + #define CS_OUT() gpio_direction_output(CS_PORT, 0) + #define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) + #define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) + #define CLK_OUT() gpio_direction_output(CLK_PORT, 0) + #define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) + #define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) + #define TXD_OUT() gpio_direction_output(TXD_PORT, 0) + #define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) + #define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) + #define LCD_RST_OUT() gpio_direction_output(LCD_RST_PORT, 0) + #define LCD_RST(i) gpio_set_value(LCD_RST_PORT, i) + +// #define bits_9 + #ifdef bits_9 //9bits + #define LCDSPI_InitCMD(cmd) spi_write_9bit(0, cmd) + #define LCDSPI_InitDAT(dat) spi_write_9bit(1, dat) + #else //16bits + #define LCDSPI_InitCMD(cmd) spi_write_16bit(0, cmd) + #define LCDSPI_InitDAT(dat) spi_write_16bit(1, dat) + #endif + #define Lcd_EnvidOnOff(i) + +#else + + #define bits_9 1 + #ifdef bits_9 //9bits + #define LCDSPI_InitCMD(cmd) + #define LCDSPI_InitDAT(dat) + #else //16bits + #define LCDSPI_InitCMD(cmd) + #define LCDSPI_InitDAT(dat) + #endif + +#endif + + +/* define lcd command */ +#define ENTER_SLEEP_MODE 0x10 +#define EXIT_SLEEP_MODE 0x11 +#define SET_COLUMN_ADDRESS 0x2a +#define SET_PAGE_ADDRESS 0x2b +#define WRITE_MEMORY_START 0x2c +#define SET_DISPLAY_ON 0x29 +#define SET_DISPLAY_OFF 0x28 +#define SET_ADDRESS_MODE 0x36 +#define SET_PIXEL_FORMAT 0x3a + + +#define DRVDelayUs(i) udelay(i*2) + +static struct rk29lcd_info *gLcd_info = NULL; +int lcd_init(void); +int lcd_standby(u8 enable); + + +/* spi write a data frame,type mean command or data */ +int spi_write_9bit(u32 type, u32 value) +{ + u32 i = 0; + + if(type != 0 && type != 1) + { + return -1; + } + /*make a data frame of 9 bits,the 8th bit 0:mean command,1:mean data*/ + value &= 0xff; + value &= (type << 8); + + TXD_OUT(); + CLK_OUT(); + CS_OUT(); + DRVDelayUs(2); + DRVDelayUs(2); + + CS_SET(); + TXD_SET(); + CLK_SET(); + DRVDelayUs(2); + + CS_CLR(); + for(i = 0; i < 9; i++) //reg + { + if(value & (1 << (8-i))) + { + TXD_SET(); + } + else + { + TXD_CLR(); + } + + CLK_CLR(); + DRVDelayUs(2); + CLK_SET(); + DRVDelayUs(2); + } + + CS_SET(); + CLK_CLR(); + TXD_CLR(); + DRVDelayUs(2); + return 0; +} + + +/* spi write a data frame,type mean command or data */ +int spi_write_16bit(u32 type, u32 value) +{ + u32 i = 0; + u32 data = 0; + + if(type != 0 && type != 1) + { + return -1; + } + /*make a data frame of 16 bits,the 8th bit 0:mean command,1:mean data*/ + data = (type << 8)|value; + + TXD_OUT(); + CLK_OUT(); + CS_OUT(); + DRVDelayUs(2); + DRVDelayUs(2); + + CS_SET(); + TXD_SET(); + CLK_SET(); + DRVDelayUs(2); + + CS_CLR(); + for(i = 0; i < 16; i++) //reg + { + if(data & (1 << (15-i))) + { + TXD_SET(); + } + else + { + TXD_CLR(); + } + + CLK_CLR(); + DRVDelayUs(2); + CLK_SET(); + DRVDelayUs(2); + } + + CS_SET(); + CLK_CLR(); + TXD_CLR(); + DRVDelayUs(2); + return 0; +} +int lcd_init(void) +{ + if(gLcd_info) + gLcd_info->io_init(); + printk("lcd_init...\n"); +/* reset lcd to start init lcd by software if there is no hardware reset circuit for the lcd */ +#ifdef LCD_RST_PORT + gpio_request(LCD_RST_PORT, NULL); +#endif + +#if 1 + TXD_OUT(); + CLK_OUT(); + CS_OUT(); + CS_SET(); + TXD_SET(); + CLK_SET(); + LCD_RST_OUT(); + LCD_RST(1); + msleep(10); + LCD_RST(0); + msleep(100); + LCD_RST(1); + msleep(100); +#endif + +#if 1 + + LCDSPI_InitCMD(0xB9); // SET password + LCDSPI_InitDAT(0xFF); + LCDSPI_InitDAT(0x83); + LCDSPI_InitDAT(0x69); + + LCDSPI_InitCMD(0xB1); //Set Power + LCDSPI_InitDAT(0x85); + LCDSPI_InitDAT(0x00); + LCDSPI_InitDAT(0x34); + LCDSPI_InitDAT(0x07); + LCDSPI_InitDAT(0x00); + LCDSPI_InitDAT(0x0F); + LCDSPI_InitDAT(0x0F); + LCDSPI_InitDAT(0x2A); + LCDSPI_InitDAT(0x32); + LCDSPI_InitDAT(0x3F); + LCDSPI_InitDAT(0x3F); + LCDSPI_InitDAT(0x01); //update VBIAS + LCDSPI_InitDAT(0x3A); + LCDSPI_InitDAT(0x01); + LCDSPI_InitDAT(0xE6); + LCDSPI_InitDAT(0xE6); + LCDSPI_InitDAT(0xE6); + LCDSPI_InitDAT(0xE6); + LCDSPI_InitDAT(0xE6); + + + + LCDSPI_InitCMD(0xB2); // SET Display 480x800 + LCDSPI_InitDAT(0x00); + LCDSPI_InitDAT(0x28); //23 + LCDSPI_InitDAT(0x05); //03 + LCDSPI_InitDAT(0x05); //03 + LCDSPI_InitDAT(0x70); + LCDSPI_InitDAT(0x00); + LCDSPI_InitDAT(0xFF); + LCDSPI_InitDAT(0x00); + LCDSPI_InitDAT(0x00); + LCDSPI_InitDAT(0x00); + LCDSPI_InitDAT(0x00); + LCDSPI_InitDAT(0x03); + LCDSPI_InitDAT(0x03); + LCDSPI_InitDAT(0x00); + LCDSPI_InitDAT(0x01); + + + LCDSPI_InitCMD(0xB4); // SET Display 480x800 + LCDSPI_InitDAT(0x00); + LCDSPI_InitDAT(0x18); + LCDSPI_InitDAT(0x80); + LCDSPI_InitDAT(0x06); + LCDSPI_InitDAT(0x02); + + + + LCDSPI_InitCMD(0xB6); // SET VCOM + LCDSPI_InitDAT(0x42); // Update VCOM + LCDSPI_InitDAT(0x42); + + + + LCDSPI_InitCMD(0xD5); + LCDSPI_InitDAT(0x00); + LCDSPI_InitDAT(0x04); + LCDSPI_InitDAT(0x03); + LCDSPI_InitDAT(0x00); + LCDSPI_InitDAT(0x01); + LCDSPI_InitDAT(0x05); + LCDSPI_InitDAT(0x28); + LCDSPI_InitDAT(0x70); + LCDSPI_InitDAT(0x01); + LCDSPI_InitDAT(0x03); + LCDSPI_InitDAT(0x00); + LCDSPI_InitDAT(0x00); + LCDSPI_InitDAT(0x40); + LCDSPI_InitDAT(0x06); + LCDSPI_InitDAT(0x51); + LCDSPI_InitDAT(0x07); + LCDSPI_InitDAT(0x00); + LCDSPI_InitDAT(0x00); + LCDSPI_InitDAT(0x41); + LCDSPI_InitDAT(0x06); + LCDSPI_InitDAT(0x50); + LCDSPI_InitDAT(0x07); + LCDSPI_InitDAT(0x07); + LCDSPI_InitDAT(0x0F); + LCDSPI_InitDAT(0x04); + LCDSPI_InitDAT(0x00); + + + ///Gamma2.2 + LCDSPI_InitCMD(0xE0); + LCDSPI_InitDAT(0x00); + LCDSPI_InitDAT(0x13); + LCDSPI_InitDAT(0x19); + LCDSPI_InitDAT(0x38); + LCDSPI_InitDAT(0x3D); + LCDSPI_InitDAT(0x3F); + LCDSPI_InitDAT(0x28); + LCDSPI_InitDAT(0x46); + LCDSPI_InitDAT(0x07); + LCDSPI_InitDAT(0x0D); + LCDSPI_InitDAT(0x0E); + LCDSPI_InitDAT(0x12); + LCDSPI_InitDAT(0x15); + LCDSPI_InitDAT(0x12); + LCDSPI_InitDAT(0x14); + LCDSPI_InitDAT(0x0F); + LCDSPI_InitDAT(0x17); + LCDSPI_InitDAT(0x00); + LCDSPI_InitDAT(0x13); + LCDSPI_InitDAT(0x19); + LCDSPI_InitDAT(0x38); + LCDSPI_InitDAT(0x3D); + LCDSPI_InitDAT(0x3F); + LCDSPI_InitDAT(0x28); + LCDSPI_InitDAT(0x46); + LCDSPI_InitDAT(0x07); + LCDSPI_InitDAT(0x0D); + LCDSPI_InitDAT(0x0E); + LCDSPI_InitDAT(0x12); + LCDSPI_InitDAT(0x15); + LCDSPI_InitDAT(0x12); + LCDSPI_InitDAT(0x14); + LCDSPI_InitDAT(0x0F); + LCDSPI_InitDAT(0x17); + + + msleep(10); + +///DGC Setting + LCDSPI_InitCMD(0xC1); + LCDSPI_InitDAT(0x01); +//R + LCDSPI_InitDAT(0x04); + LCDSPI_InitDAT(0x13); + LCDSPI_InitDAT(0x1a); + LCDSPI_InitDAT(0x20); + LCDSPI_InitDAT(0x27); + LCDSPI_InitDAT(0x2c); + LCDSPI_InitDAT(0x32); + LCDSPI_InitDAT(0x36); + LCDSPI_InitDAT(0x3f); + LCDSPI_InitDAT(0x47); + LCDSPI_InitDAT(0x50); + LCDSPI_InitDAT(0x59); + LCDSPI_InitDAT(0x60); + LCDSPI_InitDAT(0x68); + LCDSPI_InitDAT(0x71); + LCDSPI_InitDAT(0x7B); + LCDSPI_InitDAT(0x82); + LCDSPI_InitDAT(0x89); + LCDSPI_InitDAT(0x91); + LCDSPI_InitDAT(0x98); + LCDSPI_InitDAT(0xA0); + LCDSPI_InitDAT(0xA8); + LCDSPI_InitDAT(0xB0); + LCDSPI_InitDAT(0xB8); + LCDSPI_InitDAT(0xC1); + LCDSPI_InitDAT(0xC9); + LCDSPI_InitDAT(0xD0); + LCDSPI_InitDAT(0xD7); + LCDSPI_InitDAT(0xE0); + LCDSPI_InitDAT(0xE7); + LCDSPI_InitDAT(0xEF); + LCDSPI_InitDAT(0xF7); + LCDSPI_InitDAT(0xFE); + LCDSPI_InitDAT(0xCF); + LCDSPI_InitDAT(0x52); + LCDSPI_InitDAT(0x34); + LCDSPI_InitDAT(0xF8); + LCDSPI_InitDAT(0x51); + LCDSPI_InitDAT(0xF5); + LCDSPI_InitDAT(0x9D); + LCDSPI_InitDAT(0x75); + LCDSPI_InitDAT(0x00); +//G + LCDSPI_InitDAT(0x04); + LCDSPI_InitDAT(0x13); + LCDSPI_InitDAT(0x1a); + LCDSPI_InitDAT(0x20); + LCDSPI_InitDAT(0x27); + LCDSPI_InitDAT(0x2c); + LCDSPI_InitDAT(0x32); + LCDSPI_InitDAT(0x36); + LCDSPI_InitDAT(0x3f); + LCDSPI_InitDAT(0x47); + LCDSPI_InitDAT(0x50); + LCDSPI_InitDAT(0x59); + LCDSPI_InitDAT(0x60); + LCDSPI_InitDAT(0x68); + LCDSPI_InitDAT(0x71); + LCDSPI_InitDAT(0x7B); + LCDSPI_InitDAT(0x82); + LCDSPI_InitDAT(0x89); + LCDSPI_InitDAT(0x91); + LCDSPI_InitDAT(0x98); + LCDSPI_InitDAT(0xA0); + LCDSPI_InitDAT(0xA8); + LCDSPI_InitDAT(0xB0); + LCDSPI_InitDAT(0xB8); + LCDSPI_InitDAT(0xC1); + LCDSPI_InitDAT(0xC9); + LCDSPI_InitDAT(0xD0); + LCDSPI_InitDAT(0xD7); + LCDSPI_InitDAT(0xE0); + LCDSPI_InitDAT(0xE7); + LCDSPI_InitDAT(0xEF); + LCDSPI_InitDAT(0xF7); + LCDSPI_InitDAT(0xFE); + LCDSPI_InitDAT(0xCF); + LCDSPI_InitDAT(0x52); + LCDSPI_InitDAT(0x34); + LCDSPI_InitDAT(0xF8); + LCDSPI_InitDAT(0x51); + LCDSPI_InitDAT(0xF5); + LCDSPI_InitDAT(0x9D); + LCDSPI_InitDAT(0x75); + LCDSPI_InitDAT(0x00); +//B + LCDSPI_InitDAT(0x04); + LCDSPI_InitDAT(0x13); + LCDSPI_InitDAT(0x1a); + LCDSPI_InitDAT(0x20); + LCDSPI_InitDAT(0x27); + LCDSPI_InitDAT(0x2c); + LCDSPI_InitDAT(0x32); + LCDSPI_InitDAT(0x36); + LCDSPI_InitDAT(0x3f); + LCDSPI_InitDAT(0x47); + LCDSPI_InitDAT(0x50); + LCDSPI_InitDAT(0x59); + LCDSPI_InitDAT(0x60); + LCDSPI_InitDAT(0x68); + LCDSPI_InitDAT(0x71); + LCDSPI_InitDAT(0x7B); + LCDSPI_InitDAT(0x82); + LCDSPI_InitDAT(0x89); + LCDSPI_InitDAT(0x91); + LCDSPI_InitDAT(0x98); + LCDSPI_InitDAT(0xA0); + LCDSPI_InitDAT(0xA8); + LCDSPI_InitDAT(0xB0); + LCDSPI_InitDAT(0xB8); + LCDSPI_InitDAT(0xC1); + LCDSPI_InitDAT(0xC9); + LCDSPI_InitDAT(0xD0); + LCDSPI_InitDAT(0xD7); + LCDSPI_InitDAT(0xE0); + LCDSPI_InitDAT(0xE7); + LCDSPI_InitDAT(0xEF); + LCDSPI_InitDAT(0xF7); + LCDSPI_InitDAT(0xFE); + LCDSPI_InitDAT(0xCF); + LCDSPI_InitDAT(0x52); + LCDSPI_InitDAT(0x34); + LCDSPI_InitDAT(0xF8); + LCDSPI_InitDAT(0x51); + LCDSPI_InitDAT(0xF5); + LCDSPI_InitDAT(0x9D); + LCDSPI_InitDAT(0x75); + LCDSPI_InitDAT(0x00); + + msleep(10); + + + //LCDSPI_InitCMD(0x36); + //LCDSPI_InitDAT(0x80); //µ÷Õû36HÖеIJÎÊý¿ÉÒÔʵÏÖGATEºÍSOURCEµÄ·­×ª + + LCDSPI_InitCMD(SET_PIXEL_FORMAT); + LCDSPI_InitDAT(0x77); + + LCDSPI_InitCMD(EXIT_SLEEP_MODE); + msleep(120); + + LCDSPI_InitCMD(SET_DISPLAY_ON); + + LCDSPI_InitCMD(WRITE_MEMORY_START); +#endif + + if(gLcd_info) + gLcd_info->io_deinit(); + + return 0; +} + +int lcd_standby(u8 enable) +{ + if(gLcd_info) + gLcd_info->io_init(); + + if(enable) { + Lcd_EnvidOnOff(0); //RGB TIMENG OFF + LCDSPI_InitCMD(ENTER_SLEEP_MODE); + Lcd_EnvidOnOff(1); //RGB TIMENG ON + msleep(200); + Lcd_EnvidOnOff(0); //RGB TIMENG OFF + msleep(100); + } else { + //LCD_RESET(); + LCDSPI_InitCMD(EXIT_SLEEP_MODE); + msleep(200); + Lcd_EnvidOnOff(1); //RGB TIMENG ON + msleep(200); + } + + if(gLcd_info) + gLcd_info->io_deinit(); + + return 0; +} + +void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) +{ + /* screen type & face */ + screen->type = OUT_TYPE; + screen->face = OUT_FACE; + + /* Screen size */ + screen->x_res = H_VD; + screen->y_res = V_VD; + + screen->width = LCD_WIDTH; + screen->height = LCD_HEIGHT; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK; + screen->pixclock = OUT_CLK; + screen->left_margin = H_BP; + screen->right_margin = H_FP; + screen->hsync_len = H_PW; + screen->upper_margin = V_BP; + screen->lower_margin = V_FP; + screen->vsync_len = V_PW; + + /* Pin polarity */ + screen->pin_hsync = 0; + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = DCLK_POL; + + /* Swap rule */ + screen->swap_rb = SWAP_RB; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = lcd_init; + screen->standby = lcd_standby; + if(lcd_info) + gLcd_info = lcd_info; +} + + + diff --git a/drivers/video/rockchip/screen/lcd_rk2928.c b/drivers/video/rockchip/screen/lcd_rk2928.c new file mode 100644 index 000000000000..92c09b11b707 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_rk2928.c @@ -0,0 +1,78 @@ +#include +#include +#include "../../rk29_fb.h" +#include +#include +#include +#include +#include "../../rockchip/hdmi/rk_hdmi.h" +#include "screen.h" + +enum { + OUT_TYPE_INDEX = 0, + OUT_FACE_INDEX, + OUT_CLK_INDEX, + LCDC_ACLK_INDEX, + H_PW_INDEX, + H_BP_INDEX, + H_VD_INDEX, + H_FP_INDEX, + V_PW_INDEX, + V_BP_INDEX, + V_VD_INDEX, + V_FP_INDEX, + LCD_WIDTH_INDEX, + LCD_HEIGHT_INDEX, + DCLK_POL_INDEX, + SWAP_RB_INDEX, + LCD_PARAM_MAX, +}; +uint lcd_param[LCD_PARAM_MAX] = DEF_LCD_PARAM; +module_param_array(lcd_param, uint, NULL, 0644); + +#define set_scaler_info NULL + +void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) +{ + /* screen type & face */ + screen->type = lcd_param[OUT_TYPE_INDEX]; + screen->face = lcd_param[OUT_FACE_INDEX]; + screen->hw_format = 1; + + /* Screen size */ + screen->x_res = lcd_param[H_VD_INDEX]; + screen->y_res = lcd_param[V_VD_INDEX]; + + screen->width = lcd_param[LCD_WIDTH_INDEX]; + screen->height = lcd_param[LCD_HEIGHT_INDEX]; + + /* Timing */ + screen->lcdc_aclk = lcd_param[LCDC_ACLK_INDEX]; + screen->pixclock = lcd_param[OUT_CLK_INDEX]; + screen->left_margin = lcd_param[H_BP_INDEX]; + screen->right_margin = lcd_param[H_FP_INDEX]; + screen->hsync_len = lcd_param[H_PW_INDEX]; + screen->upper_margin = lcd_param[V_BP_INDEX]; + screen->lower_margin = lcd_param[V_FP_INDEX]; + screen->vsync_len = lcd_param[V_PW_INDEX]; + + /* Pin polarity */ + screen->pin_hsync = 0; + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = lcd_param[DCLK_POL_INDEX]; + + /* Swap rule */ + screen->swap_rb = lcd_param[SWAP_RB_INDEX]; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = NULL; + screen->standby = NULL; +} + + + diff --git a/drivers/video/rockchip/screen/lcd_s1d13521.c b/drivers/video/rockchip/screen/lcd_s1d13521.c new file mode 100644 index 000000000000..06db84f22ae5 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_s1d13521.c @@ -0,0 +1,355 @@ +#include +#include +#include "../../rk29_fb.h" +#include +#include +#include "screen.h" + +#include "s1d13521.h" +#include "s1d13521ioctl.h" + +/* Base */ +#define OUT_TYPE SCREEN_MCU +#define OUT_FACE OUT_P16BPP4 +#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 1 +#define H_BP 1 +#define H_VD 600 +#define H_FP 5 + +#define V_PW 1 +#define V_BP 1 +#define V_VD 800 +#define V_FP 1 + +#define P_WR 200 + +#define LCD_WIDTH 600 //need modify +#define LCD_HEIGHT 800 + +/* Other */ +#define DCLK_POL 0 +#define SWAP_RB 0 + + + +int s1d13521if_refresh(u8 arg); + +#define GPIO_RESET_L RK2818_PIN_PC0//reset pin +#define GPIO_HIRQ RK2818_PIN_PC1 //IRQ +#define GPIO_HDC RK2818_PIN_PC2 //Data(HIHG) or Command(LOW) +#define GPIO_HCS_L RK2818_PIN_PC3 //Chip select +#define GPIO_HRD_L RK2818_PIN_PC4 //Read mode, low active +#define GPIO_HWE_L RK2818_PIN_PC5 //Write mode, low active +#define GPIO_HRDY RK2818_PIN_PC6 //Bus ready +#define GPIO_RMODE RK2818_PIN_PC7 //rmode ->CNF1 + + +//---------------------------------------------------------------------------- +// PRIVATE FUNCTION: +// Set registers to initial values +//---------------------------------------------------------------------------- + +int s1d13521if_wait_for_ready(void) +{ + int cnt = 1000; + int d = 0; + gpio_request(GPIO_HRDY, 0); + d = gpio_get_value(GPIO_HRDY); + + while (d == 0) + { + mdelay(1); + + if (--cnt <= 0) // Avoid endless loop + { + printk(">>>>>> wait_for_ready -- timeout! \n"); + return -1; + } + + d = gpio_get_value(GPIO_HRDY); + } + gpio_free(GPIO_HRDY); + return 0; +} + + +int s1d13521if_cmd(unsigned ioctlcmd,s1d13521_ioctl_cmd_params *params, int numparams) +{ + int i; + s1d13521if_wait_for_ready(); + + mcu_ioctl(MCU_WRCMD, ioctlcmd); + for (i = 0; i < numparams; i++) { + mcu_ioctl(MCU_WRDATA, params->param[i]); + } + + return 0; +} + +void s1d13521if_WriteReg16(u16 Index, u16 Value) +{ + s1d13521if_wait_for_ready(); + mcu_ioctl(MCU_WRCMD, WR_REG); + mcu_ioctl(MCU_WRDATA, Index); + mcu_ioctl(MCU_WRDATA, Value); +} + + +void s1d13521fb_InitRegisters(void) +{ + unsigned i, cmd,j,numparams; + s1d13521_ioctl_cmd_params cmd_params; + S1D_INSTANTIATE_REGISTERS(static,InitCmdArray); + + i = 0; + + while (i < sizeof(InitCmdArray)/sizeof(InitCmdArray[0])) + { + cmd = InitCmdArray[i++]; + numparams = InitCmdArray[i++]; + + for (j = 0; j < numparams; j++) + cmd_params.param[j] = InitCmdArray[i++]; + + s1d13521if_cmd(cmd,&cmd_params,numparams); + } +} + +void s1d13521if_init_gpio(void) +{ + int i; + int ret=0; + + rk29_mux_api_set(GPIOC_LCDC18BIT_SEL_NAME, IOMUXB_GPIO0_C01); + rk29_mux_api_set(GPIOC_LCDC24BIT_SEL_NAME, IOMUXB_GPIO0_C2_7); + + for(i = 0; i < 8; i++) + { + if(i == 1 || i == 6)//HIRQ, HRDY + { + ret = gpio_request(GPIO_RESET_L+i, NULL); + if(ret != 0) + { + gpio_free(GPIO_RESET_L+i); + printk(">>>>>> lcd cs gpio_request err \n "); + } + gpio_direction_input(GPIO_RESET_L+i); + gpio_free(GPIO_RESET_L+i); + } + else //RESET_L, HD/C, HCS_L, HRD_L, HWE_L, RMODE + { + ret = gpio_request(GPIO_RESET_L+i, NULL); + if(ret != 0) + { + gpio_free(GPIO_RESET_L+i); + printk(">>>>>> lcd cs gpio_request err \n "); + } + gpio_direction_output(GPIO_RESET_L+i, 0); + gpio_set_value(GPIO_RESET_L+i, GPIO_HIGH); + gpio_free(GPIO_RESET_L+i); + } + } +} + +void s1d13521if_set_reset(void) +{ + gpio_request(GPIO_RMODE, 0); + gpio_set_value(GPIO_RMODE, GPIO_HIGH); + gpio_request(GPIO_RESET_L, 0); + + // reset pulse + mdelay(10); + gpio_set_value(GPIO_RESET_L, GPIO_LOW); + mdelay(10); + gpio_set_value(GPIO_RESET_L, GPIO_HIGH); + mdelay(10); + gpio_free(GPIO_RMODE); + gpio_free(GPIO_RESET_L); + + //s1d13521if_WaitForHRDY(); +} + + + +int s1d13521if_init(void) +{ + int i=0; + s1d13521_ioctl_cmd_params cmd_params; + + s1d13521if_init_gpio(); + s1d13521if_set_reset(); + + mcu_ioctl(MCU_SETBYPASS, 1); + + s1d13521fb_InitRegisters(); + +#if 1 + s1d13521if_WriteReg16(0x330,0x84); // LUT AutoSelect+P4N + s1d13521if_cmd(WAIT_DSPE_TRG,&cmd_params,0); + cmd_params.param[0] = (0x2 << 4); + s1d13521if_cmd(LD_IMG,&cmd_params,1); + cmd_params.param[0] = 0x154; + s1d13521if_cmd(WR_REG,&cmd_params,1); + + for(i=0; i<600*200; i++) { + mcu_ioctl(MCU_WRDATA, 0xffff); + } + + s1d13521if_cmd(LD_IMG_END,&cmd_params,0); + cmd_params.param[0] = ((WF_MODE_INIT<<8) |0x4000); + s1d13521if_cmd(UPD_FULL,&cmd_params,1); // update all pixels + s1d13521if_cmd(WAIT_DSPE_TRG,&cmd_params,0); + s1d13521if_cmd(WAIT_DSPE_FREND,&cmd_params,0); +#endif + + mcu_ioctl(MCU_SETBYPASS, 0); + + +#if 0 + // ³õʼ»¯Í¼Ïó + mcu_ioctl(MCU_SETBYPASS, 1); + while(1) + { + int i=0, j=0; + // Copy virtual framebuffer to display framebuffer. + + unsigned mode = WF_MODE_GC; + unsigned cmd = UPD_FULL; + +// unsigned reg330 = s1d13521if_ReadReg16(0x330); + s1d13521if_WriteReg16(0x330,0x84); // LUT AutoSelect + P4N + // Copy virtual framebuffer to hardware via indirect interface burst mode write + s1d13521if_cmd(WAIT_DSPE_TRG,&cmd_params,0); + cmd_params.param[0] = (0x2<<4); + s1d13521if_cmd(LD_IMG,&cmd_params,1); + cmd_params.param[0] = 0x154; + s1d13521if_cmd(WR_REG,&cmd_params,1); + + for(i=0; i<600*100; i++) { + mcu_ioctl(MCU_WRDATA, 0xffff); + } + for(i=0; i<600*100; i++) { + mcu_ioctl(MCU_WRDATA, 0x0000); + } + + s1d13521if_cmd(LD_IMG_END,&cmd_params,0); + cmd_params.param[0] = (mode<<8); + s1d13521if_cmd(cmd,&cmd_params,1); // update all pixels + s1d13521if_cmd(WAIT_DSPE_TRG,&cmd_params,0); + s1d13521if_cmd(WAIT_DSPE_FREND,&cmd_params,0); + + msleep(2000); + printk(">>>>>> lcd_init : send test image! \n"); + } + mcu_ioctl(MCU_SETBYPASS, 0); +#endif + + + return 0; +} + +int s1d13521if_standby(u8 enable) +{ + return 0; +} + +int s1d13521if_refresh(u8 arg) +{ + mcu_ioctl(MCU_SETBYPASS, 1); + + switch(arg) + { + case REFRESH_PRE: //DMA´«ËÍÇ°×¼±¸ + { + // Copy virtual framebuffer to display framebuffer. + s1d13521_ioctl_cmd_params cmd_params; + + // unsigned reg330 = s1d13521if_ReadReg16(0x330); + s1d13521if_WriteReg16(0x330,0x84); // LUT AutoSelect + P4N + + // Copy virtual framebuffer to hardware via indirect interface burst mode write + s1d13521if_cmd(WAIT_DSPE_TRG,&cmd_params,0); + cmd_params.param[0] = (0x2<<4); + s1d13521if_cmd(LD_IMG,&cmd_params,1); + cmd_params.param[0] = 0x154; + s1d13521if_cmd(WR_REG,&cmd_params,1); + } + printk(">>>>>> lcd_refresh : REFRESH_PRE! \n"); + break; + + case REFRESH_END: //DMA´«ËͽáÊøºó + { + s1d13521_ioctl_cmd_params cmd_params; + unsigned mode = WF_MODE_GC; + unsigned cmd = UPD_FULL; + + s1d13521if_cmd(LD_IMG_END,&cmd_params,0); + + cmd_params.param[0] = (mode<<8); + s1d13521if_cmd(cmd,&cmd_params,1); // update all pixels + + s1d13521if_cmd(WAIT_DSPE_TRG,&cmd_params,0); + s1d13521if_cmd(WAIT_DSPE_FREND,&cmd_params,0); + } + printk(">>>>>> lcd_refresh : REFRESH_END! \n"); + break; + + default: + break; + } + + mcu_ioctl(MCU_SETBYPASS, 0); + + return 0; +} + + + +void set_lcd_info(struct rk28fb_screen *screen) +{ + /* screen type & face */ + screen->type = OUT_TYPE; + screen->face = OUT_FACE; + + /* Screen size */ + screen->x_res = H_VD; + screen->y_res = V_VD; + + screen->width = LCD_WIDTH; + screen->height = LCD_HEIGHT; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK; + screen->left_margin = H_BP; + screen->right_margin = H_FP; + screen->hsync_len = H_PW; + screen->upper_margin = V_BP; + screen->lower_margin = V_FP; + screen->vsync_len = V_PW; + screen->mcu_wrperiod = P_WR; + + /* Pin polarity */ + screen->pin_hsync = 0; + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = DCLK_POL; + + /* Swap rule */ + screen->swap_rb = SWAP_RB; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = s1d13521if_init; + screen->standby = s1d13521if_standby; + screen->refresh = s1d13521if_refresh; +} + + + + diff --git a/drivers/video/rockchip/screen/lcd_td043mgea1.c b/drivers/video/rockchip/screen/lcd_td043mgea1.c new file mode 100644 index 000000000000..aa007892fbda --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_td043mgea1.c @@ -0,0 +1,40 @@ +#ifndef __LCD_TD043MGEA__ +#define __LCD_TD043MGEA__ + + +/* Base */ +#define SCREEN_TYPE SCREEN_RGB +#define LVDS_FORMAT LVDS_8BIT_2 +#define OUT_FACE OUT_P888 +#define DCLK 27000000 +#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 10 +#define H_BP 206 +#define H_VD 800 +#define H_FP 40 + +#define V_PW 10 +#define V_BP 25 +#define V_VD 480 +#define V_FP 10 + +#define LCD_WIDTH 800 //need modify +#define LCD_HEIGHT 480 + +/* Other */ +#define DCLK_POL 0 +#define DEN_POL 0 +#define VSYNC_POL 0 +#define HSYNC_POL 0 + +#define SWAP_RB 0 +#define SWAP_DUMMY 0 +#define SWAP_GB 0 +#define SWAP_RG 0 + + + +#endif + diff --git a/drivers/video/rockchip/screen/lcd_tj048nc01ca.c b/drivers/video/rockchip/screen/lcd_tj048nc01ca.c new file mode 100644 index 000000000000..1799321e0845 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_tj048nc01ca.c @@ -0,0 +1,210 @@ +#include +#include +#include "../../rk29_fb.h" +#include +#include +#include +#include "screen.h" + + +/* Base */ +#define OUT_TYPE SCREEN_RGB +#define OUT_FACE OUT_P888 +#define OUT_CLK 23000000 +#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 1 +#define H_BP 120 +#define H_VD 800 +#define H_FP 20 + +#define V_PW 1 +#define V_BP 20 +#define V_VD 480 +#define V_FP 4 + +#define LCD_WIDTH 800 //need modify +#define LCD_HEIGHT 480 + +/* Other */ +#define DCLK_POL 1 +#define SWAP_RB 0 + +#define TXD_PORT gLcd_info->txd_pin +#define CLK_PORT gLcd_info->clk_pin +#define CS_PORT gLcd_info->cs_pin + +#define CS_OUT() gpio_direction_output(CS_PORT, 0) +#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) +#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) +#define CLK_OUT() gpio_direction_output(CLK_PORT, 0) +#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) +#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) +#define TXD_OUT() gpio_direction_output(TXD_PORT, 0) +#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) +#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) + +#define DRVDelayUs(i) udelay(i*2) + +static struct rk29lcd_info *gLcd_info = NULL; +int lcd_init(void); +int lcd_standby(u8 enable); + +void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) +{ + /* screen type & face */ + screen->type = OUT_TYPE; + screen->face = OUT_FACE; + + /* Screen size */ + screen->x_res = H_VD; + screen->y_res = V_VD; + + screen->width = LCD_WIDTH; + screen->height = LCD_HEIGHT; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK; + screen->pixclock = OUT_CLK; + screen->left_margin = H_BP; + screen->right_margin = H_FP; + screen->hsync_len = H_PW; + screen->upper_margin = V_BP; + screen->lower_margin = V_FP; + screen->vsync_len = V_PW; + + /* Pin polarity */ + screen->pin_hsync = 0; + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = DCLK_POL; + + /* Swap rule */ + screen->swap_rb = SWAP_RB; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = lcd_init; + screen->standby = lcd_standby; + if(lcd_info) + gLcd_info = lcd_info; +} + +void spi_screenreg_set(u32 Addr, u32 Data) +{ + u32 i; + + TXD_OUT(); + CLK_OUT(); + CS_OUT(); + DRVDelayUs(2); + DRVDelayUs(2); + + CS_SET(); + TXD_CLR(); + CLK_CLR(); + DRVDelayUs(2); + + CS_CLR(); + for(i = 0; i < 7; i++) //reg + { + if(Addr &(1<<(6-i))) + TXD_SET(); + else + TXD_CLR(); + + // \u6a21\u62dfCLK + CLK_CLR(); + DRVDelayUs(2); + CLK_SET(); + DRVDelayUs(2); + } + + TXD_CLR(); //write + + // \u6a21\u62dfCLK + CLK_CLR(); + DRVDelayUs(2); + CLK_SET(); + DRVDelayUs(2); + + for(i = 0; i < 8; i++) //data + { + if(Data &(1<<(7-i))) + TXD_SET(); + else + TXD_CLR(); + + // \u6a21\u62dfCLK + CLK_CLR(); + DRVDelayUs(2); + CLK_SET(); + DRVDelayUs(2); + } + + CS_SET(); + CLK_CLR(); + TXD_CLR(); + DRVDelayUs(2); + +} + + +int lcd_init(void) +{ + if(gLcd_info) + gLcd_info->io_init(); + //R(0xess (A5~A0) Data(D7~D0) +#if 0 + spi_screenreg_set(0x03, 0x86); + spi_screenreg_set(0x05, 0x33); + spi_screenreg_set(0x09, 0xFF); + spi_screenreg_set(0x3A, 0x95); + spi_screenreg_set(0x3C, 0xE0); + spi_screenreg_set(0x3D, 0xF4); + spi_screenreg_set(0x3E, 0x21); + spi_screenreg_set(0x3F, 0x87); + spi_screenreg_set(0x15, 0x55); + spi_screenreg_set(0x16, 0xAF); + spi_screenreg_set(0x17, 0xFC); + spi_screenreg_set(0x18, 0x00); + spi_screenreg_set(0x19, 0x4B); + spi_screenreg_set(0x1A, 0x80); + spi_screenreg_set(0x1B, 0xFF); + spi_screenreg_set(0x1C, 0x39); + spi_screenreg_set(0x1D, 0x69); + spi_screenreg_set(0x1E, 0x9F); + spi_screenreg_set(0x1F, 0x09); + spi_screenreg_set(0x20, 0x8F); + spi_screenreg_set(0x21, 0xF0); + spi_screenreg_set(0x22, 0x2B); + spi_screenreg_set(0x23, 0x58); + spi_screenreg_set(0x24, 0x7C); + spi_screenreg_set(0x25, 0xA5); + spi_screenreg_set(0x26, 0xFF); +#endif + + if(gLcd_info) + gLcd_info->io_deinit(); + return 0; +} + +int lcd_standby(u8 enable) +{ + if(gLcd_info) + gLcd_info->io_init(); + if(enable) { + spi_screenreg_set(0x43, 0x20); + } else { + spi_screenreg_set(0x43, 0xE0); + } + if(gLcd_info) + gLcd_info->io_deinit(); + return 0; +} + + diff --git a/drivers/video/rockchip/screen/lcd_tl5001_mipi.c b/drivers/video/rockchip/screen/lcd_tl5001_mipi.c new file mode 100644 index 000000000000..b9b4135d1a46 --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_tl5001_mipi.c @@ -0,0 +1,406 @@ +/* + * Copyright (C) 2012 ROCKCHIP, Inc. + * + * author: hhb@rock-chips.com + * creat date: 2012-04-19 + * route:drivers/video/display/screen/lcd_hj050na_06a.c + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include "../transmitter/tc358768.h" + +/* Base */ +#define OUT_TYPE SCREEN_RGB +#define OUT_FACE OUT_P888 +#define BYTE_PP 3 //bytes per pixel + + +#define OUT_CLK 65000000 // in fact it is 61384615 +#define LCDC_ACLK 300000000 + +/* Timing */ +#define H_PW 10 +#define H_BP 20 +#define H_VD 720 +#define H_FP 82 + +#define V_PW 8 +#define V_BP 6 +#define V_VD 1280 +#define V_FP 4 + + +#define LCD_WIDTH 62 //uint mm the lenth of lcd active area +#define LCD_HEIGHT 111 +/* Other */ +#define VSYNC_POL 0 +#define HSYNC_POL VSYNC_POL +#define DCLK_POL 1 +#define DEN_POL 0 //positive +#define SWAP_RB 0 + + +#define LCD_TEST 0 +#define CONFIG_DEEP_STANDBY_MODE 0 +#define CONFIG_TC358768_INIT_MODE 0 //1:ARRAY 0:FUNCTION + +#define dsi_init(data) mipi_dsi.dsi_init(data, ARRAY_SIZE(data)) +#define dsi_send_dcs_packet(data) mipi_dsi.dsi_send_dcs_packet(data, ARRAY_SIZE(data)) +#define dsi_hs_start(data) mipi_dsi.dsi_hs_start(data, ARRAY_SIZE(data)) + +#define lap_define ktime_t k0,k1; +#define lap_start k0 = ktime_get(); +#define lap_end { k1 = ktime_get(); k1 = ktime_sub(k1, k0); } + +static struct rk29lcd_info *gLcd_info = NULL; +struct mipi_dsi_t mipi_dsi; +struct tc358768_t *lcd_tc358768 = NULL; + +int lcd_init(void); +int lcd_standby(u8 enable); + + +#if CONFIG_TC358768_INIT_MODE +struct spi_cmd_data32 { + unsigned int delay; + unsigned int value; +}; + +struct spi_cmd_data32 TC358768XBG_INIT[] = { + + {0xffffffff, 0xffffffff} +}; + +#else + +//high speed mode +static unsigned int re_initialize[] = { + + +}; + +static unsigned int initialize[] = { +// ************************************************** +// Initizlize -> Display On after power-on +// ************************************************** +// ************************************************** +// Power on TC358768XBG according to recommended power-on sequence +// Relase reset (RESX="H") +// Start input REFCK and PCLK +// ************************************************** +// ************************************************** +// TC358768XBG Software Reset +// ************************************************** + 0x00020001, //SYSctl, S/W Reset + 10, + 0x00020000, //SYSctl, S/W Reset release + +// ************************************************** +// TC358768XBG PLL,Clock Setting +// ************************************************** + 0x00161063, //PLL Control Register 0 (PLL_PRD,PLL_FBD) + 0x00180603, //PLL_FRS,PLL_LBWS, PLL oscillation enable + 1000, + 0x00180613, //PLL_FRS,PLL_LBWS, PLL clock out enable + +// ************************************************** +// TC358768XBG DPI Input Control +// ************************************************** + 0x00060032, //FIFO Control Register + +// ************************************************** +// TC358768XBG D-PHY Setting +// ************************************************** + 0x01400000, //D-PHY Clock lane enable + 0x01420000, // + 0x01440000, //D-PHY Data lane0 enable + 0x01460000, // + 0x01480000, //D-PHY Data lane1 enable + 0x014A0000, // + 0x014C0000, //D-PHY Data lane2 enable + 0x014E0000, // + 0x01500000, //D-PHY Data lane3 enable + 0x01520000, // + +// ************************************************** +// TC358768XBG DSI-TX PPI Control +// ************************************************** + 0x021009C4, //LINEINITCNT + 0x02120000, // + 0x02140002, //LPTXTIMECNT + 0x02160000, // + 0x02200002, //THS_HEADERCNT + 0x02220000, // + 0x02244268, //TWAKEUPCNT + 0x02260000, // + 0x022C0001, //THS_TRAILCNT + 0x022E0000, // + 0x02300005, //HSTXVREGCNT + 0x02320000, // + 0x0234001F, //HSTXVREGEN enable + 0x02360000, // + 0x02380001, //DSI clock Enable/Disable during LP + 0x023A0000, // + 0x023C0001, //BTACNTRL1 + 0x023E0002, // + 0x02040001, //STARTCNTRL + 0x02060000, // + +// ************************************************** +// TC358768XBG DSI-TX Timing Control +// ************************************************** + 0x06200001, //Sync Pulse/Sync Event mode setting + 0x0622000E, //V Control Register1 + 0x06240006, //V Control Register2 + 0x06260500, //V Control Register3 + 0x0628005E, //H Control Register1 + 0x062A003F, //H Control Register2 + 0x062C0870, //H Control Register3 + + 0x05180001, //DSI Start + 0x051A0000, // + +}; + + + +static unsigned int start_dsi_hs_mode[] = { + +// ************************************************** +// Set to HS mode +// ************************************************** + 0x05000087, //DSI lane setting, DSI mode=HS + 0x0502A300, //bit set + 0x05008000, //Switch to DSI mode + 0x0502C300, // + +// ************************************************** +// Host: RGB(DPI) input start +// ************************************************** + + 0x00080037, //DSI-TX Format setting + 0x0050003E, //DSI-TX Pixel stream packet Data Type setting + 0x00040044 //Configuration Control Register + + +}; + +#endif + +static unsigned char boe_set_extension_command[] = {0xB9, 0xFF, 0x83, 0x94}; +static unsigned char boe_set_MIPI_ctrl[] = {0xBA, 0x13}; +static unsigned char boe_set_power[] = {0xB1, 0x7C, 0x00, 0x34, 0x09, 0x01, 0x11, 0x11, 0x36, 0x3E, 0x26, 0x26, 0x57, 0x12, 0x01, 0xE6}; +static unsigned char boe_setcyc[] = {0xB4, 0x00, 0x00, 0x00, 0x05, 0x06, 0x41, 0x42, 0x02, 0x41, 0x42, 0x43, 0x47, 0x19, 0x58, + 0x60, 0x08, 0x85, 0x10}; +static unsigned char boe_config05[] = {0xC7, 0x00, 0x20}; +static unsigned char boe_set_gip[] = {0xD5,0x4C,0x01,0x00,0x01,0xCD,0x23,0xEF,0x45,0x67,0x89,0xAB,0x11,0x00,0xDC,0x10,0xFE,0x32, + 0xBA,0x98,0x76,0x54,0x00,0x11,0x40}; + +//static unsigned char boe_set_panel[] = {0xCC, 0x01}; +//static unsigned char boe_set_vcom[] = {0xB6, 0x2a}; +static unsigned char boe_set_panel[] = {0xCC, 0x05}; +static unsigned char boe_set_vcom[] = {0xB6, 0x31}; + +static unsigned char boe_set_gamma[] = {0xE0,0x24,0x33,0x36,0x3F,0x3f,0x3f,0x3c,0x56,0x05,0x0C,0x0e,0x11,0x13,0x12,0x14,0x12,0x1e, + 0x24,0x33,0x36,0x3F,0x3f,0x3F,0x3c,0x56,0x05,0x0c, 0x0e,0x11,0x13,0x12,0x14,0x12, 0x1e}; // +static unsigned char boe_set_addr_mode[] = {0x36, 0x00}; +static unsigned char boe_set_pixel[] = {0x3a, 0x60}; + +static unsigned char boe_enter_sleep_mode[] = {0x10}; +static unsigned char boe_exit_sleep_mode[] = {0x11}; +static unsigned char boe_set_diaplay_on[] = {0x29}; +static unsigned char boe_set_diaplay_off[] = {0x28}; +static unsigned char boe_enter_invert_mode[] = {0x21}; +static unsigned char boe_all_pixel_on[] = {0x23}; +static unsigned char boe_set_id[] = {0xc3, 0xaa, 0x55, 0xee}; + + +void lcd_power_on(void) { + + +} + +void lcd_power_off(void) { + + +} +#if LCD_TEST +void lcd_test(void) { + u8 buf[8]; + printk("**mipi lcd test\n"); + buf[0] = 0x0c; + mipi_dsi.dsi_read_dcs_packet(buf, 1); + printk("**Get_pixel_format 0x0c:%02x\n", buf[0]); + buf[0] = 0x0a; + mipi_dsi.dsi_read_dcs_packet(buf, 1); + printk("**Get_power_mode 0x0a:%02x\n", buf[0]); + buf[0] = 0x0f; + mipi_dsi.dsi_read_dcs_packet(buf, 1); + printk("**Get_diagnostic_result 0x0f:%02x\n", buf[0]); + buf[0] = 0x09; + mipi_dsi.dsi_read_dcs_packet(buf, 4); + printk("**Read Display Status 0x09:%02x,%02x,%02x,%02x\n", buf[0],buf[1],buf[2],buf[3]); +} +#endif + + + +static unsigned char boe_set_wrdisbv[] = {0x51, 0xff}; +static unsigned char boe_set_wrctrld[] = {0x53, 0x24}; +static unsigned char boe_set_wrcabc[] = {0x55, 0x02}; +static unsigned char boe_set_wrcabcmb[] = {0x5e, 0x0}; +static unsigned char boe_set_cabc[] = {0xc9, 0x0d, 0x01, 0x0, 0x0, 0x0, 0x22, 0x0, 0x0, 0x0}; +static unsigned char boe_set_cabc_gain[] = {0xca, 0x32, 0x2e, 0x2c, 0x2a, 0x28, 0x26, 0x24, 0x22, 0x20}; + + +void lcd_cabc(u8 brightness) { + +} + + + +int lcd_init(void) +{ + + int i = 0; + lap_define + //power on + lcd_tc358768->power_up(NULL); + + if(gLcd_info) + gLcd_info->io_init(); + + i = 0; + lap_start + //Re-Initialize +#if CONFIG_TC358768_INIT_MODE + i = 0; + while (1) { + if(TC358768XBG_INIT[i].delay == 0xffffffff) + break; + tc358768_wr_reg_32bits_delay(TC358768XBG_INIT[i].delay, TC358768XBG_INIT[i].value); + i++; + } +#else + dsi_init(initialize); + + + //lcd init + dsi_send_dcs_packet(boe_exit_sleep_mode); + msleep(150); + dsi_send_dcs_packet(boe_set_extension_command); + msleep(1); + dsi_send_dcs_packet(boe_set_MIPI_ctrl); + msleep(1); + dsi_send_dcs_packet(boe_set_power); + msleep(1); + dsi_send_dcs_packet(boe_setcyc); + msleep(1); + dsi_send_dcs_packet(boe_set_vcom); + msleep(1); + dsi_send_dcs_packet(boe_set_panel); + msleep(1); + dsi_send_dcs_packet(boe_set_gip); + msleep(1); + dsi_send_dcs_packet(boe_set_gamma); + msleep(1); + dsi_send_dcs_packet(boe_set_addr_mode); + msleep(1); + dsi_send_dcs_packet(boe_set_diaplay_on); +#if LCD_TEST + lcd_test(); +#endif + dsi_hs_start(start_dsi_hs_mode); + + msleep(10); +#endif + lap_end + printk(">>time:%lld\n", k1.tv64); + return 0; + +} + +int lcd_standby(u8 enable) +{ + //int ret = 0; + if(enable) { + + printk("suspend lcd\n"); + //power down + if(gLcd_info) + gLcd_info->io_deinit(); + + lcd_tc358768->power_down(NULL); + + } else { + lcd_init(); + } + + return 0; +} + +void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) +{ + /* screen type & face */ + screen->type = OUT_TYPE; + screen->face = OUT_FACE; + + /* Screen size */ + screen->x_res = H_VD; + screen->y_res = V_VD; + + screen->width = LCD_WIDTH; + screen->height = LCD_HEIGHT; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK; + screen->pixclock = OUT_CLK; + screen->left_margin = H_BP; + screen->right_margin = H_FP; + screen->hsync_len = H_PW; + screen->upper_margin = V_BP; + screen->lower_margin = V_FP; + screen->vsync_len = V_PW; + + /* Pin polarity */ + screen->pin_hsync = HSYNC_POL; + screen->pin_vsync = VSYNC_POL; + screen->pin_den = DEN_POL; + screen->pin_dclk = DCLK_POL; + + /* Swap rule */ + screen->swap_rb = SWAP_RB; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = lcd_init; + screen->standby = lcd_standby; + + if(lcd_info) + gLcd_info = lcd_info; + + if(tc358768_init(&mipi_dsi) == 0) + lcd_tc358768 = (struct tc358768_t *)mipi_dsi.chip; + else + printk("%s: %s:%d",__FILE__, __func__, __LINE__); + +} diff --git a/drivers/video/rockchip/screen/lcd_tx23d88vm.c b/drivers/video/rockchip/screen/lcd_tx23d88vm.c new file mode 100644 index 000000000000..d0fce5c9886c --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_tx23d88vm.c @@ -0,0 +1,78 @@ +#include +#include +#include "../../rk29_fb.h" +#include +#include +#include +#include "screen.h" + + +/* Base */ +#define OUT_TYPE SCREEN_RGB + +#define OUT_FACE OUT_D888_P666 +//#define OUT_FACE OUT_P888//modify by xhh + + +#define OUT_CLK 66000000//64000000 +#define LCDC_ACLK 500000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 10 +#define H_BP 20 +#define H_VD 1200 +#define H_FP 70 + +#define V_PW 2 +#define V_BP 4 +#define V_VD 800 +#define V_FP 14 + +#define LCD_WIDTH 188 +#define LCD_HEIGHT 125 +/* Other */ +#define DCLK_POL 0 +//#define DCLK_POL 1//xhh +#define SWAP_RB 0 + + +void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) +{ + /* screen type & face */ + screen->type = OUT_TYPE; + screen->face = OUT_FACE; + + /* Screen size */ + screen->x_res = H_VD; + screen->y_res = V_VD; + + screen->width = LCD_WIDTH; + screen->height = LCD_HEIGHT; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK; + screen->pixclock = OUT_CLK; + screen->left_margin = H_BP; + screen->right_margin = H_FP; + screen->hsync_len = H_PW; + screen->upper_margin = V_BP; + screen->lower_margin = V_FP; + screen->vsync_len = V_PW; + + /* Pin polarity */ + screen->pin_hsync = 0; + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = DCLK_POL; + + /* Swap rule */ + screen->swap_rb = SWAP_RB; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = NULL; + screen->standby = NULL; +} diff --git a/drivers/video/rockchip/screen/lcd_wy_800x480.c b/drivers/video/rockchip/screen/lcd_wy_800x480.c new file mode 100644 index 000000000000..5be80d6c5d5a --- /dev/null +++ b/drivers/video/rockchip/screen/lcd_wy_800x480.c @@ -0,0 +1,109 @@ +#include +#include +#include "../../rk29_fb.h" +#include +#include +#include +#include "screen.h" + +/* Base */ +#define LCD_WIDTH 154 //need modify +#define LCD_HEIGHT 85 + +#define OUT_TYPE SCREEN_RGB +#define OUT_FACE OUT_P666 +#define OUT_CLK 33000000 +#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ + +/* Timing */ +#define H_PW 30 +#define H_BP 16 +#define H_VD 800 +#define H_FP 210 + +#define V_PW 13 +#define V_BP 10 +#define V_VD 480 +#define V_FP 22 + +/* Other */ +#define DCLK_POL 0 +#define SWAP_RB 0 + +static struct rk29lcd_info *gLcd_info = NULL; + +static int init(void) +{ + int ret = 0; + + if(gLcd_info && gLcd_info->io_init) + gLcd_info->io_init(); + + return 0; +} + +static int standby(u8 enable) +{ + if(!enable) + { + if(gLcd_info && gLcd_info->io_enable) + gLcd_info->io_enable(); + } + else + { + if(gLcd_info && gLcd_info->io_disable) + gLcd_info->io_disable(); + } + return 0; +} + +void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) +{ + /* screen type & face */ + screen->type = OUT_TYPE; + screen->face = OUT_FACE; + + /* Screen size */ + screen->x_res = H_VD; + screen->y_res = V_VD; + + screen->width = LCD_WIDTH; + screen->height = LCD_HEIGHT; + + /* Timing */ + screen->lcdc_aclk = LCDC_ACLK; + screen->pixclock = OUT_CLK; + screen->left_margin = H_BP; + screen->right_margin = H_FP; + screen->hsync_len = H_PW; + screen->upper_margin = V_BP; + screen->lower_margin = V_FP; + screen->vsync_len = V_PW; + + /* Pin polarity */ + screen->pin_hsync = 0; + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = DCLK_POL; + + /* Swap rule */ + screen->swap_rb = SWAP_RB; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = init; + screen->standby = standby; + if(lcd_info) + { + gLcd_info = lcd_info; + } + else + { + printk("%s lcd_info==NULL\n", __func__); + } + +} + diff --git a/drivers/video/rockchip/screen/rk_screen.c b/drivers/video/rockchip/screen/rk_screen.c new file mode 100644 index 000000000000..b7a4e580a587 --- /dev/null +++ b/drivers/video/rockchip/screen/rk_screen.c @@ -0,0 +1,260 @@ + +#include +#include "lcd.h" +#if defined(CONFIG_RK_HDMI) +#include "../hdmi/rk_hdmi.h" +#endif + + + + + + +// if we use one lcdc with jetta for dual display,we need these configration +#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF) && defined(CONFIG_RK_HDMI) +static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution) +{ + #if defined(CONFIG_RK610_LVDS) + screen->s_clk_inv = S_DCLK_POL; + screen->s_den_inv = 0; + screen->s_hv_sync_inv = 0; + #endif + + switch(hdmi_resolution) + { + case HDMI_1920x1080p_60Hz: + /* Scaler Timing */ + #if defined(CONFIG_RK610_LVDS) + screen->hdmi_resolution = hdmi_resolution; + screen->s_pixclock = S_OUT_CLK; + screen->s_hsync_len = S_H_PW; + screen->s_left_margin = S_H_BP; + screen->s_right_margin = S_H_FP; + screen->s_hsync_len = S_H_PW; + screen->s_upper_margin = S_V_BP; + screen->s_lower_margin = S_V_FP; + screen->s_vsync_len = S_V_PW; + screen->s_hsync_st = S_H_ST; + screen->s_vsync_st = S_V_ST; + #endif + + //bellow are for JettaB + #if defined(CONFIG_RK616_LVDS) + screen->pll_cfg_val = S_PLL_CFG_VAL; + screen->frac = S_FRAC; + screen->scl_vst = S_SCL_VST; + screen->scl_hst = S_SCL_HST; + screen->vif_vst = S_VIF_VST; + screen->vif_hst = S_VIF_HST; + #endif + break; + case HDMI_1920x1080p_50Hz: + /* Scaler Timing */ + #if defined(CONFIG_RK610_LVDS) + screen->hdmi_resolution = hdmi_resolution; + screen->s_pixclock = S1_OUT_CLK; + screen->s_hsync_len = S1_H_PW; + screen->s_left_margin = S1_H_BP; + screen->s_right_margin = S1_H_FP; + screen->s_hsync_len = S1_H_PW; + screen->s_upper_margin = S1_V_BP; + screen->s_lower_margin = S1_V_FP; + screen->s_vsync_len = S1_V_PW; + screen->s_hsync_st = S1_H_ST; + screen->s_vsync_st = S1_V_ST; + #endif + + #if defined(CONFIG_RK616_LVDS) + screen->pll_cfg_val = S1_PLL_CFG_VAL; + screen->frac = S1_FRAC; + screen->scl_vst = S1_SCL_VST; + screen->scl_hst = S1_SCL_HST; + screen->vif_vst = S1_VIF_VST; + screen->vif_hst = S1_VIF_HST; + #endif + break; + case HDMI_1280x720p_60Hz: + /* Scaler Timing */ + #if defined(CONFIG_RK610_LVDS) + screen->hdmi_resolution = hdmi_resolution; + screen->s_pixclock = S2_OUT_CLK; + screen->s_hsync_len = S2_H_PW; + screen->s_left_margin = S2_H_BP; + screen->s_right_margin = S2_H_FP; + screen->s_hsync_len = S2_H_PW; + screen->s_upper_margin = S2_V_BP; + screen->s_lower_margin = S2_V_FP; + screen->s_vsync_len = S2_V_PW; + screen->s_hsync_st = S2_H_ST; + screen->s_vsync_st = S2_V_ST; + #endif + + #if defined(CONFIG_RK616_LVDS) + screen->pll_cfg_val = S2_PLL_CFG_VAL; + screen->frac = S2_FRAC; + screen->scl_vst = S2_SCL_VST; + screen->scl_hst = S2_SCL_HST; + screen->vif_vst = S2_VIF_VST; + screen->vif_hst = S2_VIF_HST; + #endif + break; + case HDMI_1280x720p_50Hz: + /* Scaler Timing */ + #if defined(CONFIG_RK610_LVDS) + screen->hdmi_resolution = hdmi_resolution; + screen->s_pixclock = S3_OUT_CLK; + screen->s_hsync_len = S3_H_PW; + screen->s_left_margin = S3_H_BP; + screen->s_right_margin = S3_H_FP; + screen->s_hsync_len = S3_H_PW; + screen->s_upper_margin = S3_V_BP; + screen->s_lower_margin = S3_V_FP; + screen->s_vsync_len = S3_V_PW; + screen->s_hsync_st = S3_H_ST; + screen->s_vsync_st = S3_V_ST; + #endif + + #if defined(CONFIG_RK616_LVDS) + screen->pll_cfg_val = S3_PLL_CFG_VAL; + screen->frac = S3_FRAC; + screen->scl_vst = S3_SCL_VST; + screen->scl_hst = S3_SCL_HST; + screen->vif_vst = S3_VIF_VST; + screen->vif_hst = S3_VIF_HST; + #endif + break; + case HDMI_720x576p_50Hz_4_3: + case HDMI_720x576p_50Hz_16_9: + /* Scaler Timing */ + #if defined(CONFIG_RK610_LVDS) + screen->hdmi_resolution = hdmi_resolution; + screen->s_pixclock = S4_OUT_CLK; + screen->s_hsync_len = S4_H_PW; + screen->s_left_margin = S4_H_BP; + screen->s_right_margin = S4_H_FP; + screen->s_hsync_len = S4_H_PW; + screen->s_upper_margin = S4_V_BP; + screen->s_lower_margin = S4_V_FP; + screen->s_vsync_len = S4_V_PW; + screen->s_hsync_st = S4_H_ST; + screen->s_vsync_st = S4_V_ST; + #endif + + #if defined(CONFIG_RK616_LVDS) + screen->pll_cfg_val = S4_PLL_CFG_VAL; + screen->frac = S4_FRAC; + screen->scl_vst = S4_SCL_VST; + screen->scl_hst = S4_SCL_HST; + screen->vif_vst = S4_VIF_VST; + screen->vif_hst = S4_VIF_HST; + #endif + break; + + case HDMI_720x480p_60Hz_16_9: + case HDMI_720x480p_60Hz_4_3: + /* Scaler Timing */ + #if defined(CONFIG_RK610_LVDS) + screen->hdmi_resolution = hdmi_resolution; + screen->s_pixclock = S5_OUT_CLK; + screen->s_hsync_len = S5_H_PW; + screen->s_left_margin = S5_H_BP; + screen->s_right_margin = S5_H_FP; + screen->s_hsync_len = S5_H_PW; + screen->s_upper_margin = S5_V_BP; + screen->s_lower_margin = S5_V_FP; + screen->s_vsync_len = S5_V_PW; + screen->s_hsync_st = S5_H_ST; + screen->s_vsync_st = S5_V_ST; + #endif + + #if defined(CONFIG_RK616_LVDS) + screen->pll_cfg_val = S5_PLL_CFG_VAL; + screen->frac = S5_FRAC; + screen->scl_vst = S5_SCL_VST; + screen->scl_hst = S5_SCL_HST; + screen->vif_vst = S5_VIF_VST; + screen->vif_hst = S5_VIF_HST; + #endif + break; + default : + printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution); + return -1; + break; + } + + return 0; +} +#else +#define set_scaler_info NULL +#endif + +void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info ) +{ + +#if defined(RK_USE_SCREEN_ID) + set_lcd_info_by_id(screen,lcd_info); +#else + screen->type = SCREEN_TYPE; + screen->face = OUT_FACE; + screen->lvds_format = LVDS_FORMAT; //lvds data format + + + screen->x_res = H_VD; //screen resolution + screen->y_res = V_VD; + + screen->width = LCD_WIDTH; + screen->height = LCD_HEIGHT; + + + screen->lcdc_aclk = LCDC_ACLK; // Timing + screen->pixclock = DCLK; + screen->left_margin = H_BP; + screen->right_margin = H_FP; + screen->hsync_len = H_PW; + screen->upper_margin = V_BP; + screen->lower_margin = V_FP; + screen->vsync_len = V_PW; + + + screen->pin_hsync = HSYNC_POL; //Pin polarity + screen->pin_vsync = VSYNC_POL; + screen->pin_den = DEN_POL; + screen->pin_dclk = DCLK_POL; + + + screen->swap_rb = SWAP_RB; // Swap rule + screen->swap_rg = SWAP_RG; + screen->swap_gb = SWAP_GB; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ +#if defined(RK_SCREEN_INIT) //some screen need to init by spi or i2c + screen->init = rk_lcd_init; + screen->standby = rk_lcd_standby; + if(lcd_info) + gLcd_info = lcd_info; +#endif + +#if defined(USE_RK_DSP_LUT) + screen->dsp_lut = dsp_lut; +#endif + +#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF) + screen->sscreen_get = set_scaler_info; +#endif + +#endif + +} + +size_t get_fb_size(void) +{ + size_t size = 0; + #if defined(CONFIG_THREE_FB_BUFFER) + size = ((H_VD)*(V_VD)<<2)* 3; //three buffer + #else + size = ((H_VD)*(V_VD)<<2)<<1; //two buffer + #endif + return ALIGN(size,SZ_1M); +} diff --git a/drivers/video/rockchip/screen/s1d13521.h b/drivers/video/rockchip/screen/s1d13521.h new file mode 100644 index 000000000000..edaf6292aac0 --- /dev/null +++ b/drivers/video/rockchip/screen/s1d13521.h @@ -0,0 +1,95 @@ +/*=============================================================================== +** Generic Header information generated by 13521CFG.EXE (Build 4) +** (C)SEIKO EPSON CORPORATION 2002-2007. All rights reserved. +** +** DISPLAYS WxH FREQ SUBTYPE +** ------------- ----------- ------- ------------------------------------------- +** *LCD1=Parallel 800x600 NA EPD Panel +** +** DIMENSIONS WxHxBPP @ STRIDE START SADDR ADDITIONAL +** ----------- ---------------------- ------- --------- ----------------------- +** *Main 800x600x4 @ 800 NA 000EA600h LUTAuto=on +** +** CLOCKS FREQ SOURCE +** ------------- ----------- --------------------------------------------------- +** INCLK 132.000 MHz PLL +** SYSCLK 66.000 MHz PLL/2 +** PCLK 26.400 MHz PLL/5 +** SPICLK 13.200 MHz SYSCLK/5 +** I2CCLK 4.125 MHz PLL/16 +** SDRAMCLK 132.000 MHz PLL +** SDRAMREFCLK 63.954 KHz CLKI/516 +** +** This file defines the configuration environment and registers, +** which can be used by any software, such as display drivers. +** +** Note: If you transfer this file to any non-PC system, use ASCII +** mode (not BINARY) to maintain system-specific line terminators. +**===============================================================================*/ + +#define S1D_13521 + +#define S1D_DISPLAY_WIDTH 600 +#define S1D_DISPLAY_HEIGHT 800 + +#define S1D_DISPLAY_BPP 8 + +//#define S1D_DISPLAY_SCANLINE_BYTES 600 +#define S1D_DISPLAY_FRAME_RATE 0 +#define S1D_DISPLAY_PCLK 26400000L +#define S1D_PHYSICAL_REG_ADDR 0x00000000L +#define S1D_PHYSICAL_REG_SIZE 90L +#define S1D_PHYSICAL_VMEM_REQUIRED 640000L +#define S1D_PALETTE_SIZE 256 +#define S1D_POWER_DELAY_OFF 0 +#define S1D_POWER_DELAY_ON 0 +#define S1D_HWBLT +#define S1D_SWBLT + + +#define BS60_INIT_HSIZE 800 +#define BS60_INIT_VSIZE 600 + +#define BS60_INIT_FSLEN 4 +#define BS60_INIT_FBLEN 4 +#define BS60_INIT_FELEN 10 +#define BS60_INIT_LSLEN 10 +#define BS60_INIT_LBLEN 4 +#define BS60_INIT_LELEN 100 +#define BS60_INIT_PIXCLKDIV 6 +#define BS60_INIT_SDRV_CFG (100 | (1<< 8) | (1<<9)) +#define BS60_INIT_GDRV_CFG 0x2 +#define BS60_INIT_LUTIDXFMT (4 | (1<<7)) +#define BS60_INIT_ROTMODE 3 // rotation mode = 180 degrees + +#define WF_MODE_INIT 0 +#define WF_MODE_MU 1 +#define WF_MODE_GU 2 +#define WF_MODE_GC 3 +#define WF_MODE_PU 4 + +typedef unsigned short S1D_INDEX; +typedef unsigned short S1D_VALUE; + +#define S1D_INSTANTIATE_REGISTERS(scope_prefix,variable_name) \ + scope_prefix S1D_VALUE variable_name[] = \ + { \ + INIT_SYS_RUN, 0, \ + INIT_DSPE_CFG, 5, BS60_INIT_HSIZE, \ + BS60_INIT_VSIZE, \ + BS60_INIT_SDRV_CFG, \ + BS60_INIT_GDRV_CFG, \ + BS60_INIT_LUTIDXFMT, \ + INIT_DSPE_TMG, 5, BS60_INIT_FSLEN, \ + (BS60_INIT_FELEN<<8)|BS60_INIT_FBLEN, \ + BS60_INIT_LSLEN, \ + (BS60_INIT_LELEN<<8)|BS60_INIT_LBLEN, \ + BS60_INIT_PIXCLKDIV, \ + RD_WFM_INFO, 2, 0x0886, 0, \ + UPD_GDRV_CLR, 0, \ + WAIT_DSPE_TRG, 0, \ + INIT_ROTMODE, 1, (BS60_INIT_ROTMODE << 8) \ + } + + + diff --git a/drivers/video/rockchip/screen/s1d13521ioctl.h b/drivers/video/rockchip/screen/s1d13521ioctl.h new file mode 100644 index 000000000000..3170b90d807e --- /dev/null +++ b/drivers/video/rockchip/screen/s1d13521ioctl.h @@ -0,0 +1,134 @@ +//----------------------------------------------------------------------------- +// +// linux/drivers/video/epson/s1d1352ioctl.h -- IOCTL definitions for Epson +// S1D13521 controller frame buffer driver. +// +// Copyright(c) Seiko Epson Corporation 2009. +// All rights reserved. +// +// This file is subject to the terms and conditions of the GNU General Public +// License. See the file COPYING in the main directory of this archive for +// more details. +// +//---------------------------------------------------------------------------- + +/* ioctls + 0x45 is 'E' */ + +struct s1d13521_ioctl_hwc +{ + unsigned addr; + unsigned value; + void* buffer; +}; + +#define S1D13521_REGREAD 0x4540 +#define S1D13521_REGWRITE 0x4541 +#define S1D13521_MEMBURSTREAD 0x4546 +#define S1D13521_MEMBURSTWRITE 0x4547 +#define S1D13521_VBUF_REFRESH 0x4548 + +// System commands +#define INIT_CMD_SET 0x00 +#define INIT_PLL_STANDBY 0x01 +#define RUN_SYS 0x02 +#define STBY 0x04 +#define SLP 0x05 +#define INIT_SYS_RUN 0x06 +#define INIT_SYS_STBY 0x07 +#define INIT_SDRAM 0x08 +#define INIT_DSPE_CFG 0x09 +#define INIT_DSPE_TMG 0x0A +#define INIT_ROTMODE 0x0B + +// Register and memory access commands +#define RD_REG 0x10 +#define WR_REG 0x11 +#define RD_SFM 0x12 +#define WR_SFM 0x13 +#define END_SFM 0x14 + +// Burst access commands +#define BST_RD_SDR 0x1C +#define BST_WR_SDR 0x1D +#define BST_END_SDR 0x1E + +// Image loading commands +#define LD_IMG 0x20 +#define LD_IMG_AREA 0x22 +#define LD_IMG_END 0x23 +#define LD_IMG_WAIT 0x24 +#define LD_IMG_SETADR 0x25 +#define LD_IMG_DSPEADR 0x26 + +// Polling commands +#define WAIT_DSPE_TRG 0x28 +#define WAIT_DSPE_FREND 0x29 +#define WAIT_DSPE_LUTFREE 0x2A +#define WAIT_DSPE_MLUTFREE 0x2B + +// Waveform update commands +#define RD_WFM_INFO 0x30 +#define UPD_INIT 0x32 +#define UPD_FULL 0x33 +#define UPD_FULL_AREA 0x34 +#define UPD_PART 0x35 +#define UPD_PART_AREA 0x36 +#define UPD_GDRV_CLR 0x37 +#define UPD_SET_IMGADR 0x38 + +#pragma pack(1) + +typedef struct +{ + u16 param[5]; +}s1d13521_ioctl_cmd_params; + +#pragma pack() + +#define S1D13521_INIT_CMD_SET (0x4500 | INIT_CMD_SET) +#define S1D13521_INIT_PLL_STANDBY (0x4500 | INIT_PLL_STANDBY) +#define S1D13521_RUN_SYS (0x4500 | RUN_SYS) +#define S1D13521_STBY (0x4500 | STBY) +#define S1D13521_SLP (0x4500 | SLP) +#define S1D13521_INIT_SYS_RUN (0x4500 | INIT_SYS_RUN) +#define S1D13521_INIT_SYS_STBY (0x4500 | INIT_SYS_STBY) +#define S1D13521_INIT_SDRAM (0x4500 | INIT_SDRAM) +#define S1D13521_INIT_DSPE_CFG (0x4500 | INIT_DSPE_CFG) +#define S1D13521_INIT_DSPE_TMG (0x4500 | INIT_DSPE_TMG) +#define S1D13521_INIT_ROTMODE (0x4500 | INIT_ROTMODE) +#define S1D13521_RD_REG (0x4500 | RD_REG) +#define S1D13521_WR_REG (0x4500 | WR_REG) +#define S1D13521_RD_SFM (0x4500 | RD_SFM) +#define S1D13521_WR_SFM (0x4500 | WR_SFM) +#define S1D13521_END_SFM (0x4500 | END_SFM) + +// Burst access commands +#define S1D13521_BST_RD_SDR (0x4500 | BST_RD_SDR) +#define S1D13521_BST_WR_SDR (0x4500 | BST_WR_SDR) +#define S1D13521_BST_END_SDR (0x4500 | BST_END_SDR) + +// Image loading IOCTL commands +#define S1D13521_LD_IMG (0x4500 | LD_IMG) +#define S1D13521_LD_IMG_AREA (0x4500 | LD_IMG_AREA) +#define S1D13521_LD_IMG_END (0x4500 | LD_IMG_END) +#define S1D13521_LD_IMG_WAIT (0x4500 | LD_IMG_WAIT) +#define S1D13521_LD_IMG_SETADR (0x4500 | LD_IMG_SETADR) +#define S1D13521_LD_IMG_DSPEADR (0x4500 | LD_IMG_DSPEADR) + +// Polling commands +#define S1D13521_WAIT_DSPE_TRG (0x4500 | WAIT_DSPE_TRG) +#define S1D13521_WAIT_DSPE_FREND (0x4500 | WAIT_DSPE_FREND) +#define S1D13521_WAIT_DSPE_LUTFREE (0x4500 | WAIT_DSPE_LUTFREE) +#define S1D13521_WAIT_DSPE_MLUTFREE (0x4500 | WAIT_DSPE_MLUTFREE) + +// Waveform update IOCTL commands +#define S1D13521_RD_WFM_INFO (0x4500 | RD_WFM_INFO) +#define S1D13521_UPD_INIT (0x4500 | UPD_INIT) +#define S1D13521_UPD_FULL (0x4500 | UPD_FULL) +#define S1D13521_UPD_FULL_AREA (0x4500 | UPD_FULL_AREA) +#define S1D13521_UPD_PART (0x4500 | UPD_PART) +#define S1D13521_UPD_PART_AREA (0x4500 | UPD_PART_AREA) +#define S1D13521_UPD_GDRV_CLR (0x4500 | UPD_GDRV_CLR) +#define S1D13521_UPD_SET_IMGADR (0x4500 | UPD_SET_IMGADR) + diff --git a/drivers/video/rockchip/transmitter/Kconfig b/drivers/video/rockchip/transmitter/Kconfig new file mode 100644 index 000000000000..820fc1916377 --- /dev/null +++ b/drivers/video/rockchip/transmitter/Kconfig @@ -0,0 +1,44 @@ + +menuconfig RK_TRSM + bool "RockChip display transmitter support" + depends on FB_ROCKCHIP + +config RK2928_LVDS + bool "RK2928、RK2926 lvds transmitter support" + depends on ARCH_RK2928 && RK_TRSM + +config RK610_LVDS + bool "RK610(Jetta) lvds transmitter support" + depends on MFD_RK610 && RK_TRSM + help + Support Jetta(RK610) to output LCD1 and LVDS. + +config RK616_LVDS + bool "RK616(JettaB) lvds,lcd,scaler vido interface support" + depends on MFD_RK616 && RK_TRSM + help + RK616(Jetta B) LVDS,LCD,scaler transmitter support. + + +config DP_ANX6345 + bool "RGB to Display Port transmitter anx6345,anx9804,anx9805 support" + depends on RK_TRSM + +config DP501 + bool"RGB to Display Port transmitter dp501 support" + depends on RK_TRSM + +config TC358768_RGB2MIPI + bool "toshiba TC358768 RGB to MIPI DSI" + depends on RK_TRSM + help + "a chip that change RGB interface parallel signal into DSI serial signal" + +config SSD2828_RGB2MIPI + bool "solomon SSD2828 RGB to MIPI DSI" + depends on RK_TRSM + help + "a chip that change RGB interface parallel signal into DSI serial signal" + + + diff --git a/drivers/video/rockchip/transmitter/Makefile b/drivers/video/rockchip/transmitter/Makefile new file mode 100644 index 000000000000..0fa2485703cb --- /dev/null +++ b/drivers/video/rockchip/transmitter/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for display transmitter like lvds edp mipi +# +obj-$(CONFIG_RK2928_LVDS) += rk2928_lvds.o +obj-$(CONFIG_RK610_LVDS) += rk610_lcd.o +obj-$(CONFIG_RK616_LVDS) += rk616_lvds.o +obj-$(CONFIG_TC358768_RGB2MIPI) += mipi_dsi.o tc358768.o +obj-$(CONFIG_SSD2828_RGB2MIPI) += mipi_dsi.o ssd2828.o +obj-$(CONFIG_DP_ANX6345) += dp_anx6345.o +obj-$(CONFIG_DP501) += dp501.o diff --git a/drivers/video/rockchip/transmitter/dp501.c b/drivers/video/rockchip/transmitter/dp501.c new file mode 100644 index 000000000000..0414ae84e9df --- /dev/null +++ b/drivers/video/rockchip/transmitter/dp501.c @@ -0,0 +1,294 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + + +static int dp501_write_reg(struct i2c_client *client,char index,char reg,char val) +{ + int ret; + if(index == 0) //page 0 + { + client->addr = (DP501_P0_ADDR >> 1); + } + else if(index == 1) //page1 + { + client->addr = (DP501_P1_ADDR >> 1); + } + else if(index == 2) //page 2 + { + client->addr = (DP501_P2_ADDR >> 1); + } + else if(index == 3) + { + client->addr = (DP501_P3_ADDR >> 1); + } + else + { + dev_err(&client->dev,"invalid page number\n"); + return -EINVAL; + } + ret = i2c_master_reg8_send(client, reg, &val, 1,DP501_SCL_RATE); + if(ret < 0) + { + + dev_err(&client->dev,"%s page%d:0x%x err\n",__func__,index,reg); + ret = -EINVAL; + } + + return ret; + +} + +static char dp501_read_reg(struct i2c_client *client,char index,char reg) +{ + int ret; + char val; + if(index == 0) //page 0 + { + client->addr = (DP501_P0_ADDR >> 1); + } + else if(index == 1) //page1 + { + client->addr = (DP501_P1_ADDR>>1); + } + else if(index == 2) //page 2 + { + client->addr = (DP501_P2_ADDR>>1); + } + else if(index == 3) + { + client->addr = (DP501_P3_ADDR>>1); + } + else + { + dev_err(&client->dev,"invalid page number\n"); + return -EINVAL; + } + + + ret = i2c_master_reg8_recv(client, reg, &val, 1, DP501_SCL_RATE); + if(ret < 0) + { + dev_err(&client->dev,"%s page%d:0x%x err\n",__func__,index,reg); + return -EINVAL; + } + + return val; + +} +static int get_dp_chip_id(struct i2c_client *client) +{ + char c1,c2; + int id; + c1 = dp501_read_reg(client,2,CHIP_ID_L); + c2 = dp501_read_reg(client,2,CHIP_ID_H); + id = c2; + return (id<<8)|c1; + return 0; +} + +static int dp501_init(struct i2c_client *client) +{ + char val,val1; + + dp501_write_reg(client,2,0x00,0x6C); + dp501_write_reg(client,2,0x01,0x68); + dp501_write_reg(client,2,0x02,0x28); + dp501_write_reg(client,2,0x03,0x2A); + dp501_write_reg(client,2,0x16,0x50); + dp501_write_reg(client,2,0x24,0x22); + dp501_write_reg(client,2,0x25,0x04); + dp501_write_reg(client,2,0x26,0x10); //PIO setting + + dp501_write_reg(client,0,0x0a,0x0c); //block 74 & 76 + dp501_write_reg(client,0,0x20,0x00); + dp501_write_reg(client,0,0x27,0x30); //auto detect CRTC + dp501_write_reg(client,0,0x2f,0x82); //reset tpfifo at v blank + dp501_write_reg(client,0,0x24,0xc0); //DVO mapping ; crtc follow mode + dp501_write_reg(client,0,0x28,0x07); //crtc follow mode + dp501_write_reg(client,0,0x87,0x7f); //aux retry + dp501_write_reg(client,0,0x88,0x1e); //aux retry + dp501_write_reg(client,0,0xbb,0x06); //aux retry + dp501_write_reg(client,0,0x72,0xa9); //DPCD readable + dp501_write_reg(client,0,0x60,0x00); //Scramble on + dp501_write_reg(client,0,0x8f,0x02); //debug select, read P0.0x8d[2] can check HPD + + + //second, set up training + dp501_write_reg(client,0,0x5d,0x06); //training link rate(2.7Gbps) + dp501_write_reg(client,0,0x5e,0x84); //training lane count(4Lanes), + dp501_write_reg(client,0,0x74,0x00); //idle pattern + dp501_write_reg(client,0,0x5f,0x0d); //trigger training + mdelay(100); //delay 100ms + + //then, check training result + val = dp501_read_reg(client,0,0x63); + val1 = dp501_read_reg(client,0,0x64); //Each 4bits stand for one lane, 0x77/0x77 means training succeed with 4Lanes. + dev_info(&client->dev,"training result:>>val:0x%x>>val1:0x%x\n",val,val1); + + return 0; +} + + + +static int edp_reg_show(struct seq_file *s, void *v) +{ + int i = 0; + char val; + struct dp501 *dp501= s->private; + + seq_printf(s,"page 0:\n"); + for(i=0;i< MAX_REG;i++) + { + val = dp501_read_reg(dp501->client,0,i); + seq_printf(s,"0x%02x>>0x%02x\n",i,val); + } + + seq_printf(s,"page 1:\n"); + for(i=0;i< MAX_REG;i++) + { + val = dp501_read_reg(dp501->client,1,i); + seq_printf(s,"0x%02x>>0x%02x\n",i,val); + } + + seq_printf(s,"page 2:\n"); + for(i=0;i< MAX_REG;i++) + { + val = dp501_read_reg(dp501->client,0,i); + seq_printf(s,"0x%02x>>0x%02x\n",2,val); + } + + seq_printf(s,"page 3:\n"); + for(i=0;i< MAX_REG;i++) + { + val = dp501_read_reg(dp501->client,3,i); + seq_printf(s,"0x%02x>>0x%02x\n",i,val); + } + + return 0; +} + +static int edp_reg_open(struct inode *inode, struct file *file) +{ + struct dp501 *dp501 = inode->i_private; + return single_open(file,edp_reg_show,dp501); +} + +static const struct file_operations edp_reg_fops = { + .owner = THIS_MODULE, + .open = edp_reg_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +#ifdef CONFIG_HAS_EARLYSUSPEND +static void dp501_early_suspend(struct early_suspend *h) +{ + struct dp501 *dp501 = container_of(h, struct dp501, early_suspend); + gpio_set_value(dp501->pdata->dvdd33_en_pin,!dp501->pdata->dvdd33_en_val); + gpio_set_value(dp501->pdata->dvdd18_en_pin,!dp501->pdata->dvdd18_en_val); + +} + +static void dp501_late_resume(struct early_suspend *h) +{ + struct dp501 *dp501 = container_of(h, struct dp501, early_suspend); + gpio_set_value(dp501->pdata->dvdd33_en_pin,dp501->pdata->dvdd33_en_val); + gpio_set_value(dp501->pdata->dvdd18_en_pin,dp501->pdata->dvdd18_en_val); + gpio_set_value(dp501->pdata->edp_rst_pin,0); + msleep(10); + gpio_set_value(dp501->pdata->edp_rst_pin,1); + dp501->edp_init(dp501->client); +} +#endif +static int dp501_i2c_probe(struct i2c_client *client,const struct i2c_device_id *id) +{ + int ret; + + struct dp501 *dp501 = NULL; + int chip_id; + + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) + { + dev_err(&client->dev, "Must have I2C_FUNC_I2C.\n"); + ret = -ENODEV; + } + dp501 = kzalloc(sizeof(struct dp501), GFP_KERNEL); + if (dp501 == NULL) + { + dev_err(&client->dev,"alloc for struct dp501 fail\n"); + ret = -ENOMEM; + } + + dp501->client = client; + dp501->pdata = client->dev.platform_data; + i2c_set_clientdata(client,dp501); + if(dp501->pdata->power_ctl) + dp501->pdata->power_ctl(); + + debugfs_create_file("edp-reg", S_IRUSR,NULL,dp501,&edp_reg_fops); + +#ifdef CONFIG_HAS_EARLYSUSPEND + dp501->early_suspend.suspend = dp501_early_suspend; + dp501->early_suspend.resume = dp501_late_resume; + dp501->early_suspend.level = EARLY_SUSPEND_LEVEL_STOP_DRAWING; + register_early_suspend(&dp501->early_suspend); +#endif + + chip_id = get_dp_chip_id(client); + dp501->edp_init = dp501_init; + dp501->edp_init(client); + + + printk("edp dp%x probe ok\n",chip_id); + + return ret; +} + +static int __devexit dp501_i2c_remove(struct i2c_client *client) +{ + return 0; +} + + +static const struct i2c_device_id id_table[] = { + {"dp501", 0 }, + { } +}; + +static struct i2c_driver dp501_i2c_driver = { + .driver = { + .name = "dp501", + .owner = THIS_MODULE, + }, + .probe = &dp501_i2c_probe, + .remove = &dp501_i2c_remove, + .id_table = id_table, +}; + + +static int __init dp501_module_init(void) +{ + return i2c_add_driver(&dp501_i2c_driver); +} + +static void __exit dp501_module_exit(void) +{ + i2c_del_driver(&dp501_i2c_driver); +} + +fs_initcall_sync(dp501_module_init); +module_exit(dp501_module_exit); + diff --git a/drivers/video/rockchip/transmitter/dp_anx6345.c b/drivers/video/rockchip/transmitter/dp_anx6345.c new file mode 100644 index 000000000000..13ae7d9adeed --- /dev/null +++ b/drivers/video/rockchip/transmitter/dp_anx6345.c @@ -0,0 +1,849 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_DEBUG_FS) +#include +#include +#include +#endif + + +//#define BIST_MODE 0 + +static int anx6345_i2c_read_p0_reg(struct i2c_client *client, char reg, char *val) +{ + int ret; + client->addr = DP_TX_PORT0_ADDR >> 1; + ret = i2c_master_reg8_recv(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL; + if(ret < 0) + { + printk(KERN_ERR "%s>>err\n",__func__); + } + + return ret; +} +static int anx6345_i2c_write_p0_reg(struct i2c_client *client, char reg, char *val) +{ + int ret; + client->addr = DP_TX_PORT0_ADDR >> 1; + ret = i2c_master_reg8_send(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL; + if(ret < 0) + { + printk(KERN_ERR "%s>>err\n",__func__); + } + + return ret; +} +static int anx6345_i2c_read_p1_reg(struct i2c_client *client, char reg, char *val) +{ + int ret; + client->addr = HDMI_TX_PORT0_ADDR >> 1; + ret = i2c_master_reg8_recv(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL; + if(ret < 0) + { + printk(KERN_ERR "%s>>err\n",__func__); + } + + return ret; +} + +static int anx6345_i2c_write_p1_reg(struct i2c_client *client, char reg, char *val) +{ + int ret; + client->addr = HDMI_TX_PORT0_ADDR >> 1; + ret = i2c_master_reg8_send(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL; + if(ret < 0) + { + printk(KERN_ERR "%s>>err\n",__func__); + } + + return ret; +} + +#if defined(CONFIG_DEBUG_FS) +static int edp_reg_show(struct seq_file *s, void *v) +{ + int i = 0; + char val; + struct edp_anx6345 *anx6345 = s->private; + if(!anx6345) + { + printk(KERN_ERR "no edp device!\n"); + return 0; + } + + seq_printf(s,"0x70:\n"); + for(i=0;i< MAX_REG;i++) + { + anx6345_i2c_read_p0_reg(anx6345->client, i , &val); + seq_printf(s,"0x%02x>>0x%02x\n",i,val); + } + + + seq_printf(s,"\n0x72:\n"); + for(i=0;i< MAX_REG;i++) + { + anx6345_i2c_read_p1_reg(anx6345->client, i , &val); + seq_printf(s,"0x%02x>>0x%02x\n",i,val); + } + return 0; +} + +static int edp_reg_open(struct inode *inode, struct file *file) +{ + struct edp_anx6345 *anx6345 = inode->i_private; + return single_open(file, edp_reg_show, anx6345); +} + +static const struct file_operations edp_reg_fops = { + .owner = THIS_MODULE, + .open = edp_reg_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; +#endif + +//get chip ID. Make sure I2C is OK +static int get_dp_chip_id(struct i2c_client *client) +{ + char c1,c2; + int id; + anx6345_i2c_read_p1_reg(client,SP_TX_DEV_IDL_REG,&c1); + anx6345_i2c_read_p1_reg(client,SP_TX_DEV_IDH_REG,&c2); + id = c2; + return (id<<8)|c1; +} + + +static int anx980x_bist_mode(struct i2c_client *client) +{ + char val,i; + u8 cnt=0; + + //Power on total and select DP mode + val = 00; + anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val); + + //HW reset + val = DP_TX_RST_HW_RST; + anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val); + msleep(10); + val = 0x00; + anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val); + + + anx6345_i2c_read_p1_reg(client, DP_POWERD_CTRL_REG, &val); + val = 0x00; + anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val); + + + //get chip ID. Make sure I2C is OK + anx6345_i2c_read_p1_reg(client, DP_TX_DEV_IDH_REG , &val); + if (val==0x98) + printk("Chip found\n"); + + //for clocl detect + for(i=0;i<100;i++) + { + anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val); + anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val); + anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val); + if((val&DP_TX_SYS_CTRL1_DET_STA)!=0) + { + printk("clock is detected.\n"); + break; + } + + msleep(10); + } + //check whther clock is stable + for(i=0;i<50;i++) + { + anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val); + anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val); + anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val); + if((val&DP_TX_SYS_CTRL2_CHA_STA)==0) + { + printk("clock is stable.\n"); + break; + } + msleep(10); + } + + //VESA range, 8bits BPC, RGB + val = 0x10; + anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL2_REG, &val); + //RK_EDP chip analog setting + val = 0x07; + anx6345_i2c_write_p0_reg(client, DP_TX_PLL_CTRL_REG, &val); + val = 0x19; + anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL3, &val); + val = 0xd9; + anx6345_i2c_write_p1_reg(client, DP_TX_PLL_CTRL3, &val); + + //Select AC mode + val = 0x40; + anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val); + + //RK_EDP chip analog setting + val = 0xf0; + anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val); + val = 0x99; + anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG3, &val); + val = 0x7b; + anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val); + val = 0x30; + anx6345_i2c_write_p0_reg(client, DP_TX_LINK_DEBUG_REG,&val); + val = 0x06; + anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL, &val); + + //force HPD + val = 0x30; + anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL3_REG, &val); + //power on 4 lanes + val = 0x00; + anx6345_i2c_write_p0_reg(client, 0xc8, &val); + //lanes setting + anx6345_i2c_write_p0_reg(client, 0xa3, &val); + anx6345_i2c_write_p0_reg(client, 0xa4, &val); + anx6345_i2c_write_p0_reg(client, 0xa5,&val); + anx6345_i2c_write_p0_reg(client, 0xa6, &val); + + //reset AUX CH + val = 0x44; + anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val); + val = 0x40; + anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val); + + //Select 1.62G + val = 0x06; + anx6345_i2c_write_p0_reg(client, DP_TX_LINK_BW_SET_REG, &val); + //Select 4 lanes + val = 0x04; + anx6345_i2c_write_p0_reg(client, DP_TX_LANE_COUNT_SET_REG, &val); + + //strart link traing + //DP_TX_LINK_TRAINING_CTRL_EN is self clear. If link training is OK, it will self cleared. + #if 1 + val = DP_TX_LINK_TRAINING_CTRL_EN; + anx6345_i2c_write_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val); + msleep(5); + anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val); + while((val&0x01)&&(cnt++ < 10)) + { + printk("Waiting...\n"); + msleep(5); + anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val); + } + + if(cnt >= 10) + { + printk(KERN_INFO "HW LT fail\n"); + } + else + { + printk(KERN_INFO "HW LT success ...cnt:%d\n",cnt); + } + #else + DP_TX_HW_LT(client,0x0a,0x04); //2.7Gpbs 4lane + #endif + //DP_TX_Write_Reg(0x7a, 0x7c, 0x02); + + //Set bist format 2048x1536 + val = 0x2c; + anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_LINEL_REG, &val); + val = 0x06; + anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_LINEH_REG, &val); + + val = 0x00; + anx6345_i2c_write_p1_reg(client, DP_TX_ACT_LINEL_REG, &val); + val = 0x06; + anx6345_i2c_write_p1_reg(client, DP_TX_ACT_LINEH_REG,&val); + val = 0x02; + anx6345_i2c_write_p1_reg(client, DP_TX_VF_PORCH_REG, &val); + val = 0x04; + anx6345_i2c_write_p1_reg(client, DP_TX_VSYNC_CFG_REG,&val); + val = 0x26; + anx6345_i2c_write_p1_reg(client, DP_TX_VB_PORCH_REG, &val); + val = 0x50; + anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_PIXELL_REG, &val); + val = 0x04; + anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_PIXELH_REG, &val); + val = 0x00; + anx6345_i2c_write_p1_reg(client, DP_TX_ACT_PIXELL_REG, &val); + val = 0x04; + anx6345_i2c_write_p1_reg(client, DP_TX_ACT_PIXELH_REG, &val); + + val = 0x18; + anx6345_i2c_write_p1_reg(client, DP_TX_HF_PORCHL_REG, &val); + val = 0x00; + anx6345_i2c_write_p1_reg(client, DP_TX_HF_PORCHH_REG, &val); + + val = 0x10; + anx6345_i2c_write_p1_reg(client, DP_TX_HSYNC_CFGL_REG,&val); + val = 0x00; + anx6345_i2c_write_p1_reg(client, DP_TX_HSYNC_CFGH_REG,&val); + val = 0x28; + anx6345_i2c_write_p1_reg(client, DP_TX_HB_PORCHL_REG, &val); + val = 0x00; + anx6345_i2c_write_p1_reg(client, DP_TX_HB_PORCHH_REG, &val); + val = 0x03; + anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL10_REG, &val); + + //enable BIST + val = DP_TX_VID_CTRL4_BIST; + anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL4_REG, &val); + //enable video input + val = 0x8d; + anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val); + //force HPD and stream valid + val = 0x33; + anx6345_i2c_write_p0_reg(client, 0x82, &val); + + return 0; +} + +static int anx980x_aux_rst(struct i2c_client *client) +{ + char val; + anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL2_REG, &val); + val |= DP_TX_AUX_RST; + anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val); + val &= ~DP_TX_AUX_RST; + anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val); + return 0; +} + + +static int anx980x_wait_aux_finished(struct i2c_client *client) +{ + char val,cnt; + cnt = 0; + + anx6345_i2c_read_p0_reg(client,DP_TX_AUX_CTRL_REG2, &val); + while(val&0x01) + { + //delay_ms(20); + cnt ++; + if(cnt == 10) + { + printk("aux break"); + anx980x_aux_rst(client); + //cnt = 0; + break; + } + anx6345_i2c_read_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val); + } + + return 0; +} + +static int anx980x_aux_dpcdread_bytes(struct i2c_client *client,unsigned long addr, char cCount,char* pBuf) +{ + char val,i; + + val = 0x80; + anx6345_i2c_write_p0_reg(client, DP_TX_BUF_DATA_COUNT_REG, &val); + + //set read cmd and count + val = (((char)(cCount-1) <<4)&(0xf0))|0x09; + anx6345_i2c_write_p0_reg(client, DP_TX_AUX_CTRL_REG, &val); + + //set aux address15:0 + val = (char)addr&0xff; + anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_7_0_REG, &val); + val = (char)((addr>>8)&0xff); + anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_15_8_REG, &val); + + //set address19:16 and enable aux + anx6345_i2c_read_p0_reg(client, DP_TX_AUX_ADDR_19_16_REG, &val); + val &=(0xf0)|(char)((addr>>16)&0xff); + anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_19_16_REG, &val); + + //Enable Aux + anx6345_i2c_read_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val); + val |= 0x01; + anx6345_i2c_write_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val); + + //delay_ms(2); + anx980x_wait_aux_finished(client); + + for(i =0;i= MAX_BUF_CNT) + return 1; + //break; + } + + return 0; + + +} + +static int anx_video_map_config(struct i2c_client *client) +{ + char val = 0; + char i = 0; + anx6345_i2c_write_p1_reg(client, 0x40, &val); + anx6345_i2c_write_p1_reg(client, 0x41, &val); + anx6345_i2c_write_p1_reg(client, 0x48, &val); + anx6345_i2c_write_p1_reg(client, 0x49, &val); + anx6345_i2c_write_p1_reg(client, 0x50, &val); + anx6345_i2c_write_p1_reg(client, 0x51, &val); + for(i=0; i<6; i++) + { + val = i; + anx6345_i2c_write_p1_reg(client, 0x42+i, &val); + } + + for(i=0; i<6; i++) + { + val = 6+i; + anx6345_i2c_write_p1_reg(client, 0x4a+i, &val); + } + + for(i=0; i<6; i++) + { + val = 0x0c+i; + anx6345_i2c_write_p1_reg(client, 0x52+i, &val); + } + + return 0; + +} +static int anx980x_eanble_video_input(struct i2c_client *client) +{ + char val; + + anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val); + val |= DP_TX_VID_CTRL1_VID_EN; + anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val); + + anx_video_map_config(client); + + return 0; +} + +static int anx980x_init(struct i2c_client *client) +{ + char val = 0x00; + char safe_mode = 0; + char ByteBuf[2]; + char dp_tx_bw,dp_tx_lane_count; + char cnt = 10; + +#if defined(BIST_MODE) + return anx980x_bist_mode(client); +#endif + //power on all block and select DisplayPort mode + val |= DP_POWERD_AUDIO_REG; + anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val ); + + anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val); + val &= ~DP_TX_VID_CTRL1_VID_EN; + anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val); + + //software reset + anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL_REG, &val); + val |= DP_TX_RST_SW_RST; + anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG,&val); + val &= ~DP_TX_RST_SW_RST; + anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val); + + + val = 0x07; + anx6345_i2c_write_p0_reg(client, DP_TX_PLL_CTRL_REG, &val); + val = 0x50; + anx6345_i2c_write_p0_reg(client, DP_TX_EXTRA_ADDR_REG, &val); + + //24bit SDR,negedge latch, and wait video stable + val = 0x01; + anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);//72:08 for 9804 SDR, neg edge 05/04/09 extra pxl + val = 0x19; + anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL3, &val); + val = 0xd9; + anx6345_i2c_write_p1_reg(client, DP_TX_PLL_CTRL3, &val); + + //serdes ac mode. + anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL2_REG, &val); + val |= DP_TX_AC_MODE; + anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val); + + //set termination + val = 0xf0; + anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val); + //set duty cycle + val = 0x99; + anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG3, &val); + + anx6345_i2c_read_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val); + val |= 0x2a; + anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val); + + //anx6345_i2c_write_p0_reg(client, DP_TX_HDCP_CTRL, 0x01); + val = 0x30; + anx6345_i2c_write_p0_reg(client, DP_TX_LINK_DEBUG_REG,&val); + + //for DP link CTS + anx6345_i2c_read_p0_reg(client, DP_TX_GNS_CTRL_REG, &val); + val |= 0x40; + anx6345_i2c_write_p0_reg(client, DP_TX_GNS_CTRL_REG, &val); + + //power down PLL filter + val = 0x06; + anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL,&val); + + anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE0_SET_REG, &val); + anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE1_SET_REG, &val); + anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE2_SET_REG, &val); + anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE3_SET_REG, &val); + + val = 0x06; + anx6345_i2c_write_p0_reg(client, DP_TX_LINK_BW_SET_REG, &val); + val = 0x04; + anx6345_i2c_write_p0_reg(client, DP_TX_LANE_COUNT_SET_REG, &val); + + val = DP_TX_LINK_TRAINING_CTRL_EN; + anx6345_i2c_write_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG,&val); + msleep(2); + anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val); + while((val & DP_TX_LINK_TRAINING_CTRL_EN)&&(cnt--)) + { + anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val); + cnt--; + } + if(cnt < 0) + { + printk(KERN_INFO "HW LT fail\n"); + } + else + printk(KERN_INFO "HW LT Success!>>:times:%d\n",(11-cnt)); + //DP_TX_Config_Video(client); + anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val); + anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val); + if(!(val & DP_TX_SYS_CTRL1_DET_STA)) + { + printk("No pclk\n"); + //return; //mask by yxj + } + + anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val); + anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val); + anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val); + if(val & DP_TX_SYS_CTRL2_CHA_STA) + { + printk("pclk not stable!\n"); + //return; mask by yxj + } + + anx980x_aux_dpcdread_bytes(client,(unsigned long)0x00001,2,ByteBuf); + dp_tx_bw = ByteBuf[0]; + dp_tx_lane_count = ByteBuf[1] & 0x0f; + printk("%s..lc:%d--bw:%d\n",__func__,dp_tx_lane_count,dp_tx_bw); + + if(!safe_mode) + { + //set Input BPC mode & color space + anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL2_REG, &val); + val &= 0x8c; + val = val |((char)(0) << 4); //8bits ,rgb + anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL2_REG, &val); + } + + + + //enable video input + anx980x_eanble_video_input(client); + + return 0; +} + +static int anx6345_bist_mode(struct i2c_client *client) +{ + char val = 0x00; + //these register are for bist mode + val = 0x2c; + anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEL_REG,&val); + val = 0x06; + anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEH_REG,&val); + val = 0x00; + anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEL_REG,&val); + val = 0x06; + anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEH_REG,&val); + val = 0x02; + anx6345_i2c_write_p1_reg(client,SP_TX_VF_PORCH_REG,&val); + val = 0x04; + anx6345_i2c_write_p1_reg(client,SP_TX_VSYNC_CFG_REG,&val); + val = 0x26; + anx6345_i2c_write_p1_reg(client,SP_TX_VB_PORCH_REG,&val); + val = 0x50; + anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELL_REG,&val); + val = 0x04; + anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELH_REG,&val); + val = 0x00; + anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELL_REG,&val); + val = 0x04; + anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELH_REG,&val); + val = 0x18; + anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHL_REG,&val); + val = 0x00; + anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHH_REG,&val); + val = 0x10; + anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGL_REG,&val); + val = 0x00; + anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGH_REG,&val); + val = 0x28; + anx6345_i2c_write_p1_reg(client,SP_TX_HB_PORCHL_REG,&val); + val = 0x13; + anx6345_i2c_write_p1_reg(client,SP_TX_VID_CTRL10_REG,&val); + + + //enable BIST. In normal mode, don't need to config this reg + val = 0x08; + anx6345_i2c_write_p1_reg(client, 0x0b, &val); + printk("anx6345 enter bist mode\n"); + + return 0; +} +static int anx6345_init(struct i2c_client *client) +{ + char val = 0x00; + char i = 0; + char lc,bw; + char cnt = 50; + + val = 0x30; + anx6345_i2c_write_p1_reg(client,SP_POWERD_CTRL_REG,&val); + + //clock detect + for(i=0;i<50;i++) + { + + anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val); + anx6345_i2c_write_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val); + anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val); + if((val&SP_TX_SYS_CTRL1_DET_STA)!=0) + { + break; + } + + mdelay(10); + } + if(i>49) + printk("no clock detected by anx6345\n"); + + //check whether clock is stable + for(i=0;i<50;i++) + { + anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL2_REG, &val); + anx6345_i2c_write_p0_reg(client,SP_TX_SYS_CTRL2_REG, &val); + anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL2_REG, &val); + if((val&SP_TX_SYS_CTRL2_CHA_STA)==0) + { + break; + } + mdelay(10); + } + if(i>49) + printk("clk is not stable\n"); + + //VESA range, 6bits BPC, RGB + val = 0x00; + anx6345_i2c_write_p1_reg(client, SP_TX_VID_CTRL2_REG, &val); + + //ANX6345 chip pll setting + val = 0x00; + anx6345_i2c_write_p0_reg(client, SP_TX_PLL_CTRL_REG, &val); //UPDATE: FROM 0X07 TO 0X00 + + + //ANX chip analog setting + val = 0x70; + anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val); //UPDATE: FROM 0XF0 TO 0X70 + val = 0x30; + anx6345_i2c_write_p0_reg(client, SP_TX_LINK_DEBUG_REG, &val); + + //force HPD + //anx6345_i2c_write_p0_reg(client, SP_TX_SYS_CTRL3_REG, &val); + + + //reset AUX + anx6345_i2c_read_p1_reg(client, SP_TX_RST_CTRL2_REG, &val); + val |= SP_TX_AUX_RST; + anx6345_i2c_write_p1_reg(client, SP_TX_RST_CTRL2_REG, &val); + val &= ~SP_TX_AUX_RST; + anx6345_i2c_write_p1_reg(client, SP_TX_RST_CTRL2_REG, &val); + + //Select 2.7G + val = 0x0a; + anx6345_i2c_write_p0_reg(client, SP_TX_LINK_BW_SET_REG, &val); + //Select 2 lanes + val = 0x02; + anx6345_i2c_write_p0_reg(client,SP_TX_LANE_COUNT_SET_REG,&val); + + val = SP_TX_LINK_TRAINING_CTRL_EN; + anx6345_i2c_write_p0_reg(client, SP_TX_LINK_TRAINING_CTRL_REG, &val); + mdelay(5); + anx6345_i2c_read_p0_reg(client, SP_TX_LINK_TRAINING_CTRL_REG, &val); + while((val&0x80)&&(cnt)) //UPDATE: FROM 0X01 TO 0X80 + { + printk("Waiting...\n"); + mdelay(5); + anx6345_i2c_read_p0_reg(client,SP_TX_LINK_TRAINING_CTRL_REG,&val); + cnt--; + } + if(cnt <= 0) + { + printk(KERN_INFO "HW LT fail\n"); + } + else + printk("HW LT Success>>:times:%d\n",(51-cnt)); + + + + //enable video input, set DDR mode, the input DCLK should be 102.5MHz; + //In normal mode, set this reg to 0x81, SDR mode, the input DCLK should be 205MHz + +#if defined(BIST_MODE) + anx6345_bist_mode(client); + val = 0x8f; +#else + val = 0x81; +#endif + anx6345_i2c_write_p1_reg(client,SP_TX_VID_CTRL1_REG,&val); + + anx_video_map_config(client); + //force HPD and stream valid + val = 0x33; + anx6345_i2c_write_p0_reg(client,SP_TX_SYS_CTRL3_REG,&val); + + anx6345_i2c_read_p0_reg(client,SP_TX_LANE_COUNT_SET_REG, &lc); + anx6345_i2c_read_p0_reg(client,SP_TX_LINK_BW_SET_REG, &bw); + printk("%s..lc:%d--bw:%d\n",__func__,lc,bw); + + return 0; +} + + +#ifdef CONFIG_HAS_EARLYSUSPEND +static void anx6345_early_suspend(struct early_suspend *h) +{ + struct edp_anx6345 *anx6345 = container_of(h, struct edp_anx6345, early_suspend); + gpio_set_value(anx6345->pdata->dvdd33_en_pin,!anx6345->pdata->dvdd33_en_val); + gpio_set_value(anx6345->pdata->dvdd18_en_pin,!anx6345->pdata->dvdd18_en_val); +} + +static void anx6345_late_resume(struct early_suspend *h) +{ + struct edp_anx6345 *anx6345 = container_of(h, struct edp_anx6345, early_suspend); + gpio_set_value(anx6345->pdata->dvdd33_en_pin,anx6345->pdata->dvdd33_en_val); + msleep(5); + gpio_set_value(anx6345->pdata->dvdd18_en_pin,anx6345->pdata->dvdd18_en_val); + gpio_set_value(anx6345->pdata->edp_rst_pin,0); + msleep(50); + gpio_set_value(anx6345->pdata->edp_rst_pin,1); + anx6345->edp_anx_init(anx6345->client); +} +#endif + +static int anx6345_i2c_probe(struct i2c_client *client,const struct i2c_device_id *id) +{ + int ret; + + struct edp_anx6345 *anx6345 = NULL; + int chip_id; + + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) + { + dev_err(&client->dev, "Must have I2C_FUNC_I2C.\n"); + ret = -ENODEV; + } + anx6345 = kzalloc(sizeof(struct edp_anx6345), GFP_KERNEL); + if (anx6345 == NULL) + { + printk(KERN_ALERT "alloc for struct anx6345 fail\n"); + ret = -ENOMEM; + } + + anx6345->client = client; + anx6345->pdata = client->dev.platform_data; + i2c_set_clientdata(client,anx6345); + if(anx6345->pdata->power_ctl) + anx6345->pdata->power_ctl(); + +#if defined(CONFIG_DEBUG_FS) + anx6345->debugfs_dir = debugfs_create_dir("edp", NULL); + if (IS_ERR(anx6345->debugfs_dir)) + { + printk(KERN_ERR "failed to create debugfs dir for edp!\n"); + } + else + debugfs_create_file("edp-reg", S_IRUSR,anx6345->debugfs_dir,anx6345,&edp_reg_fops); +#endif + +#ifdef CONFIG_HAS_EARLYSUSPEND + anx6345->early_suspend.suspend = anx6345_early_suspend; + anx6345->early_suspend.resume = anx6345_late_resume; + anx6345->early_suspend.level = EARLY_SUSPEND_LEVEL_STOP_DRAWING; + register_early_suspend(&anx6345->early_suspend); +#endif + chip_id = get_dp_chip_id(client); + if(chip_id == 0x9805) + anx6345->edp_anx_init = anx980x_init; + else + anx6345->edp_anx_init = anx6345_init; + + anx6345->edp_anx_init(client); + + printk("edp anx%x probe ok\n",get_dp_chip_id(client)); + + return ret; +} + +static int __devexit anx6345_i2c_remove(struct i2c_client *client) +{ + return 0; +} + +static const struct i2c_device_id id_table[] = { + {"anx6345", 0 }, + { } +}; + +static struct i2c_driver anx6345_i2c_driver = { + .driver = { + .name = "anx6345", + .owner = THIS_MODULE, + }, + .probe = &anx6345_i2c_probe, + .remove = &anx6345_i2c_remove, + .id_table = id_table, +}; + + +static int __init anx6345_module_init(void) +{ + return i2c_add_driver(&anx6345_i2c_driver); +} + +static void __exit anx6345_module_exit(void) +{ + i2c_del_driver(&anx6345_i2c_driver); +} + +fs_initcall_sync(anx6345_module_init); +module_exit(anx6345_module_exit); + diff --git a/drivers/video/rockchip/transmitter/mipi_dsi.c b/drivers/video/rockchip/transmitter/mipi_dsi.c new file mode 100644 index 000000000000..e14fd2a1800a --- /dev/null +++ b/drivers/video/rockchip/transmitter/mipi_dsi.c @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2012 ROCKCHIP, Inc. + * drivers/video/display/transmitter/mipi_dsi.c + * author: hhb@rock-chips.com + * create date: 2013-01-17 + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "mipi_dsi.h" +#include +#include +#include + +#define MAX_DSI_CHIPS 5 + +static struct mipi_dsi_ops *dsi_ops[MAX_DSI_CHIPS] = {NULL}; +static struct mipi_dsi_ops *cur_dsi_ops; + +int register_dsi_ops(struct mipi_dsi_ops *ops) { + + int i = 0; + for(i = 0; i < MAX_DSI_CHIPS; i++) { + if(!dsi_ops[i]) { + dsi_ops[i] = ops; + break; + } + } + if(i == MAX_DSI_CHIPS) { + printk("dsi ops support 5 chips at most\n"); + return -1; + } + return 0; +} +EXPORT_SYMBOL(register_dsi_ops); + + +int del_dsi_ops(struct mipi_dsi_ops *ops) { + + int i = 0; + for(i = 0; i < MAX_DSI_CHIPS; i++) { + if(dsi_ops[i] == ops) { + dsi_ops[i] = NULL; + break; + } + } + if(cur_dsi_ops == ops) + cur_dsi_ops = NULL; + if(i == MAX_DSI_CHIPS) { + printk("dsi ops not found\n"); + return -1; + } + return 0; +} +EXPORT_SYMBOL(del_dsi_ops); + +int dsi_probe_current_chip(void) { + + u32 i = 0, id; + struct mipi_dsi_ops *ops = NULL; + if(cur_dsi_ops) + return 0; + for(i = 0; i < MAX_DSI_CHIPS; i++) { + if(dsi_ops[i]) { + ops = dsi_ops[i]; + id = ops->get_id(); + if(id == ops->id) { + cur_dsi_ops = ops; + printk("load mipi dsi chip:%s id:%08x\n", ops->name, ops->id); + break; + } else { + printk("mipi dsi chip is not found, read id:%08x, but %08x is correct\n", id, ops->id); + dsi_ops[i] = NULL; + cur_dsi_ops = NULL; + } + } + } + if(i == MAX_DSI_CHIPS) + printk("no mipi dsi chip\n"); + + return 0; +} +EXPORT_SYMBOL(dsi_probe_current_chip); + +int dsi_power_up(void) { + + if(!cur_dsi_ops) + return -1; + if(cur_dsi_ops->power_up) + cur_dsi_ops->power_up(); + return 0; +} +EXPORT_SYMBOL(dsi_power_up); + + +int dsi_power_off(void) { + + if(!cur_dsi_ops) + return -1; + if(cur_dsi_ops->power_down) + cur_dsi_ops->power_down(); + return 0; +} +EXPORT_SYMBOL(dsi_power_off); + +int dsi_set_regs(void *array, int n) { + + if(!cur_dsi_ops) + return -1; + if(cur_dsi_ops->dsi_set_regs) + cur_dsi_ops->dsi_set_regs(array, n); + return 0; +} +EXPORT_SYMBOL(dsi_set_regs); + +int dsi_init(void *array, int n) { + + if(!cur_dsi_ops) + return -1; + if(cur_dsi_ops->dsi_init) + cur_dsi_ops->dsi_init(array, n); + return 0; +} +EXPORT_SYMBOL(dsi_init); + + +int dsi_send_dcs_packet(unsigned char *packet, int n) { + + if(!cur_dsi_ops) + return -1; + if(cur_dsi_ops->dsi_send_dcs_packet) + cur_dsi_ops->dsi_send_dcs_packet(packet, n); + return 0; +} +EXPORT_SYMBOL(dsi_send_dcs_packet); + + +int dsi_read_dcs_packet(unsigned char *packet, int n) { + + if(!cur_dsi_ops) + return -1; + if(cur_dsi_ops->dsi_read_dcs_packet) + cur_dsi_ops->dsi_read_dcs_packet(packet, n); + return 0; +} +EXPORT_SYMBOL(dsi_read_dcs_packet); + + +int dsi_send_packet(void *packet, int n) { + + if(!cur_dsi_ops) + return -1; + if(cur_dsi_ops->dsi_send_packet) + cur_dsi_ops->dsi_send_packet(packet, n); + + return 0; +} +EXPORT_SYMBOL(dsi_send_packet); diff --git a/drivers/video/rockchip/transmitter/mipi_dsi.h b/drivers/video/rockchip/transmitter/mipi_dsi.h new file mode 100644 index 000000000000..b0d54f803539 --- /dev/null +++ b/drivers/video/rockchip/transmitter/mipi_dsi.h @@ -0,0 +1,136 @@ + +//drivers/video/display/transmitter/mipi_dsi.h + +#ifndef MIPI_DSI_H_ +#define MIPI_DSI_H_ + +#include +#include +#include +#include +#include + + +//DSI DATA TYPE +#define DTYPE_DCS_SWRITE_0P 0X05 +#define DTYPE_DCS_SWRITE_1P 0X15 +#define DTYPE_DCS_LWRITE 0X39 +#define DTYPE_GEN_LWRITE 0X29 +#define DTYPE_GEN_SWRITE_2P 0X23 +#define DTYPE_GEN_SWRITE_1P 0X13 +#define DTYPE_GEN_SWRITE_0P 0X03 + +//Video Mode +#define VM_NBMWSP 0X00 //Non burst mode with sync pulses +#define VM_NBMWSE 0X01 //Non burst mode with sync events +#define VM_BM 0X02 //Burst mode + +//Video Pixel Format +#define VPF_16BPP 0X00 +#define VPF_18BPP 0X01 //packed +#define VPF_18BPPL 0X02 //loosely packed +#define VPF_24BPP 0X03 + +//iomux +#define OLD_RK_IOMUX 0 + +struct spi_t { + int cs; +#if OLD_RK_IOMUX + char* cs_mux_name; +#endif + int sck; +#if OLD_RK_IOMUX + char* sck_mux_name; +#endif + int miso; +#if OLD_RK_IOMUX + char* miso_mux_name; +#endif + int mosi; +#if OLD_RK_IOMUX + char* mosi_mux_name; +#endif +}; + +struct power_t { + int enable_pin; //gpio that control power +#if OLD_RK_IOMUX + char* mux_name; + u32 mux_mode; +#endif + u32 effect_value; + + char *name; + u32 voltage; + int (*enable)(void *); + int (*disable)(void *); +}; + +struct reset_t { + int reset_pin; //gpio that control reset +#if OLD_RK_IOMUX + char* mux_name; + u32 mux_mode; +#endif + u32 effect_value; + + u32 time_before_reset; //ms + u32 time_after_reset; + + int (*do_reset)(void *); +}; + +struct tc358768_t { + u32 id; + struct reset_t reset; + struct power_t vddc; + struct power_t vddio; + struct power_t vdd_mipi; + struct i2c_client *client; + int (*gpio_init)(void *); + int (*gpio_deinit)(void *); + int (*power_up)(void); + int (*power_down)(void); +}; + + +struct ssd2828_t { + u32 id; + struct reset_t reset; + struct power_t shut; + struct power_t vddio; + struct power_t vdd_mipi; + + struct spi_t spi; + int (*gpio_init)(void *); + int (*gpio_deinit)(void *); + int (*power_up)(void); + int (*power_down)(void); +}; + +struct mipi_dsi_ops { + u32 id; + char *name; + int (*get_id)(void); + int (*dsi_init)(void *, int n); + int (*dsi_set_regs)(void *, int n); + int (*dsi_send_dcs_packet)(unsigned char *, int n); + int (*dsi_read_dcs_packet)(unsigned char *, int n); + int (*dsi_send_packet)(void *, int n); + int (*power_up)(void); + int (*power_down)(void); +}; + + +int register_dsi_ops(struct mipi_dsi_ops *ops); +int del_dsi_ops(struct mipi_dsi_ops *ops); +int dsi_power_up(void); +int dsi_power_off(void); +int dsi_probe_current_chip(void); +int dsi_init(void *array, int n); +int dsi_set_regs(void *array, int n); +int dsi_send_dcs_packet(unsigned char *packet, int n); +int dsi_read_dcs_packet(unsigned char *packet, int n); +int dsi_send_packet(void *packet, int n); +#endif /* end of MIPI_DSI_H_ */ diff --git a/drivers/video/rockchip/transmitter/rk2928_lvds.c b/drivers/video/rockchip/transmitter/rk2928_lvds.c new file mode 100644 index 000000000000..1c130cea26ea --- /dev/null +++ b/drivers/video/rockchip/transmitter/rk2928_lvds.c @@ -0,0 +1,63 @@ +#include +#include +#include +#include +#include +#include "rk_lvds.h" + +static void rk_output_lvds(rk_screen *screen) +{ + LVDSWrReg(m_PDN_CBG(1)|m_PD_PLL(0)|m_PDN(1)|m_OEN(0) \ + |m_DS(DS_10PF)|m_MSBSEL(DATA_D0_MSB) \ + |m_OUT_FORMAT(screen->hw_format) \ + |m_LCDC_SEL(screen->lcdc_id)); + + printk("%s>>connect to lcdc output interface%d\n",__func__,screen->lcdc_id); +} + +static void rk_output_lvttl(rk_screen *screen) +{ + LVDSWrReg(m_PDN_CBG(0)|m_PD_PLL(1)|m_PDN(0)|m_OEN(1) \ + |m_DS(DS_10PF)|m_MSBSEL(DATA_D0_MSB) \ + |m_OUT_FORMAT(screen->hw_format) \ + |m_LCDC_SEL(screen->lcdc_id)); + printk("%s>>connect to lcdc output interface%d\n",__func__,screen->lcdc_id); +} + +static void rk_output_disable(void) +{ + LVDSWrReg(m_PDN_CBG(0)|m_PD_PLL(1)|m_PDN(0)|m_OEN(0)); + printk("%s: reg = 0x%x\n", __func__, LVDSRdReg()); +} + +static int rk_lvds_set_param(rk_screen *screen,bool enable ) +{ + if(OUT_ENABLE == enable){ + switch(screen->type){ + case SCREEN_LVDS: + rk_output_lvds(screen); + + break; + case SCREEN_RGB: + rk_output_lvttl(screen); + break; + default: + printk("%s>>>>LVDS not support this screen type %d,power down LVDS\n",__func__,screen->type); + rk_output_disable(); + break; + } + }else{ + rk_output_disable(); + } + return 0; +} + +int rk_lvds_register(rk_screen *screen) +{ + if(screen->sscreen_set == NULL) + screen->sscreen_set = rk_lvds_set_param; + + rk_lvds_set_param(screen , OUT_ENABLE); + + return 0; +} diff --git a/drivers/video/rockchip/transmitter/rk2928_lvds.h b/drivers/video/rockchip/transmitter/rk2928_lvds.h new file mode 100644 index 000000000000..6cd2f889afd6 --- /dev/null +++ b/drivers/video/rockchip/transmitter/rk2928_lvds.h @@ -0,0 +1,49 @@ +#ifndef RK_LVDS_H_ +#define RK_LVDS_H + +#define LVDS_CON0_OFFSET 0x150 +#define LVDS_CON0_REG (RK2928_GRF_BASE + LVDS_CON0_OFFSET) + +#define LVDSRdReg() __raw_readl(LVDS_CON0_REG) +#define LVDSWrReg(val) __raw_writel( val ,LVDS_CON0_REG) + +#define m_value(x,offset,mask) \ + ((mask<<(offset+16)) | (x&mask)< +#include +#include +#include +#include +#include "rk610_lcd.h" +#include +#include +#include "../../rockchip/hdmi/rk_hdmi.h" + +static struct rk610_lcd_info *g_lcd_inf = NULL; +//static int rk610_scaler_read_p0_reg(struct i2c_client *client, char reg, char *val) +//{ + //return i2c_master_reg8_recv(client, reg, val, 1, 100*1000) > 0? 0: -EINVAL; +//} + +static int rk610_scaler_write_p0_reg(struct i2c_client *client, char reg, char *val) +{ + return i2c_master_reg8_send(client, reg, val, 1, 100*1000) > 0? 0: -EINVAL; +} +static void rk610_scaler_pll_enable(struct i2c_client *client) +{ + char c; + RK610_DBG(&client->dev,"%s \n",__FUNCTION__); + + g_lcd_inf->scl_inf.pll_pwr = ENABLE; + + c = S_PLL_PWR(0)|S_PLL_RESET(0)|S_PLL_BYPASS(0); + rk610_scaler_write_p0_reg(client, S_PLL_CON2, &c); +} +static void rk610_scaler_pll_disable(struct i2c_client *client) +{ + char c; + RK610_DBG(&client->dev,"%s \n",__FUNCTION__); + + g_lcd_inf->scl_inf.pll_pwr = DISABLE; + + c = S_PLL_PWR(1) |S_PLL_RESET(0) |S_PLL_BYPASS(1); + rk610_scaler_write_p0_reg(client, S_PLL_CON2, &c); +} +static void rk610_scaler_enable(struct i2c_client *client) +{ + char c; + bool den_inv = 0,hv_sync_inv = 0,clk_inv = 0; + RK610_DBG(&client->dev,"%s \n",__FUNCTION__); + g_lcd_inf->scl_inf.scl_pwr = ENABLE; + #if defined(CONFIG_HDMI_DUAL_DISP) || defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF) + if(g_lcd_inf->screen !=NULL){ + den_inv = g_lcd_inf->screen->s_den_inv; + hv_sync_inv = g_lcd_inf->screen->s_hv_sync_inv; + clk_inv = g_lcd_inf->screen->s_clk_inv; + } + #endif + c= SCL_BYPASS(0) |SCL_DEN_INV(den_inv) |SCL_H_V_SYNC_INV(hv_sync_inv) |SCL_OUT_CLK_INV(clk_inv) |SCL_ENABLE(ENABLE); + rk610_scaler_write_p0_reg(client, SCL_CON0, &c); +} +static void rk610_scaler_disable(struct i2c_client *client) +{ + char c; + bool den_inv = 0,hv_sync_inv = 0,clk_inv = 0; + RK610_DBG(&client->dev,"%s \n",__FUNCTION__); + + g_lcd_inf->scl_inf.scl_pwr = DISABLE; + #if defined(CONFIG_HDMI_DUAL_DISP) || defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF) + if(g_lcd_inf->screen !=NULL){ + den_inv = g_lcd_inf->screen->s_den_inv; + hv_sync_inv = g_lcd_inf->screen->s_hv_sync_inv; + clk_inv = g_lcd_inf->screen->s_clk_inv; + } + #endif + c= SCL_BYPASS(1) |SCL_DEN_INV(den_inv) |SCL_H_V_SYNC_INV(hv_sync_inv) |SCL_OUT_CLK_INV(clk_inv) |SCL_ENABLE(DISABLE); + rk610_scaler_write_p0_reg(client, SCL_CON0, &c); +} + +static int rk610_output_config(struct i2c_client *client,struct rk29fb_screen *screen,int mode) +{ + char c=0; + RK610_DBG(&client->dev,"%s \n",__FUNCTION__); + if(SCREEN_LVDS == screen->type){ + if(mode == LCD_OUT_SCL || mode == LCD_OUT_BYPASS){ + c = LVDS_OUT_CLK_PIN(0) |LVDS_OUT_CLK_PWR_PIN(1) |LVDS_PLL_PWR_PIN(0) \ + |LVDS_LANE_IN_FORMAT(DATA_D0_MSB) |LVDS_INPUT_SOURCE(FROM_LCD0_OR_SCL) \ + |LVDS_OUTPUT_FORMAT(screen->hw_format) | LVDS_BIASE_PWR(1); + rk610_scaler_write_p0_reg(client, LVDS_CON0, &c); + c = LVDS_OUT_ENABLE(0x0) |LVDS_TX_PWR_ENABLE(0x0); + rk610_scaler_write_p0_reg(client, LVDS_CON1, &c); + } + else{ + c = LVDS_OUT_CLK_PIN(0) |LVDS_OUT_CLK_PWR_PIN(0) |LVDS_PLL_PWR_PIN(1) \ + |LVDS_LANE_IN_FORMAT(DATA_D0_MSB) |LVDS_INPUT_SOURCE(FROM_LCD0_OR_SCL) \ + |LVDS_OUTPUT_FORMAT(screen->hw_format) | LVDS_BIASE_PWR(0); + rk610_scaler_write_p0_reg(client, LVDS_CON0, &c); + c = LVDS_OUT_ENABLE(0xf) |LVDS_TX_PWR_ENABLE(0xf); + rk610_scaler_write_p0_reg(client, LVDS_CON1, &c); + + } + }else if(SCREEN_RGB == screen->type){ + if(mode == LCD_OUT_SCL || mode == LCD_OUT_BYPASS){ + c = LCD1_OUT_ENABLE(LCD1_AS_OUT) | LCD1_OUT_SRC((mode == LCD_OUT_SCL)?LCD1_FROM_SCL : LCD1_FROM_LCD0); + rk610_scaler_write_p0_reg(client, LCD1_CON, &c); + } + else { + c = LCD1_OUT_ENABLE(LCD1_AS_IN); + rk610_scaler_write_p0_reg(client, LCD1_CON, &c); + } + } + return 0; +} +#if defined(CONFIG_HDMI_DUAL_DISP) || defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF) +static int rk610_scaler_pll_set(struct i2c_client *client,struct rk29fb_screen *screen,u32 clkin ) +{ + char c=0; + char M=0,N=0,OD=0; + RK610_DBG(&client->dev,"%s \n",__FUNCTION__); + /***************SET SCALER PLL FROM CLKIN ,DIV 0*/ + if(screen->s_pixclock != 0){ + OD = (screen->s_pixclock)&0x3; + N = (screen->s_pixclock >>4)&0xf; + M = (screen->s_pixclock >>8)&0xff; + }else { + RK610_ERR(&client->dev,"RK610 Scaler pll not support rate \n"); + } + c = S_PLL_FROM_DIV<<3 | S_PLL_DIV(0); + rk610_scaler_write_p0_reg(client, CLOCK_CON0, &c); + + c = S_DIV_N(N)| S_DIV_OD(OD); + rk610_scaler_write_p0_reg(client, S_PLL_CON0, &c); + c = S_DIV_M(M); + rk610_scaler_write_p0_reg(client, S_PLL_CON1, &c); + rk610_scaler_pll_enable(client); + return 0; +} + + +static int scale_hv_factor(struct i2c_client *client ,u32 Hin_act, u32 Hout_act, u32 Vin_act, u32 Vout_act) + { + char c; + u32 hfactor_f,vfactor_f,scl_factor_f; + int hfactor; + int vfactor; + struct scl_hv_info HV2; + hfactor_f = ((Hin_act-1)*4096)/(Hout_act-1); + if(hfactor_f==4096) + {hfactor = 0x1000;} + else if(hfactor_f>(int)hfactor_f) + {hfactor = (int)hfactor_f+1;} + else + {hfactor = (int)hfactor_f;} + + scl_factor_f = Vin_act/Vout_act; + if(scl_factor_f<2) + {vfactor_f = ((Vin_act-1)*4096)/(Vout_act-1);} + else + {vfactor_f = ((Vin_act-2)*4096)/(Vout_act-1);} + if(vfactor_f==4096) + {vfactor = 0x1000;} + else if(vfactor_f>(int)vfactor_f) + {vfactor = (int)vfactor_f+1;} + else + {vfactor = (int)vfactor_f;} + + HV2.scl_h= hfactor; + HV2.scl_v= vfactor; + /* SCL FACTOR */ + c = SCL_H_FACTOR_LSB(HV2.scl_h); + rk610_scaler_write_p0_reg(client, SCL_CON1, &c); + c = SCL_H_FACTOR_MSB(HV2.scl_h); + rk610_scaler_write_p0_reg(client, SCL_CON2, &c); + + c = SCL_V_FACTOR_LSB(HV2.scl_v); + rk610_scaler_write_p0_reg(client, SCL_CON3, &c); + c = SCL_V_FACTOR_MSB(HV2.scl_v); + rk610_scaler_write_p0_reg(client, SCL_CON4, &c); + return 0; + } + +static int rk610_scaler_fator_config(struct i2c_client *client ,struct rk29fb_screen *screen) +{ + switch(screen->hdmi_resolution){ + case HDMI_1920x1080p_60Hz: + case HDMI_1920x1080p_50Hz: + rk610_scaler_pll_set(client,screen,148500000); + /***************set scaler factor********************/ + scale_hv_factor(client,1920,screen->x_res,1080,screen->y_res); + break; + case HDMI_1280x720p_60Hz: + case HDMI_1280x720p_50Hz: + rk610_scaler_pll_set(client,screen,74250000); + /***************set scaler factor********************/ + scale_hv_factor(client,1280,screen->x_res,720,screen->y_res); + break; + case HDMI_720x576p_50Hz_16_9: + case HDMI_720x576p_50Hz_4_3: + rk610_scaler_pll_set(client,screen,27000000); + /***************set scaler factor********************/ + scale_hv_factor(client,720,screen->x_res,576,screen->y_res); + break; + case HDMI_720x480p_60Hz_16_9: + case HDMI_720x480p_60Hz_4_3: + rk610_scaler_pll_set(client,screen,27000000); + /***************set scaler factor********************/ + scale_hv_factor(client,720,screen->x_res,480,screen->y_res); + break; + default : + RK610_ERR(&client->dev,"RK610 not support dual display at hdmi resolution=%d \n",screen->hdmi_resolution); + return -1; + break; + } + return 0; +} +static int rk610_scaler_output_timing_config(struct i2c_client *client,struct rk29fb_screen *screen) +{ + char c; + int h_st = screen->s_hsync_st; + int hs_end = screen->s_hsync_len; + int h_act_st = hs_end + screen->s_left_margin; + int xres = screen->x_res; + int h_act_end = h_act_st + xres; + int h_total = h_act_end + screen->s_right_margin; + int v_st = screen->s_vsync_st; + int vs_end = screen->s_vsync_len; + int v_act_st = vs_end + screen->s_upper_margin; + int yres = screen->y_res; + int v_act_end = v_act_st + yres; + int v_total = v_act_end + screen->s_lower_margin; + + /* SCL display Frame start point */ + c = SCL_DSP_HST_LSB(h_st); + rk610_scaler_write_p0_reg(client, SCL_CON5, &c); + c = SCL_DSP_HST_MSB(h_st); + rk610_scaler_write_p0_reg(client, SCL_CON6, &c); + + c = SCL_DSP_VST_LSB(v_st); + rk610_scaler_write_p0_reg(client, SCL_CON7, &c); + c = SCL_DSP_VST_MSB(v_st); + rk610_scaler_write_p0_reg(client, SCL_CON8, &c); + /* SCL output timing */ + + c = SCL_DSP_HTOTAL_LSB(h_total); + rk610_scaler_write_p0_reg(client, SCL_CON9, &c); + c = SCL_DSP_HTOTAL_MSB(h_total); + rk610_scaler_write_p0_reg(client, SCL_CON10, &c); + + c = SCL_DSP_HS_END(hs_end); + rk610_scaler_write_p0_reg(client, SCL_CON11, &c); + + c = SCL_DSP_HACT_ST_LSB(h_act_st); + rk610_scaler_write_p0_reg(client, SCL_CON12, &c); + c = SCL_DSP_HACT_ST_MSB(h_act_st); + rk610_scaler_write_p0_reg(client, SCL_CON13, &c); + + c = SCL_DSP_HACT_END_LSB(h_act_end); + rk610_scaler_write_p0_reg(client, SCL_CON14, &c); + c = SCL_DSP_HACT_END_MSB(h_act_end); + rk610_scaler_write_p0_reg(client, SCL_CON15, &c); + + c = SCL_DSP_VTOTAL_LSB(v_total); + rk610_scaler_write_p0_reg(client, SCL_CON16, &c); + c = SCL_DSP_VTOTAL_MSB(v_total); + rk610_scaler_write_p0_reg(client, SCL_CON17, &c); + + c = SCL_DSP_VS_END(vs_end); + rk610_scaler_write_p0_reg(client, SCL_CON18, &c); + + c = SCL_DSP_VACT_ST(v_act_st); + rk610_scaler_write_p0_reg(client, SCL_CON19, &c); + + c = SCL_DSP_VACT_END_LSB(v_act_end); + rk610_scaler_write_p0_reg(client, SCL_CON20, &c); + c = SCL_DSP_VACT_END_MSB(v_act_end); + rk610_scaler_write_p0_reg(client, SCL_CON21, &c); + + c = SCL_H_BORD_ST_LSB(h_act_st); + rk610_scaler_write_p0_reg(client, SCL_CON22, &c); + c = SCL_H_BORD_ST_MSB(h_act_st); + rk610_scaler_write_p0_reg(client, SCL_CON23, &c); + + c = SCL_H_BORD_END_LSB(h_act_end); + rk610_scaler_write_p0_reg(client, SCL_CON24, &c); + c = SCL_H_BORD_END_MSB(h_act_end); + rk610_scaler_write_p0_reg(client, SCL_CON25, &c); + + c = SCL_V_BORD_ST(v_act_st); + rk610_scaler_write_p0_reg(client, SCL_CON26, &c); + + c = SCL_V_BORD_END_LSB(v_act_end); + rk610_scaler_write_p0_reg(client, SCL_CON27, &c); + c = SCL_V_BORD_END_MSB(v_act_end); + rk610_scaler_write_p0_reg(client, SCL_CON28, &c); + + return 0; +} +static int rk610_scaler_chg(struct i2c_client *client ,struct rk29fb_screen *screen) +{ + + RK610_DBG(&client->dev,"%s screen->hdmi_resolution=%d\n",__FUNCTION__,screen->hdmi_resolution); + rk610_scaler_fator_config(client,screen); + rk610_scaler_enable(client); + rk610_scaler_output_timing_config(client,screen); + + return 0; + +} +#endif +static int rk610_lcd_scaler_bypass(struct i2c_client *client,bool enable)//enable:0 bypass 1: scale +{ + RK610_DBG(&client->dev,"%s \n",__FUNCTION__); + + rk610_scaler_disable(client); + rk610_scaler_pll_disable(client); + + return 0; +} + +#ifdef CONFIG_HAS_EARLYSUSPEND +static void rk610_lcd_early_suspend(struct early_suspend *h) +{ + struct i2c_client *client = g_lcd_inf->client; + char c; + RK610_DBG(&client->dev,"%s \n",__FUNCTION__); + if(g_lcd_inf->screen != NULL){ + rk610_output_config(client,g_lcd_inf->screen,LCD_OUT_DISABLE); + } + + if(ENABLE == g_lcd_inf->scl_inf.scl_pwr){ + c= SCL_BYPASS(1) |SCL_DEN_INV(0) |SCL_H_V_SYNC_INV(0) |SCL_OUT_CLK_INV(0) |SCL_ENABLE(DISABLE); + rk610_scaler_write_p0_reg(client, SCL_CON0, &c); + } + if(ENABLE == g_lcd_inf->scl_inf.pll_pwr ){ + c = S_PLL_PWR(1) |S_PLL_RESET(0) |S_PLL_BYPASS(1); + rk610_scaler_write_p0_reg(client, S_PLL_CON2, &c); + } +} + +static void rk610_lcd_early_resume(struct early_suspend *h) +{ + struct i2c_client *client = g_lcd_inf->client; + char c; + RK610_DBG(&client->dev,"%s \n",__FUNCTION__); + + if(g_lcd_inf->screen != NULL){ + rk610_output_config(client,g_lcd_inf->screen,g_lcd_inf->disp_mode); + } + if(ENABLE == g_lcd_inf->scl_inf.scl_pwr){ + c= SCL_BYPASS(0) |SCL_DEN_INV(0) |SCL_H_V_SYNC_INV(0) |SCL_OUT_CLK_INV(0) |SCL_ENABLE(ENABLE); + rk610_scaler_write_p0_reg(client, SCL_CON0, &c); + } + if(ENABLE == g_lcd_inf->scl_inf.pll_pwr ){ + c = S_PLL_PWR(1) |S_PLL_RESET(0) |S_PLL_BYPASS(1); + rk610_scaler_write_p0_reg(client, S_PLL_CON2, &c); + } +} +#endif +int rk610_lcd_scaler_set_param(struct rk29fb_screen *screen,bool enable )//enable:0 bypass 1: scale +{ + int ret=0; + struct i2c_client *client = g_lcd_inf->client; + if(client == NULL){ + printk("%s client == NULL FAIL\n",__FUNCTION__); + return -1; + } + if(screen == NULL){ + printk("%s screen == NULL FAIL\n",__FUNCTION__); + return -1; + } + RK610_DBG(&client->dev,"%s \n",__FUNCTION__); + + g_lcd_inf->screen = screen; + +#if defined(CONFIG_HDMI_DUAL_DISP) || defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF) + if(enable == 1){ + g_lcd_inf->disp_mode = LCD_OUT_SCL; + rk610_output_config(client,screen,LCD_OUT_SCL); + ret = rk610_scaler_chg(client,screen); + } + else +#endif + { + g_lcd_inf->disp_mode = LCD_OUT_BYPASS; + rk610_output_config(client,screen,LCD_OUT_BYPASS); + ret = rk610_lcd_scaler_bypass(client,enable); + } + return ret; +} +int rk610_lcd_init(struct rk610_core_info *rk610_core_info) +{ + if(rk610_core_info->client == NULL){ + printk("%s client == NULL FAIL\n",__FUNCTION__); + return -1; + } + RK610_DBG(&rk610_core_info->client->dev,"%s \n",__FUNCTION__); + + g_lcd_inf = kmalloc(sizeof(struct rk610_lcd_info), GFP_KERNEL); + if(!g_lcd_inf) + { + dev_err(&rk610_core_info->client->dev, ">> rk610 inf kmalloc fail!"); + return -ENOMEM; + } + memset(g_lcd_inf, 0, sizeof(struct rk610_lcd_info)); + + g_lcd_inf->client= rk610_core_info->client; + + rk610_core_info->lcd_pdata = (void *)g_lcd_inf; +#ifdef CONFIG_HAS_EARLYSUSPEND + g_lcd_inf->early_suspend.suspend = rk610_lcd_early_suspend; + g_lcd_inf->early_suspend.resume = rk610_lcd_early_resume; + g_lcd_inf->early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB- 1; + register_early_suspend(&g_lcd_inf->early_suspend); +#endif + g_lcd_inf->scl_inf.pll_pwr = DISABLE; + g_lcd_inf->scl_inf.scl_pwr = DISABLE; + g_lcd_inf->disp_mode = LCD_OUT_BYPASS; + return 0; +} diff --git a/drivers/video/rockchip/transmitter/rk610_lcd.h b/drivers/video/rockchip/transmitter/rk610_lcd.h new file mode 100644 index 000000000000..7b3376c69955 --- /dev/null +++ b/drivers/video/rockchip/transmitter/rk610_lcd.h @@ -0,0 +1,230 @@ +#ifndef _RK610_LCD_H +#define _RK610_LCD_H +#include +#include +#define ENABLE 1 +#define DISABLE 0 + +//LVDS lane input format +#define DATA_D0_MSB 0 +#define DATA_D7_MSB 1 +//LVDS input source +#define FROM_LCD1 0 +#define FROM_LCD0_OR_SCL 1 + +/* LCD1 config */ +#define LCD1_AS_IN 0 +#define LCD1_AS_OUT 1 + +//LCD1 output source +#define LCD1_FROM_LCD0 0 +#define LCD1_FROM_SCL 1 + +//SCALER config +#define NOBYPASS 0 +#define BYPASS 1 + +//SCALER PLL config +#define S_PLL_PWR_ON 0 +#define S_PLL_PWR_DOWN 1 + +/* clock config */ +#define S_PLL_FROM_DIV 0 +#define S_PLL_FROM_CLKIN 1 +#define S_PLL_DIV(x) ((x)&0x7) +/*********S_PLL_CON************/ +//S_PLL_CON0 +#define S_DIV_N(x) (((x)&0xf)<<4) +#define S_DIV_OD(x) (((x)&3)<<0) +//S_PLL_CON1 +#define S_DIV_M(x) ((x)&0xff) +//S_PLL_CON2 +#define S_PLL_UNLOCK (0<<7) //0:unlock 1:pll_lock +#define S_PLL_LOCK (1<<7) //0:unlock 1:pll_lock +#define S_PLL_PWR(x) (((x)&1)<<2) //0:POWER UP 1:POWER DOWN +#define S_PLL_RESET(x) (((x)&1)<<1) //0:normal 1:reset M/N dividers +#define S_PLL_BYPASS(x) (((x)&1)<<0) //0:normal 1:bypass +//LVDS_CON0 +#define LVDS_OUT_CLK_PIN(x) (((x)&1)<<7) //clk enable pin, 0: enable +#define LVDS_OUT_CLK_PWR_PIN(x) (((x)&1)<<6) //clk pwr enable pin, 1: enable +#define LVDS_PLL_PWR_PIN(x) (((x)&1)<<5) //pll pwr enable pin, 0:enable +#define LVDS_BIASE_PWR(x) (((x)&1)<<4) //0: power down 1: normal work +#define LVDS_LANE_IN_FORMAT(x) (((x)&1)<<3) //0: msb on D0 1:msb on D7 +#define LVDS_INPUT_SOURCE(x) (((x)&1)<<2) //0: from lcd1 1:from lcd0 or scaler +#define LVDS_OUTPUT_FORMAT(x) (((x)&3)<<0) //00:8bit format-1 01:8bit format-2 10:8bit format-3 11:6bit format +//LVDS_CON1 +#define LVDS_OUT_ENABLE(x) (((x)&0xf)<<4) //0:output enable 1:output disable +#define LVDS_TX_PWR_ENABLE(x) (((x)&0xf)<<0) //0:working mode 1:power down +//LCD1_CON +#define LCD1_OUT_ENABLE(x) (((x)&1)<<1) //0:lcd1 as input 1:lcd1 as output +#define LCD1_OUT_SRC(x) (((x)&1)<<0) //0:from lcd0 1:from scaler +//SCL_CON0 +#define SCL_BYPASS(x) (((x)&1)<<4) //0:not bypass 1:bypass +#define SCL_DEN_INV(x) (((x)&1)<<3) //scl_den_inv +#define SCL_H_V_SYNC_INV(x) (((x)&1)<<2) //scl_sync_inv +#define SCL_OUT_CLK_INV(x) (((x)&1)<<1) //scl_dclk_inv +#define SCL_ENABLE(x) (((x)&1)<<0) //scaler enable +//SCL_CON1 +#define SCL_H_FACTOR_LSB(x) ((x)&0xff) //scl_h_factor[7:0] +//SCL_CON2 +#define SCL_H_FACTOR_MSB(x) (((x)>>8)&0x3f) //scl_h_factor[13:8] +//SCL_CON3 +#define SCL_V_FACTOR_LSB(x) ((x)&0xff) //scl_v_factor[7:0] +//SCL_CON4 +#define SCL_V_FACTOR_MSB(x) (((x)>>8)&0x3f) //scl_v_factor[13:8] +//SCL_CON5 +#define SCL_DSP_HST_LSB(x) ((x)&0xff) //dsp_frame_hst[7:0] +//SCL_CON6 +#define SCL_DSP_HST_MSB(x) (((x)>>8)&0xf) //dsp_frame_hst[11:8] +//SCL_CON7 +#define SCL_DSP_VST_LSB(x) ((x)&0xff) //dsp_frame_vst[7:0] +//SCL_CON8 +#define SCL_DSP_VST_MSB(x) (((x)>>8)&0xf) //dsp_frame_vst[11:8] +//SCL_CON9 +#define SCL_DSP_HTOTAL_LSB(x) ((x)&0xff) //dsp_frame_htotal[7:0] +//SCL_CON10 +#define SCL_DSP_HTOTAL_MSB(x) (((x)>>8)&0xf) //dsp_frame_htotal[11:8] +//SCL_CON11 +#define SCL_DSP_HS_END(x) ((x)&0xff) //dsp_hs_end +//SCL_CON12 +#define SCL_DSP_HACT_ST_LSB(x) ((x)&0xff) //dsp_hact_st[7:0] +//SCL_CON13 +#define SCL_DSP_HACT_ST_MSB(x) (((x)>>8)&0x3) //dsp_hact_st[9:8] +//SCL_CON14 +#define SCL_DSP_HACT_END_LSB(x) ((x)&0xff) //dsp_hact_end[7:0] +//SCL_CON15 +#define SCL_DSP_HACT_END_MSB(x) (((x)>>8)&0xf) //dsp_frame_htotal[11:8] +//SCL_CON16 +#define SCL_DSP_VTOTAL_LSB(x) ((x)&0xff) //dsp_frame_vtotal[7:0] +//SCL_CON17 +#define SCL_DSP_VTOTAL_MSB(x) (((x)>>8)&0xf) //dsp_frame_vtotal[11:8] +//SCL_CON18 +#define SCL_DSP_VS_END(x) ((x)&0xff) //dsp_vs_end +//SCL_CON19 +#define SCL_DSP_VACT_ST(x) ((x)&0xff) //dsp_vact_st[7:0] +//SCL_CON20 +#define SCL_DSP_VACT_END_LSB(x) ((x)&0xff) //dsp_vact_end[7:0] +//SCL_CON21 +#define SCL_DSP_VACT_END_MSB(x) (((x)>>8)&0xf) //dsp_frame_vtotal[11:8] +//SCL_CON22 +#define SCL_H_BORD_ST_LSB(x) ((x)&0xff) //dsp_hbord_st[7:0] +//SCL_CON23 +#define SCL_H_BORD_ST_MSB(x) (((x)>>8)&0x3) //dsp_hbord_st[9:8] +//SCL_CON24 +#define SCL_H_BORD_END_LSB(x) ((x)&0xff) //dsp_hbord_end[7:0] +//SCL_CON25 +#define SCL_H_BORD_END_MSB(x) (((x)>>8)&0xf) //dsp_hbord_end[11:8] +//SCL_CON26 +#define SCL_V_BORD_ST(x) ((x)&0xff) //dsp_vbord_st[7:0] +//SCL_CON27 +#define SCL_V_BORD_END_LSB(x) ((x)&0xff) //dsp_vbord_end[7:0] +//SCL_CON25 +#define SCL_V_BORD_END_MSB(x) (((x)>>8)&0xf) //dsp_vbord_end[11:8] + +/* Scaler PLL CONFIG */ +#define S_PLL_NO_1 0 +#define S_PLL_NO_2 1 +#define S_PLL_NO_4 2 +#define S_PLL_NO_8 3 +#define S_PLL_M(x) (((x)&0xff)<<8) +#define S_PLL_N(x) (((x)&0xf)<<4) +#define S_PLL_NO(x) ((S_PLL_NO_##x)&0x3) + +enum{ + HDMI_RATE_148500000, + HDMI_RATE_74250000, + HDMI_RATE_27000000, +}; +/* Scaler clk setting */ +#define SCALE_PLL(_parent_rate,_rate,_m,_n,_no) \ + HDMI_RATE_ ## _parent_rate ##_S_RATE_ ## _rate \ + = S_PLL_M(_m) | S_PLL_N(_n) | S_PLL_NO(_no) +#define SCALE_RATE(_parent_rate , _rate) \ + (HDMI_RATE_ ## _parent_rate ## _S_RATE_ ## _rate) + +enum{ + SCALE_PLL(148500000, 66000000, 16, 9, 4), + SCALE_PLL(148500000, 57375000, 17, 11, 4), + SCALE_PLL(148500000, 54000000, 16, 11, 4), + SCALE_PLL(148500000, 33000000, 16, 9, 8), + SCALE_PLL(148500000, 30375000, 18, 11, 8), + SCALE_PLL(148500000, 29700000, 16, 10, 8), + SCALE_PLL(148500000, 25312500, 15, 11, 8), + SCALE_PLL(148500000, 74250000, 12, 6, 4), + SCALE_PLL(148500000, 50625000, 15, 11, 4), + SCALE_PLL(148500000, 79199997, 32, 15, 4), + SCALE_PLL(148500000, 45375000, 22, 9, 8), + + SCALE_PLL(74250000, 66000000, 32, 9, 4), + SCALE_PLL(74250000, 57375000, 34, 11, 4), + SCALE_PLL(74250000, 54000000, 32, 11, 4), + SCALE_PLL(74250000, 33000000, 32, 9, 8), + SCALE_PLL(74250000, 30375000, 36, 11, 8), + SCALE_PLL(74250000, 25312500, 30, 11, 8), + SCALE_PLL(74250000, 74250000, 12, 3, 4), + SCALE_PLL(74250000, 67500000, 40, 11, 4), + SCALE_PLL(74250000, 50625000, 30, 11, 4), + SCALE_PLL(74250000, 79199997, 64,15,4), + SCALE_PLL(74250000, 44343750, 43, 9, 8), + + SCALE_PLL(27000000, 75000000, 100, 9, 4), + SCALE_PLL(27000000, 72000000, 32, 3, 4), + SCALE_PLL(27000000, 63281250, 75, 4, 8), + SCALE_PLL(27000000, 60000000, 80, 9, 4), + SCALE_PLL(27000000, 54375000, 145, 9, 8), + SCALE_PLL(27000000, 31500000, 28, 3, 8), + SCALE_PLL(27000000, 30000000, 80, 9, 8), + SCALE_PLL(27000000, 70312500, 125, 6, 8), + SCALE_PLL(27000000, 46875000, 125, 9, 8), + SCALE_PLL(27000000, 56250000, 25, 3, 4) +}; + +enum { + LCD_OUT_SCL, + LCD_OUT_BYPASS, + LCD_OUT_DISABLE, +}; +struct rk610_pll_info{ + u32 parent_rate; + u32 rate; + int m; + int n; + int od; +}; +struct lcd_mode_inf{ + int h_pw; + int h_bp; + int h_vd; + int h_fp; + int v_pw; + int v_bp; + int v_vd; + int v_fp; + int f_hst; + int f_vst; + struct rk610_pll_info pllclk; +}; +struct scl_hv_info{ + int scl_h ; + int scl_v; + }; + +struct scl_info{ + bool pll_pwr; + bool scl_pwr; + struct scl_hv_info scl_hv; +}; +struct rk610_lcd_info{ + int disp_mode; + + struct rk29fb_screen *screen; + struct scl_info scl_inf; + struct i2c_client *client; + +#ifdef CONFIG_HAS_EARLYSUSPEND + struct early_suspend early_suspend; +#endif +}; +extern int rk610_lcd_init(struct rk610_core_info *rk610_core_info); +extern int rk610_lcd_scaler_set_param(struct rk29fb_screen *screen,bool enable ); +#endif diff --git a/drivers/video/rockchip/transmitter/rk616_lvds.c b/drivers/video/rockchip/transmitter/rk616_lvds.c new file mode 100644 index 000000000000..fd1339481755 --- /dev/null +++ b/drivers/video/rockchip/transmitter/rk616_lvds.c @@ -0,0 +1,223 @@ +#include +#include +#include +#include +#include "rk616_lvds.h" + +struct rk616_lvds *g_lvds; + + +static int rk616_lvds_cfg(struct mfd_rk616 *rk616,rk_screen *screen) +{ + struct rk616_route *route = &rk616->route; + u32 val = 0; + int ret; + int odd = (screen->left_margin&0x01)?0:1; + + if(!route->lvds_en) //lvds port is not used ,power down lvds + { + val &= ~(LVDS_CH1TTL_EN | LVDS_CH0TTL_EN | LVDS_CH1_PWR_EN | + LVDS_CH0_PWR_EN | LVDS_CBG_PWR_EN); + val |= LVDS_PLL_PWR_DN | (LVDS_CH1TTL_EN << 16) | (LVDS_CH0TTL_EN << 16) | + (LVDS_CH1_PWR_EN << 16) | (LVDS_CH0_PWR_EN << 16) | + (LVDS_CBG_PWR_EN << 16) | (LVDS_PLL_PWR_DN << 16); + ret = rk616->write_dev(rk616,CRU_LVDS_CON0,&val); + + if(!route->lcd1_input) //set lcd1 port for output as RGB interface + { + val = (LCD1_INPUT_EN << 16); + ret = rk616->write_dev(rk616,CRU_IO_CON0,&val); + } + } + else + { + if(route->lvds_mode) //lvds mode + { + + if(route->lvds_ch_nr == 2) //dual lvds channel + { + val = 0; + val &= ~(LVDS_CH0TTL_EN | LVDS_CH1TTL_EN | LVDS_PLL_PWR_DN); + val = (LVDS_DCLK_INV)|(LVDS_CH1_PWR_EN) |(LVDS_CH0_PWR_EN) | LVDS_HBP_ODD(odd) | + (LVDS_CBG_PWR_EN) | (LVDS_CH_SEL) | (LVDS_OUT_FORMAT(screen->hw_format)) | + (LVDS_CH0TTL_EN << 16) | (LVDS_CH1TTL_EN << 16) |(LVDS_CH1_PWR_EN << 16) | + (LVDS_CH0_PWR_EN << 16) | (LVDS_CBG_PWR_EN << 16) | (LVDS_CH_SEL << 16) | + (LVDS_OUT_FORMAT_MASK) | (LVDS_DCLK_INV << 16) | (LVDS_PLL_PWR_DN << 16) | + (LVDS_HBP_ODD_MASK); + ret = rk616->write_dev(rk616,CRU_LVDS_CON0,&val); + + dev_info(rk616->dev,"rk616 use dual lvds channel.......\n"); + } + else //single lvds channel + { + val = 0; + val &= ~(LVDS_CH0TTL_EN | LVDS_CH1TTL_EN | LVDS_CH1_PWR_EN | LVDS_PLL_PWR_DN | LVDS_CH_SEL); //use channel 0 + val |= (LVDS_CH0_PWR_EN) |(LVDS_CBG_PWR_EN) | (LVDS_OUT_FORMAT(screen->hw_format)) | + (LVDS_CH0TTL_EN << 16) | (LVDS_CH1TTL_EN << 16) |(LVDS_CH0_PWR_EN << 16) | + (LVDS_DCLK_INV ) | (LVDS_CH0TTL_EN << 16) | (LVDS_CH1TTL_EN << 16) |(LVDS_CH0_PWR_EN << 16) | + (LVDS_CBG_PWR_EN << 16)|(LVDS_CH_SEL << 16) | (LVDS_PLL_PWR_DN << 16)| + (LVDS_OUT_FORMAT_MASK) | (LVDS_DCLK_INV << 16); + ret = rk616->write_dev(rk616,CRU_LVDS_CON0,&val); + + dev_info(rk616->dev,"rk616 use single lvds channel.......\n"); + + } + + } + else //mux lvds port to RGB mode + { + val &= ~(LVDS_CBG_PWR_EN| LVDS_CH1_PWR_EN | LVDS_CH0_PWR_EN); + val |= (LVDS_CH0TTL_EN)|(LVDS_CH1TTL_EN )|(LVDS_PLL_PWR_DN)| + (LVDS_CH0TTL_EN<< 16)|(LVDS_CH1TTL_EN<< 16)|(LVDS_CH1_PWR_EN << 16) | + (LVDS_CH0_PWR_EN << 16)|(LVDS_CBG_PWR_EN << 16)|(LVDS_PLL_PWR_DN << 16); + ret = rk616->write_dev(rk616,CRU_LVDS_CON0,&val); + + val &= ~(LVDS_OUT_EN); + val |= (LVDS_OUT_EN << 16); + ret = rk616->write_dev(rk616,CRU_IO_CON0,&val); + dev_info(rk616->dev,"rk616 use RGB output.....\n"); + + } + } + + return 0; + +} + + +static int rk616_dither_cfg(struct mfd_rk616 *rk616,rk_screen *screen,bool enable) +{ + u32 val = 0; + int ret = 0; + val = FRC_DCLK_INV | (FRC_DCLK_INV << 16); + if((screen->face != OUT_P888) && enable) //enable frc dither if the screen is not 24bit + val |= FRC_DITHER_EN | (FRC_DITHER_EN << 16); + //val |= (FRC_DITHER_EN << 16); + else + val |= (FRC_DITHER_EN << 16); + ret = rk616->write_dev(rk616,FRC_REG,&val); + + return 0; + +} + + + + +int rk610_lcd_scaler_set_param(rk_screen *screen,bool enable )//enable:0 bypass 1: scale +{ + int ret; + struct mfd_rk616 *rk616 = g_lvds->rk616; + if(!rk616) + { + printk(KERN_ERR "%s:mfd rk616 is null!\n",__func__); + return -1; + } + g_lvds->screen = screen; + ret = rk616_display_router_cfg(rk616,screen,enable); + + ret = rk616_dither_cfg(rk616,screen,enable); + ret = rk616_lvds_cfg(rk616,screen); + return ret; +} + + + +#if defined(CONFIG_HAS_EARLYSUSPEND) +static void rk616_lvds_early_suspend(struct early_suspend *h) +{ + struct rk616_lvds *lvds = container_of(h, struct rk616_lvds,early_suspend); + struct mfd_rk616 *rk616 = lvds->rk616; + u32 val = 0; + int ret = 0; + + val &= ~(LVDS_CH1_PWR_EN | LVDS_CH0_PWR_EN | LVDS_CBG_PWR_EN); + val |= LVDS_PLL_PWR_DN |(LVDS_CH1_PWR_EN << 16) | (LVDS_CH0_PWR_EN << 16) | + (LVDS_CBG_PWR_EN << 16) | (LVDS_PLL_PWR_DN << 16); + ret = rk616->write_dev(rk616,CRU_LVDS_CON0,&val); + + val = LCD1_INPUT_EN | (LCD1_INPUT_EN << 16); + ret = rk616->write_dev(rk616,CRU_IO_CON0,&val); + + +} + +static void rk616_lvds_late_resume(struct early_suspend *h) +{ + struct rk616_lvds *lvds = container_of(h, struct rk616_lvds,early_suspend); + struct mfd_rk616 *rk616 = lvds->rk616; + rk616_lvds_cfg(rk616,lvds->screen); +} + +#endif + +static int rk616_lvds_probe(struct platform_device *pdev) +{ + struct rk616_lvds *lvds = NULL; + struct mfd_rk616 *rk616 = NULL; + + lvds = kzalloc(sizeof(struct rk616_lvds),GFP_KERNEL); + if(!lvds) + { + printk(KERN_ALERT "alloc for struct rk616_lvds fail\n"); + return -ENOMEM; + } + + rk616 = dev_get_drvdata(pdev->dev.parent); + if(!rk616) + { + dev_err(&pdev->dev,"null mfd device rk616!\n"); + return -ENODEV; + } + else + g_lvds = lvds; + lvds->rk616 = rk616; + +#ifdef CONFIG_HAS_EARLYSUSPEND + lvds->early_suspend.suspend = rk616_lvds_early_suspend; + lvds->early_suspend.resume = rk616_lvds_late_resume; + lvds->early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB - 1; + register_early_suspend(&lvds->early_suspend); +#endif + + + dev_info(&pdev->dev,"rk616 lvds probe success!\n"); + + return 0; + +} + +static int rk616_lvds_remove(struct platform_device *pdev) +{ + + return 0; +} + +static void rk616_lvds_shutdown(struct platform_device *pdev) +{ + + return; +} + +static struct platform_driver rk616_lvds_driver = { + .driver = { + .name = "rk616-lvds", + .owner = THIS_MODULE, + }, + .probe = rk616_lvds_probe, + .remove = rk616_lvds_remove, + .shutdown = rk616_lvds_shutdown, +}; + +static int __init rk616_lvds_init(void) +{ + return platform_driver_register(&rk616_lvds_driver); +} +subsys_initcall_sync(rk616_lvds_init); + +static void __exit rk616_lvds_exit(void) +{ + platform_driver_unregister(&rk616_lvds_driver); +} +module_exit(rk616_lvds_exit); + diff --git a/drivers/video/rockchip/transmitter/rk616_lvds.h b/drivers/video/rockchip/transmitter/rk616_lvds.h new file mode 100644 index 000000000000..2b6b27427ad4 --- /dev/null +++ b/drivers/video/rockchip/transmitter/rk616_lvds.h @@ -0,0 +1,16 @@ +#ifndef __RK616_VIF_H__ +#define __RK616_VIF_H__ +#include +#include +#include + + +struct rk616_lvds { + struct mfd_rk616 *rk616; + rk_screen *screen; +#ifdef CONFIG_HAS_EARLYSUSPEND + struct early_suspend early_suspend; +#endif +}; + +#endif diff --git a/drivers/video/rockchip/transmitter/ssd2828.c b/drivers/video/rockchip/transmitter/ssd2828.c new file mode 100644 index 000000000000..74bb6b3876d2 --- /dev/null +++ b/drivers/video/rockchip/transmitter/ssd2828.c @@ -0,0 +1,689 @@ +/* + * Copyright (C) 2012 ROCKCHIP, Inc. + * drivers/video/display/transmitter/ssd2828.c + * author: hhb@rock-chips.com + * create date: 2013-01-17 + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include "mipi_dsi.h" +#include +#include +#include + + +/* define spi gpio*/ +#define TXD_PORT ssd2828->spi.mosi +#define CLK_PORT ssd2828->spi.sck +#define CS_PORT ssd2828->spi.cs +#define RXD_PORT ssd2828->spi.miso + +#define CS_OUT() gpio_direction_output(CS_PORT, 0) +#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH) +#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW) +#define CLK_OUT() gpio_direction_output(CLK_PORT, 0) +#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH) +#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW) +#define TXD_OUT() gpio_direction_output(TXD_PORT, 0) +#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH) +#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW) +#define RXD_INPUT() gpio_direction_input(RXD_PORT) +#define RXD_GET() gpio_get_value(RXD_PORT) + + +struct ssd2828_t *ssd2828 = NULL; +void ssd_set_register(unsigned int reg_and_value); + +int ssd2828_gpio_init(void *data) { + int ret = 0; + struct reset_t *reset = &ssd2828->reset; + struct power_t *vdd = &ssd2828->vddio; + struct spi_t *spi = &ssd2828->spi; + + if(reset->reset_pin > INVALID_GPIO) { + ret = gpio_request(reset->reset_pin, "ssd2828_reset"); + if (ret != 0) { + //gpio_free(reset->reset_pin); + printk("%s: request ssd2828_RST_PIN error\n", __func__); + } else { +#if OLD_RK_IOMUX + if(reset->mux_name) + rk30_mux_api_set(reset->mux_name, 0); +#endif + gpio_direction_output(reset->reset_pin, !reset->effect_value); + } + } + + if(vdd->enable_pin > INVALID_GPIO) { + ret = gpio_request(vdd->enable_pin, "ssd2828_vddio"); + if (ret != 0) { + //gpio_free(vdd->enable_pin); + printk("%s: request ssd2828_vddio_PIN error\n", __func__); + } else { +#if OLD_RK_IOMUX + if(vdd->mux_name) + rk30_mux_api_set(vdd->mux_name, 0); +#endif + gpio_direction_output(vdd->enable_pin, !vdd->effect_value); + } + } + + vdd = &ssd2828->vdd_mipi; + if(vdd->enable_pin > INVALID_GPIO) { + ret = gpio_request(vdd->enable_pin, "ssd2828_vdd_mipi"); + if (ret != 0) { + //gpio_free(vdd->enable_pin); + printk("%s: request ssd2828_vdd_mipi_PIN error\n", __func__); + } else { +#if OLD_RK_IOMUX + if(vdd->mux_name) + rk30_mux_api_set(vdd->mux_name, 0); +#endif + gpio_direction_output(vdd->enable_pin, !vdd->effect_value); + } + } + + vdd = &ssd2828->shut; + if(vdd->enable_pin > INVALID_GPIO) { + ret = gpio_request(vdd->enable_pin, "ssd2828_shut"); + if (ret != 0) { + //gpio_free(vdd->enable_pin); + printk("%s: request ssd2828_shut_PIN error\n", __func__); + } else { +#if OLD_RK_IOMUX + if(vdd->mux_name) + rk30_mux_api_set(vdd->mux_name, 0); +#endif + gpio_direction_output(vdd->enable_pin, !vdd->effect_value); + } + } + + if(spi->cs > INVALID_GPIO) { + ret = gpio_request(spi->cs, "ssd2828_spi_cs"); + if (ret != 0) { + //gpio_free(spi->cs); + printk("%s: request ssd2828_spi->cs_PIN error\n", __func__); + } else { +#if OLD_RK_IOMUX + if(spi->cs_mux_name) + rk30_mux_api_set(spi->cs_mux_name, 0); +#endif + gpio_direction_output(spi->cs, GPIO_HIGH); + } + } + if(spi->sck > INVALID_GPIO) { + ret = gpio_request(spi->sck, "ssd2828_spi_sck"); + if (ret != 0) { + //gpio_free(spi->sck); + printk("%s: request ssd2828_spi->sck_PIN error\n", __func__); + } else { +#if OLD_RK_IOMUX + if(spi->sck_mux_name) + rk30_mux_api_set(spi->sck_mux_name, 0); +#endif + gpio_direction_output(spi->sck, GPIO_HIGH); + } + } + if(spi->mosi > INVALID_GPIO) { + ret = gpio_request(spi->mosi, "ssd2828_spi_mosi"); + if (ret != 0) { + //gpio_free(spi->mosi); + printk("%s: request ssd2828_spi->mosi_PIN error\n", __func__); + } else { +#if OLD_RK_IOMUX + if(spi->mosi_mux_name) + rk30_mux_api_set(spi->mosi_mux_name, 0); +#endif + gpio_direction_output(spi->mosi, GPIO_HIGH); + } + } + if(spi->miso > INVALID_GPIO) { + ret = gpio_request(spi->miso, "ssd2828_spi_miso"); + if (ret != 0) { + //gpio_free(spi->miso); + printk("%s: request ssd2828_spi->miso_PIN error\n", __func__); + } else { +#if OLD_RK_IOMUX + if(spi->miso_mux_name) + rk30_mux_api_set(spi->miso_mux_name, 0); +#endif + gpio_direction_input(spi->miso); + } + } + + return 0; + +} + +int ssd2828_gpio_deinit(void *data) { + struct reset_t *reset = &ssd2828->reset; + struct power_t *vdd = &ssd2828->vddio; + struct spi_t *spi = &ssd2828->spi; + + if(reset->reset_pin > INVALID_GPIO) { + gpio_direction_input(reset->reset_pin); + gpio_free(reset->reset_pin); + } + if(vdd->enable_pin > INVALID_GPIO) { + gpio_direction_input(vdd->enable_pin); + gpio_free(vdd->enable_pin); + } + vdd = &ssd2828->vdd_mipi; + if(vdd->enable_pin > INVALID_GPIO) { + gpio_direction_input(vdd->enable_pin); + gpio_free(vdd->enable_pin); + } + vdd = &ssd2828->shut; + if(vdd->enable_pin > INVALID_GPIO) { + gpio_direction_input(vdd->enable_pin); + gpio_free(vdd->enable_pin); + } + if(spi->cs > INVALID_GPIO) { + gpio_direction_input(spi->cs); + gpio_free(spi->cs); + } + if(spi->sck > INVALID_GPIO) { + gpio_direction_input(spi->sck); + gpio_free(spi->sck); + } + if(spi->mosi > INVALID_GPIO) { + gpio_direction_input(spi->mosi); + gpio_free(spi->mosi); + } + if(spi->miso > INVALID_GPIO) { + gpio_free(spi->miso); + } + return 0; +} + +int ssd2828_reset(void *data) { + int ret = 0; + struct reset_t *reset = &ssd2828->reset; + if(reset->reset_pin <= INVALID_GPIO) + return -1; + gpio_set_value(reset->reset_pin, reset->effect_value); + if(reset->time_before_reset <= 0) + msleep(10); + else + msleep(reset->time_before_reset); + + gpio_set_value(reset->reset_pin, !reset->effect_value); + if(reset->time_after_reset <= 0) + msleep(5); + else + msleep(reset->time_after_reset); + return ret; +} + +int ssd2828_vdd_enable(void *data) { + int ret = 0; + struct power_t *vdd = (struct power_t *)data; + if(vdd->enable_pin > INVALID_GPIO) { + gpio_set_value(vdd->enable_pin, vdd->effect_value); + } else if(vdd->name) { + struct regulator *ldo = regulator_get(NULL, vdd->name); + if (ldo == NULL || IS_ERR(ldo) ){ + printk("%s: get %s ldo failed!\n", __func__, vdd->name); + ret = -1; + return ret; + } + regulator_set_voltage(ldo, vdd->voltage, vdd->voltage); + regulator_enable(ldo); + printk(" %s set %s=%dmV end\n", __func__, vdd->name, regulator_get_voltage(ldo)); + regulator_put(ldo); + } + return ret; +} + +int ssd2828_vdd_disable(void *data) { + int ret = 0; + struct power_t *vdd = (struct power_t *)data; + + if(vdd->enable_pin > INVALID_GPIO) { + gpio_set_value(vdd->enable_pin, !vdd->effect_value); + } else if(vdd->name) { + struct regulator *ldo = regulator_get(NULL, vdd->name); + if (ldo == NULL || IS_ERR(ldo) ){ + printk("%s: get %s ldo failed!\n", __func__, vdd->name); + ret = -1; + return ret; + } + while(regulator_is_enabled(ldo) > 0){ + regulator_disable(ldo); + } + regulator_put(ldo); + } + return ret; +} + + +int ssd2828_power_up(void) { + + int ret = 0; + struct ssd2828_t *ssd = (struct ssd2828_t *)ssd2828; + struct spi_t *spi = &ssd2828->spi; + ssd->vdd_mipi.enable(&ssd->vdd_mipi); + ssd->vddio.enable(&ssd->vddio); + ssd->reset.do_reset(&ssd->reset); + ssd->shut.enable(&ssd->shut); + + gpio_direction_output(spi->cs, GPIO_HIGH); + gpio_direction_output(spi->sck, GPIO_LOW); + gpio_direction_input(spi->miso); + gpio_direction_output(spi->mosi, GPIO_LOW); + + return ret; +} + +int ssd2828_power_down(void) { + + int ret = 0; + struct ssd2828_t *ssd = (struct ssd2828_t *)ssd2828; + struct spi_t *spi = &ssd2828->spi; + + ssd->shut.disable(&ssd->shut); + msleep(10); + + ssd_set_register(0x00b70300); + msleep(1); + ssd_set_register(0x00b70304); + msleep(1); + ssd_set_register(0x00b90000); + msleep(10); + + //set all gpio to low to avoid current leakage + gpio_direction_output(spi->cs, GPIO_LOW); + gpio_direction_output(spi->sck, GPIO_LOW); + gpio_direction_output(spi->miso, GPIO_LOW); + gpio_direction_output(spi->mosi, GPIO_LOW); + gpio_direction_output(ssd->reset.reset_pin, GPIO_LOW); + + ssd->vddio.disable(&ssd->vddio); + ssd->vdd_mipi.disable(&ssd->vdd_mipi); + ssd->shut.enable(&ssd->shut); + + return ret; +} + + + +/* spi write a data frame,type mean command or data + 3 wire 24 bit SPI interface +*/ + +static void spi_send_data(unsigned int data) +{ + unsigned int i; + + CS_SET(); + udelay(1); + CLK_SET(); + TXD_SET(); + + CS_CLR(); + udelay(1); + + for (i = 0; i < 24; i++) + { + //udelay(1); + CLK_CLR(); + udelay(1); + if (data & 0x00800000) { + TXD_SET(); + } else { + TXD_CLR(); + } + udelay(1); + CLK_SET(); + udelay(1); + data <<= 1; + } + + TXD_SET(); + CS_SET(); +} + +static void spi_recv_data(unsigned int* data) +{ + unsigned int i = 0, temp = 0x73; //read data + + CS_SET(); + udelay(1); + CLK_SET(); + TXD_SET(); + + CS_CLR(); + udelay(1); + + for(i = 0; i < 8; i++) // 8 bits Data + { + udelay(1); + CLK_CLR(); + if (temp & 0x80) + TXD_SET(); + else + TXD_CLR(); + temp <<= 1; + udelay(1); + CLK_SET(); + udelay(1); + } + udelay(1); + temp = 0; + for(i = 0; i < 16; i++) // 16 bits Data + { + udelay(1); + CLK_CLR(); + udelay(1); + CLK_SET(); + udelay(1); + temp <<= 1; + if(RXD_GET() == GPIO_HIGH) + temp |= 0x01; + + } + + TXD_SET(); + CS_SET(); + *data = temp; +} + +#define DEVIE_ID (0x70 << 16) +void send_ctrl_cmd(unsigned int cmd) +{ + unsigned int out = (DEVIE_ID | cmd ); + spi_send_data(out); +} + +static void send_data_cmd(unsigned int data) +{ + unsigned int out = (DEVIE_ID | (0x2 << 16) | data ); + spi_send_data(out); +} + +unsigned int ssd_read_register(unsigned int reg) { + unsigned int data = 0; + send_ctrl_cmd(reg); + spi_recv_data(&data); + return data; +} + +void ssd_set_register(unsigned int reg_and_value) +{ + send_ctrl_cmd(reg_and_value >> 16); + send_data_cmd(reg_and_value & 0x0000ffff); +} + +int ssd_set_registers(unsigned int reg_array[], int n) { + + int i = 0; + for(i = 0; i < n; i++) { + if(reg_array[i] < 0x00b00000) { //the lowest address is 0xb0 of ssd2828 + if(reg_array[i] < 20000) + udelay(reg_array[i]); + else { + mdelay(reg_array[i]/1000); + } + } else { + ssd_set_register(reg_array[i]); + } + } + return 0; +} + +int ssd_mipi_dsi_send_dcs_packet(unsigned char regs[], int n) { + //unsigned int data = 0, i = 0; + ssd_set_register(0x00B70343); // + ssd_set_register(0x00B80000); + ssd_set_register(0x00Bc0001); + + ssd_set_register(0x00Bf0000 | regs[0]); + msleep(1); + ssd_set_register(0x00B7034b); + return 0; +} + + +int _ssd2828_send_packet(unsigned char type, unsigned char regs[], int n) { + + + return 0; +} + +int ssd2828_send_packet(unsigned char type, unsigned char regs[], int n) { + return _ssd2828_send_packet(type, regs, n); +} + +int ssd_mipi_dsi_read_dcs_packet(unsigned char *data, int n) { + //DCS READ + unsigned int i = 0; + + i = ssd_read_register(0xc6); + printk("read mipi slave error:%04x\n", i); + ssd_set_register(0x00B70382); + ssd_set_register(0x00BB0008); + ssd_set_register(0x00C1000A); + ssd_set_register(0x00C00001); + ssd_set_register(0x00Bc0001); + ssd_set_register(0x00Bf0000 | *data); + msleep(10); + i = ssd_read_register(0xc6); + printk("read mipi slave error:%04x\n", i); + + if(i & 1) { + i = ssd_read_register(0xff); + printk("read %02x:%04x\n", *data, i); + i = ssd_read_register(0xff); + printk("read %02x:%04x\n", *data, i); + i = ssd_read_register(0xff); + printk("read %02x:%04x\n", *data, i); + + } + + return 0; +} + + +int ssd2828_get_id(void) { + + int id = -1; + ssd2828_power_up(); + id = ssd_read_register(0xb0); + + return id; +} + +static struct mipi_dsi_ops ssd2828_ops = { + .id = 0x2828, + .name = "ssd2828", + .get_id = ssd2828_get_id, + .dsi_set_regs = ssd_set_registers, + .dsi_send_dcs_packet = ssd_mipi_dsi_send_dcs_packet, + .dsi_read_dcs_packet = ssd_mipi_dsi_read_dcs_packet, + .power_up = ssd2828_power_up, + .power_down = ssd2828_power_down, + +}; + +static struct proc_dir_entry *reg_proc_entry; + +int reg_proc_write(struct file *file, const char __user *buff, size_t count, loff_t *offp) +{ + int ret = -1; + char *buf = kmalloc(count, GFP_KERNEL); + char *data = buf; + unsigned int regs_val = 0, read_val = 0; + ret = copy_from_user((void*)buf, buff, count); + + while(1) { + data = strstr(data, "0x"); + if(data == NULL) + goto reg_proc_write_exit; + sscanf(data, "0x%x", ®s_val); + ssd_set_register(regs_val); + read_val = ssd_read_register(regs_val >> 16); + regs_val &= 0xffff; + if(read_val != regs_val) + printk("%s fail:0x%04x\n", __func__, read_val); + data += 3; + } + +reg_proc_write_exit: + kfree(buf); + msleep(10); + return count; +} + +int reg_proc_read(struct file *file, char __user *buff, size_t count, loff_t *offp) +{ +#if 0 + int ret = -1; + const char buf[32] = {0}; + unsigned int regs_val = 0; + ret = copy_from_user((void*)buf, buff, count); + sscanf(buf, "0x%x", ®s_val); + regs_val = ssd_read_register(regs_val); + sprintf(buf, "0x%04x\n", regs_val); + copy_to_user(buff, buf, 4); + + printk("%s:%04x\n", __func__, regs_val); + msleep(10); +#endif + return count; +} + +int reg_proc_open(struct inode *inode, struct file *file) +{ + //printk("%s\n", __func__); + //msleep(10); + return 0; +} + +int reg_proc_close(struct inode *inode, struct file *file) +{ + //printk("%s\n", __func__); + //msleep(10); + return 0; +} + +struct file_operations reg_proc_fops = { + .owner = THIS_MODULE, + .open = reg_proc_open, + .release = reg_proc_close, + .write = reg_proc_write, + .read = reg_proc_read, +}; + +static int reg_proc_init(char *name) +{ + int ret = 0; + reg_proc_entry = create_proc_entry(name, 0666, NULL); + if(reg_proc_entry == NULL) { + printk("Couldn't create proc entry : %s!\n", name); + ret = -ENOMEM; + return ret ; + } + else { + printk("Create proc entry:%s success!\n", name); + reg_proc_entry->proc_fops = ®_proc_fops; + } + + return 0; +} + + +static int ssd2828_probe(struct platform_device *pdev) { + + if(pdev->dev.platform_data) + ssd2828 = pdev->dev.platform_data; + + if(!ssd2828->gpio_init) + ssd2828->gpio_init = ssd2828_gpio_init; + + if(!ssd2828->gpio_deinit) + ssd2828->gpio_deinit = ssd2828_gpio_deinit; + + if(!ssd2828->power_up) + ssd2828->power_up = ssd2828_power_up; + if(!ssd2828->power_down) + ssd2828->power_down = ssd2828_power_down; + + if(!ssd2828->reset.do_reset) + ssd2828->reset.do_reset = ssd2828_reset; + + if(!ssd2828->vddio.enable) + ssd2828->vddio.enable = ssd2828_vdd_enable; + if(!ssd2828->vddio.disable) + ssd2828->vddio.disable = ssd2828_vdd_disable; + + if(!ssd2828->vdd_mipi.enable) + ssd2828->vdd_mipi.enable = ssd2828_vdd_enable; + if(!ssd2828->vdd_mipi.disable) + ssd2828->vdd_mipi.disable = ssd2828_vdd_disable; + + if(!ssd2828->shut.enable) + ssd2828->shut.enable = ssd2828_vdd_enable; + if(!ssd2828->shut.disable) + ssd2828->shut.disable = ssd2828_vdd_disable; + + + ssd2828_gpio_init(NULL); + reg_proc_init(ssd2828_ops.name); + return 0; +} + + +static int ssd2828_remove(struct platform_device *pdev) { + + if(ssd2828) { + ssd2828_gpio_deinit(NULL); + ssd2828 = NULL; + } + return 0; +} + + +static struct platform_driver ssd2828_driver = { + .probe = ssd2828_probe, + .remove = ssd2828_remove, + //.suspend = mipi_dsi_suspend, + //.resume = mipi_dsi_resume, + .driver = { + .name = "ssd2828", + .owner = THIS_MODULE, + } +}; + +static int __init ssd2828_init(void) +{ + platform_driver_register(&ssd2828_driver); + if(!ssd2828) + return -1; + register_dsi_ops(&ssd2828_ops); + if(ssd2828->id > 0) + ssd2828_ops.id = ssd2828->id; + return 0; +} + +static void __exit ssd2828_exit(void) +{ + platform_driver_unregister(&ssd2828_driver); + del_dsi_ops(&ssd2828_ops); +} + +subsys_initcall_sync(ssd2828_init); +module_exit(ssd2828_exit); diff --git a/drivers/video/rockchip/transmitter/tc358768.c b/drivers/video/rockchip/transmitter/tc358768.c new file mode 100644 index 000000000000..5f573b3dce8e --- /dev/null +++ b/drivers/video/rockchip/transmitter/tc358768.c @@ -0,0 +1,743 @@ +/* + * Copyright (C) 2012 ROCKCHIP, Inc. + * drivers/video/display/transmitter/tc358768.c + * author: hhb@rock-chips.com + * create date: 2012-10-26 + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include "mipi_dsi.h" + +#define CONFIG_TC358768_I2C 1 +#define CONFIG_TC358768_I2C_CLK 400*1000 + + +#if 0 +#define dsi_debug printk +#else +#define dsi_debug(fmt...) do { } while (0) +#endif + +#ifdef CONFIG_TC358768_I2C +static struct tc358768_t *tc358768 = NULL; +static struct i2c_client *tc358768_client = NULL; +static struct mipi_dsi_ops tc358768_ops; + + +u32 i2c_write_32bits(u32 value) +{ + struct i2c_msg msgs; + int ret = -1; + char buf[4]; + buf[0] = value>>24; + buf[1] = value>>16; + buf[2] = value>>8; + buf[3] = value; + + msgs.addr = tc358768_client->addr; + msgs.flags = tc358768_client->flags; + msgs.len = 4; + msgs.buf = buf; + msgs.scl_rate = CONFIG_TC358768_I2C_CLK; + msgs.udelay = tc358768_client->udelay; + + ret = i2c_transfer(tc358768_client->adapter, &msgs, 1); + if(ret < 0) + printk("%s:i2c_transfer fail =%d\n",__func__, ret); + return ret; +} + +u32 i2c_read_32bits(u32 value) +{ + struct i2c_msg msgs[2]; + int ret = -1; + char buf[4]; + buf[0] = value>>8; + buf[1] = value; + + msgs[0].addr = tc358768_client->addr; + msgs[0].flags = tc358768_client->flags; + msgs[0].len = 2; + msgs[0].buf = buf; + msgs[0].scl_rate = CONFIG_TC358768_I2C_CLK; + msgs[0].udelay = tc358768_client->udelay; + + msgs[1].addr = tc358768_client->addr; + msgs[1].flags = tc358768_client->flags | I2C_M_RD; + msgs[1].len = 2; + msgs[1].buf = buf; + msgs[1].scl_rate = CONFIG_TC358768_I2C_CLK; + msgs[1].udelay = tc358768_client->udelay; + + ret = i2c_transfer(tc358768_client->adapter, msgs, 2); + if(ret < 0) + printk("%s:i2c_transfer fail =%d\n",__func__, ret); + else + ret = (buf[0]<<8) | buf[1]; + + return ret; +} + + +int tc358768_gpio_init(void *data) { + int ret = 0; + struct reset_t *reset = &tc358768->reset; + struct power_t *vdd = &tc358768->vddc; + if(reset->reset_pin > INVALID_GPIO) { + ret = gpio_request(reset->reset_pin, "tc358768_reset"); + if (ret != 0) { + //gpio_free(reset->reset_pin); + printk("%s: request TC358768_RST_PIN error\n", __func__); + } else { +#if OLD_RK_IOMUX + if(reset->mux_name) + rk30_mux_api_set(reset->mux_name, reset->mux_mode); +#endif + gpio_direction_output(reset->reset_pin, !reset->effect_value); + } + } + + if(vdd->enable_pin > INVALID_GPIO) { + ret = gpio_request(vdd->enable_pin, "tc358768_vddc"); + if (ret != 0) { + //gpio_free(vdd->enable_pin); + printk("%s: request TC358768_vddc_PIN error\n", __func__); + } else { +#if OLD_RK_IOMUX + if(vdd->mux_name) + rk30_mux_api_set(vdd->mux_name, vdd->mux_mode); +#endif + gpio_direction_output(vdd->enable_pin, !vdd->effect_value); + } + } + + vdd = &tc358768->vddio; + if(vdd->enable_pin > INVALID_GPIO) { + ret = gpio_request(vdd->enable_pin, "tc358768_vddio"); + if (ret != 0) { + //gpio_free(vdd->enable_pin); + printk("%s: request TC358768_vddio_PIN error\n", __func__); + } else { +#if OLD_RK_IOMUX + if(vdd->mux_name) + rk30_mux_api_set(vdd->mux_name, vdd->mux_mode); +#endif + gpio_direction_output(vdd->enable_pin, !vdd->effect_value); + } + } + + vdd = &tc358768->vdd_mipi; + if(vdd->enable_pin > INVALID_GPIO) { + ret = gpio_request(vdd->enable_pin, "tc358768_vdd_mipi"); + if (ret != 0) { + //gpio_free(vdd->enable_pin); + printk("%s: request TC358768_vdd_mipi_PIN error\n", __func__); + } else { +#if OLD_RK_IOMUX + if(vdd->mux_name) + rk30_mux_api_set(vdd->mux_name, vdd->mux_mode); +#endif + gpio_direction_output(vdd->enable_pin, !vdd->effect_value); + } + } + return 0; + +} + +int tc358768_gpio_deinit(void *data) { + struct reset_t *reset = &tc358768->reset; + struct power_t *vdd = &tc358768->vddc; + gpio_direction_input(reset->reset_pin); + gpio_free(reset->reset_pin); + + gpio_direction_input(vdd->enable_pin); + gpio_free(vdd->enable_pin); + + vdd = &tc358768->vddio; + gpio_direction_input(vdd->enable_pin); + gpio_free(vdd->enable_pin); + + vdd = &tc358768->vdd_mipi; + gpio_direction_input(vdd->enable_pin); + gpio_free(vdd->enable_pin); + return 0; +} + +int tc358768_reset(void *data) { + int ret = 0; + struct reset_t *reset = &tc358768->reset; + if(reset->reset_pin <= INVALID_GPIO) + return -1; + gpio_set_value(reset->reset_pin, reset->effect_value); + if(reset->time_before_reset <= 0) + msleep(1); + else + msleep(reset->time_before_reset); + + gpio_set_value(reset->reset_pin, !reset->effect_value); + if(reset->time_after_reset <= 0) + msleep(5); + else + msleep(reset->time_after_reset); + return ret; +} + +int tc358768_vdd_enable(void *data) { + int ret = 0; + struct power_t *vdd = (struct power_t *)data; + if(vdd->enable_pin > INVALID_GPIO) { + gpio_set_value(vdd->enable_pin, vdd->effect_value); + } else { + //for other control + } + return ret; +} + +int tc358768_vdd_disable(void *data) { + int ret = 0; + struct power_t *vdd = (struct power_t *)data; + + if(vdd->enable_pin > INVALID_GPIO) { + gpio_set_value(vdd->enable_pin, !vdd->effect_value); + } else { + //for other control + } + return ret; +} + + +int tc358768_power_up(void) { + + int ret = 0; + struct tc358768_t *tc = (struct tc358768_t *)tc358768; + + tc->vddc.enable(&tc->vddc); + tc->vdd_mipi.enable(&tc->vdd_mipi); + tc->vddio.enable(&tc->vddio); + tc->reset.do_reset(&tc->reset); + + return ret; +} + +int tc358768_power_down(void) { + + int ret = 0; + struct tc358768_t *tc = (struct tc358768_t *)tc358768; + + tc->vddio.disable(&tc->vddio); + tc->vdd_mipi.disable(&tc->vdd_mipi); + tc->vddc.disable(&tc->vddc); + + return ret; +} + +static int tc358768_probe(struct i2c_client *client, + const struct i2c_device_id *did) +{ + struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); + int ret = 0; + + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) { + dev_warn(&adapter->dev, + "I2C-Adapter doesn't support I2C_FUNC_I2C\n"); + return -EIO; + } + + tc358768 = (struct tc358768_t *)client->dev.platform_data; + if(!tc358768) { + ret = -1; + printk("%s:%d tc358768 is null\n", __func__, __LINE__); + return ret; + } + + tc358768_client = client; + if(!tc358768_client) { + ret = -1; + printk("%s:%d tc358768_client is null\n", __func__, __LINE__); + return ret; + } + + if(!tc358768->gpio_init) + tc358768->gpio_init = tc358768_gpio_init; + + if(!tc358768->gpio_deinit) + tc358768->gpio_deinit = tc358768_gpio_deinit; + + if(!tc358768->power_up) + tc358768->power_up = tc358768_power_up; + if(!tc358768->power_down) + tc358768->power_down = tc358768_power_down; + + if(!tc358768->reset.do_reset) + tc358768->reset.do_reset = tc358768_reset; + + if(!tc358768->vddc.enable) + tc358768->vddc.enable = tc358768_vdd_enable; + if(!tc358768->vddc.disable) + tc358768->vddc.disable = tc358768_vdd_disable; + + if(!tc358768->vddio.enable) + tc358768->vddio.enable = tc358768_vdd_enable; + if(!tc358768->vddio.disable) + tc358768->vddio.disable = tc358768_vdd_disable; + + if(!tc358768->vdd_mipi.enable) + tc358768->vdd_mipi.enable = tc358768_vdd_enable; + if(!tc358768->vdd_mipi.disable) + tc358768->vdd_mipi.disable = tc358768_vdd_disable; + + tc358768_gpio_init(NULL); + + return ret; +} +static int tc358768_remove(struct i2c_client *client) +{ + tc358768_gpio_deinit(NULL); + tc358768_client = NULL; + tc358768 = NULL; + return 0; +} + +static const struct i2c_device_id tc358768_id[] = { + {"tc358768", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, tc358768_id); + +static struct i2c_driver tc358768_driver = { + .probe = tc358768_probe, + .remove = tc358768_remove, + .id_table = tc358768_id, + .driver = { + .name = "tc358768", + }, +}; +#else + +u32 spi_read_32bits(u32 addr) +{ + unsigned int i = 32; + //a frame starts + CS_CLR(); + CLK_SET(); + + addr <<= 16; + addr &= 0xfffe0000; + addr |= 0x00010000; + + udelay(2); + while(i--) { + CLK_CLR(); + if(addr & 0x80000000) + TXD_SET(); + else + TXD_CLR(); + addr <<= 1; + udelay(2); + CLK_SET(); + udelay(2); + } + //a frame ends + CS_SET(); + + + udelay(2); + CS_CLR(); + addr = 0xfffe0000; + i = 16; + while(i--) { + CLK_CLR(); + if(addr & 0x80000000) + TXD_SET(); + else + TXD_CLR(); + addr <<= 1; + udelay(2); + CLK_SET(); + udelay(2); + } + + TXD_SET(); + + addr = 0; + i = 16; + while(i--) { + CLK_CLR(); + udelay(1); + CLK_SET(); + udelay(1); + if (gpio_get_value(gLcd_info->rxd_pin) == 1) + addr |= 1 << i; + udelay(1); + } + CS_SET(); + + return addr; +} + + +//32 bits per frame +u32 spi_write_32bits(u32 value) +{ + int i = 32; + + //a frame starts + CS_CLR(); + CLK_SET(); + + while(i--) { + CLK_CLR(); + if(value & 0x80000000) + TXD_SET(); + else + TXD_CLR(); + value <<= 1; + CLK_SET(); + } + //a frame ends + CS_SET(); + + return 0; +} + +#endif + +u32 tc358768_wr_reg_32bits(u32 data) { +#ifdef CONFIG_TC358768_I2C + i2c_write_32bits(data); +#else + spi_write_32bits(data); +#endif + return 0; +} + + +u32 tc358768_wr_reg_32bits_delay(u32 delay, u32 data) { + //wait a minute according to the source format + if(delay < 20000) + udelay(delay); + else { + mdelay(delay/1000); + } + +#ifdef CONFIG_TC358768_I2C + i2c_write_32bits(data); +#else + spi_write_32bits(data); +#endif + return 0; +} + + + +u32 tc358768_rd_reg_32bits(u32 addr) { +#ifdef CONFIG_TC358768_I2C + return i2c_read_32bits(addr); +#else + return spi_read_32bits(addr); +#endif +} + + + +void tc_print(u32 addr) { + dsi_debug("+++++++++++addr->%04x: %04x\n", addr, tc358768_rd_reg_32bits(addr)); +} + +#define tc358768_wr_regs_32bits(reg_array) _tc358768_wr_regs_32bits(reg_array, ARRAY_SIZE(reg_array)) +int _tc358768_wr_regs_32bits(unsigned int reg_array[], int n) { + + int i = 0; + dsi_debug("%s:%d\n", __func__, n); + for(i = 0; i < n; i++) { + if(reg_array[i] < 0x00020000) { + if(reg_array[i] < 20000) + udelay(reg_array[i]); + else { + mdelay(reg_array[i]/1000); + } + } else { + tc358768_wr_reg_32bits(reg_array[i]); + } + } + return 0; +} + +int tc358768_command_tx_less8bytes(unsigned char type, unsigned char *regs, int n) { + int i = 0; + unsigned int command[] = { + 0x06020000, + 0x06040000, + 0x06100000, + 0x06120000, + 0x06140000, + 0x06160000, + }; + + if(n <= 2) + command[0] |= 0x1000; //short packet + else { + command[0] |= 0x4000; //long packet + command[1] |= n; //word count byte + } + command[0] |= type; //data type + + //dsi_debug("*cmd:\n"); + //dsi_debug("0x%08x\n", command[0]); + //dsi_debug("0x%08x\n", command[1]); + + for(i = 0; i < (n + 1)/2; i++) { + command[i+2] |= regs[i*2]; + if((i*2 + 1) < n) + command[i+2] |= regs[i*2 + 1] << 8; + dsi_debug("0x%08x\n", command[i+2]); + } + + _tc358768_wr_regs_32bits(command, (n + 1)/2 + 2); + tc358768_wr_reg_32bits(0x06000001); //Packet Transfer + //wait until packet is out + i = 100; + while(tc358768_rd_reg_32bits(0x0600) & 0x01) { + if(i-- == 0) + break; + tc_print(0x0600); + } + //udelay(50); + return 0; +} + +int tc358768_command_tx_more8bytes_hs(unsigned char type, unsigned char regs[], int n) { + + int i = 0; + unsigned int dbg_data = 0x00E80000, temp = 0; + unsigned int command[] = { + 0x05000080, //HS data 4 lane, EOT is added + 0x0502A300, + 0x00080001, + 0x00500000, //Data ID setting + 0x00220000, //Transmission byte count= byte + 0x00E08000, //Enable I2C/SPI write to VB + 0x00E20048, //Total word count = 0x48 (max 0xFFF). This value should be adjusted considering trade off between transmission time and transmission start/stop time delay + 0x00E4007F, //Vertical blank line = 0x7F + }; + + + command[3] |= type; //data type + command[4] |= n & 0xffff; //Transmission byte count + + tc358768_wr_regs_32bits(command); + + for(i = 0; i < (n + 1)/2; i++) { + temp = dbg_data | regs[i*2]; + if((i*2 + 1) < n) + temp |= (regs[i*2 + 1] << 8); + //dsi_debug("0x%08x\n", temp); + tc358768_wr_reg_32bits(temp); + } + if((n % 4 == 1) || (n % 4 == 2)) //4 bytes align + tc358768_wr_reg_32bits(dbg_data); + + tc358768_wr_reg_32bits(0x00E0C000); //Start command transmisison + tc358768_wr_reg_32bits(0x00E00000); //Stop command transmission. This setting should be done just after above setting to prevent multiple output + udelay(200); + //Re-Initialize + //tc358768_wr_regs_32bits(re_initialize); + return 0; +} + +//low power mode only for tc358768a +int tc358768_command_tx_more8bytes_lp(unsigned char type, unsigned char regs[], int n) { + + int i = 0; + unsigned int dbg_data = 0x00E80000, temp = 0; + unsigned int command[] = { + 0x00080001, + 0x00500000, //Data ID setting + 0x00220000, //Transmission byte count= byte + 0x00E08000, //Enable I2C/SPI write to VB + }; + + command[1] |= type; //data type + command[2] |= n & 0xffff; //Transmission byte count + + tc358768_wr_regs_32bits(command); + + for(i = 0; i < (n + 1)/2; i++) { + temp = dbg_data | regs[i*2]; + if((i*2 + 1) < n) + temp |= (regs[i*2 + 1] << 8); + //dsi_debug("0x%08x\n", temp); + tc358768_wr_reg_32bits(temp); + + } + if((n % 4 == 1) || (n % 4 == 2)) //4 bytes align + tc358768_wr_reg_32bits(dbg_data); + + tc358768_wr_reg_32bits(0x00E0E000); //Start command transmisison + udelay(1000); + tc358768_wr_reg_32bits(0x00E02000); //Keep Mask High to prevent short packets send out + tc358768_wr_reg_32bits(0x00E00000); //Stop command transmission. This setting should be done just after above setting to prevent multiple output + udelay(10); + return 0; +} + +int _tc358768_send_packet(unsigned char type, unsigned char regs[], int n) { + + if(n <= 8) { + tc358768_command_tx_less8bytes(type, regs, n); + } else { + //tc358768_command_tx_more8bytes_hs(type, regs, n); + tc358768_command_tx_more8bytes_lp(type, regs, n); + } + return 0; +} + +int tc358768_send_packet(unsigned char type, unsigned char regs[], int n) { + return _tc358768_send_packet(type, regs, n); +} + + +/* +The DCS is separated into two functional areas: the User Command Set and the Manufacturer Command +Set. Each command is an eight-bit code with 00h to AFh assigned to the User Command Set and all other +codes assigned to the Manufacturer Command Set. +*/ +int _mipi_dsi_send_dcs_packet(unsigned char regs[], int n) { + + unsigned char type = 0; + if(n == 1) { + type = DTYPE_DCS_SWRITE_0P; + } else if (n == 2) { + type = DTYPE_DCS_SWRITE_1P; + } else if (n > 2) { + type = DTYPE_DCS_LWRITE; + } + _tc358768_send_packet(type, regs, n); + return 0; +} + +int mipi_dsi_send_dcs_packet(unsigned char regs[], int n) { + return _mipi_dsi_send_dcs_packet(regs, n); +} + + +int _tc358768_rd_lcd_regs(unsigned char type, char comd, int size, unsigned char* buf) { + + unsigned char regs[8]; + u32 count = 0, data30, data32; + regs[0] = size; + regs[1] = 0; + tc358768_command_tx_less8bytes(0x37, regs, 2); + tc358768_wr_reg_32bits(0x05040010); + tc358768_wr_reg_32bits(0x05060000); + regs[0] = comd; + tc358768_command_tx_less8bytes(type, regs, 1); + + while (!(tc358768_rd_reg_32bits(0x0410) & 0x20)){ + printk("error 0x0410:%04x\n", tc358768_rd_reg_32bits(0x0410)); + msleep(1); + if(count++ > 10) { + break; + } + } + + data30 = tc358768_rd_reg_32bits(0x0430); //data id , word count[0:7] + //printk("0x0430:%04x\n", data30); + data32 = tc358768_rd_reg_32bits(0x0432); //word count[8:15] ECC + //printk("0x0432:%04x\n", data32); + + while(size > 0) { + data30 = tc358768_rd_reg_32bits(0x0430); + //printk("0x0430:%04x\n", data30); + data32 = tc358768_rd_reg_32bits(0x0432); + //printk("0x0432:%04x\n", data32); + + if(size-- > 0) + *buf++ = (u8)data30; + else + break; + if(size-- > 0) + *buf++ = (u8)(data30 >> 8); + else + break; + if(size-- > 0) { + *buf++ = (u8)data32; + if(size-- > 0) + *buf++ = (u8)(data32 >> 8); + } + } + + data30 = tc358768_rd_reg_32bits(0x0430); + //printk("0x0430:%04x\n", data30); + data32 = tc358768_rd_reg_32bits(0x0432); + //printk("0x0432:%04x\n", data32); + return 0; +} + +int mipi_dsi_read_dcs_packet(unsigned char *data, int n) { + //DCS READ + _tc358768_rd_lcd_regs(0x06, *data, n, data); + return 0; +} + +int tc358768_get_id(void) { + + int id = -1; + + tc358768_power_up(); + id = tc358768_rd_reg_32bits(0); + return id; +} + +static struct mipi_dsi_ops tc358768_ops = { + .id = 0x4401, + .name = "tc358768a", + .get_id = tc358768_get_id, + .dsi_set_regs = _tc358768_wr_regs_32bits, + .dsi_send_dcs_packet = mipi_dsi_send_dcs_packet, + .dsi_read_dcs_packet = mipi_dsi_read_dcs_packet, + .power_up = tc358768_power_up, + .power_down = tc358768_power_down, + +}; + +static int __init tc358768_module_init(void) +{ +#ifdef CONFIG_TC358768_I2C + i2c_add_driver(&tc358768_driver); + + if(!tc358768 || !tc358768_client) + return -1; +#endif + + register_dsi_ops(&tc358768_ops); + if(tc358768->id > 0) + tc358768_ops.id = tc358768->id; + return 0; +} + +static void __exit tc358768_module_exit(void) +{ + del_dsi_ops(&tc358768_ops); +#ifdef CONFIG_TC358768_I2C + i2c_del_driver(&tc358768_driver); +#endif +} + +subsys_initcall_sync(tc358768_module_init); +//module_exit(tc358768_module_init); +module_exit(tc358768_module_exit); diff --git a/drivers/video/rockchip/tve/Kconfig b/drivers/video/rockchip/tve/Kconfig new file mode 100644 index 000000000000..74eaf28651be --- /dev/null +++ b/drivers/video/rockchip/tve/Kconfig @@ -0,0 +1,14 @@ +config RK610_TVOUT + bool "RK610(Jetta) tvout support" + depends on MFD_RK610 + default n + help + Support Jetta(RK610) to output YPbPr and CVBS. + +config RK610_TVOUT_YPbPr + bool "support YPbPr output" + depends on RK610_TVOUT + +config RK610_TVOUT_CVBS + bool "support CVBS output" + depends on RK610_TVOUT diff --git a/drivers/video/rockchip/tve/Makefile b/drivers/video/rockchip/tve/Makefile new file mode 100644 index 000000000000..b7d457326d26 --- /dev/null +++ b/drivers/video/rockchip/tve/Makefile @@ -0,0 +1,6 @@ +# +# Makefile for the jetta tv control. +# +obj-$(CONFIG_RK610_TVOUT) += rk610_tv.o +obj-$(CONFIG_RK610_TVOUT_YPbPr) += rk610_tv_ypbpr.o +obj-$(CONFIG_RK610_TVOUT_CVBS) += rk610_tv_cvbs.o \ No newline at end of file diff --git a/drivers/video/rockchip/tve/rk610_tv.c b/drivers/video/rockchip/tve/rk610_tv.c new file mode 100644 index 000000000000..03237ce4a410 --- /dev/null +++ b/drivers/video/rockchip/tve/rk610_tv.c @@ -0,0 +1,246 @@ +/* + * rk610_tv.c + * + * Driver for rockchip rk610 tv control + * Copyright (C) 2009 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk610_tv.h" +#include "../../rk29_fb.h" + +#define DRV_NAME "rk610_tvout" +#define RK610_I2C_RATE 100*1000 + +volatile int rk610_tv_output_status = RK610_TVOUT_DEAULT; +static struct i2c_client *rk610_tv_i2c_client = NULL; + +int rk610_tv_wirte_reg(u8 reg, u8 data) +{ + int ret; + if(rk610_tv_i2c_client == NULL) + return -1; + ret = i2c_master_reg8_send(rk610_tv_i2c_client, reg, &data, 1, RK610_I2C_RATE); + if (ret > 0) + ret = 0; + return ret; +} + +int rk610_switch_fb(const struct fb_videomode *modedb, int tv_mode) +{ + struct rk29fb_screen *screen; + + if(modedb == NULL) + return -1; + screen = kzalloc(sizeof(struct rk29fb_screen), GFP_KERNEL); + if(screen == NULL) + return -1; + + memset(screen, 0, sizeof(struct rk29fb_screen)); + /* screen type & face */ + screen->type = SCREEN_HDMI; + screen->mode = modedb->vmode; + screen->face = modedb->flag; + /* Screen size */ + screen->x_res = modedb->xres; + screen->y_res = modedb->yres; + + /* Timing */ + screen->pixclock = modedb->pixclock; + + screen->lcdc_aclk = 500000000; + screen->left_margin = modedb->left_margin; + screen->right_margin = modedb->right_margin; + screen->hsync_len = modedb->hsync_len; + screen->upper_margin = modedb->upper_margin; + screen->lower_margin = modedb->lower_margin; + screen->vsync_len = modedb->vsync_len; + + /* Pin polarity */ + if(FB_SYNC_HOR_HIGH_ACT & modedb->sync) + screen->pin_hsync = 1; + else + screen->pin_hsync = 0; + if(FB_SYNC_VERT_HIGH_ACT & modedb->sync) + screen->pin_vsync = 1; + else + screen->pin_vsync = 0; + screen->pin_den = 0; + screen->pin_dclk = 0; + + /* Swap rule */ + screen->swap_rb = 0; + screen->swap_rg = 0; + screen->swap_gb = 0; + screen->swap_delta = 0; + screen->swap_dumy = 0; + + /* Operation function*/ + screen->init = NULL; + screen->standby = NULL; + + switch(tv_mode) + { +#ifdef CONFIG_RK610_TVOUT_CVBS + case TVOUT_CVBS_NTSC: + case TVOUT_CVBS_PAL: + screen->init = rk610_tv_cvbs_init;; + break; +#endif + +#ifdef CONFIG_RK610_TVOUT_YPbPr + case TVOUT_YPbPr_720x480p_60: + case TVOUT_YPbPr_720x576p_50: + case TVOUT_YPbPr_1280x720p_50: + case TVOUT_YPbPr_1280x720p_60: + //case TVOUT_YPbPr_1920x1080i_50: + case TVOUT_YPbPr_1920x1080i_60: + case TVOUT_YPbPr_1920x1080p_50: + case TVOUT_YPbPr_1920x1080p_60: + screen->init = rk610_tv_ypbpr_init; + break; +#endif + default:{ + kfree(screen); + return -1; + } + break; + } + rk610_tv_output_status = tv_mode; + FB_Switch_Screen(screen, 1); + kfree(screen); + return 0; +} + +int rk610_tv_standby(int type) +{ + int ret; + + switch(type) + { + #ifdef CONFIG_RK610_TVOUT_CVBS + case RK610_TVOUT_CVBS: + if(rk610_cvbs_monspecs.enable == 0) + return 0; + #ifdef CONFIG_RK610_TVOUT_YPbPr + if(rk610_ypbpr_monspecs.enable == 1) + return 0; + #endif + break; + #endif + #ifdef CONFIG_RK610_TVOUT_YPbPr + case RK610_TVOUT_YPBPR: + if(rk610_ypbpr_monspecs.enable == 0) + return 0; + #ifdef CONFIG_RK610_TVOUT_CVBS + if(rk610_cvbs_monspecs.enable == 1) + return 0; + #endif + break; + #endif + default: + break; + } + + ret = rk610_tv_wirte_reg(TVE_POWERCR, 0); + if(ret < 0){ + printk("[%s] rk610_tv_wirte_reg err!\n", __FUNCTION__); + return ret; + } + + ret = rk610_control_send_byte(RK610_CONTROL_REG_TVE_CON, 0); + if(ret < 0){ + printk("[%s] rk610_control_send_byte err!\n", __FUNCTION__); + return ret; + } + return 0; +} + +static int rk610_tv_probe(struct i2c_client *client,const struct i2c_device_id *id) +{ + int rc = 0; + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { + rc = -ENODEV; + goto failout; + } + rk610_tv_i2c_client = client; + +#ifdef CONFIG_RK610_TVOUT_YPbPr + rk610_register_display_ypbpr(&client->dev); + if(rk610_tv_output_status > TVOUT_CVBS_PAL) + rk_display_device_enable(rk610_ypbpr_monspecs.ddev); +#endif + +#ifdef CONFIG_RK610_TVOUT_CVBS + rk610_register_display_cvbs(&client->dev); + if(rk610_tv_output_status < TVOUT_YPbPr_720x480p_60) + rk_display_device_enable(rk610_cvbs_monspecs.ddev); +#endif + + printk(KERN_INFO "rk610_tv ver 1.0 probe ok\n"); + return 0; +failout: + kfree(client); + return rc; +} + +static int rk610_tv_remove(struct i2c_client *client) +{ + return 0; +} + + +static const struct i2c_device_id rk610_tv_id[] = { + { DRV_NAME, 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, rk610_tv_id); + +static struct i2c_driver rk610_tv_driver = { + .driver = { + .name = DRV_NAME, + }, + .id_table = rk610_tv_id, + .probe = rk610_tv_probe, + .remove = rk610_tv_remove, +}; + +static int __init rk610_tv_init(void) +{ + int ret = 0; + ret = i2c_add_driver(&rk610_tv_driver); + if(ret < 0){ + printk("i2c_add_driver err, ret = %d\n", ret); + } + return ret; +} + +static void __exit rk610_tv_exit(void) +{ + i2c_del_driver(&rk610_tv_driver); +} + +module_init(rk610_tv_init); +//late_initcall(rk610_tv_init); +module_exit(rk610_tv_exit); + +/* Module information */ +MODULE_DESCRIPTION("ROCKCHIP RK610 TV Output"); +MODULE_LICENSE("GPL"); + + diff --git a/drivers/video/rockchip/tve/rk610_tv.h b/drivers/video/rockchip/tve/rk610_tv.h new file mode 100644 index 000000000000..422e8f25c83a --- /dev/null +++ b/drivers/video/rockchip/tve/rk610_tv.h @@ -0,0 +1,131 @@ +#ifndef _RK610_TV_H +#define _RK610_TV_H +#include +#include +#include +#include +#ifdef CONFIG_ARCH_RK29 +#include +#endif +#include "../screen/screen.h" +#include "../../rk29_fb.h" +#include + +#define TVE_VFCR 0x00 + #define TVE_VFCR_ENABLE_SUBCARRIER_RESET 0 << 6 + #define TVE_VFCR_DISABLE_SUBCARRIER_RESET 1 << 6 + #define TVE_VFCR_VIN_RANGE_16_235 0 << 3 + #define TVE_VFCR_VIN_RANGE_1_254 1 << 3 + #define TVE_VFCR_BLACK_7_5_IRE 0 << 2 + #define TVE_VFCR_BLACK_0_IRE 1 << 2 + #define TVE_VFCR_NTSC 0 + #define TVE_VFCR_PAL_M 1 + #define TVE_VFCR_PAL_B_N 2 + #define TVE_VFCR_PAL_NC 3 + +#define TVE_VINCR 0x01 + #define TVE_VINCR_PIX_DATA_DELAY(n) (n << 5) + #define TVE_VINCR_H_SYNC_POLARITY_NEGTIVE 0 << 4 + #define TVE_VINCR_H_SYNC_POLARITY_POSITIVE 1 << 4 + #define TVE_VINCR_V_SYNC_POLARITY_NEGTIVE 0 << 3 + #define TVE_VINCR_V_SYNC_POLARITY_POSITIVE 1 << 3 +enum { + INPUT_FORMAT_BT601_SLAVE = 0, + INPUT_FORMAT_BT656, + INPUT_FORMAT_BT601_MASTER, + INPUT_FORMAT_INTERNAL_COLLOR_BAR +}; + #define TVE_VINCR_INPUT_FORMAT(n) (n << 1) + #define TVE_VINCR_VSYNC_FUNCTION_VSYNC 0 + #define TVE_VINCR_VSYNC_FUNCTION_FIELD 1 + +#define TVE_VOUTCR 0x02 + #define TVE_VOUTCR_OUTPUT_CVBS 0 << 6 + #define TVE_VOUTCR_OUTPUT_YPBPR 1 << 6 + #define TVE_VOUTCR_OUTPUT_ENABLE_BLUE 1 << 5 + #define TVE_VOUTCR_OUTPUT_ENABLE_BLACK 1 << 4 + #define TVE_VOUTCR_DISABLE_CVBS_COLOR 1 << 3 + #define TVE_VOUTCR_CVBS_Y2C_DELAY(n) (n << 0) + +#define TVE_POWERCR 0x03 + #define TVE_PIX_CLK_INVERSE_ENABLE 1 << 4 + #define TVE_DAC_CLK_INVERSE_DISABLE 1 << 3 + #define TVE_DAC_Y_ENABLE 1 << 2 + #define TVE_DAC_U_ENABLE 1 << 1 + #define TVE_DAC_V_ENABLE 1 << 0 + +#define TVE_HDTVCR 0x05 + #define TVE_RESET 1 << 7 + #define TVE_FILTER(n) (n << 5) + #define TVE_COLOR_CONVERT_REC601 0 << 4 + #define TVE_COLOR_CONVERT_REC709 1 << 4 + #define TVE_INPUT_DATA_RGB 0 << 3 + #define TVE_INPUT_DATA_YUV 1 << 3 + #define TVE_OUTPUT_50HZ 0 << 2 + #define TVE_OUTPUT_60HZ 1 << 2 + #define TVE_OUTPUT_MODE_PAL_NTSC 0 + #define TVE_OUTPUT_MODE_576P 1 + #define TVE_OUTPUT_MODE_480P 2 + #define TVE_OUTPUT_MODE_720P 3 + +#define TVE_YADJCR 0x06 + #define TVE_OUTPUT_MODE_1080P 1 << 6 + #define TVE_OUTPUT_MODE_1080I 1 << 5 + #define TVE_Y_ADJ_VALUE(n) n +#define TVE_YCBADJCR 0x07 +#define TVE_YCRADJCR 0x08 + +/******************* TVOUT OUTPUT TYPE **********************/ +struct rk610_monspecs { + struct rk_display_device *ddev; + unsigned int enable; + struct fb_videomode *mode; + struct list_head modelist; + unsigned int mode_set; +}; + +enum { + TVOUT_CVBS_NTSC = 1, + TVOUT_CVBS_PAL, + TVOUT_YPbPr_720x480p_60, + TVOUT_YPbPr_720x576p_50, + TVOUT_YPbPr_1280x720p_50, + TVOUT_YPbPr_1280x720p_60, + //TVOUT_YPbPr_1920x1080i_50, + TVOUT_YPbPr_1920x1080i_60, + TVOUT_YPbPr_1920x1080p_50, + TVOUT_YPbPr_1920x1080p_60 +}; + +#define RK610_TVOUT_DEAULT TVOUT_CVBS_NTSC + +enum { + RK610_TVOUT_CVBS = 0, + RK610_TVOUT_YC, + RK610_TVOUT_YPBPR, +}; + +extern volatile int rk610_tv_output_status; +extern struct rk_display_ops rk610_display_ops; + +extern int FB_Switch_Screen( struct rk29fb_screen *screen, u32 enable ); + +extern int rk610_tv_wirte_reg(u8 reg, u8 data); +extern int rk610_tv_standby(int type); +extern int rk610_switch_fb(const struct fb_videomode *modedb, int tv_mode); +extern int rk610_register_display(struct device *parent); + +#ifdef CONFIG_RK610_TVOUT_YPbPr +extern int rk610_tv_ypbpr_init(void); +extern int rk610_register_display_ypbpr(struct device *parent); +extern struct rk610_monspecs rk610_ypbpr_monspecs; +#endif + +#ifdef CONFIG_RK610_TVOUT_CVBS +extern int rk610_tv_cvbs_init(void); +extern int rk610_register_display_cvbs(struct device *parent); +extern struct rk610_monspecs rk610_cvbs_monspecs; +#endif + +#endif + diff --git a/drivers/video/rockchip/tve/rk610_tv_cvbs.c b/drivers/video/rockchip/tve/rk610_tv_cvbs.c new file mode 100644 index 000000000000..ea0fe8a0d79c --- /dev/null +++ b/drivers/video/rockchip/tve/rk610_tv_cvbs.c @@ -0,0 +1,209 @@ +#include +#include +#include +#include "rk610_tv.h" + + +#ifdef CONFIG_DISPLAY_KEY_LED_CONTROL +#define RK610_LED_CVBS_PIN RK29_PIN4_PD3 +#else +#define RK610_LED_CVBS_PIN INVALID_GPIO +#endif + +#ifdef USE_RGB2CCIR +static const struct fb_videomode rk610_cvbs_mode [] = { + //name refresh xres yres pixclock h_bp h_fp v_bp v_fp h_pw v_pw polariry PorI flag + { "NTSC", 60, 720, 480, 27000000, 116, 16, 25, 14, 6, 6, 0, 1, OUT_P888 }, + { "PAL", 50, 720, 576, 27000000, 126, 12, 37, 6, 6, 6, 0, 1, OUT_P888 }, +}; +#else +static const struct fb_videomode rk610_cvbs_mode [] = { + //name refresh xres yres pixclock h_bp h_fp v_bp v_fp h_pw v_pw polariry PorI flag + { "NTSC", 60, 720, 480, 27000000, 116, 16, 16, 3, 6, 3, 0, 1, OUT_CCIR656 }, + { "PAL", 50, 720, 576, 27000000, 126, 12, 19, 2, 6, 3, 0, 1, OUT_CCIR656 }, +}; +#endif + +struct rk610_monspecs rk610_cvbs_monspecs; + + +int rk610_tv_cvbs_init(void) +{ + unsigned char TVE_Regs[9]; + unsigned char TVE_CON_Reg; + int ret, i; + + rk610_tv_wirte_reg(TVE_HDTVCR, TVE_RESET); + + memset(TVE_Regs, 0, 9); + TVE_CON_Reg = TVE_CONTROL_CVBS_3_CHANNEL_ENALBE; + TVE_Regs[TVE_VINCR] = TVE_VINCR_PIX_DATA_DELAY(0) | TVE_VINCR_H_SYNC_POLARITY_NEGTIVE | TVE_VINCR_V_SYNC_POLARITY_NEGTIVE | TVE_VINCR_VSYNC_FUNCTION_VSYNC; + TVE_Regs[TVE_POWERCR] = TVE_DAC_Y_ENABLE | TVE_DAC_U_ENABLE | TVE_DAC_V_ENABLE; + TVE_Regs[TVE_VOUTCR] = TVE_VOUTCR_OUTPUT_CVBS; + TVE_Regs[TVE_YADJCR] = 0x17; + TVE_Regs[TVE_YCBADJCR] = 0x10; + TVE_Regs[TVE_YCRADJCR] = 0x10; + + switch(rk610_tv_output_status) { + case TVOUT_CVBS_NTSC: + TVE_Regs[TVE_VFCR] = TVE_VFCR_ENABLE_SUBCARRIER_RESET | TVE_VFCR_VIN_RANGE_16_235 | TVE_VFCR_BLACK_7_5_IRE | TVE_VFCR_NTSC; + #ifdef USE_RGB2CCIR + TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT601_SLAVE); + TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_COLOR_CONVERT_REC601 | TVE_INPUT_DATA_RGB | TVE_OUTPUT_MODE_PAL_NTSC; + TVE_CON_Reg |= RGB2CCIR_INPUT_DATA_FORMAT(0) | RGB2CCIR_RGB_SWAP_DISABLE | RGB2CCIR_INPUT_PROGRESSIVE | RGB2CCIR_CVBS_NTSC | RGB2CCIR_ENABLE; + #else + TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT656); + TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_INPUT_DATA_YUV | TVE_OUTPUT_MODE_PAL_NTSC; + #endif + break; + case TVOUT_CVBS_PAL: + TVE_Regs[TVE_VFCR] = TVE_VFCR_ENABLE_SUBCARRIER_RESET | TVE_VFCR_VIN_RANGE_16_235 | TVE_VFCR_BLACK_0_IRE | TVE_VFCR_PAL_B_N; + #ifdef USE_RGB2CCIR + TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT601_SLAVE); + TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_COLOR_CONVERT_REC601 | TVE_INPUT_DATA_RGB | TVE_OUTPUT_MODE_PAL_NTSC; + TVE_CON_Reg |= RGB2CCIR_INPUT_DATA_FORMAT(0) | RGB2CCIR_RGB_SWAP_DISABLE | RGB2CCIR_INPUT_PROGRESSIVE | RGB2CCIR_CVBS_PAL | RGB2CCIR_ENABLE; + #else + TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT656); + TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_INPUT_DATA_YUV | TVE_OUTPUT_MODE_PAL_NTSC; + #endif + break; + default: + return -1; + } + + for(i = 0; i < sizeof(TVE_Regs); i++){ +// printk(KERN_ERR "reg[%d] = 0x%02x\n", i, TVE_Regs[i]); + ret = rk610_tv_wirte_reg(i, TVE_Regs[i]); + if(ret < 0){ + printk(KERN_ERR "rk610_tv_wirte_reg %d err!\n", i); + return ret; + } + } +// printk(KERN_ERR "TVE_CON_Reg = 0x%02x\n", TVE_CON_Reg); + rk610_control_send_byte(RK610_CONTROL_REG_TVE_CON, TVE_CON_Reg); + #ifdef USE_RGB2CCIR + rk610_control_send_byte(RK610_CONTROL_REG_CCIR_RESET, 0x01); + #endif + return 0; +} + +static int rk610_cvbs_set_enable(struct rk_display_device *device, int enable) +{ + if(rk610_cvbs_monspecs.enable != enable || rk610_cvbs_monspecs.mode_set != rk610_tv_output_status) + { + if(enable == 0) + { + rk610_tv_standby(RK610_TVOUT_CVBS); + rk610_cvbs_monspecs.enable = 0; + if(RK610_LED_CVBS_PIN != INVALID_GPIO) + gpio_direction_output(RK610_LED_CVBS_PIN, GPIO_HIGH); + } + else if(enable == 1) + { + rk610_switch_fb(rk610_cvbs_monspecs.mode, rk610_cvbs_monspecs.mode_set); + rk610_cvbs_monspecs.enable = 1; + if(RK610_LED_CVBS_PIN != INVALID_GPIO) + gpio_direction_output(RK610_LED_CVBS_PIN, GPIO_LOW); + } + } + return 0; +} + +static int rk610_cvbs_get_enable(struct rk_display_device *device) +{ + return rk610_cvbs_monspecs.enable; +} + +static int rk610_cvbs_get_status(struct rk_display_device *device) +{ + if(rk610_tv_output_status < TVOUT_YPbPr_720x480p_60) + return 1; + else + return 0; +} + +static int rk610_cvbs_get_modelist(struct rk_display_device *device, struct list_head **modelist) +{ + *modelist = &(rk610_cvbs_monspecs.modelist); + return 0; +} + +static int rk610_cvbs_set_mode(struct rk_display_device *device, struct fb_videomode *mode) +{ + int i; + + for(i = 0; i < ARRAY_SIZE(rk610_cvbs_mode); i++) + { + if(fb_mode_is_equal(&rk610_cvbs_mode[i], mode)) + { + if( ((i + 1) != rk610_tv_output_status) ) + { + rk610_cvbs_monspecs.mode_set = i + 1; + rk610_cvbs_monspecs.mode = (struct fb_videomode *)&rk610_cvbs_mode[i]; + } + return 0; + } + } + + return -1; +} + +static int rk610_cvbs_get_mode(struct rk_display_device *device, struct fb_videomode *mode) +{ + *mode = *(rk610_cvbs_monspecs.mode); + return 0; +} + +static struct rk_display_ops rk610_cvbs_display_ops = { + .setenable = rk610_cvbs_set_enable, + .getenable = rk610_cvbs_get_enable, + .getstatus = rk610_cvbs_get_status, + .getmodelist = rk610_cvbs_get_modelist, + .setmode = rk610_cvbs_set_mode, + .getmode = rk610_cvbs_get_mode, +}; + +static int rk610_display_cvbs_probe(struct rk_display_device *device, void *devdata) +{ + device->owner = THIS_MODULE; + strcpy(device->type, "TV"); + device->priority = DISPLAY_PRIORITY_TV; + device->priv_data = devdata; + device->ops = &rk610_cvbs_display_ops; + return 1; +} + +static struct rk_display_driver display_rk610_cvbs = { + .probe = rk610_display_cvbs_probe, +}; + +int rk610_register_display_cvbs(struct device *parent) +{ + int i; + + memset(&rk610_cvbs_monspecs, 0, sizeof(struct rk610_monspecs)); + INIT_LIST_HEAD(&rk610_cvbs_monspecs.modelist); + for(i = 0; i < ARRAY_SIZE(rk610_cvbs_mode); i++) + fb_add_videomode(&rk610_cvbs_mode[i], &rk610_cvbs_monspecs.modelist); + if(rk610_tv_output_status < TVOUT_YPbPr_720x480p_60) { + rk610_cvbs_monspecs.mode = (struct fb_videomode *)&(rk610_cvbs_mode[rk610_tv_output_status - 1]); + rk610_cvbs_monspecs.mode_set = rk610_tv_output_status; + } + else { + rk610_cvbs_monspecs.mode = (struct fb_videomode *)&(rk610_cvbs_mode[0]); + rk610_cvbs_monspecs.mode_set = TVOUT_CVBS_NTSC; + } + rk610_cvbs_monspecs.ddev = rk_display_device_register(&display_rk610_cvbs, parent, NULL); + if(RK610_LED_CVBS_PIN != INVALID_GPIO) + { + if(gpio_request(RK610_LED_CVBS_PIN, NULL) != 0) + { + gpio_free(RK610_LED_CVBS_PIN); + dev_err(rk610_cvbs_monspecs.ddev->dev, ">>>>>> RK610_LED_CVBS_PIN gpio_request err \n "); + return -1; + } + gpio_pull_updown(RK610_LED_CVBS_PIN,GPIOPullUp); + gpio_direction_output(RK610_LED_CVBS_PIN, GPIO_HIGH); + } + return 0; +} diff --git a/drivers/video/rockchip/tve/rk610_tv_ypbpr.c b/drivers/video/rockchip/tve/rk610_tv_ypbpr.c new file mode 100644 index 000000000000..af74126f7604 --- /dev/null +++ b/drivers/video/rockchip/tve/rk610_tv_ypbpr.c @@ -0,0 +1,229 @@ +#include +#include +#include +#include "rk610_tv.h" + + +#ifdef CONFIG_DISPLAY_KEY_LED_CONTROL +#define RK610_LED_YPbPr_PIN RK29_PIN4_PD5 +#else +#define RK610_LED_YPbPr_PIN INVALID_GPIO +#endif +#define E(fmt, arg...) printk("<3>!!!%s:%d: " fmt, __FILE__, __LINE__, ##arg) + +static const struct fb_videomode rk610_YPbPr_mode [] = { + //name refresh xres yres pixclock h_bp h_fp v_bp v_fp h_pw v_pw polariry PorI flag + { "YPbPr480p", 60, 720, 480, 27000000, 55, 19, 37, 5, 64, 5, 0, 0, OUT_P888 }, + { "YPbPr576p", 50, 720, 576, 27000000, 68, 12, 39, 5, 64, 5, 0, 0, OUT_P888 }, + { "YPbPr720p@50", 50, 1280, 720, 74250000, 600, 0, 20, 5, 100, 5, 0, 0, OUT_P888 }, + { "YPbPr720p@60", 60, 1280, 720, 74250000, 270, 0, 20, 5, 100, 5, 0, 0, OUT_P888 }, + //{ "YPbPr1080i@50", 50, 1920, 1080, 148500000, 620, 0, 15, 2, 100, 5, 0, 1, OUT_CCIR656 }, + { "YPbPr1080i@60", 60, 1920, 1080, 148500000, 180, 0, 15, 2, 100, 5, 0, 1, OUT_CCIR656 }, + { "YPbPr1080p@50", 50, 1920, 1080, 148500000, 620, 0, 36, 4, 100, 5, 0, 0, OUT_P888 }, + { "YPbPr1080p@60", 60, 1920, 1080, 148500000, 180, 0, 36, 4, 100, 5, 0, 0, OUT_P888 }, +}; + +struct rk610_monspecs rk610_ypbpr_monspecs; + +int rk610_tv_ypbpr_init(void) +{ + unsigned char TVE_Regs[9]; + unsigned char TVE_CON_Reg; + int i, ret; + + rk610_tv_wirte_reg(TVE_HDTVCR, TVE_RESET); + memset(TVE_Regs, 0, 9); + + TVE_CON_Reg = 0x00; + + TVE_Regs[TVE_VINCR] = TVE_VINCR_PIX_DATA_DELAY(0) | TVE_VINCR_H_SYNC_POLARITY_NEGTIVE | TVE_VINCR_V_SYNC_POLARITY_NEGTIVE | TVE_VINCR_VSYNC_FUNCTION_VSYNC; + TVE_Regs[TVE_POWERCR] = TVE_DAC_CLK_INVERSE_DISABLE | TVE_DAC_Y_ENABLE | TVE_DAC_U_ENABLE | TVE_DAC_V_ENABLE; + TVE_Regs[TVE_VOUTCR] = TVE_VOUTCR_OUTPUT_YPBPR; + TVE_Regs[TVE_YADJCR] = 0x17; + TVE_Regs[TVE_YCBADJCR] = 0x10; + TVE_Regs[TVE_YCRADJCR] = 0x10; + + switch(rk610_tv_output_status) + { + case TVOUT_YPbPr_720x480p_60: + TVE_Regs[TVE_VFCR] = TVE_VFCR_BLACK_0_IRE; + TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT601_SLAVE); + TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_COLOR_CONVERT_REC601 | TVE_INPUT_DATA_RGB | TVE_OUTPUT_60HZ | TVE_OUTPUT_MODE_480P; + break; + case TVOUT_YPbPr_720x576p_50: + TVE_Regs[TVE_VFCR] = TVE_VFCR_BLACK_0_IRE | TVE_VFCR_PAL_NC; + TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT601_SLAVE); + TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_COLOR_CONVERT_REC601 | TVE_INPUT_DATA_RGB | TVE_OUTPUT_50HZ | TVE_OUTPUT_MODE_576P; + break; + case TVOUT_YPbPr_1280x720p_50: + TVE_Regs[TVE_VFCR] = TVE_VFCR_BLACK_0_IRE | TVE_VFCR_PAL_NC; + TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT601_SLAVE); + TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_COLOR_CONVERT_REC709 | TVE_INPUT_DATA_RGB | TVE_OUTPUT_50HZ | TVE_OUTPUT_MODE_720P; + break; + case TVOUT_YPbPr_1280x720p_60: + TVE_Regs[TVE_VFCR] = TVE_VFCR_BLACK_0_IRE | TVE_VFCR_PAL_NC; + TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT601_SLAVE); + TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_COLOR_CONVERT_REC709 | TVE_INPUT_DATA_RGB | TVE_OUTPUT_60HZ | TVE_OUTPUT_MODE_720P; + break; + /*case TVOUT_YPbPr_1920x1080i_50: + TVE_Regs[TVE_VFCR] = TVE_VFCR_BLACK_0_IRE | TVE_VFCR_PAL_NC; + TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT656); + TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_INPUT_DATA_YUV | TVE_OUTPUT_50HZ; + TVE_Regs[TVE_YADJCR] |= TVE_OUTPUT_MODE_1080I; + break; + */ + case TVOUT_YPbPr_1920x1080i_60: + TVE_Regs[TVE_VFCR] = TVE_VFCR_BLACK_0_IRE | TVE_VFCR_PAL_NC; + TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT656); + TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_INPUT_DATA_YUV | TVE_OUTPUT_60HZ; + TVE_Regs[TVE_YADJCR] |= TVE_OUTPUT_MODE_1080I; + break; + case TVOUT_YPbPr_1920x1080p_50: + TVE_Regs[TVE_VFCR] = TVE_VFCR_BLACK_0_IRE | TVE_VFCR_PAL_NC; + TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT601_SLAVE); + TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_COLOR_CONVERT_REC709 | TVE_INPUT_DATA_RGB | TVE_OUTPUT_50HZ; + TVE_Regs[TVE_YADJCR] |= TVE_OUTPUT_MODE_1080P; + break; + case TVOUT_YPbPr_1920x1080p_60: + TVE_Regs[TVE_VFCR] = TVE_VFCR_BLACK_0_IRE | TVE_VFCR_PAL_NC; + TVE_Regs[TVE_VINCR] |= TVE_VINCR_INPUT_FORMAT(INPUT_FORMAT_BT601_SLAVE); + TVE_Regs[TVE_HDTVCR] = TVE_FILTER(0) | TVE_COLOR_CONVERT_REC709 | TVE_INPUT_DATA_RGB | TVE_OUTPUT_60HZ; + TVE_Regs[TVE_YADJCR] |= TVE_OUTPUT_MODE_1080P; + break; + default: + return -1; + } + + rk610_control_send_byte(RK610_CONTROL_REG_TVE_CON, TVE_CON_Reg); + + for(i = 0; i < sizeof(TVE_Regs); i++){ +// printk(KERN_ERR "reg[%d] = 0x%02x\n", i, TVE_Regs[i]); + ret = rk610_tv_wirte_reg(i, TVE_Regs[i]); + if(ret < 0){ + E("rk610_tv_wirte_reg %d err!\n", i); + return ret; + } + } + return 0; +} + +static int rk610_ypbpr_set_enable(struct rk_display_device *device, int enable) +{ + if(rk610_ypbpr_monspecs.enable != enable || rk610_ypbpr_monspecs.mode_set != rk610_tv_output_status) + { + if(enable == 0) + { + rk610_tv_standby(RK610_TVOUT_YPBPR); + rk610_ypbpr_monspecs.enable = 0; + if(RK610_LED_YPbPr_PIN != INVALID_GPIO) + gpio_direction_output(RK610_LED_YPbPr_PIN, GPIO_HIGH); + } + else if(enable == 1) + { + rk610_switch_fb(rk610_ypbpr_monspecs.mode, rk610_ypbpr_monspecs.mode_set); + rk610_ypbpr_monspecs.enable = 1; + if(RK610_LED_YPbPr_PIN != INVALID_GPIO) + gpio_direction_output(RK610_LED_YPbPr_PIN, GPIO_LOW); + } + } + return 0; +} + +static int rk610_ypbpr_get_enable(struct rk_display_device *device) +{ + return rk610_ypbpr_monspecs.enable; +} + +static int rk610_ypbpr_get_status(struct rk_display_device *device) +{ + if(rk610_tv_output_status > TVOUT_CVBS_PAL) + return 1; + else + return 0; +} + +static int rk610_ypbpr_get_modelist(struct rk_display_device *device, struct list_head **modelist) +{ + *modelist = &(rk610_ypbpr_monspecs.modelist); + return 0; +} + +static int rk610_ypbpr_set_mode(struct rk_display_device *device, struct fb_videomode *mode) +{ + int i; + + for(i = 0; i < ARRAY_SIZE(rk610_YPbPr_mode); i++) + { + if(fb_mode_is_equal(&rk610_YPbPr_mode[i], mode)) + { + if( (i + 3) != rk610_tv_output_status ) + { + rk610_ypbpr_monspecs.mode_set = i + 3; + rk610_ypbpr_monspecs.mode = (struct fb_videomode *)&rk610_YPbPr_mode[i]; + } + return 0; + } + } + + return -1; +} + +static int rk610_ypbpr_get_mode(struct rk_display_device *device, struct fb_videomode *mode) +{ + *mode = *(rk610_ypbpr_monspecs.mode); + return 0; +} + +static struct rk_display_ops rk610_ypbpr_display_ops = { + .setenable = rk610_ypbpr_set_enable, + .getenable = rk610_ypbpr_get_enable, + .getstatus = rk610_ypbpr_get_status, + .getmodelist = rk610_ypbpr_get_modelist, + .setmode = rk610_ypbpr_set_mode, + .getmode = rk610_ypbpr_get_mode, +}; + +static int rk610_display_YPbPr_probe(struct rk_display_device *device, void *devdata) +{ + device->owner = THIS_MODULE; + strcpy(device->type, "YPbPr"); + device->priority = DISPLAY_PRIORITY_YPbPr; + device->priv_data = devdata; + device->ops = &rk610_ypbpr_display_ops; + return 1; +} + +static struct rk_display_driver display_rk610_YPbPr = { + .probe = rk610_display_YPbPr_probe, +}; + +int rk610_register_display_ypbpr(struct device *parent) +{ + int i; + + memset(&rk610_ypbpr_monspecs, 0, sizeof(struct rk610_monspecs)); + INIT_LIST_HEAD(&rk610_ypbpr_monspecs.modelist); + for(i = 0; i < ARRAY_SIZE(rk610_YPbPr_mode); i++) + fb_add_videomode(&rk610_YPbPr_mode[i], &rk610_ypbpr_monspecs.modelist); + if(rk610_tv_output_status > TVOUT_CVBS_PAL) { + rk610_ypbpr_monspecs.mode = (struct fb_videomode *)&(rk610_YPbPr_mode[rk610_tv_output_status - 3]); + rk610_ypbpr_monspecs.mode_set = rk610_tv_output_status; + } + else { + rk610_ypbpr_monspecs.mode = (struct fb_videomode *)&(rk610_YPbPr_mode[3]); + rk610_ypbpr_monspecs.mode_set = TVOUT_YPbPr_1280x720p_60; + } + rk610_ypbpr_monspecs.ddev = rk_display_device_register(&display_rk610_YPbPr, parent, NULL); + if(RK610_LED_YPbPr_PIN != INVALID_GPIO) + { + if(gpio_request(RK610_LED_YPbPr_PIN, NULL) != 0) + { + gpio_free(RK610_LED_YPbPr_PIN); + dev_err(rk610_ypbpr_monspecs.ddev->dev, ">>>>>> RK610_LED_YPbPr_PIN gpio_request err \n "); + return -1; + } + gpio_pull_updown(RK610_LED_YPbPr_PIN,GPIOPullUp); + gpio_direction_output(RK610_LED_YPbPr_PIN, GPIO_HIGH); + } + return 0; +} diff --git a/include/linux/rk_screen.h b/include/linux/rk_screen.h index ada2e2404ac1..4b969b8b7caa 100644 --- a/include/linux/rk_screen.h +++ b/include/linux/rk_screen.h @@ -109,7 +109,7 @@ struct rk29lcd_info { typedef struct rk29fb_screen { /* screen type & hardware connect format & out face */ u16 type; - u16 hw_format; + u16 hw_format; //lvds data format u16 face; u8 lcdc_id; //which output interface the screeen connect to u8 screen_id; //screen number