From: Zhenyu Wang Date: Sat, 19 Sep 2009 06:54:06 +0000 (+0800) Subject: drm/i915: Fix typo for wrong LVDS clock setting on IGDNG X-Git-Tag: firefly_0821_release~12332^2~40 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=b09aea7fb38f328c02e9f9b79617cabed02455e4;p=firefly-linux-kernel-4.4.55.git drm/i915: Fix typo for wrong LVDS clock setting on IGDNG New register for PCH LVDS on IGDNG should be used. This is a copy-n-paste typo. This fixes possible dual channel LVDS panel failure on IGDNG. Cc: Stable Team Signed-off-by: Zhenyu Wang Signed-off-by: Jesse Barnes --- diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index cadb9efdfb1b..d2f3692be8eb 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -877,7 +877,7 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, refclk, best_clock); if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { - if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == + if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) clock.p2 = limit->p2.p2_fast; else