From: Chris Lattner Date: Fri, 28 Oct 2005 22:49:02 +0000 (+0000) Subject: Rename Record::getValueAsListDef to getValueAsListOfDefs, to more accurately X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=b0e103d46bf8799ac5523157a6ed4a78d1751a89;p=oota-llvm.git Rename Record::getValueAsListDef to getValueAsListOfDefs, to more accurately reflect what it is. Convert some more code over to use it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24072 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp index 1b3605a273c..e85170d5a6e 100644 --- a/utils/TableGen/CodeGenTarget.cpp +++ b/utils/TableGen/CodeGenTarget.cpp @@ -84,15 +84,8 @@ CodeGenTarget::CodeGenTarget() : PointerType(MVT::Other) { throw std::string("ERROR: Multiple subclasses of Target defined!"); TargetRec = Targets[0]; - // Read in all of the CalleeSavedRegisters... - ListInit *LI = TargetRec->getValueAsListInit("CalleeSavedRegisters"); - for (unsigned i = 0, e = LI->getSize(); i != e; ++i) - if (DefInit *DI = dynamic_cast(LI->getElement(i))) - CalleeSavedRegisters.push_back(DI->getDef()); - else - throw "Target: " + TargetRec->getName() + - " expected register definition in CalleeSavedRegisters list!"; - + // Read in all of the CalleeSavedRegisters. + CalleeSavedRegisters =TargetRec->getValueAsListOfDefs("CalleeSavedRegisters"); PointerType = getValueType(TargetRec->getValueAsDef("PointerType")); } @@ -108,12 +101,10 @@ Record *CodeGenTarget::getInstructionSet() const { /// getAsmWriter - Return the AssemblyWriter definition for this target. /// Record *CodeGenTarget::getAsmWriter() const { - ListInit *LI = TargetRec->getValueAsListInit("AssemblyWriters"); - if (AsmWriterNum >= LI->getSize()) + std::vector LI = TargetRec->getValueAsListOfDefs("AssemblyWriters"); + if (AsmWriterNum >= LI.size()) throw "Target does not have an AsmWriter #" + utostr(AsmWriterNum) + "!"; - DefInit *DI = dynamic_cast(LI->getElement(AsmWriterNum)); - if (!DI) throw std::string("AssemblyWriter list should be a list of defs!"); - return DI->getDef(); + return LI[AsmWriterNum]; } void CodeGenTarget::ReadRegisters() const { @@ -159,12 +150,9 @@ CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) { MethodBodies = R->getValueAsCode("MethodBodies"); MethodProtos = R->getValueAsCode("MethodProtos"); - ListInit *RegList = R->getValueAsListInit("MemberList"); - for (unsigned i = 0, e = RegList->getSize(); i != e; ++i) { - DefInit *RegDef = dynamic_cast(RegList->getElement(i)); - if (!RegDef) throw "Register class member is not a record!"; - Record *Reg = RegDef->getDef(); - + std::vector RegList = R->getValueAsListOfDefs("MemberList"); + for (unsigned i = 0, e = RegList.size(); i != e; ++i) { + Record *Reg = RegList[i]; if (!Reg->isSubClassOf("Register")) throw "Register Class member '" + Reg->getName() + "' does not derive from the Register class!"; diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp index 590a5badd46..fb52355bee1 100644 --- a/utils/TableGen/DAGISelEmitter.cpp +++ b/utils/TableGen/DAGISelEmitter.cpp @@ -228,7 +228,7 @@ SDNodeInfo::SDNodeInfo(Record *R) : Def(R) { // Parse the properties. Properties = 0; - std::vector PropList = R->getValueAsListDef("Properties"); + std::vector PropList = R->getValueAsListOfDefs("Properties"); for (unsigned i = 0, e = PropList.size(); i != e; ++i) { if (PropList[i]->getName() == "SDNPCommutative") { Properties |= 1 << SDNPCommutative; @@ -243,8 +243,9 @@ SDNodeInfo::SDNodeInfo(Record *R) : Def(R) { // Parse the type constraints. - std::vector ConstList =TypeProfile->getValueAsListDef("Constraints"); - TypeConstraints.assign(ConstList.begin(), ConstList.end()); + std::vector ConstraintList = + TypeProfile->getValueAsListOfDefs("Constraints"); + TypeConstraints.assign(ConstraintList.begin(), ConstraintList.end()); } //===----------------------------------------------------------------------===// diff --git a/utils/TableGen/Record.cpp b/utils/TableGen/Record.cpp index 109ed392513..3bbb2d9116e 100644 --- a/utils/TableGen/Record.cpp +++ b/utils/TableGen/Record.cpp @@ -709,12 +709,12 @@ ListInit *Record::getValueAsListInit(const std::string &FieldName) const { "' does not have a list initializer!"; } -/// getValueAsListDef - This method looks up the specified field and returns +/// getValueAsListOfDefs - This method looks up the specified field and returns /// its value as a vector of records, throwing an exception if the field does /// not exist or if the value is not the right type. /// -std::vector Record::getValueAsListDef(const std::string &FieldName) - const { +std::vector +Record::getValueAsListOfDefs(const std::string &FieldName) const { ListInit *List = getValueAsListInit(FieldName); std::vector Defs; for (unsigned i = 0; i < List->getSize(); i++) { diff --git a/utils/TableGen/Record.h b/utils/TableGen/Record.h index ecd6d7020a8..9f300041671 100644 --- a/utils/TableGen/Record.h +++ b/utils/TableGen/Record.h @@ -1000,11 +1000,11 @@ public: /// ListInit *getValueAsListInit(const std::string &FieldName) const; - /// getValueAsListDef - This method looks up the specified field and returns - /// its value as a vector of records, throwing an exception if the field does - /// not exist or if the value is not the right type. + /// getValueAsListOfDefs - This method looks up the specified field and + /// returnsits value as a vector of records, throwing an exception if the + /// field does not exist or if the value is not the right type. /// - std::vector getValueAsListDef(const std::string &FieldName) const; + std::vector getValueAsListOfDefs(const std::string &FieldName) const; /// getValueAsDef - This method looks up the specified field and returns its /// value as a Record, throwing an exception if the field does not exist or if diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp index e6429eaecb8..86b5201d544 100644 --- a/utils/TableGen/SubtargetEmitter.cpp +++ b/utils/TableGen/SubtargetEmitter.cpp @@ -137,7 +137,8 @@ void SubtargetEmitter::CPUKeyValues(std::ostream &OS) { Record *Processor = ProcessorList[i]; std::string Name = Processor->getValueAsString("Name"); - std::vector FeatureList = Processor->getValueAsListDef("Features"); + std::vector FeatureList = + Processor->getValueAsListOfDefs("Features"); // Emit as { "cpu", "description", f1 | f2 | ... fn }, OS << " { " @@ -206,7 +207,7 @@ void SubtargetEmitter::FormItineraryString(Record *ItinData, std::string &ItinString, unsigned &NStages) { // Get states list - std::vector StageList = ItinData->getValueAsListDef("Stages"); + std::vector StageList = ItinData->getValueAsListOfDefs("Stages"); // For each stage unsigned N = NStages = StageList.size(); @@ -219,7 +220,7 @@ void SubtargetEmitter::FormItineraryString(Record *ItinData, ItinString += " ,{ " + itostr(Cycles) + ", "; // Get unit list - std::vector UnitList = Stage->getValueAsListDef("Units"); + std::vector UnitList = Stage->getValueAsListOfDefs("Units"); // For each unit for (unsigned j = 0, M = UnitList.size(); j < M;) { @@ -272,7 +273,7 @@ void SubtargetEmitter::EmitStageData(std::ostream &OS, ItinList.resize(NItinClasses); // Get itinerary data list - std::vector ItinDataList = Proc->getValueAsListDef("IID"); + std::vector ItinDataList = Proc->getValueAsListOfDefs("IID"); // For each itinerary data for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) {