From: Michael Kuperstein <michael.m.kuperstein@intel.com>
Date: Thu, 26 Feb 2015 14:30:09 +0000 (+0000)
Subject: [X86][Haswell][SchedModel] Fix WriteMULm latency.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=b2b5ffd4522c44f706867c1bf7e3e972abdc2334;p=oota-llvm.git

[X86][Haswell][SchedModel] Fix WriteMULm latency.

The latency for the WriteMULm class was set to 4, which is actually lower than the latency for WriteMULr (5).
A better estimate would be 4 added to WriteMULr, that is, 9.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230634 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86SchedHaswell.td b/lib/Target/X86/X86SchedHaswell.td
index 73a32304302..61c06000fc7 100644
--- a/lib/Target/X86/X86SchedHaswell.td
+++ b/lib/Target/X86/X86SchedHaswell.td
@@ -1895,7 +1895,7 @@ def : InstRW<[WriteMULr], (instregex "(V?)MUL(P|S)(S|D)rr")>;
 
 // x,m / v,v,m.
 def WriteMULm : SchedWriteRes<[HWPort01, HWPort23]> {
-  let Latency = 4;
+  let Latency = 9;
   let NumMicroOps = 2;
   let ResourceCycles = [1, 1];
 }