From: Jakob Stoklund Olesen <stoklund@2pi.dk>
Date: Sun, 2 Aug 2009 20:29:41 +0000 (+0000)
Subject: Fix issue in regscavenger when scavenging a callee-saved register that has not been... 
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=b36eb9df205aa83cfdfc8ecebc93e1043d6253d9;p=oota-llvm.git

Fix issue in regscavenger when scavenging a callee-saved register that has not been spilled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77912 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp
index e32d23264d6..e1c8f2fe22e 100644
--- a/lib/CodeGen/RegisterScavenging.cpp
+++ b/lib/CodeGen/RegisterScavenging.cpp
@@ -471,9 +471,16 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
     Reg = Candidates.find_next(Reg);
   }
 
-  assert(ScavengedReg == 0 && 
+  assert(ScavengedReg == 0 &&
          "Scavenger slot is live, unable to scavenge another register!");
 
+  // Make sure SReg is marked as used. It could be considered available if it is
+  // one of the callee saved registers, but hasn't been spilled.
+  if (!isUsed(SReg)) {
+    MBB->addLiveIn(SReg);
+    setUsed(SReg);
+  }
+
   // Spill the scavenged register before I.
   TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
   MachineBasicBlock::iterator II = prior(I);
diff --git a/test/CodeGen/Blackfin/addsub-i128.ll b/test/CodeGen/Blackfin/addsub-i128.ll
index 8dd04d808a4..f0934e9307f 100644
--- a/test/CodeGen/Blackfin/addsub-i128.ll
+++ b/test/CodeGen/Blackfin/addsub-i128.ll
@@ -1,7 +1,7 @@
 ; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs
-; XFAIL: *
-; Assertion failed: (isUsed(Reg) && "Using an undefined register!"),
-; function forward, file RegisterScavenging.cpp, line 182.
+
+; These functions have just the right size to annoy the register scavenger: They
+; use all the scratch registers, but not all the callee-saved registers.
 
 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
 entry: