From: Michel Thierry Date: Mon, 7 Jul 2014 11:40:17 +0000 (+0100) Subject: drm/i915/bdw: 3D_CHICKEN3 has write mask bits X-Git-Tag: firefly_0821_release~176^2~3450^2~49^2~67 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=b3f9ad93b7621364ed51f9c37b9cf9abc9855991;p=firefly-linux-kernel-4.4.55.git drm/i915/bdw: 3D_CHICKEN3 has write mask bits The workaround to limit SDE poly depth FIFO to 2 is not applied because 3D Chicken-3 mask bit is not set. WaLimitSizeOfSDEPolyFifo is only for BDW-A and could be removed. Signed-off-by: Michel Thierry Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 41c1b79959f7..f2a40565ef98 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5375,7 +5375,7 @@ static void gen8_init_clock_gating(struct drm_device *dev) I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE)); I915_WRITE(_3D_CHICKEN3, - _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)); + _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2))); I915_WRITE(COMMON_SLICE_CHICKEN2, _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));