From: Owen Anderson <resistor@mac.com>
Date: Wed, 31 Aug 2011 22:00:41 +0000 (+0000)
Subject: The asm parser currently selects the wrong encoding for non-conditional Thumb2 branch... 
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=b45b11bce1fd79b0973d2df8db295583b5477c62;p=oota-llvm.git

The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches.  However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful.  Specify additional fixed bits to close those gaps.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138910 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 10b17f37519..431c67a5377 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -3243,7 +3243,9 @@ class T2SpecialReg<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
   : T2I<oops, iops, itin, opc, asm, pattern> {
   let Inst{31-20} = op31_20{11-0};
   let Inst{15-14} = op15_14{1-0};
+  let Inst{13}    = 0b0;
   let Inst{12} = op12{0};
+  let Inst{7-0}   = 0;
 }
 
 class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
@@ -3276,7 +3278,6 @@ def t2MSR : T2SpecialReg<0b111100111000 /* op31-20 */, 0b10 /* op15-14 */,
   bits<4> Rn;
   let Inst{19-16} = Rn;
   let Inst{20}    = mask{4}; // R Bit
-  let Inst{13}    = 0b0;
   let Inst{11-8}  = mask{3-0};
 }
 
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index f4ca9ecc5d6..0c2abe28ec9 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -2603,17 +2603,17 @@ DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
 
   unsigned pred = fieldFromInstruction32(Insn, 22, 4);
   if (pred == 0xE || pred == 0xF) {
-    unsigned opc = fieldFromInstruction32(Insn, 4, 2);
+    unsigned opc = fieldFromInstruction32(Insn, 4, 28);
     switch (opc) {
       default:
         return Fail;
-      case 0:
+      case 0xf3bf8f4:
         Inst.setOpcode(ARM::t2DSB);
         break;
-      case 1:
+      case 0xf3bf8f5:
         Inst.setOpcode(ARM::t2DMB);
         break;
-      case 2:
+      case 0xf3bf8f6:
         Inst.setOpcode(ARM::t2ISB);
         return Success;
     }