From: Greg Meiste Date: Fri, 27 Aug 2010 14:51:44 +0000 (-0500) Subject: [ARM] tegra: stingray: CPCAP switcher voltage settings correction X-Git-Tag: firefly_0821_release~9834^2~631 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=b669cdfaa1d5740674cffc2f09b1ac59d3aa667d;p=firefly-linux-kernel-4.4.55.git [ARM] tegra: stingray: CPCAP switcher voltage settings correction CPCAP should not be automatically dropping SW2 and SW4 to 0.95v when the primary standby line drops. This must be controlled by DVS as per nVidia. Change-Id: I336dd3fc30ec0ff8672c88eeed81a6b0a8617b00 Signed-off-by: Greg Meiste Signed-off-by: Nick Pelly --- diff --git a/arch/arm/mach-tegra/board-stingray-power.c b/arch/arm/mach-tegra/board-stingray-power.c index 4cbfacf453b5..fb5c1c6b14c8 100644 --- a/arch/arm/mach-tegra/board-stingray-power.c +++ b/arch/arm/mach-tegra/board-stingray-power.c @@ -297,11 +297,11 @@ static struct platform_device *cpcap_devices[] = { struct cpcap_spi_init_data stingray_cpcap_spi_init[] = { {CPCAP_REG_S1C1, 0x0000}, {CPCAP_REG_S1C2, 0x0000}, - {CPCAP_REG_S2C1, 0x2830}, - {CPCAP_REG_S2C2, 0x301C}, - {CPCAP_REG_S3C, 0x0141}, - {CPCAP_REG_S4C1, 0x2830}, - {CPCAP_REG_S4C2, 0x301C}, + {CPCAP_REG_S2C1, 0x4830}, + {CPCAP_REG_S2C2, 0x3030}, + {CPCAP_REG_S3C, 0x0541}, + {CPCAP_REG_S4C1, 0x4830}, + {CPCAP_REG_S4C2, 0x3030}, {CPCAP_REG_S6C, 0x0000}, {CPCAP_REG_VRF1C, 0x0000}, {CPCAP_REG_VRF2C, 0x0000},