From: 黄涛 Date: Thu, 28 Jul 2011 02:08:21 +0000 (+0800) Subject: rk2818: remove all rk2818 stuff, prepare for 2.6.36 X-Git-Tag: firefly_0821_release~10073 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=b9556fd539fd2000abb09afead4e4bbe19706d0b;p=firefly-linux-kernel-4.4.55.git rk2818: remove all rk2818 stuff, prepare for 2.6.36 --- diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c03809f37c53..ccf23ffc9006 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -707,20 +707,6 @@ config ARCH_BCMRING help Support for Broadcom's BCMRing platform. -config ARCH_RK2818 - bool "Rockchip soc rk2818" - select CPU_ARM926T - select CPU_CP15_MMU - select HAVE_TCM - select HAVE_CLK - select COMMON_CLKDEV - select ARCH_HAS_CPUFREQ - select GENERIC_TIME - select GENERIC_CLOCKEVENTS - select ARCH_REQUIRE_GPIOLIB - help - Support for Rockchip RK2818 soc. - config ARCH_RK29 bool "Rockchip Soc Rk29" select CPU_V7 @@ -840,8 +826,6 @@ source "arch/arm/mach-w90x900/Kconfig" source "arch/arm/mach-bcmring/Kconfig" -source "arch/arm/mach-rk2818/Kconfig" - source "arch/arm/mach-rk29/Kconfig" # Definitions to make life easier diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 13a724dbab29..e15c936b7cc8 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -170,7 +170,6 @@ machine-$(CONFIG_ARCH_VERSATILE) := versatile machine-$(CONFIG_ARCH_W90X900) := w90x900 machine-$(CONFIG_FOOTBRIDGE) := footbridge machine-$(CONFIG_ARCH_MXC91231) := mxc91231 -machine-$(CONFIG_ARCH_RK2818) := rk2818 machine-$(CONFIG_ARCH_RK29) := rk29 # Platform directory name. This list is sorted alphanumerically diff --git a/arch/arm/configs/rk2818_info_defconfig b/arch/arm/configs/rk2818_info_defconfig deleted file mode 100755 index 096610f90229..000000000000 --- a/arch/arm/configs/rk2818_info_defconfig +++ /dev/null @@ -1,1943 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.32.9 -# Tue Sep 7 18:19:13 2010 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_HAVE_TCM=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_ARCH_HAS_CPUFREQ=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_LOCK_KERNEL=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -# CONFIG_LOCALVERSION_AUTO is not set -# CONFIG_SWAP is not set -# CONFIG_SYSVIPC is not set -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_IKCONFIG is not set -CONFIG_LOG_BUF_SHIFT=17 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -CONFIG_RT_GROUP_SCHED=y -# CONFIG_USER_SCHED is not set -CONFIG_CGROUP_SCHED=y -CONFIG_CGROUPS=y -CONFIG_CGROUP_DEBUG=y -# CONFIG_CGROUP_NS is not set -CONFIG_CGROUP_FREEZER=y -# CONFIG_CGROUP_DEVICE is not set -# CONFIG_CPUSETS is not set -CONFIG_CGROUP_CPUACCT=y -CONFIG_RESOURCE_COUNTERS=y -# CONFIG_CGROUP_MEM_RES_CTLR is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_PANIC_TIMEOUT=5 -CONFIG_EMBEDDED=y -CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -# CONFIG_ELF_CORE is not set -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_ASHMEM=y -CONFIG_AIO=y - -# -# Kernel Performance Events And Counters -# -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_CLK=y - -# -# GCOV-based kernel profiling -# -# CONFIG_SLOW_WORK is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_BLOCK=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -# CONFIG_IOSCHED_AS is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_FREEZER=y - -# -# System Type -# -CONFIG_MMU=y -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_STMP3XXX is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PC1XX is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_U300 is not set -# CONFIG_ARCH_DAVINCI is not set -# CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_BCMRING is not set -CONFIG_ARCH_RK2818=y - -# -# ROCKCHIP rk2818 Board Type -# -# CONFIG_MACH_RK2818MID is not set -# CONFIG_MACH_RK2818PHONE is not set -# CONFIG_MACH_RAHO is not set -CONFIG_MACH_RK2818INFO=y -# CONFIG_MACH_RK2818INFO_IT50 is not set -CONFIG_RK28_GPIO_IRQ=16 -CONFIG_RK28_ADC=y -CONFIG_RK28_USB_WAKE=y -CONFIG_WIFI_CONTROL_FUNC=y - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_ARM926T=y -CONFIG_CPU_32v5=y -CONFIG_CPU_ABRT_EV5TJ=y -CONFIG_CPU_PABRT_LEGACY=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_COPY_V4WB=y -CONFIG_CPU_TLB_V4WBI=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -CONFIG_ARM_THUMB=y -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set -# CONFIG_CPU_CACHE_ROUND_ROBIN is not set -CONFIG_ARM_L1_CACHE_SHIFT=5 -CONFIG_COMMON_CLKDEV=y - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 -# CONFIG_PREEMPT_NONE is not set -# CONFIG_PREEMPT_VOLUNTARY is not set -CONFIG_PREEMPT=y -CONFIG_HZ=100 -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4096 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_UACCESS_WITH_MEMCPY is not set - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_CMDLINE="mem=128M console=ttyS1,115200n8" -# CONFIG_XIP_KERNEL is not set -# CONFIG_KEXEC is not set - -# -# CPU Power Management -# -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_TABLE=y -# CONFIG_CPU_FREQ_DEBUG is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_STAT_DETAILS=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -# CONFIG_CPU_IDLE is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -# CONFIG_VFP is not set - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -CONFIG_HAVE_AOUT=y -# CONFIG_BINFMT_AOUT is not set -# CONFIG_BINFMT_MISC is not set - -# -# Power management options -# -CONFIG_PM=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_SLEEP=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_HAS_WAKELOCK=y -CONFIG_HAS_EARLYSUSPEND=y -CONFIG_WAKELOCK=y -CONFIG_WAKELOCK_STAT=y -CONFIG_USER_WAKELOCK=y -CONFIG_EARLYSUSPEND=y -# CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL is not set -CONFIG_CONSOLE_EARLYSUSPEND=y -# CONFIG_FB_EARLYSUSPEND is not set -# CONFIG_APM_EMULATION is not set -# CONFIG_PM_RUNTIME is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -CONFIG_ANDROID_PARANOID_NETWORK=y -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -CONFIG_BT=y -CONFIG_BT_L2CAP=y -CONFIG_BT_SCO=y -CONFIG_BT_RFCOMM=y -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=y -# CONFIG_BT_BNEP_MC_FILTER is not set -# CONFIG_BT_BNEP_PROTO_FILTER is not set -CONFIG_BT_HIDP=y - -# -# Bluetooth device drivers -# -# CONFIG_BT_HCIBTUSB is not set -# CONFIG_BT_HCIBTSDIO is not set -CONFIG_BT_HCIUART=y -CONFIG_BT_HCIUART_H4=y -# CONFIG_BT_HCIUART_BCSP is not set -# CONFIG_BT_HCIUART_LL is not set -# CONFIG_BT_HCIBCM203X is not set -# CONFIG_BT_HCIBPA10X is not set -# CONFIG_BT_HCIBFUSB is not set -# CONFIG_BT_HCIVHCI is not set -# CONFIG_BT_MRVL is not set -# CONFIG_BT_HCIBCM4325 is not set -# CONFIG_AF_RXRPC is not set -CONFIG_WIRELESS=y -# CONFIG_CFG80211 is not set -CONFIG_CFG80211_DEFAULT_PS_VALUE=0 -# CONFIG_WIRELESS_OLD_REGULATORY is not set -CONFIG_WIRELESS_EXT=y -CONFIG_WIRELESS_EXT_SYSFS=y -CONFIG_LIB80211=y -# CONFIG_LIB80211_DEBUG is not set - -# -# CFG80211 needs to be enabled for MAC80211 -# -# CONFIG_WIMAX is not set -CONFIG_RFKILL=y -CONFIG_RFKILL_PM=y -# CONFIG_RFKILL_INPUT is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -# CONFIG_FIRMWARE_IN_KERNEL is not set -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set -# CONFIG_MTD_CONCAT is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set -# CONFIG_MTD_SST25L is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND_IDS=y -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -# CONFIG_MTD_NAND_GPIO is not set -# CONFIG_MTD_NAND_DISKONCHIP is not set -CONFIG_MTD_NAND_RK2818=y -# CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_PLATFORM is not set -# CONFIG_MTD_ALAUDA is not set -# CONFIG_MTD_ONENAND is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_WL_THRESHOLD=256 -CONFIG_MTD_UBI_BEB_RESERVE=1 -CONFIG_MTD_UBI_GLUEBI=y - -# -# UBI debugging options -# -# CONFIG_MTD_UBI_DEBUG is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_MG_DISK is not set -CONFIG_MISC_DEVICES=y -CONFIG_ANDROID_PMEM=y -# CONFIG_ICS932S401 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_KERNEL_DEBUGGER_CORE is not set -# CONFIG_ISL29003 is not set -CONFIG_UID_STAT=y -# CONFIG_WL127X_RFKILL is not set -CONFIG_APANIC=y -CONFIG_APANIC_PLABEL="kpanic" -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_MAX6875 is not set -# CONFIG_EEPROM_93CX6 is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set -# CONFIG_SCSI_DMA is not set -# CONFIG_SCSI_NETLINK is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -# CONFIG_PHYLIB is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_SMC91X is not set -CONFIG_DM9000=y -CONFIG_DM9000_DEBUGLEVEL=4 -CONFIG_DM9000_USE_NAND_CONTROL=y -# CONFIG_DM9000_USE_NOR_CONTROL is not set -# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -# CONFIG_SMC911X is not set -# CONFIG_SMSC911X is not set -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851 is not set -# CONFIG_KS8851_MLL is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -CONFIG_WLAN=y -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set -CONFIG_BCM4329=y -CONFIG_BCM4329_FW_PATH="/etc/firmware/fw_bcm4329.bin" -CONFIG_BCM4329_NVRAM_PATH="/etc/firmware/nvram_bcm4329_B23.txt" - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_USBNET is not set -# CONFIG_USB_HSO is not set -# CONFIG_WAN is not set -CONFIG_PPP=y -# CONFIG_PPP_MULTILINK is not set -# CONFIG_PPP_FILTER is not set -CONFIG_PPP_ASYNC=y -# CONFIG_PPP_SYNC_TTY is not set -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_BSDCOMP=y -CONFIG_PPP_MPPE=y -# CONFIG_PPPOE is not set -# CONFIG_PPPOL2TP is not set -CONFIG_PPPOLAC=y -CONFIG_PPPOPNS=y -# CONFIG_SLIP is not set -CONFIG_SLHC=y -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -CONFIG_INPUT_POLLDEV=y - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set -CONFIG_INPUT_KEYRESET=y - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_QT2160 is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_GPIO is not set -CONFIG_KEYBOARD_MATRIX=y -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -CONFIG_KEYBOARD_RK28ADC=y -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -CONFIG_INPUT_TOUCHSCREEN=y -# CONFIG_TOUCHSCREEN_ADS7846 is not set -# CONFIG_TOUCHSCREEN_AD7877 is not set -# CONFIG_TOUCHSCREEN_XPT2046_SPI is not set -CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI=y -# CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI is not set -# CONFIG_TOUCHSCREEN_XPT2046_320X480_CBN_SPI is not set -# CONFIG_TOUCHSCREEN_IT7250 is not set -# CONFIG_TOUCHSCREEN_AD7879_I2C is not set -# CONFIG_TOUCHSCREEN_AD7879_SPI is not set -# CONFIG_TOUCHSCREEN_AD7879 is not set -# CONFIG_TOUCHSCREEN_EETI is not set -# CONFIG_TOUCHSCREEN_FUJITSU is not set -# CONFIG_TOUCHSCREEN_GUNZE is not set -# CONFIG_TOUCHSCREEN_ELO is not set -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set -# CONFIG_TOUCHSCREEN_MCS5000 is not set -# CONFIG_TOUCHSCREEN_MTOUCH is not set -# CONFIG_TOUCHSCREEN_INEXIO is not set -# CONFIG_TOUCHSCREEN_MK712 is not set -# CONFIG_TOUCHSCREEN_PENMOUNT is not set -# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set -# CONFIG_TOUCHSCREEN_TSC2007 is not set -# CONFIG_TOUCHSCREEN_W90X900 is not set -CONFIG_INPUT_MISC=y -# CONFIG_INPUT_LPSENSOR_CM3602 is not set -# CONFIG_INPUT_ATI_REMOTE is not set -# CONFIG_INPUT_ATI_REMOTE2 is not set -CONFIG_INPUT_KEYCHORD=y -# CONFIG_INPUT_KEYSPAN_REMOTE is not set -# CONFIG_INPUT_POWERMATE is not set -# CONFIG_INPUT_YEALINK is not set -# CONFIG_INPUT_CM109 is not set -CONFIG_INPUT_UINPUT=y -# CONFIG_INPUT_GPIO is not set -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set -# CONFIG_G_SENSOR_DEVICE is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_DEVMEM=y -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_MAX3100 is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_SERIAL_RK2818=y -CONFIG_UART0_RK2818=y -CONFIG_UART1_RK2818=y -# CONFIG_UART2_RK2818 is not set -# CONFIG_UART3_RK2818 is not set -CONFIG_SERIAL_RK2818_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -# CONFIG_DCC_TTY is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -# CONFIG_I2C_CHARDEV is not set -CONFIG_I2C_HELPER_AUTO=y - -# -# I2C Hardware Bus support -# -CONFIG_I2C_RK2818=y - -# -# Now, there are two I2C interfaces selected by developer, I2C0 and I2C1. -# -CONFIG_I2C0_RK2818=y -CONFIG_I2C1_RK2818=y - -# -# Miscellaneous I2C Chip support -# -# CONFIG_DS1682 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_SENSORS_PCA963X is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -CONFIG_SPI_BITBANG=y -CONFIG_SPI_GPIO=y -CONFIG_SPIM_RK2818=y - -# -# SPI Protocol Masters -# -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_TLE62X0 is not set -# CONFIG_SPI_FPGA is not set -CONFIG_HEADSET_DET=y - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -# CONFIG_GPIO_SYSFS is not set - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCF857X is not set - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set -# CONFIG_GPIO_MC33880 is not set - -# -# AC97 GPIO expanders: -# -# CONFIG_GPIO_PCA9554 is not set -CONFIG_IOEXTEND_TCA6424=y -CONFIG_EXPANDED_GPIO_NUM=24 -CONFIG_EXPANDED_GPIO_IRQ_NUM=24 -CONFIG_EXPAND_GPIO_SOFT_INTERRUPT=y -CONFIG_SPI_FPGA_GPIO_NUM=0 -CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0 -# CONFIG_W1 is not set -CONFIG_POWER_SUPPLY=y -# CONFIG_POWER_SUPPLY_DEBUG is not set -# CONFIG_PDA_POWER is not set -# CONFIG_BATTERY_DS2760 is not set -# CONFIG_BATTERY_DS2782 is not set -# CONFIG_BATTERY_BQ27x00 is not set -# CONFIG_BATTERY_MAX17040 is not set -CONFIG_BATTERY_RK2818=y -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -# CONFIG_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_MC13783 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_EZX_PCAP is not set -CONFIG_REGULATOR=y -CONFIG_REGULATOR_DEBUG=y -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_REGULATOR_BQ24022 is not set -# CONFIG_REGULATOR_MAX1586 is not set -# CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set -# CONFIG_RK2818_REGULATOR_CHARGE is not set -# CONFIG_RK2818_REGULATOR_LP8725 is not set -CONFIG_MEDIA_SUPPORT=y - -# -# Multimedia core support -# -CONFIG_VIDEO_DEV=y -CONFIG_VIDEO_V4L2_COMMON=y -CONFIG_VIDEO_ALLOW_V4L1=y -CONFIG_VIDEO_V4L1_COMPAT=y -# CONFIG_DVB_CORE is not set -CONFIG_VIDEO_MEDIA=y - -# -# Multimedia drivers -# -# CONFIG_MEDIA_ATTACH is not set -CONFIG_MEDIA_TUNER=y -# CONFIG_MEDIA_TUNER_CUSTOMISE is not set -CONFIG_MEDIA_TUNER_SIMPLE=y -CONFIG_MEDIA_TUNER_TDA8290=y -CONFIG_MEDIA_TUNER_TDA9887=y -CONFIG_MEDIA_TUNER_TEA5761=y -CONFIG_MEDIA_TUNER_TEA5767=y -CONFIG_MEDIA_TUNER_MT20XX=y -CONFIG_MEDIA_TUNER_XC2028=y -CONFIG_MEDIA_TUNER_XC5000=y -CONFIG_MEDIA_TUNER_MC44S803=y -CONFIG_VIDEO_V4L2=y -CONFIG_VIDEO_V4L1=y -CONFIG_VIDEOBUF_GEN=y -CONFIG_VIDEOBUF_DMA_CONTIG=y -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -CONFIG_VIDEO_HELPER_CHIPS_AUTO=y -# CONFIG_VIDEO_VIVI is not set -# CONFIG_VIDEO_CPIA is not set -# CONFIG_VIDEO_CPIA2 is not set -# CONFIG_VIDEO_SAA5246A is not set -# CONFIG_VIDEO_SAA5249 is not set -CONFIG_SOC_CAMERA=y -# CONFIG_SOC_CAMERA_MT9M001 is not set -# CONFIG_SOC_CAMERA_MT9M111 is not set -# CONFIG_SOC_CAMERA_MT9T031 is not set -# CONFIG_SOC_CAMERA_MT9V022 is not set -# CONFIG_SOC_CAMERA_TW9910 is not set -# CONFIG_SOC_CAMERA_PLATFORM is not set -# CONFIG_SOC_CAMERA_OV772X is not set -CONFIG_SOC_CAMERA_OV2655=y -# CONFIG_SOC_CAMERA_OV3640 is not set -# CONFIG_SOC_CAMERA_OV5642 is not set -# CONFIG_VIDEO_SH_MOBILE_CEU is not set -CONFIG_VIDEO_RK2818=y -CONFIG_V4L_USB_DRIVERS=y -# CONFIG_USB_VIDEO_CLASS is not set -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -CONFIG_USB_GSPCA=m -# CONFIG_USB_M5602 is not set -# CONFIG_USB_STV06XX is not set -# CONFIG_USB_GL860 is not set -# CONFIG_USB_GSPCA_CONEX is not set -# CONFIG_USB_GSPCA_ETOMS is not set -# CONFIG_USB_GSPCA_FINEPIX is not set -# CONFIG_USB_GSPCA_JEILINJ is not set -# CONFIG_USB_GSPCA_MARS is not set -# CONFIG_USB_GSPCA_MR97310A is not set -# CONFIG_USB_GSPCA_OV519 is not set -# CONFIG_USB_GSPCA_OV534 is not set -# CONFIG_USB_GSPCA_PAC207 is not set -# CONFIG_USB_GSPCA_PAC7311 is not set -# CONFIG_USB_GSPCA_SN9C20X is not set -# CONFIG_USB_GSPCA_SONIXB is not set -# CONFIG_USB_GSPCA_SONIXJ is not set -# CONFIG_USB_GSPCA_SPCA500 is not set -# CONFIG_USB_GSPCA_SPCA501 is not set -# CONFIG_USB_GSPCA_SPCA505 is not set -# CONFIG_USB_GSPCA_SPCA506 is not set -# CONFIG_USB_GSPCA_SPCA508 is not set -# CONFIG_USB_GSPCA_SPCA561 is not set -# CONFIG_USB_GSPCA_SQ905 is not set -# CONFIG_USB_GSPCA_SQ905C is not set -# CONFIG_USB_GSPCA_STK014 is not set -# CONFIG_USB_GSPCA_SUNPLUS is not set -# CONFIG_USB_GSPCA_T613 is not set -# CONFIG_USB_GSPCA_TV8532 is not set -# CONFIG_USB_GSPCA_VC032X is not set -# CONFIG_USB_GSPCA_ZC3XX is not set -# CONFIG_VIDEO_PVRUSB2 is not set -# CONFIG_VIDEO_HDPVR is not set -# CONFIG_VIDEO_EM28XX is not set -# CONFIG_VIDEO_CX231XX is not set -# CONFIG_VIDEO_USBVISION is not set -# CONFIG_USB_VICAM is not set -# CONFIG_USB_IBMCAM is not set -# CONFIG_USB_KONICAWC is not set -# CONFIG_USB_QUICKCAM_MESSENGER is not set -# CONFIG_USB_ET61X251 is not set -# CONFIG_VIDEO_OVCAMCHIP is not set -# CONFIG_USB_OV511 is not set -# CONFIG_USB_SE401 is not set -# CONFIG_USB_SN9C102 is not set -# CONFIG_USB_STV680 is not set -# CONFIG_USB_ZC0301 is not set -# CONFIG_USB_PWC is not set -CONFIG_USB_PWC_INPUT_EVDEV=y -# CONFIG_USB_ZR364XX is not set -# CONFIG_USB_STKWEBCAM is not set -# CONFIG_USB_S2255 is not set -CONFIG_RADIO_ADAPTERS=y -# CONFIG_I2C_SI4713 is not set -# CONFIG_RADIO_SI4713 is not set -# CONFIG_USB_DSBR is not set -# CONFIG_RADIO_SI470X is not set -# CONFIG_USB_MR800 is not set -# CONFIG_RADIO_TEA5764 is not set -# CONFIG_SMS_SIANO_MDTV is not set -# CONFIG_DAB is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -CONFIG_VIDEO_OUTPUT_CONTROL=y -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_S1D13XXX is not set -CONFIG_FB_RK2818=y -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -CONFIG_BACKLIGHT_LCD_SUPPORT=y -# CONFIG_LCD_CLASS_DEVICE is not set -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set -CONFIG_BACKLIGHT_RK2818_BL=y - -# -# Display device support -# -CONFIG_DISPLAY_SUPPORT=y - -# -# Display hardware drivers -# -# CONFIG_LCD_NULL is not set -CONFIG_LCD_TD043MGEA1=y -# CONFIG_LCD_HX8357 is not set -# CONFIG_LCD_TJ048NC01CA is not set -# CONFIG_LCD_HL070VM4AU is not set -# CONFIG_LCD_HSD070IDW1 is not set -# CONFIG_LCD_A060SE02 is not set -# CONFIG_LCD_S1D13521 is not set -# CONFIG_LCD_NT35582 is not set -# CONFIG_LCD_NT35580 is not set -CONFIG_TV_NULL=y -CONFIG_HDMI_NULL=y -# CONFIG_HDMI_ANX7150 is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FONTS=y -# CONFIG_FONT_8x8 is not set -CONFIG_FONT_8x16=y -# CONFIG_FONT_6x11 is not set -# CONFIG_FONT_7x14 is not set -# CONFIG_FONT_PEARL_8x8 is not set -# CONFIG_FONT_ACORN_8x8 is not set -# CONFIG_FONT_MINI_4x6 is not set -# CONFIG_FONT_SUN8x16 is not set -# CONFIG_FONT_SUN12x22 is not set -# CONFIG_FONT_10x18 is not set -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_LOGO_LINUX_CLUT224=y -CONFIG_SOUND=y -# CONFIG_SOUND_OSS_CORE is not set -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_JACK=y -# CONFIG_SND_SEQUENCER is not set -# CONFIG_SND_MIXER_OSS is not set -# CONFIG_SND_PCM_OSS is not set -# CONFIG_SND_HRTIMER is not set -# CONFIG_SND_DYNAMIC_MINORS is not set -# CONFIG_SND_SUPPORT_OLD_API is not set -# CONFIG_SND_VERBOSE_PROCFS is not set -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -# CONFIG_SND_RAWMIDI_SEQ is not set -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_ARM is not set -# CONFIG_SND_SPI is not set -CONFIG_SND_USB=y -# CONFIG_SND_USB_AUDIO is not set -# CONFIG_SND_USB_CAIAQ is not set -CONFIG_SND_SOC=y -CONFIG_SND_ROCKCHIP_SOC=y -CONFIG_SND_ROCKCHIP_SOC_I2S=y -# CONFIG_SND_ROCKCHIP_SOC_WM8988 is not set -CONFIG_SND_ROCKCHIP_SOC_WM8994=y -# CONFIG_SND_INSIDE_EARPIECE is not set -CONFIG_SND_OUTSIDE_EARPIECE=y -# CONFIG_SND_NO_EARPIECE is not set -CONFIG_SND_BB_NORMAL_INPUT=y -# CONFIG_SND_BB_DIFFERENTIAL_INPUT is not set -CONFIG_WM8994_SPEAKER_INCALL_VOL=15 -CONFIG_WM8994_SPEAKER_INCALL_MIC_VOL=15 -CONFIG_WM8994_SPEAKER_NORMAL_VOL=15 -CONFIG_WM8994_EARPIECE_INCALL_VOL=0 -CONFIG_WM8994_HEADSET_INCALL_VOL=-9 -CONFIG_WM8994_HEADSET_INCALL_MIC_VOL=-6 -CONFIG_WM8994_HEADSET_NORMAL_VOL=15 -CONFIG_WM8994_BT_INCALL_VOL=30 -CONFIG_WM8994_BT_INCALL_MIC_VOL=-20 -CONFIG_WM8994_RECORDER_VOL=40 -CONFIG_SND_CODEC_SOC_MASTER=y -# CONFIG_SND_CODEC_SOC_SLAVE is not set -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SOC_ALL_CODECS is not set -CONFIG_SND_SOC_WM8994=y -# CONFIG_SOUND_PRIME is not set -# CONFIG_HID_SUPPORT is not set -CONFIG_HID=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set - -# -# Miscellaneous USB options -# -# CONFIG_USB_DEVICEFS is not set -CONFIG_USB_DEVICE_CLASS=y -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_SUSPEND is not set -# CONFIG_USB_OTG is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -# CONFIG_USB_MON is not set -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_ISP1362_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set -# CONFIG_USB_MUSB_HDRC is not set -# CONFIG_USB_GADGET_MUSB_HDRC is not set - -# -# USB Device Class drivers -# -CONFIG_USB_ACM=y -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_WDM is not set -# CONFIG_USB_TMC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set - -# -# USB port drivers -# -CONFIG_USB_SERIAL=y -# CONFIG_USB_SERIAL_CONSOLE is not set -# CONFIG_USB_EZUSB is not set -CONFIG_USB_SERIAL_GENERIC=y -# CONFIG_USB_SERIAL_AIRCABLE is not set -# CONFIG_USB_SERIAL_ARK3116 is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_CH341 is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_CP210X is not set -# CONFIG_USB_SERIAL_CYPRESS_M8 is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_FUNSOFT is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IPAQ is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_EDGEPORT_TI is not set -# CONFIG_USB_SERIAL_GARMIN is not set -# CONFIG_USB_SERIAL_IPW is not set -# CONFIG_USB_SERIAL_IUU is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KLSI is not set -# CONFIG_USB_SERIAL_KOBIL_SCT is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_MOS7720 is not set -# CONFIG_USB_SERIAL_MOS7840 is not set -# CONFIG_USB_SERIAL_MOTOROLA is not set -# CONFIG_USB_SERIAL_NAVMAN is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_OTI6858 is not set -# CONFIG_USB_SERIAL_QUALCOMM is not set -# CONFIG_USB_SERIAL_SPCP8X5 is not set -# CONFIG_USB_SERIAL_HP4X is not set -# CONFIG_USB_SERIAL_SAFE is not set -# CONFIG_USB_SERIAL_SIEMENS_MPI is not set -# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set -# CONFIG_USB_SERIAL_SYMBOL is not set -# CONFIG_USB_SERIAL_TI is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -CONFIG_USB_SERIAL_OPTION=y -# CONFIG_USB_SERIAL_OMNINET is not set -# CONFIG_USB_SERIAL_OPTICON is not set -# CONFIG_USB_SERIAL_DEBUG is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -CONFIG_USB_GADGET_VBUS_DRAW=500 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_R8A66597 is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C_HSOTG is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LANGWELL is not set -CONFIG_USB_GADGET_DWC_OTG=y -CONFIG_USB_DWC_OTG=y -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -# CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_ETH is not set -# CONFIG_USB_GADGETFS is not set -# CONFIG_USB_FILE_STORAGE is not set -# CONFIG_USB_G_SERIAL is not set -# CONFIG_USB_MIDI_GADGET is not set -# CONFIG_USB_G_PRINTER is not set -CONFIG_USB_ANDROID=y -# CONFIG_USB_ANDROID_ACM is not set -# CONFIG_USB_ANDROID_ADB is not set -CONFIG_USB_ANDROID_MASS_STORAGE=y -CONFIG_USB_ANDROID_RNDIS=y -CONFIG_USB_ANDROID_RNDIS_WCEIS=y -# CONFIG_USB_CDC_COMPOSITE is not set - -# -# OTG and related infrastructure -# -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set -CONFIG_RK2818_HOST11=y -CONFIG_DWC_OTG=y -# CONFIG_DWC_OTG_DEBUG is not set -# CONFIG_DWC_OTG_HOST_ONLY is not set -# CONFIG_DWC_OTG_DEVICE_ONLY is not set -CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y -# CONFIG_DWC_OTG_NORMAL_PREFERENCE is not set -# CONFIG_DWC_OTG_HOST_PREFERENCE is not set -CONFIG_DWC_OTG_DEVICE_PREFERENCE=y -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set -CONFIG_MMC_EMBEDDED_SDIO=y -# CONFIG_MMC_PARANOID_SD_INIT is not set - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -CONFIG_MMC_BLOCK_DEFERRED_RESUME=y -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -CONFIG_SDMMC_RK2818=y - -# -# Now, there are two SDMMC controllers selected, SDMMC0 and SDMMC1. -# -CONFIG_SDMMC0_RK2818=y -CONFIG_SDMMC1_RK2818=y -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set -# CONFIG_MMC_SPI is not set -# CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set -CONFIG_SWITCH=y -CONFIG_SWITCH_GPIO=y -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -# CONFIG_RTC_INTF_SYSFS is not set -# CONFIG_RTC_INTF_PROC is not set -# CONFIG_RTC_INTF_DEV is not set -CONFIG_RTC_INTF_ALARM=y -CONFIG_RTC_INTF_ALARM_DEV=y -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -CONFIG_RTC_HYM8563=y -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_S35392A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set - -# -# SPI RTC drivers -# -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_DS3234 is not set -# CONFIG_RTC_DRV_PCF2123 is not set - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set - -# -# TI VLYNQ -# -CONFIG_STAGING=y -# CONFIG_STAGING_EXCLUDE_BUILD is not set -# CONFIG_USB_IP_COMMON is not set -# CONFIG_PRISM2_USB is not set -# CONFIG_ECHO is not set -# CONFIG_COMEDI is not set -# CONFIG_ASUS_OLED is not set -# CONFIG_INPUT_MIMIO is not set -# CONFIG_TRANZPORT is not set - -# -# Android -# -CONFIG_ANDROID=y -CONFIG_ANDROID_BINDER_IPC=y -CONFIG_ANDROID_LOGGER=y -CONFIG_ANDROID_RAM_CONSOLE=y -CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_DATA_SIZE=128 -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_ECC_SIZE=16 -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE=8 -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_POLYNOMIAL=0x11d -# CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT is not set -CONFIG_ANDROID_TIMED_OUTPUT=y -CONFIG_ANDROID_TIMED_GPIO=y -CONFIG_ANDROID_LOW_MEMORY_KILLER=y - -# -# Qualcomm MSM Camera And Video -# - -# -# Camera Sensor Selection -# -# CONFIG_DST is not set -# CONFIG_POHMELFS is not set -# CONFIG_PLAN9AUTH is not set -# CONFIG_LINE6_USB is not set -# CONFIG_USB_SERIAL_QUATECH2 is not set -# CONFIG_USB_SERIAL_QUATECH_USB2 is not set -# CONFIG_VT6656 is not set -# CONFIG_FB_UDL is not set - -# -# RAR Register Driver -# -# CONFIG_RAR_REGISTER is not set -# CONFIG_IIO is not set - -# -# DSP -# -CONFIG_RK2818_DSP=y - -# -# RK1000 control -# -# CONFIG_RK1000_CONTROL is not set - -# -# rk2818 POWER CONTROL -# -CONFIG_RK2818_POWER=y - -# -# CMMB -# -# CONFIG_CMMB is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -CONFIG_EXT3_FS_XATTR=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -# CONFIG_EXT4_FS is not set -CONFIG_JBD=y -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y -# CONFIG_XFS_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -# CONFIG_DNOTIFY is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -# CONFIG_MSDOS_FS is not set -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_YAFFS_FS=y -CONFIG_YAFFS_YAFFS1=y -# CONFIG_YAFFS_9BYTE_TAGS is not set -# CONFIG_YAFFS_DOES_ECC is not set -CONFIG_YAFFS_YAFFS2=y -CONFIG_YAFFS_AUTO_YAFFS2=y -# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set -# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set -# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set -CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y -# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_UBIFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_NFS_V4_1=y -CONFIG_ROOT_NFS=y -# CONFIG_NFSD is not set -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -CONFIG_NLS_CODEPAGE_850=y -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -CONFIG_NLS_CODEPAGE_936=y -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -CONFIG_NLS_ISO8859_15=y -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -CONFIG_NLS_UTF8=y -# CONFIG_DLM is not set - -# -# Kernel hacking -# -CONFIG_PRINTK_TIME=y -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -# CONFIG_SCHED_DEBUG is not set -CONFIG_SCHEDSTATS=y -CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_KMEMLEAK is not set -# CONFIG_DEBUG_PREEMPT is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_BUGVERBOSE=y -# CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_TRACING_SUPPORT=y -# CONFIG_FTRACE is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set -CONFIG_DEBUG_ERRORS=y -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_LL is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -CONFIG_CRYPTO_WORKQUEUE=y -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -CONFIG_CRYPTO_ECB=y -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_GHASH is not set -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -CONFIG_CRYPTO_SHA1=y -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_ARC4=y -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -# CONFIG_CRC_T10DIF is not set -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_REED_SOLOMON=y -CONFIG_REED_SOLOMON_ENC8=y -CONFIG_REED_SOLOMON_DEC8=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/arch/arm/configs/rk2818_info_it50_defconfig b/arch/arm/configs/rk2818_info_it50_defconfig deleted file mode 100644 index b952d2a0ba51..000000000000 --- a/arch/arm/configs/rk2818_info_it50_defconfig +++ /dev/null @@ -1,1898 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.32.9 -# Wed Sep 8 19:42:09 2010 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_HAVE_TCM=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_ARCH_HAS_CPUFREQ=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_LOCK_KERNEL=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -# CONFIG_LOCALVERSION_AUTO is not set -# CONFIG_SWAP is not set -# CONFIG_SYSVIPC is not set -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_IKCONFIG is not set -CONFIG_LOG_BUF_SHIFT=17 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -CONFIG_RT_GROUP_SCHED=y -# CONFIG_USER_SCHED is not set -CONFIG_CGROUP_SCHED=y -CONFIG_CGROUPS=y -CONFIG_CGROUP_DEBUG=y -# CONFIG_CGROUP_NS is not set -CONFIG_CGROUP_FREEZER=y -# CONFIG_CGROUP_DEVICE is not set -# CONFIG_CPUSETS is not set -CONFIG_CGROUP_CPUACCT=y -CONFIG_RESOURCE_COUNTERS=y -# CONFIG_CGROUP_MEM_RES_CTLR is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_PANIC_TIMEOUT=5 -CONFIG_EMBEDDED=y -CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -# CONFIG_ELF_CORE is not set -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_ASHMEM=y -CONFIG_AIO=y - -# -# Kernel Performance Events And Counters -# -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_CLK=y - -# -# GCOV-based kernel profiling -# -# CONFIG_SLOW_WORK is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_BLOCK=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -# CONFIG_IOSCHED_AS is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_FREEZER=y - -# -# System Type -# -CONFIG_MMU=y -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_STMP3XXX is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PC1XX is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_U300 is not set -# CONFIG_ARCH_DAVINCI is not set -# CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_BCMRING is not set -CONFIG_ARCH_RK2818=y - -# -# ROCKCHIP rk2818 Board Type -# -# CONFIG_MACH_RK2818MID is not set -# CONFIG_MACH_RK2818PHONE is not set -# CONFIG_MACH_RAHO is not set -# CONFIG_MACH_RK2818INFO is not set -CONFIG_MACH_RK2818INFO_IT50=y -CONFIG_RK28_GPIO_IRQ=16 -CONFIG_RK28_ADC=y -CONFIG_RK28_USB_WAKE=y -CONFIG_WIFI_CONTROL_FUNC=y - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_ARM926T=y -CONFIG_CPU_32v5=y -CONFIG_CPU_ABRT_EV5TJ=y -CONFIG_CPU_PABRT_LEGACY=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_COPY_V4WB=y -CONFIG_CPU_TLB_V4WBI=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -CONFIG_ARM_THUMB=y -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set -# CONFIG_CPU_CACHE_ROUND_ROBIN is not set -CONFIG_ARM_L1_CACHE_SHIFT=5 -CONFIG_COMMON_CLKDEV=y - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 -# CONFIG_PREEMPT_NONE is not set -# CONFIG_PREEMPT_VOLUNTARY is not set -CONFIG_PREEMPT=y -CONFIG_HZ=100 -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4096 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_UACCESS_WITH_MEMCPY is not set - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_CMDLINE="mem=128M console=ttyS1,115200n8" -# CONFIG_XIP_KERNEL is not set -# CONFIG_KEXEC is not set - -# -# CPU Power Management -# -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_TABLE=y -# CONFIG_CPU_FREQ_DEBUG is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_STAT_DETAILS=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -# CONFIG_CPU_IDLE is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -# CONFIG_VFP is not set - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -CONFIG_HAVE_AOUT=y -# CONFIG_BINFMT_AOUT is not set -# CONFIG_BINFMT_MISC is not set - -# -# Power management options -# -CONFIG_PM=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_SLEEP=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_HAS_WAKELOCK=y -CONFIG_HAS_EARLYSUSPEND=y -CONFIG_WAKELOCK=y -CONFIG_WAKELOCK_STAT=y -CONFIG_USER_WAKELOCK=y -CONFIG_EARLYSUSPEND=y -# CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL is not set -CONFIG_CONSOLE_EARLYSUSPEND=y -# CONFIG_FB_EARLYSUSPEND is not set -# CONFIG_APM_EMULATION is not set -# CONFIG_PM_RUNTIME is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -CONFIG_ANDROID_PARANOID_NETWORK=y -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -CONFIG_BT=y -CONFIG_BT_L2CAP=y -CONFIG_BT_SCO=y -CONFIG_BT_RFCOMM=y -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=y -# CONFIG_BT_BNEP_MC_FILTER is not set -# CONFIG_BT_BNEP_PROTO_FILTER is not set -CONFIG_BT_HIDP=y - -# -# Bluetooth device drivers -# -# CONFIG_BT_HCIBTUSB is not set -# CONFIG_BT_HCIBTSDIO is not set -CONFIG_BT_HCIUART=y -CONFIG_BT_HCIUART_H4=y -# CONFIG_BT_HCIUART_BCSP is not set -# CONFIG_BT_HCIUART_LL is not set -# CONFIG_BT_HCIBCM203X is not set -# CONFIG_BT_HCIBPA10X is not set -# CONFIG_BT_HCIBFUSB is not set -# CONFIG_BT_HCIVHCI is not set -# CONFIG_BT_MRVL is not set -# CONFIG_BT_HCIBCM4325 is not set -# CONFIG_AF_RXRPC is not set -CONFIG_WIRELESS=y -# CONFIG_CFG80211 is not set -CONFIG_CFG80211_DEFAULT_PS_VALUE=0 -# CONFIG_WIRELESS_OLD_REGULATORY is not set -CONFIG_WIRELESS_EXT=y -CONFIG_WIRELESS_EXT_SYSFS=y -CONFIG_LIB80211=y -# CONFIG_LIB80211_DEBUG is not set - -# -# CFG80211 needs to be enabled for MAC80211 -# -# CONFIG_WIMAX is not set -CONFIG_RFKILL=y -CONFIG_RFKILL_PM=y -# CONFIG_RFKILL_INPUT is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -# CONFIG_FIRMWARE_IN_KERNEL is not set -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set -# CONFIG_MTD_CONCAT is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set -# CONFIG_MTD_SST25L is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND_IDS=y -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -# CONFIG_MTD_NAND_GPIO is not set -# CONFIG_MTD_NAND_DISKONCHIP is not set -CONFIG_MTD_NAND_RK2818=y -# CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_PLATFORM is not set -# CONFIG_MTD_ALAUDA is not set -# CONFIG_MTD_ONENAND is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_WL_THRESHOLD=256 -CONFIG_MTD_UBI_BEB_RESERVE=1 -CONFIG_MTD_UBI_GLUEBI=y - -# -# UBI debugging options -# -# CONFIG_MTD_UBI_DEBUG is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_MG_DISK is not set -CONFIG_MISC_DEVICES=y -CONFIG_ANDROID_PMEM=y -# CONFIG_ICS932S401 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_KERNEL_DEBUGGER_CORE is not set -# CONFIG_ISL29003 is not set -CONFIG_UID_STAT=y -# CONFIG_WL127X_RFKILL is not set -CONFIG_APANIC=y -CONFIG_APANIC_PLABEL="kpanic" -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_MAX6875 is not set -# CONFIG_EEPROM_93CX6 is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set -# CONFIG_SCSI_DMA is not set -# CONFIG_SCSI_NETLINK is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -# CONFIG_NET_ETHERNET is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -CONFIG_WLAN=y -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set -CONFIG_BCM4329=y -CONFIG_BCM4329_FW_PATH="/etc/firmware/fw_bcm4329.bin" -CONFIG_BCM4329_NVRAM_PATH="/etc/firmware/nvram_bcm4329_B23.txt" - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_USBNET is not set -# CONFIG_USB_HSO is not set -# CONFIG_WAN is not set -CONFIG_PPP=y -# CONFIG_PPP_MULTILINK is not set -# CONFIG_PPP_FILTER is not set -CONFIG_PPP_ASYNC=y -# CONFIG_PPP_SYNC_TTY is not set -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_BSDCOMP=y -CONFIG_PPP_MPPE=y -# CONFIG_PPPOE is not set -# CONFIG_PPPOL2TP is not set -CONFIG_PPPOLAC=y -CONFIG_PPPOPNS=y -# CONFIG_SLIP is not set -CONFIG_SLHC=y -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -CONFIG_INPUT_POLLDEV=y - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set -CONFIG_INPUT_KEYRESET=y - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_QT2160 is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_KEYBOARD_RK28ADC is not set -CONFIG_KEYBOARD_RK28ADC_IT50=y -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -CONFIG_INPUT_TOUCHSCREEN=y -# CONFIG_TOUCHSCREEN_ADS7846 is not set -# CONFIG_TOUCHSCREEN_AD7877 is not set -CONFIG_TOUCHSCREEN_XPT2046_SPI=y -# CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI is not set -# CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI is not set -# CONFIG_TOUCHSCREEN_XPT2046_320X480_CBN_SPI is not set -# CONFIG_TOUCHSCREEN_IT7250 is not set -# CONFIG_TOUCHSCREEN_AD7879_I2C is not set -# CONFIG_TOUCHSCREEN_AD7879_SPI is not set -# CONFIG_TOUCHSCREEN_AD7879 is not set -# CONFIG_TOUCHSCREEN_EETI is not set -# CONFIG_TOUCHSCREEN_FUJITSU is not set -# CONFIG_TOUCHSCREEN_GUNZE is not set -# CONFIG_TOUCHSCREEN_ELO is not set -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set -# CONFIG_TOUCHSCREEN_MCS5000 is not set -# CONFIG_TOUCHSCREEN_MTOUCH is not set -# CONFIG_TOUCHSCREEN_INEXIO is not set -# CONFIG_TOUCHSCREEN_MK712 is not set -# CONFIG_TOUCHSCREEN_PENMOUNT is not set -# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set -# CONFIG_TOUCHSCREEN_TSC2007 is not set -# CONFIG_TOUCHSCREEN_W90X900 is not set -CONFIG_TP_800x480=y -# CONFIG_TP_1024x600 is not set -CONFIG_INPUT_MISC=y -# CONFIG_INPUT_LPSENSOR_CM3602 is not set -# CONFIG_INPUT_ATI_REMOTE is not set -# CONFIG_INPUT_ATI_REMOTE2 is not set -CONFIG_INPUT_KEYCHORD=y -# CONFIG_INPUT_KEYSPAN_REMOTE is not set -# CONFIG_INPUT_POWERMATE is not set -# CONFIG_INPUT_YEALINK is not set -# CONFIG_INPUT_CM109 is not set -CONFIG_INPUT_UINPUT=y -# CONFIG_INPUT_GPIO is not set -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set -CONFIG_G_SENSOR_DEVICE=y -CONFIG_GS_MMA7660=y -CONFIG_INPUT_JOGBALL=y -CONFIG_RK2818_JOGBALL=y - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_DEVMEM=y -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_MAX3100 is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_SERIAL_RK2818=y -CONFIG_UART0_RK2818=y -CONFIG_UART1_RK2818=y -CONFIG_UART2_RK2818=y -# CONFIG_UART3_RK2818 is not set -CONFIG_SERIAL_RK2818_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -# CONFIG_DCC_TTY is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -# CONFIG_I2C_CHARDEV is not set -CONFIG_I2C_HELPER_AUTO=y - -# -# I2C Hardware Bus support -# -CONFIG_I2C_RK2818=y - -# -# Now, there are two I2C interfaces selected by developer, I2C0 and I2C1. -# -CONFIG_I2C0_RK2818=y -CONFIG_I2C1_RK2818=y - -# -# Miscellaneous I2C Chip support -# -# CONFIG_DS1682 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_SENSORS_PCA963X is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -CONFIG_SPI_BITBANG=y -CONFIG_SPI_GPIO=y -CONFIG_SPIM_RK2818=y - -# -# SPI Protocol Masters -# -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_TLE62X0 is not set -# CONFIG_SPI_FPGA is not set -CONFIG_HEADSET_DET=y - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_GPIO_SYSFS is not set - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCF857X is not set - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set -# CONFIG_GPIO_MC33880 is not set - -# -# AC97 GPIO expanders: -# -# CONFIG_GPIO_PCA9554 is not set -CONFIG_IOEXTEND_TCA6424=y -CONFIG_EXPANDED_GPIO_NUM=24 -CONFIG_EXPANDED_GPIO_IRQ_NUM=24 -CONFIG_EXPAND_GPIO_SOFT_INTERRUPT=y -CONFIG_SPI_FPGA_GPIO_NUM=0 -CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0 -# CONFIG_W1 is not set -CONFIG_POWER_SUPPLY=y -# CONFIG_POWER_SUPPLY_DEBUG is not set -# CONFIG_PDA_POWER is not set -# CONFIG_BATTERY_DS2760 is not set -# CONFIG_BATTERY_DS2782 is not set -# CONFIG_BATTERY_BQ27x00 is not set -# CONFIG_BATTERY_MAX17040 is not set -CONFIG_BATTERY_RK2818=y -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -# CONFIG_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_MC13783 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_EZX_PCAP is not set -CONFIG_REGULATOR=y -CONFIG_REGULATOR_DEBUG=y -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_REGULATOR_BQ24022 is not set -# CONFIG_REGULATOR_MAX1586 is not set -# CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set -# CONFIG_RK2818_REGULATOR_CHARGE is not set -# CONFIG_RK2818_REGULATOR_LP8725 is not set -CONFIG_MEDIA_SUPPORT=y - -# -# Multimedia core support -# -CONFIG_VIDEO_DEV=y -CONFIG_VIDEO_V4L2_COMMON=y -CONFIG_VIDEO_ALLOW_V4L1=y -CONFIG_VIDEO_V4L1_COMPAT=y -# CONFIG_DVB_CORE is not set -CONFIG_VIDEO_MEDIA=y - -# -# Multimedia drivers -# -# CONFIG_MEDIA_ATTACH is not set -CONFIG_MEDIA_TUNER=y -# CONFIG_MEDIA_TUNER_CUSTOMISE is not set -CONFIG_MEDIA_TUNER_SIMPLE=y -CONFIG_MEDIA_TUNER_TDA8290=y -CONFIG_MEDIA_TUNER_TDA9887=y -CONFIG_MEDIA_TUNER_TEA5761=y -CONFIG_MEDIA_TUNER_TEA5767=y -CONFIG_MEDIA_TUNER_MT20XX=y -CONFIG_MEDIA_TUNER_XC2028=y -CONFIG_MEDIA_TUNER_XC5000=y -CONFIG_MEDIA_TUNER_MC44S803=y -CONFIG_VIDEO_V4L2=y -CONFIG_VIDEO_V4L1=y -CONFIG_VIDEOBUF_GEN=y -CONFIG_VIDEOBUF_DMA_CONTIG=y -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -CONFIG_VIDEO_HELPER_CHIPS_AUTO=y -# CONFIG_VIDEO_VIVI is not set -# CONFIG_VIDEO_CPIA is not set -# CONFIG_VIDEO_CPIA2 is not set -# CONFIG_VIDEO_SAA5246A is not set -# CONFIG_VIDEO_SAA5249 is not set -CONFIG_SOC_CAMERA=y -# CONFIG_SOC_CAMERA_MT9M001 is not set -# CONFIG_SOC_CAMERA_MT9M111 is not set -# CONFIG_SOC_CAMERA_MT9T031 is not set -# CONFIG_SOC_CAMERA_MT9V022 is not set -# CONFIG_SOC_CAMERA_TW9910 is not set -# CONFIG_SOC_CAMERA_PLATFORM is not set -# CONFIG_SOC_CAMERA_OV772X is not set -# CONFIG_SOC_CAMERA_OV2655 is not set -CONFIG_SOC_CAMERA_OV9650=y -# CONFIG_SOC_CAMERA_OV3640 is not set -# CONFIG_SOC_CAMERA_OV5642 is not set -# CONFIG_VIDEO_SH_MOBILE_CEU is not set -CONFIG_VIDEO_RK2818=y -CONFIG_V4L_USB_DRIVERS=y -# CONFIG_USB_VIDEO_CLASS is not set -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -CONFIG_USB_GSPCA=m -# CONFIG_USB_M5602 is not set -# CONFIG_USB_STV06XX is not set -# CONFIG_USB_GL860 is not set -# CONFIG_USB_GSPCA_CONEX is not set -# CONFIG_USB_GSPCA_ETOMS is not set -# CONFIG_USB_GSPCA_FINEPIX is not set -# CONFIG_USB_GSPCA_JEILINJ is not set -# CONFIG_USB_GSPCA_MARS is not set -# CONFIG_USB_GSPCA_MR97310A is not set -# CONFIG_USB_GSPCA_OV519 is not set -# CONFIG_USB_GSPCA_OV534 is not set -# CONFIG_USB_GSPCA_PAC207 is not set -# CONFIG_USB_GSPCA_PAC7311 is not set -# CONFIG_USB_GSPCA_SN9C20X is not set -# CONFIG_USB_GSPCA_SONIXB is not set -# CONFIG_USB_GSPCA_SONIXJ is not set -# CONFIG_USB_GSPCA_SPCA500 is not set -# CONFIG_USB_GSPCA_SPCA501 is not set -# CONFIG_USB_GSPCA_SPCA505 is not set -# CONFIG_USB_GSPCA_SPCA506 is not set -# CONFIG_USB_GSPCA_SPCA508 is not set -# CONFIG_USB_GSPCA_SPCA561 is not set -# CONFIG_USB_GSPCA_SQ905 is not set -# CONFIG_USB_GSPCA_SQ905C is not set -# CONFIG_USB_GSPCA_STK014 is not set -# CONFIG_USB_GSPCA_SUNPLUS is not set -# CONFIG_USB_GSPCA_T613 is not set -# CONFIG_USB_GSPCA_TV8532 is not set -# CONFIG_USB_GSPCA_VC032X is not set -# CONFIG_USB_GSPCA_ZC3XX is not set -# CONFIG_VIDEO_PVRUSB2 is not set -# CONFIG_VIDEO_HDPVR is not set -# CONFIG_VIDEO_EM28XX is not set -# CONFIG_VIDEO_CX231XX is not set -# CONFIG_VIDEO_USBVISION is not set -# CONFIG_USB_VICAM is not set -# CONFIG_USB_IBMCAM is not set -# CONFIG_USB_KONICAWC is not set -# CONFIG_USB_QUICKCAM_MESSENGER is not set -# CONFIG_USB_ET61X251 is not set -# CONFIG_VIDEO_OVCAMCHIP is not set -# CONFIG_USB_OV511 is not set -# CONFIG_USB_SE401 is not set -# CONFIG_USB_SN9C102 is not set -# CONFIG_USB_STV680 is not set -# CONFIG_USB_ZC0301 is not set -# CONFIG_USB_PWC is not set -CONFIG_USB_PWC_INPUT_EVDEV=y -# CONFIG_USB_ZR364XX is not set -# CONFIG_USB_STKWEBCAM is not set -# CONFIG_USB_S2255 is not set -CONFIG_RADIO_ADAPTERS=y -# CONFIG_I2C_SI4713 is not set -# CONFIG_RADIO_SI4713 is not set -# CONFIG_USB_DSBR is not set -# CONFIG_RADIO_SI470X is not set -# CONFIG_USB_MR800 is not set -# CONFIG_RADIO_TEA5764 is not set -# CONFIG_SMS_SIANO_MDTV is not set -# CONFIG_DAB is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -CONFIG_VIDEO_OUTPUT_CONTROL=y -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_S1D13XXX is not set -CONFIG_FB_RK2818=y -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -CONFIG_BACKLIGHT_LCD_SUPPORT=y -# CONFIG_LCD_CLASS_DEVICE is not set -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set -CONFIG_BACKLIGHT_RK2818_BL=y - -# -# Display device support -# -CONFIG_DISPLAY_SUPPORT=y - -# -# Display hardware drivers -# -# CONFIG_LCD_NULL is not set -CONFIG_LCD_TD043MGEA1=y -# CONFIG_LCD_HX8357 is not set -# CONFIG_LCD_TJ048NC01CA is not set -# CONFIG_LCD_HL070VM4AU is not set -# CONFIG_LCD_HSD070IDW1 is not set -# CONFIG_LCD_A060SE02 is not set -# CONFIG_LCD_S1D13521 is not set -# CONFIG_LCD_NT35582 is not set -# CONFIG_LCD_NT35580 is not set -CONFIG_TV_NULL=y -CONFIG_HDMI_NULL=y -# CONFIG_HDMI_ANX7150 is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FONTS=y -# CONFIG_FONT_8x8 is not set -CONFIG_FONT_8x16=y -# CONFIG_FONT_6x11 is not set -# CONFIG_FONT_7x14 is not set -# CONFIG_FONT_PEARL_8x8 is not set -# CONFIG_FONT_ACORN_8x8 is not set -# CONFIG_FONT_MINI_4x6 is not set -# CONFIG_FONT_SUN8x16 is not set -# CONFIG_FONT_SUN12x22 is not set -# CONFIG_FONT_10x18 is not set -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_LOGO_LINUX_CLUT224=y -CONFIG_SOUND=y -# CONFIG_SOUND_OSS_CORE is not set -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_JACK=y -# CONFIG_SND_SEQUENCER is not set -# CONFIG_SND_MIXER_OSS is not set -# CONFIG_SND_PCM_OSS is not set -# CONFIG_SND_HRTIMER is not set -# CONFIG_SND_DYNAMIC_MINORS is not set -# CONFIG_SND_SUPPORT_OLD_API is not set -# CONFIG_SND_VERBOSE_PROCFS is not set -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -# CONFIG_SND_RAWMIDI_SEQ is not set -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_ARM is not set -# CONFIG_SND_SPI is not set -CONFIG_SND_USB=y -# CONFIG_SND_USB_AUDIO is not set -# CONFIG_SND_USB_CAIAQ is not set -CONFIG_SND_SOC=y -CONFIG_SND_ROCKCHIP_SOC=y -CONFIG_SND_ROCKCHIP_SOC_I2S=y -# CONFIG_SND_ROCKCHIP_SOC_WM8988 is not set -CONFIG_SND_ROCKCHIP_SOC_WM8994=y -# CONFIG_SND_INSIDE_EARPIECE is not set -# CONFIG_SND_OUTSIDE_EARPIECE is not set -CONFIG_SND_NO_EARPIECE=y -CONFIG_SND_BB_NORMAL_INPUT=y -# CONFIG_SND_BB_DIFFERENTIAL_INPUT is not set -CONFIG_WM8994_SPEAKER_INCALL_VOL=15 -CONFIG_WM8994_SPEAKER_INCALL_MIC_VOL=15 -CONFIG_WM8994_SPEAKER_NORMAL_VOL=15 -CONFIG_WM8994_HEADSET_INCALL_VOL=-9 -CONFIG_WM8994_HEADSET_INCALL_MIC_VOL=-6 -CONFIG_WM8994_HEADSET_NORMAL_VOL=15 -CONFIG_WM8994_BT_INCALL_VOL=30 -CONFIG_WM8994_BT_INCALL_MIC_VOL=-20 -CONFIG_WM8994_RECORDER_VOL=40 -CONFIG_SND_CODEC_SOC_MASTER=y -# CONFIG_SND_CODEC_SOC_SLAVE is not set -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SOC_ALL_CODECS is not set -CONFIG_SND_SOC_WM8994=y -# CONFIG_SOUND_PRIME is not set -# CONFIG_HID_SUPPORT is not set -CONFIG_HID=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set - -# -# Miscellaneous USB options -# -# CONFIG_USB_DEVICEFS is not set -CONFIG_USB_DEVICE_CLASS=y -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_SUSPEND is not set -# CONFIG_USB_OTG is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -# CONFIG_USB_MON is not set -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_ISP1362_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set -# CONFIG_USB_MUSB_HDRC is not set -# CONFIG_USB_GADGET_MUSB_HDRC is not set - -# -# USB Device Class drivers -# -CONFIG_USB_ACM=y -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_WDM is not set -# CONFIG_USB_TMC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set - -# -# USB port drivers -# -CONFIG_USB_SERIAL=y -# CONFIG_USB_SERIAL_CONSOLE is not set -# CONFIG_USB_EZUSB is not set -CONFIG_USB_SERIAL_GENERIC=y -# CONFIG_USB_SERIAL_AIRCABLE is not set -# CONFIG_USB_SERIAL_ARK3116 is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_CH341 is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_CP210X is not set -# CONFIG_USB_SERIAL_CYPRESS_M8 is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_FUNSOFT is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IPAQ is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_EDGEPORT_TI is not set -# CONFIG_USB_SERIAL_GARMIN is not set -# CONFIG_USB_SERIAL_IPW is not set -# CONFIG_USB_SERIAL_IUU is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KLSI is not set -# CONFIG_USB_SERIAL_KOBIL_SCT is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_MOS7720 is not set -# CONFIG_USB_SERIAL_MOS7840 is not set -# CONFIG_USB_SERIAL_MOTOROLA is not set -# CONFIG_USB_SERIAL_NAVMAN is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_OTI6858 is not set -# CONFIG_USB_SERIAL_QUALCOMM is not set -# CONFIG_USB_SERIAL_SPCP8X5 is not set -# CONFIG_USB_SERIAL_HP4X is not set -# CONFIG_USB_SERIAL_SAFE is not set -# CONFIG_USB_SERIAL_SIEMENS_MPI is not set -# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set -# CONFIG_USB_SERIAL_SYMBOL is not set -# CONFIG_USB_SERIAL_TI is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -CONFIG_USB_SERIAL_OPTION=y -# CONFIG_USB_SERIAL_OMNINET is not set -# CONFIG_USB_SERIAL_OPTICON is not set -# CONFIG_USB_SERIAL_DEBUG is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG_FILES is not set -CONFIG_USB_GADGET_VBUS_DRAW=500 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_R8A66597 is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C_HSOTG is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LANGWELL is not set -CONFIG_USB_GADGET_DWC_OTG=y -CONFIG_USB_DWC_OTG=y -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -# CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_ETH is not set -# CONFIG_USB_GADGETFS is not set -# CONFIG_USB_FILE_STORAGE is not set -# CONFIG_USB_G_SERIAL is not set -# CONFIG_USB_MIDI_GADGET is not set -# CONFIG_USB_G_PRINTER is not set -CONFIG_USB_ANDROID=y -# CONFIG_USB_ANDROID_ACM is not set -# CONFIG_USB_ANDROID_ADB is not set -CONFIG_USB_ANDROID_MASS_STORAGE=y -CONFIG_USB_ANDROID_RNDIS=y -CONFIG_USB_ANDROID_RNDIS_WCEIS=y -# CONFIG_USB_CDC_COMPOSITE is not set - -# -# OTG and related infrastructure -# -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set -CONFIG_RK2818_HOST11=y -CONFIG_DWC_OTG=y -# CONFIG_DWC_OTG_DEBUG is not set -# CONFIG_DWC_OTG_HOST_ONLY is not set -# CONFIG_DWC_OTG_DEVICE_ONLY is not set -CONFIG_DWC_OTG_BOTH_HOST_SLAVE=y -# CONFIG_DWC_OTG_NORMAL_PREFERENCE is not set -# CONFIG_DWC_OTG_HOST_PREFERENCE is not set -CONFIG_DWC_OTG_DEVICE_PREFERENCE=y -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set -CONFIG_MMC_EMBEDDED_SDIO=y -# CONFIG_MMC_PARANOID_SD_INIT is not set - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -CONFIG_MMC_BLOCK_DEFERRED_RESUME=y -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -CONFIG_SDMMC_RK2818=y - -# -# Now, there are two SDMMC controllers selected, SDMMC0 and SDMMC1. -# -CONFIG_SDMMC0_RK2818=y -CONFIG_SDMMC1_RK2818=y -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set -# CONFIG_MMC_SPI is not set -# CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set -CONFIG_SWITCH=y -CONFIG_SWITCH_GPIO=y -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -# CONFIG_RTC_INTF_SYSFS is not set -# CONFIG_RTC_INTF_PROC is not set -# CONFIG_RTC_INTF_DEV is not set -CONFIG_RTC_INTF_ALARM=y -CONFIG_RTC_INTF_ALARM_DEV=y -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -CONFIG_RTC_HYM8563=y -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_S35392A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set - -# -# SPI RTC drivers -# -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_DS3234 is not set -# CONFIG_RTC_DRV_PCF2123 is not set - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set - -# -# TI VLYNQ -# -CONFIG_STAGING=y -# CONFIG_STAGING_EXCLUDE_BUILD is not set -# CONFIG_USB_IP_COMMON is not set -# CONFIG_PRISM2_USB is not set -# CONFIG_ECHO is not set -# CONFIG_COMEDI is not set -# CONFIG_ASUS_OLED is not set -# CONFIG_INPUT_MIMIO is not set -# CONFIG_TRANZPORT is not set - -# -# Android -# -CONFIG_ANDROID=y -CONFIG_ANDROID_BINDER_IPC=y -CONFIG_ANDROID_LOGGER=y -CONFIG_ANDROID_RAM_CONSOLE=y -CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_DATA_SIZE=128 -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_ECC_SIZE=16 -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE=8 -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_POLYNOMIAL=0x11d -# CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT is not set -CONFIG_ANDROID_TIMED_OUTPUT=y -CONFIG_ANDROID_TIMED_GPIO=y -CONFIG_ANDROID_LOW_MEMORY_KILLER=y - -# -# Qualcomm MSM Camera And Video -# - -# -# Camera Sensor Selection -# -# CONFIG_DST is not set -# CONFIG_POHMELFS is not set -# CONFIG_PLAN9AUTH is not set -# CONFIG_LINE6_USB is not set -# CONFIG_USB_SERIAL_QUATECH2 is not set -# CONFIG_USB_SERIAL_QUATECH_USB2 is not set -# CONFIG_VT6656 is not set -# CONFIG_FB_UDL is not set - -# -# RAR Register Driver -# -# CONFIG_RAR_REGISTER is not set -# CONFIG_IIO is not set - -# -# DSP -# -CONFIG_RK2818_DSP=y - -# -# RK1000 control -# -# CONFIG_RK1000_CONTROL is not set - -# -# rk2818 POWER CONTROL -# -CONFIG_RK2818_POWER=y - -# -# CMMB -# -# CONFIG_CMMB is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -CONFIG_EXT3_FS_XATTR=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -# CONFIG_EXT4_FS is not set -CONFIG_JBD=y -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y -# CONFIG_XFS_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -# CONFIG_DNOTIFY is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -# CONFIG_MSDOS_FS is not set -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_YAFFS_FS=y -CONFIG_YAFFS_YAFFS1=y -# CONFIG_YAFFS_9BYTE_TAGS is not set -# CONFIG_YAFFS_DOES_ECC is not set -CONFIG_YAFFS_YAFFS2=y -CONFIG_YAFFS_AUTO_YAFFS2=y -# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set -# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set -# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set -CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y -# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_UBIFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -# CONFIG_NETWORK_FILESYSTEMS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -CONFIG_NLS_CODEPAGE_850=y -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -CONFIG_NLS_CODEPAGE_936=y -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -CONFIG_NLS_ISO8859_15=y -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -CONFIG_NLS_UTF8=y -# CONFIG_DLM is not set - -# -# Kernel hacking -# -CONFIG_PRINTK_TIME=y -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -# CONFIG_SCHED_DEBUG is not set -CONFIG_SCHEDSTATS=y -CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_KMEMLEAK is not set -# CONFIG_DEBUG_PREEMPT is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_BUGVERBOSE=y -# CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_TRACING_SUPPORT=y -# CONFIG_FTRACE is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set -CONFIG_DEBUG_ERRORS=y -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_LL is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -CONFIG_CRYPTO_WORKQUEUE=y -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -CONFIG_CRYPTO_ECB=y -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_GHASH is not set -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -CONFIG_CRYPTO_SHA1=y -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_ARC4=y -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -# CONFIG_CRC_T10DIF is not set -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_REED_SOLOMON=y -CONFIG_REED_SOLOMON_ENC8=y -CONFIG_REED_SOLOMON_DEC8=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/arch/arm/configs/rk2818_mid_defconfig b/arch/arm/configs/rk2818_mid_defconfig deleted file mode 100644 index 22907843fec5..000000000000 --- a/arch/arm/configs/rk2818_mid_defconfig +++ /dev/null @@ -1,1652 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.32.9 -# Wed Jul 28 20:14:13 2010 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_HAVE_TCM=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_ARCH_HAS_CPUFREQ=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_LOCK_KERNEL=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -# CONFIG_LOCALVERSION_AUTO is not set -# CONFIG_SWAP is not set -# CONFIG_SYSVIPC is not set -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_IKCONFIG is not set -CONFIG_LOG_BUF_SHIFT=17 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -CONFIG_RT_GROUP_SCHED=y -# CONFIG_USER_SCHED is not set -CONFIG_CGROUP_SCHED=y -CONFIG_CGROUPS=y -CONFIG_CGROUP_DEBUG=y -# CONFIG_CGROUP_NS is not set -CONFIG_CGROUP_FREEZER=y -# CONFIG_CGROUP_DEVICE is not set -# CONFIG_CPUSETS is not set -CONFIG_CGROUP_CPUACCT=y -CONFIG_RESOURCE_COUNTERS=y -# CONFIG_CGROUP_MEM_RES_CTLR is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_PANIC_TIMEOUT=5 -CONFIG_EMBEDDED=y -CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -# CONFIG_ELF_CORE is not set -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_ASHMEM=y -CONFIG_AIO=y - -# -# Kernel Performance Events And Counters -# -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_CLK=y - -# -# GCOV-based kernel profiling -# -# CONFIG_SLOW_WORK is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_BLOCK=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -# CONFIG_IOSCHED_AS is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_FREEZER=y - -# -# System Type -# -CONFIG_MMU=y -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_STMP3XXX is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PC1XX is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_U300 is not set -# CONFIG_ARCH_DAVINCI is not set -# CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_BCMRING is not set -CONFIG_ARCH_RK2818=y - -# -# ROCKCHIP rk2818 Board Type -# -CONFIG_MACH_RK2818MID=y -# CONFIG_MACH_RK2818PHONE is not set -# CONFIG_MACH_RAHO is not set -CONFIG_RK28_GPIO_IRQ=16 -CONFIG_RK28_ADC=y -CONFIG_RK28_USB_WAKE=y - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_ARM926T=y -CONFIG_CPU_32v5=y -CONFIG_CPU_ABRT_EV5TJ=y -CONFIG_CPU_PABRT_LEGACY=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_COPY_V4WB=y -CONFIG_CPU_TLB_V4WBI=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -CONFIG_ARM_THUMB=y -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set -# CONFIG_CPU_CACHE_ROUND_ROBIN is not set -CONFIG_ARM_L1_CACHE_SHIFT=5 -CONFIG_COMMON_CLKDEV=y - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 -# CONFIG_PREEMPT_NONE is not set -# CONFIG_PREEMPT_VOLUNTARY is not set -CONFIG_PREEMPT=y -CONFIG_HZ=100 -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4096 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_UACCESS_WITH_MEMCPY is not set - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_CMDLINE="mem=128M console=ttyS1,115200n8" -# CONFIG_XIP_KERNEL is not set -# CONFIG_KEXEC is not set - -# -# CPU Power Management -# -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_TABLE=y -# CONFIG_CPU_FREQ_DEBUG is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_STAT_DETAILS=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -# CONFIG_CPU_IDLE is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -# CONFIG_VFP is not set - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -CONFIG_HAVE_AOUT=y -# CONFIG_BINFMT_AOUT is not set -# CONFIG_BINFMT_MISC is not set - -# -# Power management options -# -CONFIG_PM=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_SLEEP=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_HAS_WAKELOCK=y -CONFIG_HAS_EARLYSUSPEND=y -CONFIG_WAKELOCK=y -CONFIG_WAKELOCK_STAT=y -CONFIG_USER_WAKELOCK=y -CONFIG_EARLYSUSPEND=y -# CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL is not set -CONFIG_CONSOLE_EARLYSUSPEND=y -# CONFIG_FB_EARLYSUSPEND is not set -# CONFIG_APM_EMULATION is not set -# CONFIG_PM_RUNTIME is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -CONFIG_ANDROID_PARANOID_NETWORK=y -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -CONFIG_BT=y -CONFIG_BT_L2CAP=y -CONFIG_BT_SCO=y -CONFIG_BT_RFCOMM=y -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=y -# CONFIG_BT_BNEP_MC_FILTER is not set -# CONFIG_BT_BNEP_PROTO_FILTER is not set -CONFIG_BT_HIDP=y - -# -# Bluetooth device drivers -# -# CONFIG_BT_HCIBTSDIO is not set -CONFIG_BT_HCIUART=y -CONFIG_BT_HCIUART_H4=y -# CONFIG_BT_HCIUART_BCSP is not set -# CONFIG_BT_HCIUART_LL is not set -# CONFIG_BT_HCIVHCI is not set -# CONFIG_BT_MRVL is not set -# CONFIG_AF_RXRPC is not set -CONFIG_WIRELESS=y -# CONFIG_CFG80211 is not set -CONFIG_CFG80211_DEFAULT_PS_VALUE=0 -# CONFIG_WIRELESS_OLD_REGULATORY is not set -CONFIG_WIRELESS_EXT=y -CONFIG_WIRELESS_EXT_SYSFS=y -CONFIG_LIB80211=y -# CONFIG_LIB80211_DEBUG is not set - -# -# CFG80211 needs to be enabled for MAC80211 -# -# CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -# CONFIG_FIRMWARE_IN_KERNEL is not set -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set -# CONFIG_MTD_CONCAT is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set -# CONFIG_MTD_SST25L is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND_IDS=y -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -# CONFIG_MTD_NAND_GPIO is not set -# CONFIG_MTD_NAND_DISKONCHIP is not set -CONFIG_MTD_NAND_RK2818=y -# CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_PLATFORM is not set -# CONFIG_MTD_ONENAND is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -# CONFIG_MTD_UBI is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_MG_DISK is not set -CONFIG_MISC_DEVICES=y -CONFIG_ANDROID_PMEM=y -# CONFIG_ICS932S401 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_KERNEL_DEBUGGER_CORE is not set -# CONFIG_ISL29003 is not set -CONFIG_UID_STAT=y -CONFIG_APANIC=y -CONFIG_APANIC_PLABEL="kpanic" -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_MAX6875 is not set -# CONFIG_EEPROM_93CX6 is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set -# CONFIG_SCSI_DMA is not set -# CONFIG_SCSI_NETLINK is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -# CONFIG_PHYLIB is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_SMC91X is not set -CONFIG_DM9000=y -CONFIG_DM9000_DEBUGLEVEL=4 -CONFIG_DM9000_USE_NAND_CONTROL=y -# CONFIG_DM9000_USE_NOR_CONTROL is not set -# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -# CONFIG_SMC911X is not set -# CONFIG_SMSC911X is not set -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851 is not set -# CONFIG_KS8851_MLL is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -CONFIG_WLAN=y -# CONFIG_WLAN_PRE80211 is not set -CONFIG_WLAN_80211=y -CONFIG_LIBERTAS=y -CONFIG_LIBERTAS_SDIO=y -# CONFIG_LIBERTAS_SPI is not set -# CONFIG_LIBERTAS_DEBUG is not set -# CONFIG_HOSTAP is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# -# CONFIG_WAN is not set -CONFIG_PPP=y -# CONFIG_PPP_MULTILINK is not set -# CONFIG_PPP_FILTER is not set -CONFIG_PPP_ASYNC=y -# CONFIG_PPP_SYNC_TTY is not set -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_BSDCOMP=y -CONFIG_PPP_MPPE=y -# CONFIG_PPPOE is not set -# CONFIG_PPPOL2TP is not set -CONFIG_PPPOLAC=y -CONFIG_PPPOPNS=y -# CONFIG_SLIP is not set -CONFIG_SLHC=y -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -CONFIG_INPUT_POLLDEV=y - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set -CONFIG_INPUT_KEYRESET=y - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_QT2160 is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -CONFIG_KEYBOARD_RK28ADC=y -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -CONFIG_INPUT_TOUCHSCREEN=y -# CONFIG_TOUCHSCREEN_ADS7846 is not set -# CONFIG_TOUCHSCREEN_AD7877 is not set -# CONFIG_TOUCHSCREEN_XPT2046_SPI is not set -# CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI is not set -CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI=y -# CONFIG_TOUCHSCREEN_XPT2046_320X480_CBN_SPI is not set -# CONFIG_TOUCHSCREEN_AD7879_I2C is not set -# CONFIG_TOUCHSCREEN_AD7879_SPI is not set -# CONFIG_TOUCHSCREEN_AD7879 is not set -# CONFIG_TOUCHSCREEN_EETI is not set -# CONFIG_TOUCHSCREEN_FUJITSU is not set -# CONFIG_TOUCHSCREEN_GUNZE is not set -# CONFIG_TOUCHSCREEN_ELO is not set -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set -# CONFIG_TOUCHSCREEN_MCS5000 is not set -# CONFIG_TOUCHSCREEN_MTOUCH is not set -# CONFIG_TOUCHSCREEN_INEXIO is not set -# CONFIG_TOUCHSCREEN_MK712 is not set -# CONFIG_TOUCHSCREEN_PENMOUNT is not set -# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set -# CONFIG_TOUCHSCREEN_TSC2007 is not set -# CONFIG_TOUCHSCREEN_W90X900 is not set -CONFIG_INPUT_MISC=y -# CONFIG_INPUT_ATI_REMOTE is not set -# CONFIG_INPUT_ATI_REMOTE2 is not set -CONFIG_INPUT_KEYCHORD=y -# CONFIG_INPUT_KEYSPAN_REMOTE is not set -# CONFIG_INPUT_POWERMATE is not set -# CONFIG_INPUT_YEALINK is not set -# CONFIG_INPUT_CM109 is not set -CONFIG_INPUT_UINPUT=y -# CONFIG_INPUT_GPIO is not set -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set -# CONFIG_G_SENSOR_DEVICE is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_DEVMEM=y -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_MAX3100 is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_SERIAL_RK2818=y -CONFIG_UART1_RK2818=y -CONFIG_SERIAL_RK2818_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -# CONFIG_DCC_TTY is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -# CONFIG_I2C_CHARDEV is not set -CONFIG_I2C_HELPER_AUTO=y - -# -# I2C Hardware Bus support -# -CONFIG_I2C_RK2818=y - -# -# Now, there are two I2C interfaces selected by developer, I2C0 and I2C1. -# -CONFIG_I2C0_RK2818=y -CONFIG_I2C1_RK2818=y - -# -# Miscellaneous I2C Chip support -# -# CONFIG_DS1682 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_SENSORS_PCA963X is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -CONFIG_SPI_BITBANG=y -CONFIG_SPI_GPIO=y -CONFIG_SPIM_RK2818=y - -# -# SPI Protocol Masters -# -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_TLE62X0 is not set -CONFIG_SPI_FPGA=y -CONFIG_SPI_FPGA_INIT=y -# CONFIG_SPI_FPGA_INIT_DEBUG is not set -CONFIG_SPI_UART=y -# CONFIG_SPI_UART_DEBUG is not set -# CONFIG_SPI_GPIO_DEBUG is not set -CONFIG_SPI_I2C=y -# CONFIG_SPI_I2C_DEBUG is not set -CONFIG_SPI_DPRAM=y -# CONFIG_SPI_DPRAM_DEBUG is not set - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -# CONFIG_GPIO_SYSFS is not set - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCF857X is not set - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set -# CONFIG_GPIO_MC33880 is not set - -# -# AC97 GPIO expanders: -# -# CONFIG_GPIO_PCA9554 is not set -CONFIG_EXPANDED_GPIO_NUM=0 -CONFIG_EXPANDED_GPIO_IRQ_NUM=0 -# CONFIG_W1 is not set -CONFIG_POWER_SUPPLY=y -# CONFIG_POWER_SUPPLY_DEBUG is not set -# CONFIG_PDA_POWER is not set -# CONFIG_BATTERY_DS2760 is not set -# CONFIG_BATTERY_DS2782 is not set -# CONFIG_BATTERY_BQ27x00 is not set -# CONFIG_BATTERY_MAX17040 is not set -CONFIG_BATTERY_RK2818=y -CONFIG_PMIC_LP8725=y -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -# CONFIG_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_MC13783 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_EZX_PCAP is not set -CONFIG_REGULATOR=y -CONFIG_REGULATOR_DEBUG=y -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_REGULATOR_BQ24022 is not set -# CONFIG_REGULATOR_MAX1586 is not set -# CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set -CONFIG_MEDIA_SUPPORT=y - -# -# Multimedia core support -# -# CONFIG_VIDEO_DEV is not set -# CONFIG_DVB_CORE is not set -# CONFIG_VIDEO_MEDIA is not set - -# -# Multimedia drivers -# -# CONFIG_DAB is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -CONFIG_VIDEO_OUTPUT_CONTROL=y -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_S1D13XXX is not set -CONFIG_FB_RK2818=y -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -CONFIG_BACKLIGHT_LCD_SUPPORT=y -# CONFIG_LCD_CLASS_DEVICE is not set -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set -CONFIG_BACKLIGHT_RK2818_BL=y - -# -# Display device support -# -CONFIG_DISPLAY_SUPPORT=y - -# -# Display hardware drivers -# -# CONFIG_LCD_NULL is not set -# CONFIG_LCD_TD043MGEA1 is not set -CONFIG_LCD_HX8357=y -# CONFIG_LCD_TJ048NC01CA is not set -# CONFIG_LCD_HL070VM4AU is not set -# CONFIG_LCD_HSD070IDW1 is not set -# CONFIG_LCD_A060SE02 is not set -# CONFIG_LCD_S1D13521 is not set -# CONFIG_LCD_NT35582 is not set -# CONFIG_LCD_NT35580 is not set -CONFIG_TV_NULL=y -CONFIG_HDMI_NULL=y -# CONFIG_HDMI_ANX7150 is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FONTS=y -# CONFIG_FONT_8x8 is not set -CONFIG_FONT_8x16=y -# CONFIG_FONT_6x11 is not set -# CONFIG_FONT_7x14 is not set -# CONFIG_FONT_PEARL_8x8 is not set -# CONFIG_FONT_ACORN_8x8 is not set -# CONFIG_FONT_MINI_4x6 is not set -# CONFIG_FONT_SUN8x16 is not set -# CONFIG_FONT_SUN12x22 is not set -# CONFIG_FONT_10x18 is not set -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_LOGO_LINUX_CLUT224=y -CONFIG_SOUND=y -# CONFIG_SOUND_OSS_CORE is not set -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_JACK=y -# CONFIG_SND_SEQUENCER is not set -# CONFIG_SND_MIXER_OSS is not set -# CONFIG_SND_PCM_OSS is not set -# CONFIG_SND_HRTIMER is not set -# CONFIG_SND_DYNAMIC_MINORS is not set -# CONFIG_SND_SUPPORT_OLD_API is not set -# CONFIG_SND_VERBOSE_PROCFS is not set -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -# CONFIG_SND_RAWMIDI_SEQ is not set -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_ARM is not set -# CONFIG_SND_SPI is not set -CONFIG_SND_SOC=y -CONFIG_SND_ROCKCHIP_SOC=y -CONFIG_SND_ROCKCHIP_SOC_I2S=y -# CONFIG_SND_ROCKCHIP_SOC_WM8988 is not set -CONFIG_SND_ROCKCHIP_SOC_WM8994=y -CONFIG_SND_CODEC_SOC_MASTER=y -# CONFIG_SND_CODEC_SOC_SLAVE is not set -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SOC_ALL_CODECS is not set -CONFIG_SND_SOC_WM8994=y -# CONFIG_SOUND_PRIME is not set -# CONFIG_HID_SUPPORT is not set -CONFIG_HID=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set -# CONFIG_USB is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -# CONFIG_USB_MUSB_HDRC is not set -# CONFIG_USB_GADGET_MUSB_HDRC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -CONFIG_USB_GADGET_VBUS_DRAW=500 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_R8A66597 is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C_HSOTG is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LANGWELL is not set -CONFIG_USB_GADGET_DWC_OTG=y -CONFIG_USB_DWC_OTG=y -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -# CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_ETH is not set -# CONFIG_USB_GADGETFS is not set -# CONFIG_USB_FILE_STORAGE is not set -# CONFIG_USB_G_SERIAL is not set -# CONFIG_USB_MIDI_GADGET is not set -# CONFIG_USB_G_PRINTER is not set -CONFIG_USB_ANDROID=y -# CONFIG_USB_ANDROID_ACM is not set -# CONFIG_USB_ANDROID_ADB is not set -CONFIG_USB_ANDROID_MASS_STORAGE=y -CONFIG_USB_ANDROID_RNDIS=y -CONFIG_USB_ANDROID_RNDIS_WCEIS=y -# CONFIG_USB_CDC_COMPOSITE is not set - -# -# OTG and related infrastructure -# -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set -# CONFIG_RK2818_HOST11 is not set -CONFIG_DWC_OTG=y -# CONFIG_DWC_OTG_DEBUG is not set -# CONFIG_DWC_OTG_HOST_ONLY is not set -CONFIG_DWC_OTG_DEVICE_ONLY=y -# CONFIG_DWC_OTG_BOTH_HOST_SLAVE is not set -# CONFIG_DWC_OTG_NORMAL_PREFERENCE is not set -# CONFIG_DWC_OTG_HOST_PREFERENCE is not set -CONFIG_DWC_OTG_DEVICE_PREFERENCE=y -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set -CONFIG_MMC_EMBEDDED_SDIO=y -# CONFIG_MMC_PARANOID_SD_INIT is not set - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -CONFIG_MMC_BLOCK_DEFERRED_RESUME=y -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -CONFIG_SDMMC_RK2818=y - -# -# Now, there are two SDMMC controllers selected, SDMMC0 and SDMMC1. -# -CONFIG_SDMMC0_RK2818=y -CONFIG_SDMMC1_RK2818=y -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set -# CONFIG_MMC_SPI is not set -# CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set -CONFIG_SWITCH=y -CONFIG_SWITCH_GPIO=y -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -# CONFIG_RTC_INTF_SYSFS is not set -# CONFIG_RTC_INTF_PROC is not set -# CONFIG_RTC_INTF_DEV is not set -CONFIG_RTC_INTF_ALARM=y -CONFIG_RTC_INTF_ALARM_DEV=y -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -CONFIG_RTC_HYM8563=y -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set - -# -# SPI RTC drivers -# -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_DS3234 is not set -# CONFIG_RTC_DRV_PCF2123 is not set - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set - -# -# TI VLYNQ -# -CONFIG_STAGING=y -# CONFIG_STAGING_EXCLUDE_BUILD is not set -# CONFIG_ECHO is not set - -# -# Android -# -CONFIG_ANDROID=y -CONFIG_ANDROID_BINDER_IPC=y -CONFIG_ANDROID_LOGGER=y -CONFIG_ANDROID_RAM_CONSOLE=y -CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_DATA_SIZE=128 -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_ECC_SIZE=16 -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE=8 -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_POLYNOMIAL=0x11d -# CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT is not set -CONFIG_ANDROID_TIMED_OUTPUT=y -CONFIG_ANDROID_TIMED_GPIO=y -CONFIG_ANDROID_LOW_MEMORY_KILLER=y - -# -# Qualcomm MSM Camera And Video -# - -# -# Camera Sensor Selection -# -# CONFIG_DST is not set -# CONFIG_POHMELFS is not set -# CONFIG_PLAN9AUTH is not set - -# -# RAR Register Driver -# -# CONFIG_RAR_REGISTER is not set -# CONFIG_IIO is not set - -# -# DSP -# -CONFIG_RK2818_DSP=y - -# -# RK1000 control -# -# CONFIG_RK1000_CONTROL is not set - -# -# rk2818 POWER CONTROL -# -CONFIG_RK2818_POWER=y - -# -# File systems -# -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -CONFIG_EXT3_FS_XATTR=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -# CONFIG_EXT4_FS is not set -CONFIG_JBD=y -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y -# CONFIG_XFS_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -# CONFIG_DNOTIFY is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -# CONFIG_MSDOS_FS is not set -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_YAFFS_FS=y -CONFIG_YAFFS_YAFFS1=y -# CONFIG_YAFFS_9BYTE_TAGS is not set -# CONFIG_YAFFS_DOES_ECC is not set -CONFIG_YAFFS_YAFFS2=y -CONFIG_YAFFS_AUTO_YAFFS2=y -# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set -# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set -# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set -CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y -# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_NFS_V4_1=y -CONFIG_ROOT_NFS=y -# CONFIG_NFSD is not set -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -CONFIG_NLS_CODEPAGE_850=y -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -CONFIG_NLS_CODEPAGE_936=y -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -CONFIG_NLS_ISO8859_15=y -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -CONFIG_NLS_UTF8=y -# CONFIG_DLM is not set - -# -# Kernel hacking -# -CONFIG_PRINTK_TIME=y -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -# CONFIG_SCHED_DEBUG is not set -CONFIG_SCHEDSTATS=y -CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_KMEMLEAK is not set -# CONFIG_DEBUG_PREEMPT is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_BUGVERBOSE=y -# CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_TRACING_SUPPORT=y -# CONFIG_FTRACE is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set -CONFIG_DEBUG_ERRORS=y -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_LL is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -CONFIG_CRYPTO_WORKQUEUE=y -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -CONFIG_CRYPTO_ECB=y -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_GHASH is not set -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -CONFIG_CRYPTO_SHA1=y -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_ARC4=y -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -# CONFIG_CRC_T10DIF is not set -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_REED_SOLOMON=y -CONFIG_REED_SOLOMON_ENC8=y -CONFIG_REED_SOLOMON_DEC8=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/arch/arm/configs/rk2818_phone_defconfig b/arch/arm/configs/rk2818_phone_defconfig deleted file mode 100644 index 77e77f8a3c86..000000000000 --- a/arch/arm/configs/rk2818_phone_defconfig +++ /dev/null @@ -1,1652 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.32.9 -# Thu Jul 29 09:03:55 2010 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_HAVE_TCM=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_ARCH_HAS_CPUFREQ=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_LOCK_KERNEL=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -# CONFIG_LOCALVERSION_AUTO is not set -# CONFIG_SWAP is not set -# CONFIG_SYSVIPC is not set -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_IKCONFIG is not set -CONFIG_LOG_BUF_SHIFT=17 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -CONFIG_RT_GROUP_SCHED=y -# CONFIG_USER_SCHED is not set -CONFIG_CGROUP_SCHED=y -CONFIG_CGROUPS=y -CONFIG_CGROUP_DEBUG=y -# CONFIG_CGROUP_NS is not set -CONFIG_CGROUP_FREEZER=y -# CONFIG_CGROUP_DEVICE is not set -# CONFIG_CPUSETS is not set -CONFIG_CGROUP_CPUACCT=y -CONFIG_RESOURCE_COUNTERS=y -# CONFIG_CGROUP_MEM_RES_CTLR is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_PANIC_TIMEOUT=5 -CONFIG_EMBEDDED=y -CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -# CONFIG_ELF_CORE is not set -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_ASHMEM=y -CONFIG_AIO=y - -# -# Kernel Performance Events And Counters -# -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_CLK=y - -# -# GCOV-based kernel profiling -# -# CONFIG_SLOW_WORK is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_BLOCK=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -# CONFIG_IOSCHED_AS is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_FREEZER=y - -# -# System Type -# -CONFIG_MMU=y -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_STMP3XXX is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PC1XX is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_U300 is not set -# CONFIG_ARCH_DAVINCI is not set -# CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_BCMRING is not set -CONFIG_ARCH_RK2818=y - -# -# ROCKCHIP rk2818 Board Type -# -# CONFIG_MACH_RK2818MID is not set -CONFIG_MACH_RK2818PHONE=y -# CONFIG_MACH_RAHO is not set -CONFIG_RK28_GPIO_IRQ=16 -CONFIG_RK28_ADC=y -CONFIG_RK28_USB_WAKE=y - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_ARM926T=y -CONFIG_CPU_32v5=y -CONFIG_CPU_ABRT_EV5TJ=y -CONFIG_CPU_PABRT_LEGACY=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_COPY_V4WB=y -CONFIG_CPU_TLB_V4WBI=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -CONFIG_ARM_THUMB=y -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set -# CONFIG_CPU_CACHE_ROUND_ROBIN is not set -CONFIG_ARM_L1_CACHE_SHIFT=5 -CONFIG_COMMON_CLKDEV=y - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 -# CONFIG_PREEMPT_NONE is not set -# CONFIG_PREEMPT_VOLUNTARY is not set -CONFIG_PREEMPT=y -CONFIG_HZ=100 -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4096 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_UACCESS_WITH_MEMCPY is not set - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_CMDLINE="mem=128M console=ttyS1,115200n8" -# CONFIG_XIP_KERNEL is not set -# CONFIG_KEXEC is not set - -# -# CPU Power Management -# -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_TABLE=y -# CONFIG_CPU_FREQ_DEBUG is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_STAT_DETAILS=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -# CONFIG_CPU_IDLE is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -# CONFIG_VFP is not set - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -CONFIG_HAVE_AOUT=y -# CONFIG_BINFMT_AOUT is not set -# CONFIG_BINFMT_MISC is not set - -# -# Power management options -# -CONFIG_PM=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_SLEEP=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_HAS_WAKELOCK=y -CONFIG_HAS_EARLYSUSPEND=y -CONFIG_WAKELOCK=y -CONFIG_WAKELOCK_STAT=y -CONFIG_USER_WAKELOCK=y -CONFIG_EARLYSUSPEND=y -# CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL is not set -CONFIG_CONSOLE_EARLYSUSPEND=y -# CONFIG_FB_EARLYSUSPEND is not set -# CONFIG_APM_EMULATION is not set -# CONFIG_PM_RUNTIME is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -CONFIG_ANDROID_PARANOID_NETWORK=y -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -CONFIG_BT=y -CONFIG_BT_L2CAP=y -CONFIG_BT_SCO=y -CONFIG_BT_RFCOMM=y -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=y -# CONFIG_BT_BNEP_MC_FILTER is not set -# CONFIG_BT_BNEP_PROTO_FILTER is not set -CONFIG_BT_HIDP=y - -# -# Bluetooth device drivers -# -# CONFIG_BT_HCIBTSDIO is not set -CONFIG_BT_HCIUART=y -CONFIG_BT_HCIUART_H4=y -# CONFIG_BT_HCIUART_BCSP is not set -# CONFIG_BT_HCIUART_LL is not set -# CONFIG_BT_HCIVHCI is not set -# CONFIG_BT_MRVL is not set -# CONFIG_AF_RXRPC is not set -CONFIG_WIRELESS=y -# CONFIG_CFG80211 is not set -CONFIG_CFG80211_DEFAULT_PS_VALUE=0 -# CONFIG_WIRELESS_OLD_REGULATORY is not set -CONFIG_WIRELESS_EXT=y -CONFIG_WIRELESS_EXT_SYSFS=y -CONFIG_LIB80211=y -# CONFIG_LIB80211_DEBUG is not set - -# -# CFG80211 needs to be enabled for MAC80211 -# -# CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -# CONFIG_FIRMWARE_IN_KERNEL is not set -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set -# CONFIG_MTD_CONCAT is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set -# CONFIG_MTD_SST25L is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND_IDS=y -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -# CONFIG_MTD_NAND_GPIO is not set -# CONFIG_MTD_NAND_DISKONCHIP is not set -CONFIG_MTD_NAND_RK2818=y -# CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_PLATFORM is not set -# CONFIG_MTD_ONENAND is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -# CONFIG_MTD_UBI is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_MG_DISK is not set -CONFIG_MISC_DEVICES=y -CONFIG_ANDROID_PMEM=y -# CONFIG_ICS932S401 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_KERNEL_DEBUGGER_CORE is not set -# CONFIG_ISL29003 is not set -CONFIG_UID_STAT=y -CONFIG_APANIC=y -CONFIG_APANIC_PLABEL="kpanic" -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_MAX6875 is not set -# CONFIG_EEPROM_93CX6 is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set -# CONFIG_SCSI_DMA is not set -# CONFIG_SCSI_NETLINK is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -# CONFIG_PHYLIB is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_SMC91X is not set -CONFIG_DM9000=y -CONFIG_DM9000_DEBUGLEVEL=4 -CONFIG_DM9000_USE_NAND_CONTROL=y -# CONFIG_DM9000_USE_NOR_CONTROL is not set -# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -# CONFIG_SMC911X is not set -# CONFIG_SMSC911X is not set -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851 is not set -# CONFIG_KS8851_MLL is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -CONFIG_WLAN=y -# CONFIG_WLAN_PRE80211 is not set -CONFIG_WLAN_80211=y -CONFIG_LIBERTAS=y -CONFIG_LIBERTAS_SDIO=y -# CONFIG_LIBERTAS_SPI is not set -# CONFIG_LIBERTAS_DEBUG is not set -# CONFIG_HOSTAP is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# -# CONFIG_WAN is not set -CONFIG_PPP=y -# CONFIG_PPP_MULTILINK is not set -# CONFIG_PPP_FILTER is not set -CONFIG_PPP_ASYNC=y -# CONFIG_PPP_SYNC_TTY is not set -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_BSDCOMP=y -CONFIG_PPP_MPPE=y -# CONFIG_PPPOE is not set -# CONFIG_PPPOL2TP is not set -CONFIG_PPPOLAC=y -CONFIG_PPPOPNS=y -# CONFIG_SLIP is not set -CONFIG_SLHC=y -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -CONFIG_INPUT_POLLDEV=y - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set -CONFIG_INPUT_KEYRESET=y - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_QT2160 is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -CONFIG_KEYBOARD_RK28ADC=y -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -CONFIG_INPUT_TOUCHSCREEN=y -# CONFIG_TOUCHSCREEN_ADS7846 is not set -# CONFIG_TOUCHSCREEN_AD7877 is not set -# CONFIG_TOUCHSCREEN_XPT2046_SPI is not set -# CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI is not set -CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI=y -# CONFIG_TOUCHSCREEN_XPT2046_320X480_CBN_SPI is not set -# CONFIG_TOUCHSCREEN_AD7879_I2C is not set -# CONFIG_TOUCHSCREEN_AD7879_SPI is not set -# CONFIG_TOUCHSCREEN_AD7879 is not set -# CONFIG_TOUCHSCREEN_EETI is not set -# CONFIG_TOUCHSCREEN_FUJITSU is not set -# CONFIG_TOUCHSCREEN_GUNZE is not set -# CONFIG_TOUCHSCREEN_ELO is not set -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set -# CONFIG_TOUCHSCREEN_MCS5000 is not set -# CONFIG_TOUCHSCREEN_MTOUCH is not set -# CONFIG_TOUCHSCREEN_INEXIO is not set -# CONFIG_TOUCHSCREEN_MK712 is not set -# CONFIG_TOUCHSCREEN_PENMOUNT is not set -# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set -# CONFIG_TOUCHSCREEN_TSC2007 is not set -# CONFIG_TOUCHSCREEN_W90X900 is not set -CONFIG_INPUT_MISC=y -# CONFIG_INPUT_ATI_REMOTE is not set -# CONFIG_INPUT_ATI_REMOTE2 is not set -CONFIG_INPUT_KEYCHORD=y -# CONFIG_INPUT_KEYSPAN_REMOTE is not set -# CONFIG_INPUT_POWERMATE is not set -# CONFIG_INPUT_YEALINK is not set -# CONFIG_INPUT_CM109 is not set -CONFIG_INPUT_UINPUT=y -# CONFIG_INPUT_GPIO is not set -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set -# CONFIG_G_SENSOR_DEVICE is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_DEVMEM=y -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_MAX3100 is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_SERIAL_RK2818=y -CONFIG_UART1_RK2818=y -CONFIG_SERIAL_RK2818_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -# CONFIG_DCC_TTY is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -# CONFIG_I2C_CHARDEV is not set -CONFIG_I2C_HELPER_AUTO=y - -# -# I2C Hardware Bus support -# -CONFIG_I2C_RK2818=y - -# -# Now, there are two I2C interfaces selected by developer, I2C0 and I2C1. -# -CONFIG_I2C0_RK2818=y -CONFIG_I2C1_RK2818=y - -# -# Miscellaneous I2C Chip support -# -# CONFIG_DS1682 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_SENSORS_PCA963X is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -CONFIG_SPI_BITBANG=y -CONFIG_SPI_GPIO=y -CONFIG_SPIM_RK2818=y - -# -# SPI Protocol Masters -# -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_TLE62X0 is not set -CONFIG_SPI_FPGA=y -CONFIG_SPI_FPGA_INIT=y -# CONFIG_SPI_FPGA_INIT_DEBUG is not set -CONFIG_SPI_UART=y -# CONFIG_SPI_UART_DEBUG is not set -# CONFIG_SPI_GPIO_DEBUG is not set -CONFIG_SPI_I2C=y -# CONFIG_SPI_I2C_DEBUG is not set -CONFIG_SPI_DPRAM=y -# CONFIG_SPI_DPRAM_DEBUG is not set - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -# CONFIG_GPIO_SYSFS is not set - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCF857X is not set - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set -# CONFIG_GPIO_MC33880 is not set - -# -# AC97 GPIO expanders: -# -# CONFIG_GPIO_PCA9554 is not set -CONFIG_EXPANDED_GPIO_NUM=0 -CONFIG_EXPANDED_GPIO_IRQ_NUM=0 -# CONFIG_W1 is not set -CONFIG_POWER_SUPPLY=y -# CONFIG_POWER_SUPPLY_DEBUG is not set -# CONFIG_PDA_POWER is not set -# CONFIG_BATTERY_DS2760 is not set -# CONFIG_BATTERY_DS2782 is not set -# CONFIG_BATTERY_BQ27x00 is not set -# CONFIG_BATTERY_MAX17040 is not set -CONFIG_BATTERY_RK2818=y -CONFIG_PMIC_LP8725=y -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -# CONFIG_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_MC13783 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_EZX_PCAP is not set -CONFIG_REGULATOR=y -CONFIG_REGULATOR_DEBUG=y -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_REGULATOR_BQ24022 is not set -# CONFIG_REGULATOR_MAX1586 is not set -# CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set -CONFIG_MEDIA_SUPPORT=y - -# -# Multimedia core support -# -# CONFIG_VIDEO_DEV is not set -# CONFIG_DVB_CORE is not set -# CONFIG_VIDEO_MEDIA is not set - -# -# Multimedia drivers -# -# CONFIG_DAB is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -CONFIG_VIDEO_OUTPUT_CONTROL=y -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_S1D13XXX is not set -CONFIG_FB_RK2818=y -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -CONFIG_BACKLIGHT_LCD_SUPPORT=y -# CONFIG_LCD_CLASS_DEVICE is not set -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set -CONFIG_BACKLIGHT_RK2818_BL=y - -# -# Display device support -# -CONFIG_DISPLAY_SUPPORT=y - -# -# Display hardware drivers -# -# CONFIG_LCD_NULL is not set -# CONFIG_LCD_TD043MGEA1 is not set -CONFIG_LCD_HX8357=y -# CONFIG_LCD_TJ048NC01CA is not set -# CONFIG_LCD_HL070VM4AU is not set -# CONFIG_LCD_HSD070IDW1 is not set -# CONFIG_LCD_A060SE02 is not set -# CONFIG_LCD_S1D13521 is not set -# CONFIG_LCD_NT35582 is not set -# CONFIG_LCD_NT35580 is not set -CONFIG_TV_NULL=y -CONFIG_HDMI_NULL=y -# CONFIG_HDMI_ANX7150 is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FONTS=y -# CONFIG_FONT_8x8 is not set -CONFIG_FONT_8x16=y -# CONFIG_FONT_6x11 is not set -# CONFIG_FONT_7x14 is not set -# CONFIG_FONT_PEARL_8x8 is not set -# CONFIG_FONT_ACORN_8x8 is not set -# CONFIG_FONT_MINI_4x6 is not set -# CONFIG_FONT_SUN8x16 is not set -# CONFIG_FONT_SUN12x22 is not set -# CONFIG_FONT_10x18 is not set -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_LOGO_LINUX_CLUT224=y -CONFIG_SOUND=y -# CONFIG_SOUND_OSS_CORE is not set -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_JACK=y -# CONFIG_SND_SEQUENCER is not set -# CONFIG_SND_MIXER_OSS is not set -# CONFIG_SND_PCM_OSS is not set -# CONFIG_SND_HRTIMER is not set -# CONFIG_SND_DYNAMIC_MINORS is not set -# CONFIG_SND_SUPPORT_OLD_API is not set -# CONFIG_SND_VERBOSE_PROCFS is not set -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -# CONFIG_SND_RAWMIDI_SEQ is not set -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_ARM is not set -# CONFIG_SND_SPI is not set -CONFIG_SND_SOC=y -CONFIG_SND_ROCKCHIP_SOC=y -CONFIG_SND_ROCKCHIP_SOC_I2S=y -# CONFIG_SND_ROCKCHIP_SOC_WM8988 is not set -CONFIG_SND_ROCKCHIP_SOC_WM8994=y -CONFIG_SND_CODEC_SOC_MASTER=y -# CONFIG_SND_CODEC_SOC_SLAVE is not set -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SOC_ALL_CODECS is not set -CONFIG_SND_SOC_WM8994=y -# CONFIG_SOUND_PRIME is not set -# CONFIG_HID_SUPPORT is not set -CONFIG_HID=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set -# CONFIG_USB is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -# CONFIG_USB_MUSB_HDRC is not set -# CONFIG_USB_GADGET_MUSB_HDRC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -CONFIG_USB_GADGET_VBUS_DRAW=500 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_R8A66597 is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C_HSOTG is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LANGWELL is not set -CONFIG_USB_GADGET_DWC_OTG=y -CONFIG_USB_DWC_OTG=y -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -# CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_ETH is not set -# CONFIG_USB_GADGETFS is not set -# CONFIG_USB_FILE_STORAGE is not set -# CONFIG_USB_G_SERIAL is not set -# CONFIG_USB_MIDI_GADGET is not set -# CONFIG_USB_G_PRINTER is not set -CONFIG_USB_ANDROID=y -# CONFIG_USB_ANDROID_ACM is not set -# CONFIG_USB_ANDROID_ADB is not set -CONFIG_USB_ANDROID_MASS_STORAGE=y -CONFIG_USB_ANDROID_RNDIS=y -CONFIG_USB_ANDROID_RNDIS_WCEIS=y -# CONFIG_USB_CDC_COMPOSITE is not set - -# -# OTG and related infrastructure -# -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set -# CONFIG_RK2818_HOST11 is not set -CONFIG_DWC_OTG=y -# CONFIG_DWC_OTG_DEBUG is not set -# CONFIG_DWC_OTG_HOST_ONLY is not set -CONFIG_DWC_OTG_DEVICE_ONLY=y -# CONFIG_DWC_OTG_BOTH_HOST_SLAVE is not set -# CONFIG_DWC_OTG_NORMAL_PREFERENCE is not set -# CONFIG_DWC_OTG_HOST_PREFERENCE is not set -CONFIG_DWC_OTG_DEVICE_PREFERENCE=y -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set -CONFIG_MMC_EMBEDDED_SDIO=y -# CONFIG_MMC_PARANOID_SD_INIT is not set - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -CONFIG_MMC_BLOCK_DEFERRED_RESUME=y -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -CONFIG_SDMMC_RK2818=y - -# -# Now, there are two SDMMC controllers selected, SDMMC0 and SDMMC1. -# -CONFIG_SDMMC0_RK2818=y -CONFIG_SDMMC1_RK2818=y -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set -# CONFIG_MMC_SPI is not set -# CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set -CONFIG_SWITCH=y -CONFIG_SWITCH_GPIO=y -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -# CONFIG_RTC_INTF_SYSFS is not set -# CONFIG_RTC_INTF_PROC is not set -# CONFIG_RTC_INTF_DEV is not set -CONFIG_RTC_INTF_ALARM=y -CONFIG_RTC_INTF_ALARM_DEV=y -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -CONFIG_RTC_HYM8563=y -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set - -# -# SPI RTC drivers -# -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_DS3234 is not set -# CONFIG_RTC_DRV_PCF2123 is not set - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set - -# -# TI VLYNQ -# -CONFIG_STAGING=y -# CONFIG_STAGING_EXCLUDE_BUILD is not set -# CONFIG_ECHO is not set - -# -# Android -# -CONFIG_ANDROID=y -CONFIG_ANDROID_BINDER_IPC=y -CONFIG_ANDROID_LOGGER=y -CONFIG_ANDROID_RAM_CONSOLE=y -CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_DATA_SIZE=128 -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_ECC_SIZE=16 -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE=8 -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_POLYNOMIAL=0x11d -# CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT is not set -CONFIG_ANDROID_TIMED_OUTPUT=y -CONFIG_ANDROID_TIMED_GPIO=y -CONFIG_ANDROID_LOW_MEMORY_KILLER=y - -# -# Qualcomm MSM Camera And Video -# - -# -# Camera Sensor Selection -# -# CONFIG_DST is not set -# CONFIG_POHMELFS is not set -# CONFIG_PLAN9AUTH is not set - -# -# RAR Register Driver -# -# CONFIG_RAR_REGISTER is not set -# CONFIG_IIO is not set - -# -# DSP -# -CONFIG_RK2818_DSP=y - -# -# RK1000 control -# -# CONFIG_RK1000_CONTROL is not set - -# -# rk2818 POWER CONTROL -# -CONFIG_RK2818_POWER=y - -# -# File systems -# -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -CONFIG_EXT3_FS_XATTR=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -# CONFIG_EXT4_FS is not set -CONFIG_JBD=y -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y -# CONFIG_XFS_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -# CONFIG_DNOTIFY is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -# CONFIG_MSDOS_FS is not set -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_YAFFS_FS=y -CONFIG_YAFFS_YAFFS1=y -# CONFIG_YAFFS_9BYTE_TAGS is not set -# CONFIG_YAFFS_DOES_ECC is not set -CONFIG_YAFFS_YAFFS2=y -CONFIG_YAFFS_AUTO_YAFFS2=y -# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set -# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set -# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set -CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y -# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_NFS_V4_1=y -CONFIG_ROOT_NFS=y -# CONFIG_NFSD is not set -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -CONFIG_NLS_CODEPAGE_850=y -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -CONFIG_NLS_CODEPAGE_936=y -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -CONFIG_NLS_ISO8859_15=y -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -CONFIG_NLS_UTF8=y -# CONFIG_DLM is not set - -# -# Kernel hacking -# -CONFIG_PRINTK_TIME=y -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -# CONFIG_SCHED_DEBUG is not set -CONFIG_SCHEDSTATS=y -CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_KMEMLEAK is not set -# CONFIG_DEBUG_PREEMPT is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_BUGVERBOSE=y -# CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_TRACING_SUPPORT=y -# CONFIG_FTRACE is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set -CONFIG_DEBUG_ERRORS=y -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_LL is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -CONFIG_CRYPTO_WORKQUEUE=y -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -CONFIG_CRYPTO_ECB=y -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_GHASH is not set -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -CONFIG_CRYPTO_SHA1=y -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_ARC4=y -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -# CONFIG_CRC_T10DIF is not set -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_REED_SOLOMON=y -CONFIG_REED_SOLOMON_ENC8=y -CONFIG_REED_SOLOMON_DEC8=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/arch/arm/configs/rk2818_raho_defconfig b/arch/arm/configs/rk2818_raho_defconfig deleted file mode 100755 index 83e026bb96f0..000000000000 --- a/arch/arm/configs/rk2818_raho_defconfig +++ /dev/null @@ -1,1749 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.32.9 -# Sun Sep 5 00:43:03 2010 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_HAVE_TCM=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_ARCH_HAS_CPUFREQ=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_LOCK_KERNEL=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -# CONFIG_LOCALVERSION_AUTO is not set -# CONFIG_SWAP is not set -# CONFIG_SYSVIPC is not set -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_IKCONFIG is not set -CONFIG_LOG_BUF_SHIFT=17 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -CONFIG_RT_GROUP_SCHED=y -# CONFIG_USER_SCHED is not set -CONFIG_CGROUP_SCHED=y -CONFIG_CGROUPS=y -CONFIG_CGROUP_DEBUG=y -# CONFIG_CGROUP_NS is not set -CONFIG_CGROUP_FREEZER=y -# CONFIG_CGROUP_DEVICE is not set -# CONFIG_CPUSETS is not set -CONFIG_CGROUP_CPUACCT=y -CONFIG_RESOURCE_COUNTERS=y -# CONFIG_CGROUP_MEM_RES_CTLR is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_PANIC_TIMEOUT=5 -CONFIG_EMBEDDED=y -CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -# CONFIG_ELF_CORE is not set -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_ASHMEM=y -CONFIG_AIO=y - -# -# Kernel Performance Events And Counters -# -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_CLK=y - -# -# GCOV-based kernel profiling -# -# CONFIG_SLOW_WORK is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_BLOCK=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -# CONFIG_IOSCHED_AS is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_FREEZER=y - -# -# System Type -# -CONFIG_MMU=y -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_STMP3XXX is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PC1XX is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_U300 is not set -# CONFIG_ARCH_DAVINCI is not set -# CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_BCMRING is not set -CONFIG_ARCH_RK2818=y - -# -# ROCKCHIP rk2818 Board Type -# -# CONFIG_MACH_RK2818MID is not set -# CONFIG_MACH_RK2818PHONE is not set -CONFIG_MACH_RAHO=y -# CONFIG_MACH_RK2818INFO is not set -CONFIG_RK28_GPIO_IRQ=16 -CONFIG_RK28_ADC=y -CONFIG_RK28_USB_WAKE=y -CONFIG_WIFI_CONTROL_FUNC=y -CONFIG_RK2818_SOC_PM=y - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_ARM926T=y -CONFIG_CPU_32v5=y -CONFIG_CPU_ABRT_EV5TJ=y -CONFIG_CPU_PABRT_LEGACY=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_COPY_V4WB=y -CONFIG_CPU_TLB_V4WBI=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -CONFIG_ARM_THUMB=y -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set -# CONFIG_CPU_CACHE_ROUND_ROBIN is not set -CONFIG_ARM_L1_CACHE_SHIFT=5 -CONFIG_COMMON_CLKDEV=y - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 -# CONFIG_PREEMPT_NONE is not set -# CONFIG_PREEMPT_VOLUNTARY is not set -CONFIG_PREEMPT=y -CONFIG_HZ=100 -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4096 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_UACCESS_WITH_MEMCPY is not set - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_CMDLINE="mem=128M console=ttyS1,115200n8" -# CONFIG_XIP_KERNEL is not set -# CONFIG_KEXEC is not set - -# -# CPU Power Management -# -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_TABLE=y -# CONFIG_CPU_FREQ_DEBUG is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_STAT_DETAILS=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -# CONFIG_CPU_IDLE is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -# CONFIG_VFP is not set - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -CONFIG_HAVE_AOUT=y -# CONFIG_BINFMT_AOUT is not set -# CONFIG_BINFMT_MISC is not set - -# -# Power management options -# -CONFIG_PM=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_SLEEP=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_HAS_WAKELOCK=y -CONFIG_HAS_EARLYSUSPEND=y -CONFIG_WAKELOCK=y -CONFIG_WAKELOCK_STAT=y -CONFIG_USER_WAKELOCK=y -CONFIG_EARLYSUSPEND=y -# CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL is not set -CONFIG_CONSOLE_EARLYSUSPEND=y -# CONFIG_FB_EARLYSUSPEND is not set -# CONFIG_APM_EMULATION is not set -# CONFIG_PM_RUNTIME is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -CONFIG_ANDROID_PARANOID_NETWORK=y -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -CONFIG_BT=y -CONFIG_BT_L2CAP=y -CONFIG_BT_SCO=y -CONFIG_BT_RFCOMM=y -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=y -# CONFIG_BT_BNEP_MC_FILTER is not set -# CONFIG_BT_BNEP_PROTO_FILTER is not set -CONFIG_BT_HIDP=y - -# -# Bluetooth device drivers -# -# CONFIG_BT_HCIBTSDIO is not set -CONFIG_BT_HCIUART=y -CONFIG_BT_HCIUART_H4=y -# CONFIG_BT_HCIUART_BCSP is not set -# CONFIG_BT_HCIUART_LL is not set -# CONFIG_BT_HCIVHCI is not set -# CONFIG_BT_MRVL is not set -# CONFIG_BT_HCIBCM4325 is not set -# CONFIG_AF_RXRPC is not set -CONFIG_WIRELESS=y -# CONFIG_CFG80211 is not set -CONFIG_CFG80211_DEFAULT_PS_VALUE=0 -# CONFIG_WIRELESS_OLD_REGULATORY is not set -CONFIG_WIRELESS_EXT=y -CONFIG_WIRELESS_EXT_SYSFS=y -CONFIG_LIB80211=y -# CONFIG_LIB80211_DEBUG is not set - -# -# CFG80211 needs to be enabled for MAC80211 -# -# CONFIG_WIMAX is not set -CONFIG_RFKILL=y -CONFIG_RFKILL_PM=y -# CONFIG_RFKILL_INPUT is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -# CONFIG_FIRMWARE_IN_KERNEL is not set -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set -# CONFIG_MTD_CONCAT is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set -# CONFIG_MTD_SST25L is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND_IDS=y -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -# CONFIG_MTD_NAND_GPIO is not set -# CONFIG_MTD_NAND_DISKONCHIP is not set -CONFIG_MTD_NAND_RK2818=y -# CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_PLATFORM is not set -# CONFIG_MTD_ONENAND is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -# CONFIG_MTD_UBI is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_MG_DISK is not set -CONFIG_MISC_DEVICES=y -CONFIG_ANDROID_PMEM=y -# CONFIG_ICS932S401 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_KERNEL_DEBUGGER_CORE is not set -# CONFIG_ISL29003 is not set -CONFIG_UID_STAT=y -# CONFIG_WL127X_RFKILL is not set -CONFIG_APANIC=y -CONFIG_APANIC_PLABEL="kpanic" -CONFIG_STE=y -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_MAX6875 is not set -# CONFIG_EEPROM_93CX6 is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set -# CONFIG_SCSI_DMA is not set -# CONFIG_SCSI_NETLINK is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -# CONFIG_PHYLIB is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_SMC91X is not set -# CONFIG_DM9000 is not set -# CONFIG_DM9000_USE_NAND_CONTROL is not set -# CONFIG_DM9000_USE_NOR_CONTROL is not set -# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -# CONFIG_SMC911X is not set -# CONFIG_SMSC911X is not set -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851 is not set -# CONFIG_KS8851_MLL is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -CONFIG_WLAN=y -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set -CONFIG_BCM4329=y -CONFIG_BCM4329_FW_PATH="/etc/firmware/fw_bcm4329.bin" -CONFIG_BCM4329_NVRAM_PATH="/etc/firmware/nvram_bcm4329_B23.txt" - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# -# CONFIG_WAN is not set -CONFIG_PPP=y -# CONFIG_PPP_MULTILINK is not set -# CONFIG_PPP_FILTER is not set -CONFIG_PPP_ASYNC=y -# CONFIG_PPP_SYNC_TTY is not set -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_BSDCOMP=y -CONFIG_PPP_MPPE=y -# CONFIG_PPPOE is not set -# CONFIG_PPPOL2TP is not set -CONFIG_PPPOLAC=y -CONFIG_PPPOPNS=y -# CONFIG_SLIP is not set -CONFIG_SLHC=y -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -CONFIG_INPUT_POLLDEV=y - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set -CONFIG_INPUT_KEYRESET=y - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_QT2160 is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -CONFIG_KEYBOARD_RK28ADC=y -CONFIG_HEADSET_KEY=y -# CONFIG_KEYBOARD_RK28ADC_IT50 is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -CONFIG_INPUT_TOUCHSCREEN=y -# CONFIG_TOUCHSCREEN_ADS7846 is not set -# CONFIG_TOUCHSCREEN_AD7877 is not set -# CONFIG_TOUCHSCREEN_XPT2046_SPI is not set -# CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI is not set -CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI=y -# CONFIG_TOUCHSCREEN_XPT2046_320X480_CBN_SPI is not set -CONFIG_TOUCHSCREEN_IT7250=y -# CONFIG_TOUCHSCREEN_AD7879_I2C is not set -# CONFIG_TOUCHSCREEN_AD7879_SPI is not set -# CONFIG_TOUCHSCREEN_AD7879 is not set -# CONFIG_TOUCHSCREEN_EETI is not set -# CONFIG_TOUCHSCREEN_FUJITSU is not set -# CONFIG_TOUCHSCREEN_GUNZE is not set -# CONFIG_TOUCHSCREEN_ELO is not set -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set -# CONFIG_TOUCHSCREEN_MCS5000 is not set -# CONFIG_TOUCHSCREEN_MTOUCH is not set -# CONFIG_TOUCHSCREEN_INEXIO is not set -# CONFIG_TOUCHSCREEN_MK712 is not set -# CONFIG_TOUCHSCREEN_PENMOUNT is not set -# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set -# CONFIG_TOUCHSCREEN_TSC2007 is not set -# CONFIG_TOUCHSCREEN_W90X900 is not set -CONFIG_INPUT_MISC=y -CONFIG_INPUT_LPSENSOR_CM3602=y -# CONFIG_INPUT_ATI_REMOTE is not set -# CONFIG_INPUT_ATI_REMOTE2 is not set -CONFIG_INPUT_KEYCHORD=y -# CONFIG_INPUT_KEYSPAN_REMOTE is not set -# CONFIG_INPUT_POWERMATE is not set -# CONFIG_INPUT_YEALINK is not set -# CONFIG_INPUT_CM109 is not set -CONFIG_INPUT_UINPUT=y -# CONFIG_INPUT_GPIO is not set -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set -CONFIG_G_SENSOR_DEVICE=y -CONFIG_GS_MMA7660=y - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_DEVMEM=y -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_MAX3100 is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_SERIAL_RK2818=y -CONFIG_UART0_RK2818=y -CONFIG_UART1_RK2818=y -CONFIG_SERIAL_RK2818_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -# CONFIG_DCC_TTY is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -# CONFIG_I2C_CHARDEV is not set -CONFIG_I2C_HELPER_AUTO=y - -# -# I2C Hardware Bus support -# -CONFIG_I2C_RK2818=y - -# -# Now, there are two I2C interfaces selected by developer, I2C0 and I2C1. -# -CONFIG_I2C0_RK2818=y -CONFIG_I2C1_RK2818=y - -# -# Miscellaneous I2C Chip support -# -# CONFIG_DS1682 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_SENSORS_PCA963X is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -CONFIG_SPI_BITBANG=y -CONFIG_SPI_GPIO=y -CONFIG_SPIM_RK2818=y - -# -# SPI Protocol Masters -# -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_TLE62X0 is not set -CONFIG_SPI_FPGA=y -CONFIG_SPI_FPGA_INIT=y -# CONFIG_SPI_FPGA_INIT_DEBUG is not set -CONFIG_SPI_FPGA_UART=y -# CONFIG_SPI_UART_DEBUG is not set -CONFIG_SPI_FPGA_GPIO=y -# CONFIG_SPI_GPIO_DEBUG is not set -CONFIG_SPI_FPGA_I2C=y -# CONFIG_SPI_I2C_DEBUG is not set -CONFIG_SPI_FPGA_DPRAM=y -# CONFIG_SPI_DPRAM_DEBUG is not set -CONFIG_SPI_FPGA_FW=y -CONFIG_HEADSET_DET=y - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -# CONFIG_GPIO_SYSFS is not set - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCF857X is not set - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set -# CONFIG_GPIO_MC33880 is not set - -# -# AC97 GPIO expanders: -# -# CONFIG_GPIO_PCA9554 is not set -# CONFIG_IOEXTEND_TCA6424 is not set -CONFIG_EXPANDED_GPIO_NUM=96 -CONFIG_EXPANDED_GPIO_IRQ_NUM=16 -# CONFIG_EXPAND_GPIO_SOFT_INTERRUPT is not set -CONFIG_SPI_FPGA_GPIO_NUM=96 -CONFIG_SPI_FPGA_GPIO_IRQ_NUM=16 -# CONFIG_W1 is not set -CONFIG_POWER_SUPPLY=y -# CONFIG_POWER_SUPPLY_DEBUG is not set -# CONFIG_PDA_POWER is not set -# CONFIG_BATTERY_DS2760 is not set -# CONFIG_BATTERY_DS2782 is not set -# CONFIG_BATTERY_BQ27x00 is not set -# CONFIG_BATTERY_MAX17040 is not set -CONFIG_BATTERY_RK2818=y -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -# CONFIG_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_MC13783 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_EZX_PCAP is not set -CONFIG_REGULATOR=y -CONFIG_REGULATOR_DEBUG=y -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_REGULATOR_BQ24022 is not set -# CONFIG_REGULATOR_MAX1586 is not set -# CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set -CONFIG_RK2818_REGULATOR_CHARGE=y -CONFIG_RK2818_REGULATOR_LP8725=y -CONFIG_MEDIA_SUPPORT=y - -# -# Multimedia core support -# -CONFIG_VIDEO_DEV=y -CONFIG_VIDEO_V4L2_COMMON=y -CONFIG_VIDEO_ALLOW_V4L1=y -CONFIG_VIDEO_V4L1_COMPAT=y -# CONFIG_DVB_CORE is not set -CONFIG_VIDEO_MEDIA=y - -# -# Multimedia drivers -# -# CONFIG_MEDIA_ATTACH is not set -CONFIG_MEDIA_TUNER=y -# CONFIG_MEDIA_TUNER_CUSTOMISE is not set -CONFIG_MEDIA_TUNER_SIMPLE=y -CONFIG_MEDIA_TUNER_TDA8290=y -CONFIG_MEDIA_TUNER_TDA9887=y -CONFIG_MEDIA_TUNER_TEA5761=y -CONFIG_MEDIA_TUNER_TEA5767=y -CONFIG_MEDIA_TUNER_MT20XX=y -CONFIG_MEDIA_TUNER_XC2028=y -CONFIG_MEDIA_TUNER_XC5000=y -CONFIG_MEDIA_TUNER_MC44S803=y -CONFIG_VIDEO_V4L2=y -CONFIG_VIDEO_V4L1=y -CONFIG_VIDEOBUF_GEN=y -CONFIG_VIDEOBUF_DMA_CONTIG=y -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -CONFIG_VIDEO_HELPER_CHIPS_AUTO=y -# CONFIG_VIDEO_VIVI is not set -# CONFIG_VIDEO_CPIA is not set -# CONFIG_VIDEO_SAA5246A is not set -# CONFIG_VIDEO_SAA5249 is not set -CONFIG_SOC_CAMERA=y -# CONFIG_SOC_CAMERA_MT9M001 is not set -# CONFIG_SOC_CAMERA_MT9M111 is not set -# CONFIG_SOC_CAMERA_MT9T031 is not set -# CONFIG_SOC_CAMERA_MT9V022 is not set -# CONFIG_SOC_CAMERA_TW9910 is not set -# CONFIG_SOC_CAMERA_PLATFORM is not set -# CONFIG_SOC_CAMERA_OV772X is not set -CONFIG_SOC_CAMERA_OV2655=y -# CONFIG_SOC_CAMERA_OV3640 is not set -# CONFIG_SOC_CAMERA_OV5642 is not set -# CONFIG_VIDEO_SH_MOBILE_CEU is not set -CONFIG_VIDEO_RK2818=y -CONFIG_RADIO_ADAPTERS=y -# CONFIG_I2C_SI4713 is not set -# CONFIG_RADIO_SI4713 is not set -# CONFIG_RADIO_SI470X is not set -# CONFIG_RADIO_TEA5764 is not set -CONFIG_SMS_SIANO_MDTV=m -# CONFIG_SMS_USB_DRV is not set -# CONFIG_SMS_SDIO_DRV is not set -# CONFIG_DAB is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -CONFIG_VIDEO_OUTPUT_CONTROL=y -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_S1D13XXX is not set -CONFIG_FB_RK2818=y -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -CONFIG_BACKLIGHT_LCD_SUPPORT=y -# CONFIG_LCD_CLASS_DEVICE is not set -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set -CONFIG_BACKLIGHT_RK2818_BL=y - -# -# Display device support -# -CONFIG_DISPLAY_SUPPORT=y - -# -# Display hardware drivers -# -# CONFIG_LCD_NULL is not set -# CONFIG_LCD_TD043MGEA1 is not set -CONFIG_LCD_HX8357=y -# CONFIG_LCD_TJ048NC01CA is not set -# CONFIG_LCD_HL070VM4AU is not set -# CONFIG_LCD_HSD070IDW1 is not set -# CONFIG_LCD_A060SE02 is not set -# CONFIG_LCD_S1D13521 is not set -# CONFIG_LCD_NT35582 is not set -# CONFIG_LCD_NT35580 is not set -CONFIG_TV_NULL=y -CONFIG_HDMI_NULL=y -# CONFIG_HDMI_ANX7150 is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FONTS=y -# CONFIG_FONT_8x8 is not set -CONFIG_FONT_8x16=y -# CONFIG_FONT_6x11 is not set -# CONFIG_FONT_7x14 is not set -# CONFIG_FONT_PEARL_8x8 is not set -# CONFIG_FONT_ACORN_8x8 is not set -# CONFIG_FONT_MINI_4x6 is not set -# CONFIG_FONT_SUN8x16 is not set -# CONFIG_FONT_SUN12x22 is not set -# CONFIG_FONT_10x18 is not set -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_LOGO_LINUX_CLUT224=y -CONFIG_SOUND=y -# CONFIG_SOUND_OSS_CORE is not set -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_JACK=y -# CONFIG_SND_SEQUENCER is not set -# CONFIG_SND_MIXER_OSS is not set -# CONFIG_SND_PCM_OSS is not set -# CONFIG_SND_HRTIMER is not set -# CONFIG_SND_DYNAMIC_MINORS is not set -# CONFIG_SND_SUPPORT_OLD_API is not set -# CONFIG_SND_VERBOSE_PROCFS is not set -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -# CONFIG_SND_RAWMIDI_SEQ is not set -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_ARM is not set -# CONFIG_SND_SPI is not set -CONFIG_SND_SOC=y -CONFIG_SND_ROCKCHIP_SOC=y -CONFIG_SND_ROCKCHIP_SOC_I2S=y -# CONFIG_SND_ROCKCHIP_SOC_WM8988 is not set -CONFIG_SND_ROCKCHIP_SOC_WM8994=y -CONFIG_SND_INSIDE_EARPIECE=y -# CONFIG_SND_OUTSIDE_EARPIECE is not set -# CONFIG_SND_NO_EARPIECE is not set -# CONFIG_SND_BB_NORMAL_INPUT is not set -CONFIG_SND_BB_DIFFERENTIAL_INPUT=y -CONFIG_WM8994_SPEAKER_INCALL_VOL=15 -CONFIG_WM8994_SPEAKER_INCALL_MIC_VOL=15 -CONFIG_WM8994_SPEAKER_NORMAL_VOL=15 -CONFIG_WM8994_EARPIECE_INCALL_VOL=0 -CONFIG_WM8994_HEADSET_INCALL_VOL=-9 -CONFIG_WM8994_HEADSET_INCALL_MIC_VOL=-6 -CONFIG_WM8994_HEADSET_NORMAL_VOL=15 -CONFIG_WM8994_BT_INCALL_VOL=30 -CONFIG_WM8994_BT_INCALL_MIC_VOL=-20 -CONFIG_WM8994_RECORDER_VOL=40 -CONFIG_SND_CODEC_SOC_MASTER=y -# CONFIG_SND_CODEC_SOC_SLAVE is not set -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SOC_ALL_CODECS is not set -CONFIG_SND_SOC_WM8994=y -# CONFIG_SOUND_PRIME is not set -# CONFIG_HID_SUPPORT is not set -CONFIG_HID=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set -# CONFIG_USB is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -# CONFIG_USB_MUSB_HDRC is not set -# CONFIG_USB_GADGET_MUSB_HDRC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -CONFIG_USB_GADGET_VBUS_DRAW=500 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_R8A66597 is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C_HSOTG is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LANGWELL is not set -CONFIG_USB_GADGET_DWC_OTG=y -CONFIG_USB_DWC_OTG=y -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -# CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_ETH is not set -# CONFIG_USB_GADGETFS is not set -# CONFIG_USB_FILE_STORAGE is not set -# CONFIG_USB_G_SERIAL is not set -# CONFIG_USB_MIDI_GADGET is not set -# CONFIG_USB_G_PRINTER is not set -CONFIG_USB_ANDROID=y -# CONFIG_USB_ANDROID_ACM is not set -# CONFIG_USB_ANDROID_ADB is not set -CONFIG_USB_ANDROID_MASS_STORAGE=y -CONFIG_USB_ANDROID_RNDIS=y -CONFIG_USB_ANDROID_RNDIS_WCEIS=y -# CONFIG_USB_CDC_COMPOSITE is not set - -# -# OTG and related infrastructure -# -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set -# CONFIG_RK2818_HOST11 is not set -CONFIG_DWC_OTG=y -# CONFIG_DWC_OTG_DEBUG is not set -# CONFIG_DWC_OTG_HOST_ONLY is not set -CONFIG_DWC_OTG_DEVICE_ONLY=y -# CONFIG_DWC_OTG_BOTH_HOST_SLAVE is not set -# CONFIG_DWC_OTG_NORMAL_PREFERENCE is not set -# CONFIG_DWC_OTG_HOST_PREFERENCE is not set -CONFIG_DWC_OTG_DEVICE_PREFERENCE=y -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set -CONFIG_MMC_EMBEDDED_SDIO=y -# CONFIG_MMC_PARANOID_SD_INIT is not set - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -CONFIG_MMC_BLOCK_DEFERRED_RESUME=y -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -CONFIG_SDMMC_RK2818=y - -# -# Now, there are two SDMMC controllers selected, SDMMC0 and SDMMC1. -# -CONFIG_SDMMC0_RK2818=y -CONFIG_SDMMC1_RK2818=y -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set -# CONFIG_MMC_SPI is not set -# CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set -CONFIG_SWITCH=y -CONFIG_SWITCH_GPIO=y -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -# CONFIG_RTC_INTF_SYSFS is not set -# CONFIG_RTC_INTF_PROC is not set -# CONFIG_RTC_INTF_DEV is not set -CONFIG_RTC_INTF_ALARM=y -CONFIG_RTC_INTF_ALARM_DEV=y -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -# CONFIG_RTC_HYM8563 is not set -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_S35390A is not set -CONFIG_RTC_DRV_S35392A=y -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set - -# -# SPI RTC drivers -# -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_DS3234 is not set -# CONFIG_RTC_DRV_PCF2123 is not set - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set - -# -# TI VLYNQ -# -CONFIG_STAGING=y -# CONFIG_STAGING_EXCLUDE_BUILD is not set -# CONFIG_ECHO is not set - -# -# Android -# -CONFIG_ANDROID=y -CONFIG_ANDROID_BINDER_IPC=y -CONFIG_ANDROID_LOGGER=y -CONFIG_ANDROID_RAM_CONSOLE=y -CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_DATA_SIZE=128 -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_ECC_SIZE=16 -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE=8 -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_POLYNOMIAL=0x11d -# CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT is not set -CONFIG_ANDROID_TIMED_OUTPUT=y -CONFIG_ANDROID_TIMED_GPIO=y -CONFIG_ANDROID_LOW_MEMORY_KILLER=y - -# -# Qualcomm MSM Camera And Video -# - -# -# Camera Sensor Selection -# -# CONFIG_DST is not set -# CONFIG_POHMELFS is not set -# CONFIG_PLAN9AUTH is not set - -# -# RAR Register Driver -# -# CONFIG_RAR_REGISTER is not set -# CONFIG_IIO is not set - -# -# DSP -# -CONFIG_RK2818_DSP=y - -# -# RK1000 control -# -# CONFIG_RK1000_CONTROL is not set - -# -# rk2818 POWER CONTROL -# -CONFIG_RK2818_POWER=y - -# -# CMMB -# -CONFIG_CMMB=y - -# -# Siano module components -# -# CONFIG_SMS_DVB3_SUBSYS is not set -# CONFIG_SMS_DVB5_S2API_SUBSYS is not set -CONFIG_SMS_HOSTLIB_SUBSYS=y -# CONFIG_SMS_NET_SUBSYS is not set -CONFIG_SMS_SPI_ROCKCHIP=y - -# -# File systems -# -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -CONFIG_EXT3_FS_XATTR=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -# CONFIG_EXT4_FS is not set -CONFIG_JBD=y -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y -# CONFIG_XFS_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -# CONFIG_DNOTIFY is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -# CONFIG_MSDOS_FS is not set -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_YAFFS_FS=y -CONFIG_YAFFS_YAFFS1=y -# CONFIG_YAFFS_9BYTE_TAGS is not set -# CONFIG_YAFFS_DOES_ECC is not set -CONFIG_YAFFS_YAFFS2=y -CONFIG_YAFFS_AUTO_YAFFS2=y -# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set -# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set -# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set -CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y -# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_NFS_V4_1=y -CONFIG_ROOT_NFS=y -# CONFIG_NFSD is not set -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -CONFIG_NLS_CODEPAGE_850=y -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -CONFIG_NLS_CODEPAGE_936=y -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -CONFIG_NLS_ISO8859_15=y -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -CONFIG_NLS_UTF8=y -# CONFIG_DLM is not set - -# -# Kernel hacking -# -CONFIG_PRINTK_TIME=y -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -# CONFIG_SCHED_DEBUG is not set -CONFIG_SCHEDSTATS=y -CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_KMEMLEAK is not set -# CONFIG_DEBUG_PREEMPT is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_BUGVERBOSE=y -# CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_TRACING_SUPPORT=y -# CONFIG_FTRACE is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set -CONFIG_DEBUG_ERRORS=y -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_LL is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -CONFIG_CRYPTO_WORKQUEUE=y -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -CONFIG_CRYPTO_ECB=y -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_GHASH is not set -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -CONFIG_CRYPTO_SHA1=y -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_ARC4=y -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -# CONFIG_CRC_T10DIF is not set -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_REED_SOLOMON=y -CONFIG_REED_SOLOMON_ENC8=y -CONFIG_REED_SOLOMON_DEC8=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/arch/arm/configs/rk2818_rahosdk_defconfig b/arch/arm/configs/rk2818_rahosdk_defconfig deleted file mode 100755 index 9a3062419225..000000000000 --- a/arch/arm/configs/rk2818_rahosdk_defconfig +++ /dev/null @@ -1,1745 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.32.9 -# Sun Sep 5 00:43:03 2010 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_HAVE_TCM=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_ARCH_HAS_CPUFREQ=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_LOCK_KERNEL=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -# CONFIG_LOCALVERSION_AUTO is not set -# CONFIG_SWAP is not set -# CONFIG_SYSVIPC is not set -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_IKCONFIG is not set -CONFIG_LOG_BUF_SHIFT=17 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -CONFIG_RT_GROUP_SCHED=y -# CONFIG_USER_SCHED is not set -CONFIG_CGROUP_SCHED=y -CONFIG_CGROUPS=y -CONFIG_CGROUP_DEBUG=y -# CONFIG_CGROUP_NS is not set -CONFIG_CGROUP_FREEZER=y -# CONFIG_CGROUP_DEVICE is not set -# CONFIG_CPUSETS is not set -CONFIG_CGROUP_CPUACCT=y -CONFIG_RESOURCE_COUNTERS=y -# CONFIG_CGROUP_MEM_RES_CTLR is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_PANIC_TIMEOUT=5 -CONFIG_EMBEDDED=y -CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -# CONFIG_ELF_CORE is not set -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_ASHMEM=y -CONFIG_AIO=y - -# -# Kernel Performance Events And Counters -# -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_CLK=y - -# -# GCOV-based kernel profiling -# -# CONFIG_SLOW_WORK is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_BLOCK=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -# CONFIG_IOSCHED_AS is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_FREEZER=y - -# -# System Type -# -CONFIG_MMU=y -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_STMP3XXX is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PC1XX is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_U300 is not set -# CONFIG_ARCH_DAVINCI is not set -# CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_BCMRING is not set -CONFIG_ARCH_RK2818=y - -# -# ROCKCHIP rk2818 Board Type -# -# CONFIG_MACH_RK2818MID is not set -# CONFIG_MACH_RK2818PHONE is not set -CONFIG_MACH_RAHOSDK=y -# CONFIG_MACH_RK2818INFO is not set -CONFIG_RK28_GPIO_IRQ=16 -CONFIG_RK28_ADC=y -CONFIG_RK28_USB_WAKE=y -CONFIG_WIFI_CONTROL_FUNC=y -CONFIG_RK2818_SOC_PM=y - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_ARM926T=y -CONFIG_CPU_32v5=y -CONFIG_CPU_ABRT_EV5TJ=y -CONFIG_CPU_PABRT_LEGACY=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_COPY_V4WB=y -CONFIG_CPU_TLB_V4WBI=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -CONFIG_ARM_THUMB=y -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set -# CONFIG_CPU_CACHE_ROUND_ROBIN is not set -CONFIG_ARM_L1_CACHE_SHIFT=5 -CONFIG_COMMON_CLKDEV=y - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 -# CONFIG_PREEMPT_NONE is not set -# CONFIG_PREEMPT_VOLUNTARY is not set -CONFIG_PREEMPT=y -CONFIG_HZ=100 -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4096 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_UACCESS_WITH_MEMCPY is not set - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_CMDLINE="mem=128M console=ttyS1,115200n8" -# CONFIG_XIP_KERNEL is not set -# CONFIG_KEXEC is not set - -# -# CPU Power Management -# -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_TABLE=y -# CONFIG_CPU_FREQ_DEBUG is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_STAT_DETAILS=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -# CONFIG_CPU_IDLE is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -# CONFIG_VFP is not set - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -CONFIG_HAVE_AOUT=y -# CONFIG_BINFMT_AOUT is not set -# CONFIG_BINFMT_MISC is not set - -# -# Power management options -# -CONFIG_PM=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_SLEEP=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_HAS_WAKELOCK=y -CONFIG_HAS_EARLYSUSPEND=y -CONFIG_WAKELOCK=y -CONFIG_WAKELOCK_STAT=y -CONFIG_USER_WAKELOCK=y -CONFIG_EARLYSUSPEND=y -# CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL is not set -CONFIG_CONSOLE_EARLYSUSPEND=y -# CONFIG_FB_EARLYSUSPEND is not set -# CONFIG_APM_EMULATION is not set -# CONFIG_PM_RUNTIME is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -CONFIG_ANDROID_PARANOID_NETWORK=y -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -CONFIG_BT=y -CONFIG_BT_L2CAP=y -CONFIG_BT_SCO=y -CONFIG_BT_RFCOMM=y -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=y -# CONFIG_BT_BNEP_MC_FILTER is not set -# CONFIG_BT_BNEP_PROTO_FILTER is not set -CONFIG_BT_HIDP=y - -# -# Bluetooth device drivers -# -# CONFIG_BT_HCIBTSDIO is not set -CONFIG_BT_HCIUART=y -CONFIG_BT_HCIUART_H4=y -# CONFIG_BT_HCIUART_BCSP is not set -# CONFIG_BT_HCIUART_LL is not set -# CONFIG_BT_HCIVHCI is not set -# CONFIG_BT_MRVL is not set -# CONFIG_BT_HCIBCM4325 is not set -# CONFIG_AF_RXRPC is not set -CONFIG_WIRELESS=y -# CONFIG_CFG80211 is not set -CONFIG_CFG80211_DEFAULT_PS_VALUE=0 -# CONFIG_WIRELESS_OLD_REGULATORY is not set -CONFIG_WIRELESS_EXT=y -CONFIG_WIRELESS_EXT_SYSFS=y -CONFIG_LIB80211=y -# CONFIG_LIB80211_DEBUG is not set - -# -# CFG80211 needs to be enabled for MAC80211 -# -# CONFIG_WIMAX is not set -CONFIG_RFKILL=y -CONFIG_RFKILL_PM=y -# CONFIG_RFKILL_INPUT is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -# CONFIG_FIRMWARE_IN_KERNEL is not set -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set -# CONFIG_MTD_CONCAT is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set -# CONFIG_MTD_SST25L is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND_IDS=y -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -# CONFIG_MTD_NAND_GPIO is not set -# CONFIG_MTD_NAND_DISKONCHIP is not set -CONFIG_MTD_NAND_RK2818=y -# CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_PLATFORM is not set -# CONFIG_MTD_ONENAND is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -# CONFIG_MTD_UBI is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_MG_DISK is not set -CONFIG_MISC_DEVICES=y -CONFIG_ANDROID_PMEM=y -# CONFIG_ICS932S401 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_KERNEL_DEBUGGER_CORE is not set -# CONFIG_ISL29003 is not set -CONFIG_UID_STAT=y -# CONFIG_WL127X_RFKILL is not set -CONFIG_APANIC=y -CONFIG_APANIC_PLABEL="kpanic" -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_MAX6875 is not set -# CONFIG_EEPROM_93CX6 is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set -# CONFIG_SCSI_DMA is not set -# CONFIG_SCSI_NETLINK is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -# CONFIG_PHYLIB is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_SMC91X is not set -# CONFIG_DM9000 is not set -# CONFIG_DM9000_USE_NAND_CONTROL is not set -# CONFIG_DM9000_USE_NOR_CONTROL is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -# CONFIG_SMC911X is not set -# CONFIG_SMSC911X is not set -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851 is not set -# CONFIG_KS8851_MLL is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -CONFIG_WLAN=y -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set -CONFIG_BCM4329=y -CONFIG_BCM4329_FW_PATH="/etc/firmware/fw_bcm4329.bin" -CONFIG_BCM4329_NVRAM_PATH="/etc/firmware/nvram_bcm4329_B23.txt" - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# -# CONFIG_WAN is not set -CONFIG_PPP=y -# CONFIG_PPP_MULTILINK is not set -# CONFIG_PPP_FILTER is not set -CONFIG_PPP_ASYNC=y -# CONFIG_PPP_SYNC_TTY is not set -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_BSDCOMP=y -CONFIG_PPP_MPPE=y -# CONFIG_PPPOE is not set -# CONFIG_PPPOL2TP is not set -CONFIG_PPPOLAC=y -CONFIG_PPPOPNS=y -# CONFIG_SLIP is not set -CONFIG_SLHC=y -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -CONFIG_INPUT_POLLDEV=y - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set -CONFIG_INPUT_KEYRESET=y - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_QT2160 is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -CONFIG_KEYBOARD_RK28ADC=y -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -CONFIG_INPUT_TOUCHSCREEN=y -# CONFIG_TOUCHSCREEN_ADS7846 is not set -# CONFIG_TOUCHSCREEN_AD7877 is not set -# CONFIG_TOUCHSCREEN_XPT2046_SPI is not set -# CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI is not set -# CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI is not set -CONFIG_TOUCHSCREEN_XPT2046_320X480_CBN_SPI=y -# CONFIG_TOUCHSCREEN_IT7250 is not set -# CONFIG_TOUCHSCREEN_AD7879_I2C is not set -# CONFIG_TOUCHSCREEN_AD7879_SPI is not set -# CONFIG_TOUCHSCREEN_AD7879 is not set -# CONFIG_TOUCHSCREEN_EETI is not set -# CONFIG_TOUCHSCREEN_FUJITSU is not set -# CONFIG_TOUCHSCREEN_GUNZE is not set -# CONFIG_TOUCHSCREEN_ELO is not set -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set -# CONFIG_TOUCHSCREEN_MCS5000 is not set -# CONFIG_TOUCHSCREEN_MTOUCH is not set -# CONFIG_TOUCHSCREEN_INEXIO is not set -# CONFIG_TOUCHSCREEN_MK712 is not set -# CONFIG_TOUCHSCREEN_PENMOUNT is not set -# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set -# CONFIG_TOUCHSCREEN_TSC2007 is not set -# CONFIG_TOUCHSCREEN_W90X900 is not set -CONFIG_INPUT_MISC=y -CONFIG_INPUT_LPSENSOR_CM3602=y -# CONFIG_INPUT_ATI_REMOTE is not set -# CONFIG_INPUT_ATI_REMOTE2 is not set -CONFIG_INPUT_KEYCHORD=y -# CONFIG_INPUT_KEYSPAN_REMOTE is not set -# CONFIG_INPUT_POWERMATE is not set -# CONFIG_INPUT_YEALINK is not set -# CONFIG_INPUT_CM109 is not set -CONFIG_INPUT_UINPUT=y -# CONFIG_INPUT_GPIO is not set -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set -CONFIG_G_SENSOR_DEVICE=y -CONFIG_GS_MMA7660=y - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_DEVMEM=y -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_MAX3100 is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_SERIAL_RK2818=y -CONFIG_UART0_RK2818=y -CONFIG_UART1_RK2818=y -CONFIG_SERIAL_RK2818_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -# CONFIG_DCC_TTY is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -# CONFIG_I2C_CHARDEV is not set -CONFIG_I2C_HELPER_AUTO=y - -# -# I2C Hardware Bus support -# -CONFIG_I2C_RK2818=y - -# -# Now, there are two I2C interfaces selected by developer, I2C0 and I2C1. -# -CONFIG_I2C0_RK2818=y -CONFIG_I2C1_RK2818=y - -# -# Miscellaneous I2C Chip support -# -# CONFIG_DS1682 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_SENSORS_PCA963X is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -CONFIG_SPI_BITBANG=y -CONFIG_SPI_GPIO=y -CONFIG_SPIM_RK2818=y - -# -# SPI Protocol Masters -# -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_TLE62X0 is not set -CONFIG_SPI_FPGA=y -CONFIG_SPI_FPGA_INIT=y -# CONFIG_SPI_FPGA_INIT_DEBUG is not set -CONFIG_SPI_FPGA_UART=y -# CONFIG_SPI_UART_DEBUG is not set -CONFIG_SPI_FPGA_GPIO=y -# CONFIG_SPI_GPIO_DEBUG is not set -CONFIG_SPI_FPGA_I2C=y -# CONFIG_SPI_I2C_DEBUG is not set -CONFIG_SPI_FPGA_DPRAM=y -# CONFIG_SPI_DPRAM_DEBUG is not set -CONFIG_SPI_FPGA_FW=y -CONFIG_HEADSET_DET=y - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -# CONFIG_GPIO_SYSFS is not set - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCF857X is not set - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set -# CONFIG_GPIO_MC33880 is not set - -# -# AC97 GPIO expanders: -# -# CONFIG_GPIO_PCA9554 is not set -# CONFIG_IOEXTEND_TCA6424 is not set -CONFIG_EXPANDED_GPIO_NUM=96 -CONFIG_EXPANDED_GPIO_IRQ_NUM=16 -# CONFIG_EXPAND_GPIO_SOFT_INTERRUPT is not set -CONFIG_SPI_FPGA_GPIO_NUM=96 -CONFIG_SPI_FPGA_GPIO_IRQ_NUM=16 -# CONFIG_W1 is not set -CONFIG_POWER_SUPPLY=y -# CONFIG_POWER_SUPPLY_DEBUG is not set -# CONFIG_PDA_POWER is not set -# CONFIG_BATTERY_DS2760 is not set -# CONFIG_BATTERY_DS2782 is not set -# CONFIG_BATTERY_BQ27x00 is not set -# CONFIG_BATTERY_MAX17040 is not set -CONFIG_BATTERY_RK2818=y -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -# CONFIG_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_MC13783 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_EZX_PCAP is not set -CONFIG_REGULATOR=y -CONFIG_REGULATOR_DEBUG=y -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_REGULATOR_BQ24022 is not set -# CONFIG_REGULATOR_MAX1586 is not set -# CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set -CONFIG_RK2818_REGULATOR_CHARGE=y -CONFIG_RK2818_REGULATOR_LP8725=y -CONFIG_MEDIA_SUPPORT=y - -# -# Multimedia core support -# -CONFIG_VIDEO_DEV=y -CONFIG_VIDEO_V4L2_COMMON=y -CONFIG_VIDEO_ALLOW_V4L1=y -CONFIG_VIDEO_V4L1_COMPAT=y -# CONFIG_DVB_CORE is not set -CONFIG_VIDEO_MEDIA=y - -# -# Multimedia drivers -# -# CONFIG_MEDIA_ATTACH is not set -CONFIG_MEDIA_TUNER=y -# CONFIG_MEDIA_TUNER_CUSTOMISE is not set -CONFIG_MEDIA_TUNER_SIMPLE=y -CONFIG_MEDIA_TUNER_TDA8290=y -CONFIG_MEDIA_TUNER_TDA9887=y -CONFIG_MEDIA_TUNER_TEA5761=y -CONFIG_MEDIA_TUNER_TEA5767=y -CONFIG_MEDIA_TUNER_MT20XX=y -CONFIG_MEDIA_TUNER_XC2028=y -CONFIG_MEDIA_TUNER_XC5000=y -CONFIG_MEDIA_TUNER_MC44S803=y -CONFIG_VIDEO_V4L2=y -CONFIG_VIDEO_V4L1=y -CONFIG_VIDEOBUF_GEN=y -CONFIG_VIDEOBUF_DMA_CONTIG=y -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -CONFIG_VIDEO_HELPER_CHIPS_AUTO=y -# CONFIG_VIDEO_VIVI is not set -# CONFIG_VIDEO_CPIA is not set -# CONFIG_VIDEO_SAA5246A is not set -# CONFIG_VIDEO_SAA5249 is not set -CONFIG_SOC_CAMERA=y -# CONFIG_SOC_CAMERA_MT9M001 is not set -# CONFIG_SOC_CAMERA_MT9M111 is not set -# CONFIG_SOC_CAMERA_MT9T031 is not set -# CONFIG_SOC_CAMERA_MT9V022 is not set -# CONFIG_SOC_CAMERA_TW9910 is not set -# CONFIG_SOC_CAMERA_PLATFORM is not set -# CONFIG_SOC_CAMERA_OV772X is not set -CONFIG_SOC_CAMERA_OV2655=y -# CONFIG_SOC_CAMERA_OV3640 is not set -# CONFIG_SOC_CAMERA_OV5642 is not set -# CONFIG_VIDEO_SH_MOBILE_CEU is not set -CONFIG_VIDEO_RK2818=y -CONFIG_RADIO_ADAPTERS=y -# CONFIG_I2C_SI4713 is not set -# CONFIG_RADIO_SI4713 is not set -# CONFIG_RADIO_SI470X is not set -# CONFIG_RADIO_TEA5764 is not set -CONFIG_SMS_SIANO_MDTV=m -# CONFIG_SMS_USB_DRV is not set -# CONFIG_SMS_SDIO_DRV is not set -# CONFIG_DAB is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -CONFIG_VIDEO_OUTPUT_CONTROL=y -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_S1D13XXX is not set -CONFIG_FB_RK2818=y -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -CONFIG_BACKLIGHT_LCD_SUPPORT=y -# CONFIG_LCD_CLASS_DEVICE is not set -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set -CONFIG_BACKLIGHT_RK2818_BL=y - -# -# Display device support -# -CONFIG_DISPLAY_SUPPORT=y - -# -# Display hardware drivers -# -# CONFIG_LCD_NULL is not set -# CONFIG_LCD_TD043MGEA1 is not set -CONFIG_LCD_HX8357=y -# CONFIG_LCD_TJ048NC01CA is not set -# CONFIG_LCD_HL070VM4AU is not set -# CONFIG_LCD_HSD070IDW1 is not set -# CONFIG_LCD_A060SE02 is not set -# CONFIG_LCD_S1D13521 is not set -# CONFIG_LCD_NT35582 is not set -# CONFIG_LCD_NT35580 is not set -CONFIG_TV_NULL=y -CONFIG_HDMI_NULL=y -# CONFIG_HDMI_ANX7150 is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FONTS=y -# CONFIG_FONT_8x8 is not set -CONFIG_FONT_8x16=y -# CONFIG_FONT_6x11 is not set -# CONFIG_FONT_7x14 is not set -# CONFIG_FONT_PEARL_8x8 is not set -# CONFIG_FONT_ACORN_8x8 is not set -# CONFIG_FONT_MINI_4x6 is not set -# CONFIG_FONT_SUN8x16 is not set -# CONFIG_FONT_SUN12x22 is not set -# CONFIG_FONT_10x18 is not set -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_LOGO_LINUX_CLUT224=y -CONFIG_SOUND=y -# CONFIG_SOUND_OSS_CORE is not set -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_JACK=y -# CONFIG_SND_SEQUENCER is not set -# CONFIG_SND_MIXER_OSS is not set -# CONFIG_SND_PCM_OSS is not set -# CONFIG_SND_HRTIMER is not set -# CONFIG_SND_DYNAMIC_MINORS is not set -# CONFIG_SND_SUPPORT_OLD_API is not set -# CONFIG_SND_VERBOSE_PROCFS is not set -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -# CONFIG_SND_RAWMIDI_SEQ is not set -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_ARM is not set -# CONFIG_SND_SPI is not set -CONFIG_SND_SOC=y -CONFIG_SND_ROCKCHIP_SOC=y -CONFIG_SND_ROCKCHIP_SOC_I2S=y -# CONFIG_SND_ROCKCHIP_SOC_WM8988 is not set -CONFIG_SND_ROCKCHIP_SOC_WM8994=y -CONFIG_SND_INSIDE_EARPIECE=y -# CONFIG_SND_OUTSIDE_EARPIECE is not set -# CONFIG_SND_NO_EARPIECE is not set -# CONFIG_SND_BB_NORMAL_INPUT is not set -CONFIG_SND_BB_DIFFERENTIAL_INPUT=y -CONFIG_WM8994_SPEAKER_INCALL_VOL=15 -CONFIG_WM8994_SPEAKER_INCALL_MIC_VOL=15 -CONFIG_WM8994_SPEAKER_NORMAL_VOL=15 -CONFIG_WM8994_EARPIECE_INCALL_VOL=0 -CONFIG_WM8994_HEADSET_INCALL_VOL=-9 -CONFIG_WM8994_HEADSET_INCALL_MIC_VOL=-6 -CONFIG_WM8994_HEADSET_NORMAL_VOL=15 -CONFIG_WM8994_BT_INCALL_VOL=30 -CONFIG_WM8994_BT_INCALL_MIC_VOL=-20 -CONFIG_WM8994_RECORDER_VOL=40 -CONFIG_SND_CODEC_SOC_MASTER=y -# CONFIG_SND_CODEC_SOC_SLAVE is not set -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SOC_ALL_CODECS is not set -CONFIG_SND_SOC_WM8994=y -# CONFIG_SOUND_PRIME is not set -# CONFIG_HID_SUPPORT is not set -CONFIG_HID=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set -# CONFIG_USB is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -# CONFIG_USB_MUSB_HDRC is not set -# CONFIG_USB_GADGET_MUSB_HDRC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -CONFIG_USB_GADGET_VBUS_DRAW=500 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_R8A66597 is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C_HSOTG is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LANGWELL is not set -CONFIG_USB_GADGET_DWC_OTG=y -CONFIG_USB_DWC_OTG=y -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -# CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_ETH is not set -# CONFIG_USB_GADGETFS is not set -# CONFIG_USB_FILE_STORAGE is not set -# CONFIG_USB_G_SERIAL is not set -# CONFIG_USB_MIDI_GADGET is not set -# CONFIG_USB_G_PRINTER is not set -CONFIG_USB_ANDROID=y -# CONFIG_USB_ANDROID_ACM is not set -# CONFIG_USB_ANDROID_ADB is not set -CONFIG_USB_ANDROID_MASS_STORAGE=y -CONFIG_USB_ANDROID_RNDIS=y -CONFIG_USB_ANDROID_RNDIS_WCEIS=y -# CONFIG_USB_CDC_COMPOSITE is not set - -# -# OTG and related infrastructure -# -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set -# CONFIG_RK2818_HOST11 is not set -CONFIG_DWC_OTG=y -# CONFIG_DWC_OTG_DEBUG is not set -# CONFIG_DWC_OTG_HOST_ONLY is not set -CONFIG_DWC_OTG_DEVICE_ONLY=y -# CONFIG_DWC_OTG_BOTH_HOST_SLAVE is not set -# CONFIG_DWC_OTG_NORMAL_PREFERENCE is not set -# CONFIG_DWC_OTG_HOST_PREFERENCE is not set -CONFIG_DWC_OTG_DEVICE_PREFERENCE=y -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set -CONFIG_MMC_EMBEDDED_SDIO=y -# CONFIG_MMC_PARANOID_SD_INIT is not set - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -CONFIG_MMC_BLOCK_DEFERRED_RESUME=y -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -CONFIG_SDMMC_RK2818=y - -# -# Now, there are two SDMMC controllers selected, SDMMC0 and SDMMC1. -# -CONFIG_SDMMC0_RK2818=y -CONFIG_SDMMC1_RK2818=y -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set -# CONFIG_MMC_SPI is not set -# CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set -CONFIG_SWITCH=y -CONFIG_SWITCH_GPIO=y -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -# CONFIG_RTC_INTF_SYSFS is not set -# CONFIG_RTC_INTF_PROC is not set -# CONFIG_RTC_INTF_DEV is not set -CONFIG_RTC_INTF_ALARM=y -CONFIG_RTC_INTF_ALARM_DEV=y -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -# CONFIG_RTC_HYM8563 is not set -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_S35390A is not set -CONFIG_RTC_DRV_S35392A=y -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set - -# -# SPI RTC drivers -# -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_DS3234 is not set -# CONFIG_RTC_DRV_PCF2123 is not set - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set - -# -# TI VLYNQ -# -CONFIG_STAGING=y -# CONFIG_STAGING_EXCLUDE_BUILD is not set -# CONFIG_ECHO is not set - -# -# Android -# -CONFIG_ANDROID=y -CONFIG_ANDROID_BINDER_IPC=y -CONFIG_ANDROID_LOGGER=y -CONFIG_ANDROID_RAM_CONSOLE=y -CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_DATA_SIZE=128 -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_ECC_SIZE=16 -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE=8 -CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_POLYNOMIAL=0x11d -# CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT is not set -CONFIG_ANDROID_TIMED_OUTPUT=y -CONFIG_ANDROID_TIMED_GPIO=y -CONFIG_ANDROID_LOW_MEMORY_KILLER=y - -# -# Qualcomm MSM Camera And Video -# - -# -# Camera Sensor Selection -# -# CONFIG_DST is not set -# CONFIG_POHMELFS is not set -# CONFIG_PLAN9AUTH is not set - -# -# RAR Register Driver -# -# CONFIG_RAR_REGISTER is not set -# CONFIG_IIO is not set - -# -# DSP -# -CONFIG_RK2818_DSP=y - -# -# RK1000 control -# -# CONFIG_RK1000_CONTROL is not set - -# -# rk2818 POWER CONTROL -# -CONFIG_RK2818_POWER=y - -# -# CMMB -# -CONFIG_CMMB=y - -# -# Siano module components -# -# CONFIG_SMS_DVB3_SUBSYS is not set -# CONFIG_SMS_DVB5_S2API_SUBSYS is not set -CONFIG_SMS_HOSTLIB_SUBSYS=y -# CONFIG_SMS_NET_SUBSYS is not set -CONFIG_SMS_SPI_ROCKCHIP=y - -# -# File systems -# -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -CONFIG_EXT3_FS_XATTR=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -# CONFIG_EXT4_FS is not set -CONFIG_JBD=y -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y -# CONFIG_XFS_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -# CONFIG_DNOTIFY is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -# CONFIG_MSDOS_FS is not set -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_YAFFS_FS=y -CONFIG_YAFFS_YAFFS1=y -# CONFIG_YAFFS_9BYTE_TAGS is not set -# CONFIG_YAFFS_DOES_ECC is not set -CONFIG_YAFFS_YAFFS2=y -CONFIG_YAFFS_AUTO_YAFFS2=y -# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set -# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set -# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set -CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y -# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_NFS_V4_1=y -CONFIG_ROOT_NFS=y -# CONFIG_NFSD is not set -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -CONFIG_NLS_CODEPAGE_850=y -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -CONFIG_NLS_CODEPAGE_936=y -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -CONFIG_NLS_ISO8859_15=y -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -CONFIG_NLS_UTF8=y -# CONFIG_DLM is not set - -# -# Kernel hacking -# -CONFIG_PRINTK_TIME=y -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -# CONFIG_SCHED_DEBUG is not set -CONFIG_SCHEDSTATS=y -CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_KMEMLEAK is not set -# CONFIG_DEBUG_PREEMPT is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_BUGVERBOSE=y -# CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_TRACING_SUPPORT=y -# CONFIG_FTRACE is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set -CONFIG_DEBUG_ERRORS=y -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_LL is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -CONFIG_CRYPTO_WORKQUEUE=y -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -CONFIG_CRYPTO_ECB=y -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_GHASH is not set -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -CONFIG_CRYPTO_SHA1=y -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_ARC4=y -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -# CONFIG_CRC_T10DIF is not set -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_REED_SOLOMON=y -CONFIG_REED_SOLOMON_ENC8=y -CONFIG_REED_SOLOMON_DEC8=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/arch/arm/mach-rk2818/Kconfig b/arch/arm/mach-rk2818/Kconfig deleted file mode 100755 index 696a44cb6d89..000000000000 --- a/arch/arm/mach-rk2818/Kconfig +++ /dev/null @@ -1,74 +0,0 @@ -if ARCH_RK2818 - -comment "ROCKCHIP rk2818 Board Type" - depends on ARCH_RK2818 - -config MACH_RK2818MID - depends on ARCH_RK2818 - default y - bool "ROCKCHIP Board For Mid" - help - Support for the ROCKCHIP Board For Rk2818 Mid. - -config MACH_RK2818PHONE - depends on ARCH_RK2818 - default y - bool "ROCKCHIP Board For PHONE" - help - Support for the ROCKCHIP Board For Rk2818 Phone. - -config MACH_RAHO - depends on ARCH_RK2818 - default n - bool "ROCKCHIP Board For raho" - help - Support for the ROCKCHIP Board For raho Phone. - -config MACH_RAHOSDK - depends on ARCH_RK2818 - default n - bool "ROCKCHIP Board For raho sdk" - help - Support for the ROCKCHIP Board For raho sdk Phone. - -config MACH_RK2818INFO - depends on ARCH_RK2818 - default n - bool "ROCKCHIP Board For Info" - help - Support for the ROCKCHIP Board For Info Telephone. - -config MACH_RK2818INFO_IT50 - depends on ARCH_RK2818 - default n - bool "ROCKCHIP Board For Info It50" - help - Support for the ROCKCHIP Board For Info IT50 Telephone. - -config RK28_GPIO_IRQ - int - default 16 if ARCH_RK2818 - default 0 -config RK28_ADC - tristate "RK28 ADC Driver" - depends on ARCH_RK2818 - default y - ---help--- - RK28 ADC Driver - -config RK28_USB_WAKE - bool "Enable wake-up events for USB ports" - depends on ARCH_RK2818 && PM - default y - help - Select this option if you want to have your system wake up from USB. - This will poll usb every second while suspend, so consumes more power. - -config WIFI_CONTROL_FUNC - bool "Enable WiFi control function abstraction" - help - Enables Power/Reset/Carddetect function abstraction -config RK2818_SOC_PM - bool "Enable soc power manager function" - default n -endif diff --git a/arch/arm/mach-rk2818/Makefile b/arch/arm/mach-rk2818/Makefile deleted file mode 100755 index b61043ae6ffa..000000000000 --- a/arch/arm/mach-rk2818/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -obj-y += irq.o timer.o iomux.o gpio.o -obj-y += devices.o -obj-y += clock.o -obj-$(CONFIG_CPU_FREQ) += cpufreq.o -obj-y += ddr.o -obj-y += dma.o -obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_RK28_ADC) += adc.o -obj-$(CONFIG_MACH_RK2818MID) += board-midsdk.o -obj-$(CONFIG_MACH_RK2818PHONE) += board-phonesdk.o -obj-$(CONFIG_MACH_RAHO) += board-raho.o board-raho-rfkill.o -obj-$(CONFIG_MACH_RAHOSDK) += board-rahosdk.o board-rahosdk-rfkill.o -obj-$(CONFIG_MACH_RK2818INFO) += board-infosdk.o board-infosdk-rfkill.o -obj-$(CONFIG_MACH_RK2818INFO_IT50) += board-infoit50.o board-infoit50-rfkill.o -obj-$(CONFIG_RK2818_SOC_PM) += rk2818-socpm.o diff --git a/arch/arm/mach-rk2818/Makefile.boot b/arch/arm/mach-rk2818/Makefile.boot deleted file mode 100644 index b1c79179d4ee..000000000000 --- a/arch/arm/mach-rk2818/Makefile.boot +++ /dev/null @@ -1,3 +0,0 @@ - zreladdr-y := 0x60408000 -params_phys-y := 0x600f8000 -initrd_phys-y := 0x60800000 diff --git a/arch/arm/mach-rk2818/adc.c b/arch/arm/mach-rk2818/adc.c deleted file mode 100755 index 04fb2563c995..000000000000 --- a/arch/arm/mach-rk2818/adc.c +++ /dev/null @@ -1,527 +0,0 @@ -/* arm/arch/mach-rk2818/adc.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License. -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -/* This driver is designed to control the usage of the ADC block between - * the keyboard and any other drivers that may need to use it. - * - * Priority will be given to the touchscreen driver, but as this itself is - * rate limited it should not starve other requests which are processed in - * order that they are received. - * - * Each user registers to get a client block which uniquely identifies it - * and stores information such as the necessary functions to callback when - * action is required. - */ - -#if 0 -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -struct rk28_adc_client { - struct platform_device *pdev; - struct list_head pend; - wait_queue_head_t *wait; - unsigned int nr_samples; - int result; - unsigned char is_ts; - unsigned char channel; - - void (*select_cb)(struct rk28_adc_client *c, unsigned selected); - void (*convert_cb)(struct rk28_adc_client *c, - unsigned val1, unsigned val2, - unsigned *samples_left); -}; - -struct adc_device { - struct semaphore lock; - struct platform_device *pdev; - struct platform_device *owner; - struct clk *clk; - struct rk28_adc_client *client; - struct rk28_adc_client *cur; - struct rk28_adc_client *ts_pend; - struct workqueue_struct *timer_workqueue; - struct work_struct timer_work; - void __iomem *regs; - struct timer_list timer; - unsigned int pre_con; - int irq; -}; - -static struct adc_device *pAdcDev; -volatile int gAdcChanel = 0; -volatile int gAdcValue[4]={0, 0, 0, 0}; //0->ch0 1->ch1 2->ch2 3->ch3 - -static LIST_HEAD(adc_pending); - -#define adc_dbg(_adc, msg...) dev_dbg(&(_adc)->pdev->dev, msg) - -static inline void rk28_adc_int_enable(struct adc_device *adc) -{ - unsigned con = readl(adc->regs + RK28_ADCCON); - con |= RK28_ADC_INT_ENABLE; - writel(con, adc->regs + RK28_ADCCON); -} - -static inline void rk28_adc_int_disable(struct adc_device *adc) -{ - unsigned con = readl(adc->regs + RK28_ADCCON); - con &= RK28_ADC_INT_DISABLE; - writel(con, adc->regs + RK28_ADCCON); -} - -static inline void rk28_adc_int_clear(struct adc_device *adc) -{ - unsigned con = readl(adc->regs + RK28_ADCCON); - con &= RK28_ADC_INT_CLEAR; - writel(con, adc->regs + RK28_ADCCON); -} - -static inline void rk28_adc_power_up(struct adc_device *adc) -{ - unsigned con = readl(adc->regs + RK28_ADCCON); - con |= RK28_ADC_POWER_UP; - writel(con, adc->regs + RK28_ADCCON); -} - -static inline void rk28_adc_power_down(struct adc_device *adc) -{ - unsigned con = readl(adc->regs + RK28_ADCCON); - con &= RK28_ADC_POWER_DOWN; - writel(con, adc->regs + RK28_ADCCON); -} - -static inline void rk28_adc_convert(struct adc_device *adc) -{ - unsigned con = readl(adc->regs + RK28_ADCCON); - con |= RK28_ADC_POWER_UP | RK28_ADC_CONV_START | RK28_ADC_INT_ENABLE; - writel(con, adc->regs + RK28_ADCCON); -} - -static inline void rk28_adc_select(struct adc_device *adc, - struct rk28_adc_client *client) -{ - unsigned con = readl(adc->regs + RK28_ADCCON); - - client->select_cb(client, 1); - - con &= RK28_ADC_MASK_CH; - con &= RK28_ADC_CONV_STOP; - - if (!client->is_ts) - con |= RK28_ADC_SEL_CH(client->channel); - - writel(con, adc->regs + RK28_ADCCON); -} - -static void rk28_adc_dbgshow(struct adc_device *adc) -{ - adc_dbg(adc, "CON=0x%x, STAS=0x%x, DATA=0x%x\n", - readl(adc->regs + RK28_ADCCON), - readl(adc->regs + RK28_ADCSTAS), - readl(adc->regs + RK28_ADCDAT)); -} - -static void rk28_adc_try(struct adc_device *adc) -{ - struct rk28_adc_client *next = adc->ts_pend; - - if (!next && !list_empty(&adc_pending)) { - next = list_first_entry(&adc_pending, - struct rk28_adc_client, pend); - list_del(&next->pend); - } else - adc->ts_pend = NULL; - - if (next) { - adc_dbg(adc, "new client is %p\n", next); - adc->cur = next; - rk28_adc_select(adc, next); - rk28_adc_convert(adc); - rk28_adc_dbgshow(adc); - } -} - -int rk28_adc_start(struct rk28_adc_client *client, - unsigned int channel, unsigned int nr_samples) -{ - struct adc_device *adc = pAdcDev; - unsigned long flags; - - if (!adc) { - printk(KERN_ERR "%s: failed to find adc\n", __func__); - return -EINVAL; - } - - if (client->is_ts && adc->ts_pend) - return -EAGAIN; - - local_irq_save(flags); - - client->channel = channel; - client->nr_samples = nr_samples; - - if (client->is_ts) - adc->ts_pend = client; - else - list_add_tail(&client->pend, &adc_pending); - - if (!adc->cur) - rk28_adc_try(adc); - local_irq_restore(flags); - - return 0; -} -EXPORT_SYMBOL_GPL(rk28_adc_start); - -static void rk28_convert_done(struct rk28_adc_client *client, - unsigned v, unsigned u, unsigned *left) -{ - client->result = v; - wake_up(client->wait); -} - -int rk28_adc_read(struct rk28_adc_client *client, unsigned int ch) -{ - DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wake); - int ret; - - client->convert_cb = rk28_convert_done; - client->wait = &wake; - client->result = -1; - - ret = rk28_adc_start(client, ch, 1); - if (ret < 0) - goto err; - - ret = wait_event_timeout(wake, client->result >= 0, HZ / 2); - if (client->result < 0) { - ret = -ETIMEDOUT; - goto err; - } - - client->convert_cb = NULL; - return client->result; - -err: - return ret; -} -EXPORT_SYMBOL_GPL(rk28_adc_read); - -static void rk28_adc_default_select(struct rk28_adc_client *client, - unsigned select) -{ -} - -struct rk28_adc_client *rk28_adc_register(struct platform_device *pdev, - void (*select)(struct rk28_adc_client *client, - unsigned int selected), - void (*conv)(struct rk28_adc_client *client, - unsigned d0, unsigned d1, - unsigned *samples_left), - unsigned int is_ts) -{ - struct rk28_adc_client *client; - - WARN_ON(!pdev); - - if (!select) - select = rk28_adc_default_select; - - if (!pdev) - return ERR_PTR(-EINVAL); - - client = kzalloc(sizeof(struct rk28_adc_client), GFP_KERNEL); - if (!client) { - dev_err(&pdev->dev, "no memory for adc client\n"); - return ERR_PTR(-ENOMEM); - } - - client->pdev = pdev; - client->is_ts = is_ts; - client->select_cb = select; - client->convert_cb = conv; - - return client; -} -EXPORT_SYMBOL_GPL(rk28_adc_register); - -void rk28_adc_release(struct rk28_adc_client *client) -{ - /* We should really check that nothing is in progress. */ - if (pAdcDev->cur == client) - pAdcDev->cur = NULL; - if (pAdcDev->ts_pend == client) - pAdcDev->ts_pend = NULL; - else { - struct list_head *p, *n; - struct rk28_adc_client *tmp; - - list_for_each_safe(p, n, &adc_pending) { - tmp = list_entry(p, struct rk28_adc_client, pend); - if (tmp == client) - list_del(&tmp->pend); - } - } - - if (pAdcDev->cur == NULL) - rk28_adc_try(pAdcDev); - kfree(client); -} -EXPORT_SYMBOL_GPL(rk28_adc_release); - - -//read four ADC chanel -static int rk28_read_adc(struct adc_device *adc) -{ - int ret = 0,i; - - ret = down_interruptible(&adc->lock); - if (ret < 0) - return ret; - - for(i=0; i<4; i++) - { - gAdcValue[i] = rk28_adc_read(adc->client, i); - DBG("gAdcValue[%d]=%d\n",i,gAdcValue[i]); - } - - up(&adc->lock); - return ret; -} - -static void adc_timer_work(struct work_struct *work) -{ - rk28_read_adc(pAdcDev); -} - - -static void rk28_adcscan_timer(unsigned long data) -{ - pAdcDev->timer.expires = jiffies + msecs_to_jiffies(30); - add_timer(&pAdcDev->timer); - //schedule_work(&pAdcDev->timer_work); - queue_work(pAdcDev->timer_workqueue, &pAdcDev->timer_work); -} - -static irqreturn_t rk28_adc_irq(int irq, void *pw) -{ - struct adc_device *adc = pw; - struct rk28_adc_client *client = adc->cur; - unsigned long flags; - unsigned data0, data1 = 0; - rk28_adc_int_disable(adc); - rk28_adc_int_clear(adc); - - if (!client) { - dev_warn(&adc->pdev->dev, "%s: no adc pending\n", __func__); - return IRQ_HANDLED; - } - - data0 = readl(adc->regs + RK28_ADCDAT); - - adc_dbg(adc, "read %d: 0x%x\n", client->nr_samples, data0); - - client->nr_samples--; - - if (client->convert_cb) - (client->convert_cb)(client, data0 & 0x3ff, data1 & 0x3ff, - &client->nr_samples); - - if (client->nr_samples > 0) { - /* fire another conversion for this */ - - client->select_cb(client, 1); - rk28_adc_convert(adc); - } else { - local_irq_save(flags); - (client->select_cb)(client, 0); - adc->cur = NULL; - - rk28_adc_try(adc); - local_irq_restore(flags); - } - - return IRQ_HANDLED; -} - -static int rk28_adc_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct adc_device *adc; - struct resource *regs; - int ret; - - adc = kzalloc(sizeof(struct adc_device), GFP_KERNEL); - if (adc == NULL) { - dev_err(dev, "failed to allocate adc_device\n"); - return -ENOMEM; - } - - adc->pdev = pdev; - - adc->irq = platform_get_irq(pdev, 0); - if (adc->irq <= 0) { - dev_err(dev, "failed to get adc irq\n"); - ret = -ENOENT; - goto err_alloc; - } - - ret = request_irq(adc->irq, rk28_adc_irq, 0, dev_name(dev), adc); - if (ret < 0) { - dev_err(dev, "failed to attach adc irq\n"); - goto err_alloc; - } - - adc->clk = clk_get(dev, "lsadc"); - if (IS_ERR(adc->clk)) { - dev_err(dev, "failed to get adc clock\n"); - ret = PTR_ERR(adc->clk); - goto err_irq; - } - - regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!regs) { - dev_err(dev, "failed to find registers\n"); - ret = -ENXIO; - goto err_clk; - } - - adc->regs = ioremap(regs->start, resource_size(regs)); - if (!adc->regs) { - dev_err(dev, "failed to map registers\n"); - ret = -ENXIO; - goto err_clk; - } - - clk_enable(adc->clk); - - dev_info(dev, "attached adc driver\n"); - - platform_set_drvdata(pdev, adc); - - init_MUTEX(&adc->lock); - adc->timer_workqueue = create_freezeable_workqueue("adc timer work"); - if (!adc->timer_workqueue) { - printk("%s:cannot create workqueue\n",__FUNCTION__); - return -EBUSY; - } - INIT_WORK(&adc->timer_work, adc_timer_work); - /* Register with the core ADC driver. */ - adc->client = rk28_adc_register(pdev, NULL, NULL, 0); - if (IS_ERR(adc->client)) { - dev_err(dev, "cannot register adc\n"); - ret = PTR_ERR(adc->client); - goto err_clk; - } - - rk28_adc_int_disable(adc); - pAdcDev = adc; - - setup_timer(&adc->timer, rk28_adcscan_timer, (unsigned long)adc); - adc->timer.expires = jiffies + 50; - add_timer(&adc->timer); - printk(KERN_INFO "rk2818 adc: driver initialized\n"); - return 0; - - err_clk: - clk_put(adc->clk); - - err_irq: - free_irq(adc->irq, adc); - - err_alloc: - kfree(adc); - return ret; -} - -static int rk28_adc_remove(struct platform_device *pdev) -{ - struct adc_device *adc = platform_get_drvdata(pdev); - rk28_adc_power_down(adc); - rk28_adc_release(adc->client); - iounmap(adc->regs); - free_irq(adc->irq, adc); - clk_disable(adc->clk); - clk_put(adc->clk); - kfree(adc); - - return 0; -} - -#ifdef CONFIG_PM -static int rk28_adc_suspend(struct platform_device *pdev, pm_message_t state) -{ - struct adc_device *adc = platform_get_drvdata(pdev); - u32 con; - - con = readl(adc->regs + RK28_ADCCON); - adc->pre_con = con; - con &= RK28_ADC_POWER_DOWN; - writel(con, adc->regs + RK28_ADCCON); - - clk_disable(adc->clk); - - return 0; -} - -static int rk28_adc_resume(struct platform_device *pdev) -{ - struct adc_device *adc = platform_get_drvdata(pdev); - - clk_enable(adc->clk); - - writel(adc->pre_con, adc->regs + RK28_ADCCON); - return 0; -} - -#else -#define rk28_adc_suspend NULL -#define rk28_adc_resume NULL -#endif - -static struct platform_driver rk28_adc_driver = { - .driver = { - .name = "rk2818-adc", - .owner = THIS_MODULE, - }, - .probe = rk28_adc_probe, - .remove = __devexit_p(rk28_adc_remove), - .suspend = rk28_adc_suspend, - .resume = rk28_adc_resume, -}; - -static int __init adc_init(void) -{ - int ret; - - ret = platform_driver_register(&rk28_adc_driver); - if (ret) - printk(KERN_ERR "%s: failed to add adc driver\n", __func__); - return ret; -} - -module_init(adc_init); -MODULE_DESCRIPTION("rk28xx adc driver"); -MODULE_AUTHOR("luowei lw@rock-chips.com"); -MODULE_LICENSE("GPL"); - diff --git a/arch/arm/mach-rk2818/board-infoit50-rfkill.c b/arch/arm/mach-rk2818/board-infoit50-rfkill.c deleted file mode 100755 index e622ccf15e08..000000000000 --- a/arch/arm/mach-rk2818/board-infoit50-rfkill.c +++ /dev/null @@ -1,140 +0,0 @@ -/* linux/arch/arm/mach-rk2818/board-infoit50-rfkill.c - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include - -#define INFOIT50_BT_GPIO_POWER_N TCA6424_P01 -#define INFOIT50_BT_GPIO_RESET_N TCA6424_P14 - -static struct rfkill *bt_rfk; -static const char bt_name[] = "bcm4329"; - -static int bcm4329_set_block(void *data, bool blocked) -{ - pr_info("%s---blocked :%d\n", __func__, blocked); - - if (false == blocked) { - gpio_direction_output(INFOIT50_BT_GPIO_POWER_N, GPIO_HIGH); /* bt power on */ - gpio_direction_output(INFOIT50_BT_GPIO_RESET_N, GPIO_HIGH); /* bt reset deactive */ - mdelay(20); - pr_info("bt turn on power\n"); - }else{ - gpio_direction_output(INFOIT50_BT_GPIO_POWER_N, GPIO_LOW); /* bt power off */ - gpio_direction_output(INFOIT50_BT_GPIO_RESET_N, GPIO_LOW); /* bt reset active */ - mdelay(20); - pr_info("bt shut off power\n"); - } - - return 0; -} - - -static const struct rfkill_ops bcm4329_rfk_ops = { - .set_block = bcm4329_set_block, -}; - -static int bcm4329_rfkill_probe(struct platform_device *pdev) -{ - int rc = 0; - bool default_state = true; - - pr_info("Enter::%s,line=%d\n",__FUNCTION__,__LINE__); - - rc = gpio_request(INFOIT50_BT_GPIO_POWER_N, "bt_shutdown"); - if (rc) - return rc; - rc = gpio_request(INFOIT50_BT_GPIO_RESET_N, "bt_reset"); - if (rc){ - gpio_free(INFOIT50_BT_GPIO_POWER_N); - return rc; - } - - /* default to bluetooth off */ - bcm4329_set_block(NULL, default_state); /* blocked -> bt off */ - - bt_rfk = rfkill_alloc(bt_name, - NULL, - RFKILL_TYPE_BLUETOOTH, - &bcm4329_rfk_ops, - NULL); - - if (!bt_rfk) - { - printk("fail to rfkill_allocate************\n"); - return -ENOMEM; - } - - rfkill_set_states(bt_rfk, default_state, false); - - rc = rfkill_register(bt_rfk); - if (rc) - rfkill_destroy(bt_rfk); - - printk("rc=0x%x\n", rc); - - return rc; -} - - -static int bcm4329_rfkill_remove(struct platform_device *pdev) -{ - if (bt_rfk) - rfkill_unregister(bt_rfk); - rfkill_destroy(bt_rfk); - bt_rfk = NULL; - gpio_free(INFOIT50_BT_GPIO_POWER_N); - gpio_free(INFOIT50_BT_GPIO_RESET_N); - - platform_set_drvdata(pdev, NULL); - pr_info("Enter::%s,line=%d\n",__FUNCTION__,__LINE__); - return 0; -} - -static struct platform_driver bcm4329_rfkill_driver = { - .probe = bcm4329_rfkill_probe, - .remove = bcm4329_rfkill_remove, - .driver = { - .name = "infoit50_rfkill", - .owner = THIS_MODULE, - }, -}; - -/* - * Module initialization - */ -static int __init bcm4329_mod_init(void) -{ - int ret; - pr_info("Enter::%s,line=%d\n",__func__,__LINE__); - ret = platform_driver_register(&bcm4329_rfkill_driver); - printk("ret=0x%x\n", ret); - return ret; -} - -static void __exit bcm4329_mod_exit(void) -{ - platform_driver_unregister(&bcm4329_rfkill_driver); -} - -module_init(bcm4329_mod_init); -module_exit(bcm4329_mod_exit); -MODULE_DESCRIPTION("bcm4329 Bluetooth driver"); -MODULE_AUTHOR("roger_chen cz@rock-chips.com"); -MODULE_LICENSE("GPL"); - diff --git a/arch/arm/mach-rk2818/board-infoit50.c b/arch/arm/mach-rk2818/board-infoit50.c deleted file mode 100644 index ce7a5e443ae5..000000000000 --- a/arch/arm/mach-rk2818/board-infoit50.c +++ /dev/null @@ -1,1448 +0,0 @@ -/* linux/arch/arm/mach-rk2818/board-phonesdk.c - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include /* ddl@rock-chips.com : camera support */ -#include - -#include -#include -#include - -#include /* ddl@rock-chips.com : camera support */ - -#include "devices.h" - -#include "../../../drivers/spi/rk2818_spim.h" -#include "../../../drivers/input/touchscreen/xpt2046_ts.h" -#include "../../../drivers/staging/android/timed_gpio.h" -#include "../../../sound/soc/codecs/wm8994.h" -#include "../../../drivers/headset_observe/rk2818_headset.h" - -/* -------------------------------------------------------------------- - * ÉùÃ÷ÁËrk2818_gpioBankÊý×飬²¢¶¨ÒåÁËGPIO¼Ä´æÆ÷×éIDºÍ¼Ä´æÆ÷»ùµØÖ·¡£ - * -------------------------------------------------------------------- */ - -static struct rk2818_gpio_bank rk2818_gpioBank[] = { - { - .id = RK2818_ID_PIOA, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOB, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOC, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOD, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOE, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOF, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOG, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOH, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - } -}; - -//IOÓ³É䷽ʽÃèÊö £¬Ã¿¸öΪһ¶ÎÏßÐÔÁ¬ÐøÓ³Éä -static struct map_desc rk2818_io_desc[] __initdata = { - - { - .virtual = RK2818_MCDMA_BASE, //ÐéÄâµØÖ· - .pfn = __phys_to_pfn(RK2818_MCDMA_PHYS), //ÎïÀíµØÖ·£¬ÐëÓëÒ³±í¶ÔÆë - .length = RK2818_MCDMA_SIZE, //³¤¶È - .type = MT_DEVICE //Ó³É䷽ʽ - }, - - { - .virtual = RK2818_DWDMA_BASE, - .pfn = __phys_to_pfn(RK2818_DWDMA_PHYS), - .length = RK2818_DWDMA_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_INTC_BASE, - .pfn = __phys_to_pfn(RK2818_INTC_PHYS), - .length = RK2818_INTC_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_NANDC_BASE, - .pfn = __phys_to_pfn(RK2818_NANDC_PHYS), - .length = RK2818_NANDC_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_SDRAMC_BASE, - .pfn = __phys_to_pfn(RK2818_SDRAMC_PHYS), - .length = RK2818_SDRAMC_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_ARMDARBITER_BASE, - .pfn = __phys_to_pfn(RK2818_ARMDARBITER_PHYS), - .length = RK2818_ARMDARBITER_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_APB_BASE, - .pfn = __phys_to_pfn(RK2818_APB_PHYS), - .length = 0xa0000, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_WDT_BASE, - .pfn = __phys_to_pfn(RK2818_WDT_PHYS), - .length = 0xa0000, ///apb bus i2s i2c spi no map in this - .type = MT_DEVICE - }, -}; -/***************************************************************************************** - * SDMMC devices - *author: kfx -*****************************************************************************************/ - -static int rk2818_sdmmc0_io_init(void) -{ - rk2818_mux_api_set(GPIOF3_APWM1_MMC0DETN_NAME, IOMUXA_SDMMC1_DETECT_N); - rk2818_mux_api_set(GPIOH_MMC0D_SEL_NAME, IOMUXA_SDMMC0_DATA123); - rk2818_mux_api_set(GPIOH_MMC0_SEL_NAME, IOMUXA_SDMMC0_CMD_DATA0_CLKOUT); - return 0; -} - -static int rk2818_sdmmc1_io_init(void) -{ - rk2818_mux_api_set(GPIOG_MMC1_SEL_NAME, IOMUXA_SDMMC1_CMD_DATA0_CLKOUT); - rk2818_mux_api_set(GPIOG_MMC1D_SEL_NAME, IOMUXA_SDMMC1_DATA123); - - return 0; -} -#define CONFIG_SDMMC0_USE_DMA -#define CONFIG_SDMMC1_USE_DMA -struct rk2818_sdmmc_platform_data default_sdmmc0_data = { - .host_ocr_avail = (MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30| - MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33| - MMC_VDD_33_34|MMC_VDD_34_35| MMC_VDD_35_36), - .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED), - .io_init = rk2818_sdmmc0_io_init, - .no_detect = 0, - .dma_name = "sd_mmc", -#ifdef CONFIG_SDMMC0_USE_DMA - .use_dma = 1, -#else - .use_dma = 0, -#endif -}; - -static int info_wifi_status(struct device *dev); -static int info_wifi_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id); -struct rk2818_sdmmc_platform_data default_sdmmc1_data = { - .host_ocr_avail = (MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29| - MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32| - MMC_VDD_32_33|MMC_VDD_33_34), - .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_SDIO_IRQ| - MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED), - .io_init = rk2818_sdmmc1_io_init, - .no_detect = 1, - .dma_name = "sdio", -#ifdef CONFIG_SDMMC1_USE_DMA - .use_dma = 1, -#else - .use_dma = 0, -#endif - .status = info_wifi_status, - .register_status_notify = info_wifi_status_register, -}; - -static int info_wifi_cd; /* wifi virtual 'card detect' status */ -static void (*wifi_status_cb)(int card_present, void *dev_id); -static void *wifi_status_cb_devid; - -static int info_wifi_status(struct device *dev) -{ - return info_wifi_cd; -} - -static int info_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id) -{ - if(wifi_status_cb) - return -EAGAIN; - wifi_status_cb = callback; - wifi_status_cb_devid = dev_id; - return 0; -} - -#define INFO_WIFI_GPIO_POWER_N TCA6424_P00 -#define INFO_WIFI_GPIO_RESET_N TCA6424_P00 - -int info_wifi_power_state = 0; -int info_bt_power_state = 0; - -static int info_wifi_power(int on) -{ - pr_info("%s: %d\n", __func__, on); - if (on){ - gpio_set_value(INFO_WIFI_GPIO_POWER_N, on); - mdelay(100); - pr_info("wifi turn on power and reset deactive\n"); - }else{ - gpio_set_value(INFO_WIFI_GPIO_POWER_N, on); - mdelay(100); - pr_info("wifi shut off power and reset active\n"); - - } - - info_wifi_power_state = on; - return 0; -} - -static int info_wifi_reset_state; -static int info_wifi_reset(int on) -{ - pr_info("%s: do nothing\n", __func__); - info_wifi_reset_state = on; - return 0; -} - -static int info_wifi_set_carddetect(int val) -{ - pr_info("%s:%d\n", __func__, val); - info_wifi_cd = val; - if (wifi_status_cb){ - wifi_status_cb(val, wifi_status_cb_devid); - }else { - pr_warning("%s, nobody to notify\n", __func__); - } - return 0; -} - -static struct wifi_platform_data info_wifi_control = { - .set_power = info_wifi_power, - .set_reset = info_wifi_reset, - .set_carddetect = info_wifi_set_carddetect, -}; -static struct platform_device info_wifi_device = { - .name = "bcm4329_wlan", - .id = 1, - .dev = { - .platform_data = &info_wifi_control, - }, -}; - -/* bluetooth rfkill device */ -static struct platform_device info_rfkill = { - .name = "infoit50_rfkill", - .id = -1, -}; - -/***************************************************************************************** - * extern gpio devices - *author: xxx - *****************************************************************************************/ -#if defined (CONFIG_GPIO_PCA9554) -struct rk2818_gpio_expander_info extern_gpio_settinginfo[] = { - { - .gpio_num =RK2818_PIN_PI0, - .pin_type = GPIO_IN, - //.pin_value =GPIO_HIGH, - }, - - { - .gpio_num =RK2818_PIN_PI4,// tp3 - .pin_type = GPIO_IN, - //.pin_value =GPIO_HIGH, - }, - - { - .gpio_num =RK2818_PIN_PI5,//tp4 - .pin_type = GPIO_IN, - //.pin_value =GPIO_HIGH, - }, - { - .gpio_num =RK2818_PIN_PI6,//tp2 - .pin_type = GPIO_OUT, - //.pin_value =GPIO_HIGH, - }, - { - .gpio_num =RK2818_PIN_PI7,//tp1 - .pin_type = GPIO_OUT, - .pin_value =GPIO_HIGH, - }, - - - -}; - -struct pca9554_platform_data rk2818_pca9554_data={ - .gpio_base=GPIO_EXPANDER_BASE, - .gpio_pin_num=CONFIG_EXPANDED_GPIO_NUM, - .gpio_irq_start=NR_AIC_IRQS + 2*NUM_GROUP, - .irq_pin_num=CONFIG_EXPANDED_GPIO_IRQ_NUM, - .pca9954_irq_pin=RK2818_PIN_PE2, - .settinginfo=extern_gpio_settinginfo, - .settinginfolen=ARRAY_SIZE(extern_gpio_settinginfo), -}; -#endif - -#if defined (CONFIG_IOEXTEND_TCA6424) -struct rk2818_gpio_expander_info extgpio_tca6424_settinginfo[] = { - { - .gpio_num = TCA6424_P00, //wifi power and reset together - .pin_type = GPIO_OUT, - .pin_value = GPIO_LOW, - }, - { - .gpio_num = TCA6424_P01, //bt reg on - .pin_type = GPIO_OUT, - .pin_value = GPIO_LOW, - }, - { - .gpio_num = TCA6424_P03, ///sensor power - .pin_type = GPIO_OUT, - .pin_value = GPIO_LOW, - }, - { - .gpio_num = TCA6424_P06, //jog down up left right p06 p07 p10 p11 - .pin_type = GPIO_IN, - //.pin_value = GPIO_LOW, - }, - { - .gpio_num = TCA6424_P07, - .pin_type = GPIO_IN, - //.pin_value = GPIO_LOW, - }, - { - .gpio_num = TCA6424_P10, - .pin_type = GPIO_IN, - //.pin_value = GPIO_LOW, - }, - - { - .gpio_num = TCA6424_P11, - .pin_type = GPIO_IN, - //.pin_value = GPIO_LOW, - }, - - { - .gpio_num = TCA6424_P12,// 3G PowerOn - .pin_type = GPIO_OUT, - .pin_value =GPIO_HIGH, - }, - { - .gpio_num = TCA6424_P14, - .pin_type = GPIO_OUT, - .pin_value = GPIO_LOW, - }, - { - .gpio_num = TCA6424_P17,// 3G reset - .pin_type = GPIO_OUT, - .pin_value =GPIO_HIGH, - }, - { - .gpio_num = TCA6424_P22, //headset_observe - .pin_type = GPIO_IN, - //.pin_value = GPIO_HIGH, - }, - { - .gpio_num = TCA6424_P23, //WM8994 POWER - .pin_type = GPIO_OUT, - .pin_value = GPIO_HIGH, - }, -}; - -void tca6424_reset_itr(void) -{ - rk2818_mux_api_set(GPIOE_U1IR_I2C1_NAME, IOMUXA_GPIO1_A67); - gpio_request(RK2818_PIN_PE6,NULL); - gpio_request(RK2818_PIN_PE7,NULL); - - gpio_direction_output(RK2818_PIN_PE6,GPIO_HIGH); - gpio_direction_output(RK2818_PIN_PE7,GPIO_LOW); - udelay(3); - gpio_set_value(RK2818_PIN_PE7,GPIO_HIGH); - udelay(1); - - gpio_free(RK2818_PIN_PE6); - gpio_free(RK2818_PIN_PE7); - rk2818_mux_api_set(GPIOE_U1IR_I2C1_NAME, IOMUXA_I2C1); -} - -struct tca6424_platform_data rk2818_tca6424_data={ - .gpio_base=GPIO_EXPANDER_BASE, - .gpio_pin_num=CONFIG_EXPANDED_GPIO_NUM, - .gpio_irq_start=NR_AIC_IRQS + 2*NUM_GROUP + CONFIG_SPI_FPGA_GPIO_IRQ_NUM, - .irq_pin_num=CONFIG_EXPANDED_GPIO_IRQ_NUM, - .tca6424_irq_pin=RK2818_PIN_PA1, - .expand_port_group = 3, - .expand_port_pinnum = 8, - .rk_irq_mode = IRQF_TRIGGER_LOW, - .rk_irq_gpio_pull_up_down = GPIOPullUp, - .settinginfo=extgpio_tca6424_settinginfo, - .settinginfolen=ARRAY_SIZE(extgpio_tca6424_settinginfo), - .reseti2cpin = tca6424_reset_itr, -}; -#endif - -/***************************************************************************************** - * gsensor devices -*****************************************************************************************/ -#define GS_IRQ_PIN RK2818_PIN_PE0 - -struct rk2818_gs_platform_data rk2818_gs_platdata = { - .gsensor_irq_pin = GS_IRQ_PIN, - .swap_xy = 1, -}; - -/***************************************************************************************** - * wm8994 codec - * author: cjq@rock-chips.com - *****************************************************************************************/ -static struct wm8994_platform_data wm8994_data = { - .mic_input = 0, - .micBase_vcc = 0, - .bb_input = 0, - .bb_output = 0, - .frequence = 0, - .enable_pin = 0, - .headset_pin = 0, - .headset_call_vol = 0, - .speaker_call_vol = 0, - .earpiece_call_vol = 0, - .bt_call_vol = 0, -};// must initialize - -/***************************************************************************************** - * i2c devices - * author: kfx@rock-chips.com -*****************************************************************************************/ -static int rk2818_i2c0_io_init(void) -{ - rk2818_mux_api_set(GPIOE_I2C0_SEL_NAME, IOMUXA_I2C0); - return 0; -} - -static int rk2818_i2c1_io_init(void) -{ - rk2818_mux_api_set(GPIOE_U1IR_I2C1_NAME, IOMUXA_I2C1); - return 0; -} -struct rk2818_i2c_platform_data default_i2c0_data = { - .bus_num = 0, - .flags = 0, - .slave_addr = 0xff, - .scl_rate = 400*1000, - .mode = I2C_MODE_IRQ, - .io_init = rk2818_i2c0_io_init, -}; -struct rk2818_i2c_platform_data default_i2c1_data = { -#ifdef CONFIG_I2C0_RK2818 - .bus_num = 1, -#else - .bus_num = 0, -#endif - .flags = 0, - .slave_addr = 0xff, - .scl_rate = 400*1000, - .mode = I2C_MODE_POLL, - .io_init = rk2818_i2c1_io_init, -}; - -static struct i2c_board_info __initdata board_i2c0_devices[] = { -#if defined (CONFIG_RK1000_CONTROL) - { - .type = "rk1000_control", - .addr = 0x40, - .flags = 0, - }, -#endif - -#if defined (CONFIG_RK1000_TVOUT) - { - .type = "rk1000_tvout", - .addr = 0x42, - .flags = 0, - }, -#endif -#if defined (CONFIG_SND_SOC_RK1000) - { - .type = "rk1000_i2c_codec", - .addr = 0x60, - .flags = 0, - }, -#endif -#if defined (CONFIG_SND_SOC_WM8988) - { - .type = "wm8988", - .addr = 0x1a, - .flags = 0, - } -#endif -#if defined (CONFIG_SND_SOC_WM8994) - { - .type = "wm8994", - .addr = 0x1a, - .flags = 0, - .platform_data = &wm8994_data, - }, -#endif -}; -static struct i2c_board_info __initdata board_i2c1_devices[] = { -#if defined (CONFIG_RTC_HYM8563) - { - .type = "rtc_hym8563", - .addr = 0x51, - .flags = 0, - .irq = RK2818_PIN_PA4, - }, -#endif -#if defined (CONFIG_FM_QN8006) - { - .type = "fm_qn8006", - .addr = 0x2b, - .flags = 0, - }, -#endif -#if defined (CONFIG_GPIO_PCA9554) - { - .type = "extend_gpio_pca9554", - .addr = 0x3c, - .flags = 0, - .platform_data=&rk2818_pca9554_data.gpio_base, - }, -#endif -#if defined (CONFIG_IOEXTEND_TCA6424) - { - .type = "extend_gpio_tca6424", - .addr = 0x23, - .flags = 0, - .platform_data=&rk2818_tca6424_data.gpio_base, - }, -#endif - -#if defined (CONFIG_RK2818_REGULATOR_LP8725) - { - .type = "lp8725", - .addr = 0x79, - .flags = 0, - .platform_data=&rk2818_lp8725_data, - }, -#endif -#if defined (CONFIG_GS_MMA7660) - { - .type = "gs_mma7660", - .addr = 0x4c, - .flags = 0, - .irq = GS_IRQ_PIN, - .platform_data = &rk2818_gs_platdata, - }, -#endif - {}, -}; - - -/***************************************************************************************** - * camera devices - * author: ddl@rock-chips.com - *****************************************************************************************/ -#ifdef CONFIG_VIDEO_RK2818 -#define SENSOR_NAME_0 RK28_CAM_SENSOR_NAME_OV9650 -#define SENSOR_IIC_ADDR_0 0x60 -#define SENSOR_IIC_ADAPTER_ID_0 1 -#define SENSOR_POWER_PIN_0 TCA6424_P03 -#define SENSOR_RESET_PIN_0 INVALID_GPIO -#define SENSOR_POWERACTIVE_LEVEL_0 RK28_CAM_POWERACTIVE_L -#define SENSOR_RESETACTIVE_LEVEL_0 RK28_CAM_RESETACTIVE_L - - -#define SENSOR_NAME_1 NULL -#define SENSOR_IIC_ADDR_1 0x00 -#define SENSOR_IIC_ADAPTER_ID_1 0xff -#define SENSOR_POWER_PIN_1 INVALID_GPIO -#define SENSOR_RESET_PIN_1 INVALID_GPIO -#define SENSOR_POWERACTIVE_LEVEL_1 RK28_CAM_POWERACTIVE_L -#define SENSOR_RESETACTIVE_LEVEL_1 RK28_CAM_RESETACTIVE_L - -static int rk28_sensor_io_init(void); -static int rk28_sensor_io_deinit(void); - -struct rk28camera_platform_data rk28_camera_platform_data = { - .io_init = rk28_sensor_io_init, - .io_deinit = rk28_sensor_io_deinit, - .gpio_res = { - { - .gpio_reset = SENSOR_RESET_PIN_0, - .gpio_power = SENSOR_POWER_PIN_0, - .gpio_flag = (SENSOR_POWERACTIVE_LEVEL_0|SENSOR_RESETACTIVE_LEVEL_0), - .dev_name = SENSOR_NAME_0, - }, { - .gpio_reset = SENSOR_RESET_PIN_1, - .gpio_power = SENSOR_POWER_PIN_1, - .gpio_flag = (SENSOR_POWERACTIVE_LEVEL_1|SENSOR_RESETACTIVE_LEVEL_1), - .dev_name = SENSOR_NAME_1, - } - } -}; - -static int rk28_sensor_io_init(void) -{ - int ret = 0, i; - unsigned int camera_reset = INVALID_GPIO, camera_power = INVALID_GPIO; - unsigned int camera_ioflag; - //printk("\n%s....%d ******** ddl *********\n",__FUNCTION__,__LINE__); - - for (i=0; i<2; i++) { - camera_reset = rk28_camera_platform_data.gpio_res[i].gpio_reset; - camera_power = rk28_camera_platform_data.gpio_res[i].gpio_power; - camera_ioflag = rk28_camera_platform_data.gpio_res[i].gpio_flag; - - if (camera_power != INVALID_GPIO) { - ret = gpio_request(camera_power, "camera power"); - if (ret) - continue; - gpio_set_value(camera_reset, (((~camera_ioflag)&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - gpio_direction_output(camera_power, (((~camera_ioflag)&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - } - - if (camera_reset != INVALID_GPIO) { - ret = gpio_request(camera_reset, "camera reset"); - if (ret) { - if (camera_power != INVALID_GPIO) - gpio_free(camera_power); - - continue; - } - - gpio_set_value(camera_reset, ((camera_ioflag&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - gpio_direction_output(camera_reset, ((camera_ioflag&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - } - } - - return 0; -} - -static int rk28_sensor_io_deinit(void) -{ - unsigned int i; - unsigned int camera_reset = INVALID_GPIO, camera_power = INVALID_GPIO; - - for (i=0; i<2; i++) { - camera_reset = rk28_camera_platform_data.gpio_res[i].gpio_reset; - camera_power = rk28_camera_platform_data.gpio_res[i].gpio_power; - - if (camera_power != INVALID_GPIO){ - gpio_direction_input(camera_power); - gpio_free(camera_power); - } - - if (camera_reset != INVALID_GPIO) { - gpio_direction_input(camera_reset); - gpio_free(camera_reset); - } - } - - return 0; -} - - -static int rk28_sensor_power(struct device *dev, int on) -{ - unsigned int camera_reset = INVALID_GPIO, camera_power = INVALID_GPIO; - unsigned int camera_ioflag; - - if(rk28_camera_platform_data.gpio_res[0].dev_name && (strcmp(rk28_camera_platform_data.gpio_res[0].dev_name, dev_name(dev)) == 0)) { - camera_reset = rk28_camera_platform_data.gpio_res[0].gpio_reset; - camera_power = rk28_camera_platform_data.gpio_res[0].gpio_power; - camera_ioflag = rk28_camera_platform_data.gpio_res[0].gpio_flag; - } else if (rk28_camera_platform_data.gpio_res[1].dev_name && (strcmp(rk28_camera_platform_data.gpio_res[1].dev_name, dev_name(dev)) == 0)) { - camera_reset = rk28_camera_platform_data.gpio_res[1].gpio_reset; - camera_power = rk28_camera_platform_data.gpio_res[1].gpio_power; - camera_ioflag = rk28_camera_platform_data.gpio_res[1].gpio_flag; - } - - if (camera_reset != INVALID_GPIO) { - gpio_set_value(camera_reset, ((camera_ioflag&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - //printk("\n%s..%s..ResetPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev),camera_reset, ((camera_ioflag&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - } - if (camera_power != INVALID_GPIO) { - if (on) { - gpio_set_value(camera_power, ((camera_ioflag&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - //printk("\n%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev), camera_power, ((camera_ioflag&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - } else { - gpio_set_value(camera_power, (((~camera_ioflag)&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - //printk("\n%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev), camera_power, (((~camera_ioflag)&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - } - } - if (camera_reset != INVALID_GPIO) { - msleep(3); /* delay 3 ms */ - gpio_set_value(camera_reset,(((~camera_ioflag)&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - //printk("\n%s..%s..ResetPin= %d..PinLevel = %x \n",__FUNCTION__,dev_name(dev), camera_reset, (((~camera_ioflag)&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - } - return 0; -} - -static struct i2c_board_info rk2818_i2c_cam_info[] = { - { - I2C_BOARD_INFO(SENSOR_NAME_0, SENSOR_IIC_ADDR_0>>1) - }, -}; - -struct soc_camera_link rk2818_iclink = { - .bus_id = RK28_CAM_PLATFORM_DEV_ID, - .power = rk28_sensor_power, - .board_info = &rk2818_i2c_cam_info[0], - .i2c_adapter_id = SENSOR_IIC_ADAPTER_ID_0, - .module_name = SENSOR_NAME_0, -}; - -/*platform_device : soc-camera need */ -struct platform_device rk2818_soc_camera_pdrv = { - .name = "soc-camera-pdrv", - .id = -1, - .dev = { - .init_name = SENSOR_NAME_0, - .platform_data = &rk2818_iclink, - }, -}; -#endif - -/***************************************************************************************** - * battery devices - * author: lw@rock-chips.com - *****************************************************************************************/ -#define CHARGEOK_PIN TCA6424_P02 -struct rk2818_battery_platform_data rk2818_battery_platdata = { - .charge_ok_pin = CHARGEOK_PIN, - .charge_ok_level = 0, -}; -/***************************************************************************************** - * serial devices - * author: lhh@rock-chips.com - *****************************************************************************************/ -#ifdef CONFIG_UART0_RK2818 -static int serial_io_init(void) -{ - int ret; -#if 1 - //cz@rock-chips.com - //20100808 - //UART0µÄËĸö¹Ü½ÅÏÈIOMUX³ÉGPIO - //È»ºó·Ö±ðÉèÖÃÊäÈëÊä³ö/À­¸ßÀ­µÍ´¦Àí - //×îºóÔÙIOMUX³ÉUART - //·ÀÖ¹Ö±½ÓIOMUX³ÉUARTºóËĸö¹Ü½ÅµÄ״̬²»¶Ôʱ - //²Ù×÷UARTµ¼ÖÂUART_USR_BUSYʼÖÕΪ1Ôì³ÉÈçÏÂËÀÑ­»· - //while(rk2818_uart_read(port,UART_USR)&UART_USR_BUSY) - //UARTËĸö¹Ü½ÅÔÚδ´«ÊäʱÕý³£×´Ì¬Ó¦¸ÃΪ£º - //RX/TX£ºHIGH - //CTS/RTS£ºLOW - //×¢Ò⣺CTS/RTSΪµÍÓÐЧ£¬Ó²¼þÉϲ»Ó¦¸ÃÇ¿ÐÐ×öÉÏÀ­ - rk2818_mux_api_set(GPIOG1_UART0_MMC1WPT_NAME, IOMUXA_GPIO1_C1 /*IOMUXA_UART0_SOUT*/); - rk2818_mux_api_set(GPIOG0_UART0_MMC1DET_NAME, IOMUXA_GPIO1_C0 /*IOMUXA_UART0_SIN*/); - - ret = gpio_request(RK2818_PIN_PG0, NULL); - if(ret != 0) - { - gpio_free(RK2818_PIN_PG0); - } - gpio_direction_output(RK2818_PIN_PG0,GPIO_HIGH); - - - ret = gpio_request(RK2818_PIN_PG1, NULL); - if(ret != 0) - { - gpio_free(RK2818_PIN_PG1); - } - gpio_direction_output(RK2818_PIN_PG1,GPIO_HIGH); - - gpio_pull_updown(RK2818_PIN_PG1,GPIOPullUp); - gpio_pull_updown(RK2818_PIN_PG0,GPIOPullUp); - - rk2818_mux_api_set(GPIOG1_UART0_MMC1WPT_NAME, IOMUXA_UART0_SOUT); - rk2818_mux_api_set(GPIOG0_UART0_MMC1DET_NAME, IOMUXA_UART0_SIN); - - rk2818_mux_api_set(GPIOB2_U0CTSN_SEL_NAME, IOMUXB_GPIO0_B2/*IOMUXB_UART0_CTS_N*/); - rk2818_mux_api_set(GPIOB3_U0RTSN_SEL_NAME, IOMUXB_GPIO0_B3/*IOMUXB_UART0_RTS_N*/); - - ret = gpio_request(RK2818_PIN_PB2, NULL); - if(ret != 0) - { - gpio_free(RK2818_PIN_PB2); - } - gpio_direction_input(RK2818_PIN_PB2); - // gpio_direction_output(RK2818_PIN_PB2,GPIO_LOW); - - ret = gpio_request(RK2818_PIN_PB3, NULL); - if(ret != 0) - { - gpio_free(RK2818_PIN_PB3); - } - gpio_direction_output(RK2818_PIN_PB3,GPIO_LOW); -#endif - - rk2818_mux_api_set(GPIOB2_U0CTSN_SEL_NAME, IOMUXB_UART0_CTS_N); - rk2818_mux_api_set(GPIOB3_U0RTSN_SEL_NAME, IOMUXB_UART0_RTS_N); - - return 0; -} - -struct rk2818_serial_platform_data rk2818_serial0_platdata = { - .io_init = serial_io_init, -}; -#endif -#ifdef CONFIG_UART2_RK2818 -static int serial_io_init2(void) -{ - rk2818_mux_api_set(GPIOF01_UART2_SEL_NAME, IOMUXB_UART2_IN_OUT); - rk2818_mux_api_set(GPIOA23_UART2_SEL_NAME, IOMUXB_UART2_CTS_RTS); - return 0; -} - -struct rk2818_serial_platform_data rk2818_serial2_platdata = { - .io_init = serial_io_init2, -}; -#endif -/***************************************************************************************** - * i2s devices - * author: lhhrock-chips.com - *****************************************************************************************/ -static int i2s_io_init(void) -{ - /* Configure the I2S pins in correct mode */ - rk2818_mux_api_set(CXGPIO_I2S_SEL_NAME,IOMUXB_I2S_INTERFACE); - return 0; -} - -struct rk2818_i2s_platform_data rk2818_i2s_platdata = { - .io_init = i2s_io_init, -}; -/***************************************************************************************** - * spi devices - * author: lhhrock-chips.com - *****************************************************************************************/ -#define SPI_CHIPSELECT_NUM 1 -struct spi_cs_gpio rk2818_spi_cs_gpios[SPI_CHIPSELECT_NUM] = { - { - .name = "spi cs0", - .cs_gpio = RK2818_PIN_PB4, - .cs_iomux_name = GPIOB4_SPI0CS0_MMC0D4_NAME,//if no iomux,set it NULL - .cs_iomux_mode = IOMUXA_GPIO0_B4, - }, -}; - -static int spi_io_init(struct spi_cs_gpio *cs_gpios, int cs_num) -{ - //clk - rk2818_mux_api_set(GPIOB_SPI0_MMC0_NAME, IOMUXA_SPI0); - //cs no cs for tp - return 0; -} - -static int spi_io_deinit(struct spi_cs_gpio *cs_gpios, int cs_num) -{ - rk2818_mux_api_mode_resume(GPIOB_SPI0_MMC0_NAME); - return 0; -} - -struct rk2818_spi_platform_data rk2818_spi_platdata = { - .num_chipselect = SPI_CHIPSELECT_NUM, - .chipselect_gpios = rk2818_spi_cs_gpios, - .io_init = spi_io_init, - .io_deinit = spi_io_deinit, -}; -/***************************************************************************************** - * xpt2046 touch panel - * author: dxjrock-chips.com - *****************************************************************************************/ -#define XPT2046_GPIO_INT RK2818_PIN_PE3 -#define DEBOUNCE_REPTIME 3 - -#if defined(CONFIG_TOUCHSCREEN_XPT2046_SPI) -static struct xpt2046_platform_data xpt2046_info = { - .model = 2046, - .keep_vref_on = 1, - .swap_xy = 1, - .x_min = 0, - .x_max = 800, - .y_min = 0, - .y_max = 480, - .debounce_max = 7, - .debounce_rep = DEBOUNCE_REPTIME, - .debounce_tol = 20, - .gpio_pendown = XPT2046_GPIO_INT, - - .penirq_recheck_delay_usecs = 1, -}; -#elif defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI) -static struct xpt2046_platform_data xpt2046_info = { - .model = 2046, - .keep_vref_on = 1, - .swap_xy = 1, - .x_min = 0, - .x_max = 800, - .y_min = 0, - .y_max = 480, - .debounce_max = 7, - .debounce_rep = DEBOUNCE_REPTIME, - .debounce_tol = 20, - .gpio_pendown = XPT2046_GPIO_INT, - - .penirq_recheck_delay_usecs = 1, -}; -#endif -static struct spi_board_info board_spi_devices[] = { - { - .modalias = "xpt2046_ts", - .chip_select = 0, - .max_speed_hz = 125 * 1000 * 26,/* (max sample rate @ 3V) * (cmd + data + overhead) */ - .bus_num = 0, - .irq = XPT2046_GPIO_INT, - .platform_data = &xpt2046_info, - }, -}; - -/***************************************************************************************** - * lcd devices - * author: zyw@rock-chips.com - *****************************************************************************************/ -//#ifdef CONFIG_LCD_TD043MGEA1 -#define LCD_TXD_PIN RK2818_PIN_PE6 -#define LCD_CLK_PIN RK2818_PIN_PE7 -#define LCD_CS_PIN RK2818_PIN_PH6 -#define LCD_TXD_MUX_NAME GPIOE_U1IR_I2C1_NAME -#define LCD_CLK_MUX_NAME NULL -#define LCD_CS_MUX_NAME GPIOH6_IQ_SEL_NAME -#define LCD_TXD_MUX_MODE 0 -#define LCD_CLK_MUX_MODE 0 -#define LCD_CS_MUX_MODE 0 -//#endif -static int rk2818_lcd_io_init(void) -{ - int ret = 0; - - rk2818_mux_api_set(LCD_CS_MUX_NAME, LCD_CS_MUX_MODE); - if (LCD_CS_PIN != INVALID_GPIO) { - ret = gpio_request(LCD_CS_PIN, NULL); - if(ret != 0) - { - goto err1; - printk(">>>>>> lcd cs gpio_request err \n "); - } - } - - rk2818_mux_api_set(LCD_CLK_MUX_NAME, LCD_CLK_MUX_MODE); - if (LCD_CLK_PIN != INVALID_GPIO) { - ret = gpio_request(LCD_CLK_PIN, NULL); - if(ret != 0) - { - goto err2; - printk(">>>>>> lcd clk gpio_request err \n "); - } - } - - rk2818_mux_api_set(LCD_TXD_MUX_NAME, LCD_TXD_MUX_MODE); - if (LCD_TXD_PIN != INVALID_GPIO) { - ret = gpio_request(LCD_TXD_PIN, NULL); - if(ret != 0) - { - goto err3; - printk(">>>>>> lcd txd gpio_request err \n "); - } - } - - return 0; - -err3: - if (LCD_CLK_PIN != INVALID_GPIO) { - gpio_free(LCD_CLK_PIN); - } -err2: - if (LCD_CS_PIN != INVALID_GPIO) { - gpio_free(LCD_CS_PIN); - } -err1: - return ret; -} - -static int rk2818_lcd_io_deinit(void) -{ - int ret = 0; - - gpio_direction_output(LCD_CLK_PIN, 0); - gpio_set_value(LCD_CLK_PIN, GPIO_HIGH); - gpio_direction_output(LCD_TXD_PIN, 0); - gpio_set_value(LCD_TXD_PIN, GPIO_HIGH); - - gpio_free(LCD_CS_PIN); - rk2818_mux_api_mode_resume(LCD_CS_MUX_NAME); - gpio_free(LCD_CLK_PIN); - gpio_free(LCD_TXD_PIN); - rk2818_mux_api_mode_resume(LCD_TXD_MUX_NAME); - rk2818_mux_api_mode_resume(LCD_CLK_MUX_NAME); - - return ret; -} - -struct rk2818lcd_info rk2818_lcd_info = { - .txd_pin = LCD_TXD_PIN, - .clk_pin = LCD_CLK_PIN, - .cs_pin = LCD_CS_PIN, - .io_init = rk2818_lcd_io_init, - .io_deinit = rk2818_lcd_io_deinit, -}; -/***************************************************************************************** - * frame buffe devices - * author: zyw@rock-chips.com - *****************************************************************************************/ -#define FB_ID 0 -#define FB_DISPLAY_ON_PIN RK2818_PIN_PB4 -#define FB_LCD_STANDBY_PIN INVALID_GPIO -#define FB_MCU_FMK_PIN INVALID_GPIO - -#define FB_DISPLAY_ON_VALUE GPIO_HIGH -#define FB_LCD_STANDBY_VALUE 0 - -#define FB_DISPLAY_ON_MUX_NAME GPIOB4_SPI0CS0_MMC0D4_NAME -#define FB_DISPLAY_ON_MUX_MODE IOMUXA_GPIO0_B4 - -#define FB_LCD_STANDBY_MUX_NAME NULL -#define FB_LCD_STANDBY_MUX_MODE 1 - -#define FB_MCU_FMK_PIN_MUX_NAME NULL -#define FB_MCU_FMK_MUX_MODE 0 - -#define FB_DATA0_16_MUX_NAME GPIOC_LCDC16BIT_SEL_NAME -#define FB_DATA0_16_MUX_MODE 1 - -#define FB_DATA17_18_MUX_NAME GPIOC_LCDC18BIT_SEL_NAME -#define FB_DATA17_18_MUX_MODE 1 - -#define FB_DATA19_24_MUX_NAME GPIOC_LCDC24BIT_SEL_NAME -#define FB_DATA19_24_MUX_MODE 1 - -#define FB_DEN_MUX_NAME CXGPIO_LCDDEN_SEL_NAME -#define FB_DEN_MUX_MODE 1 - -#define FB_VSYNC_MUX_NAME CXGPIO_LCDVSYNC_SEL_NAME -#define FB_VSYNC_MUX_MODE 1 - -#define FB_MCU_FMK_MUX_NAME NULL -#define FB_MCU_FMK_MUX_MODE 0 - -static int rk2818_fb_io_init(struct rk2818_fb_setting_info *fb_setting) -{ - int ret = 0; - if(fb_setting->data_num <=16) - rk2818_mux_api_set(FB_DATA0_16_MUX_NAME, FB_DATA0_16_MUX_MODE); - if(fb_setting->data_num >16 && fb_setting->data_num<=18) - rk2818_mux_api_set(FB_DATA17_18_MUX_NAME, FB_DATA17_18_MUX_MODE); - if(fb_setting->data_num >18) - rk2818_mux_api_set(FB_DATA19_24_MUX_NAME, FB_DATA19_24_MUX_MODE); - - if(fb_setting->vsync_en) - rk2818_mux_api_set(FB_VSYNC_MUX_NAME, FB_VSYNC_MUX_MODE); - - if(fb_setting->den_en) - rk2818_mux_api_set(FB_DEN_MUX_NAME, FB_DEN_MUX_MODE); - - if(fb_setting->mcu_fmk_en && FB_MCU_FMK_MUX_NAME && (FB_MCU_FMK_PIN != INVALID_GPIO)) - { - rk2818_mux_api_set(FB_MCU_FMK_MUX_NAME, FB_MCU_FMK_MUX_MODE); - ret = gpio_request(FB_MCU_FMK_PIN, NULL); - if(ret != 0) - { - gpio_free(FB_MCU_FMK_PIN); - printk(">>>>>> FB_MCU_FMK_PIN gpio_request err \n "); - } - gpio_direction_input(FB_MCU_FMK_PIN); - } - - if(fb_setting->disp_on_en && FB_DISPLAY_ON_MUX_NAME && (FB_DISPLAY_ON_PIN != INVALID_GPIO)) - { - rk2818_mux_api_set(FB_DISPLAY_ON_MUX_NAME, FB_DISPLAY_ON_MUX_MODE); - ret = gpio_request(FB_DISPLAY_ON_PIN, NULL); - if(ret != 0) - { - gpio_free(FB_DISPLAY_ON_PIN); - printk(">>>>>> FB_DISPLAY_ON_PIN gpio_request err \n "); - } - } - - if(fb_setting->disp_on_en && FB_LCD_STANDBY_MUX_NAME && (FB_LCD_STANDBY_PIN != INVALID_GPIO)) - { - rk2818_mux_api_set(FB_LCD_STANDBY_MUX_NAME, FB_LCD_STANDBY_MUX_MODE); - ret = gpio_request(FB_LCD_STANDBY_PIN, NULL); - if(ret != 0) - { - gpio_free(FB_LCD_STANDBY_PIN); - printk(">>>>>> FB_LCD_STANDBY_PIN gpio_request err \n "); - } - } - - return ret; -} - -struct rk2818fb_info rk2818_fb_info = { - .fb_id = FB_ID, - .disp_on_pin = FB_DISPLAY_ON_PIN, - .disp_on_value = FB_DISPLAY_ON_VALUE, - .standby_pin = FB_LCD_STANDBY_PIN, - .standby_value = FB_LCD_STANDBY_VALUE, - .mcu_fmk_pin = FB_MCU_FMK_PIN, - .lcd_info = &rk2818_lcd_info, - .io_init = rk2818_fb_io_init, -}; - -/***************************************************************************************** - * backlight devices - * author: nzy@rock-chips.com - *****************************************************************************************/ - /* - GPIOF2_APWM0_SEL_NAME, IOMUXB_PWM0 - GPIOF3_APWM1_MMC0DETN_NAME, IOMUXA_PWM1 - GPIOF4_APWM2_MMC0WPT_NAME, IOMUXA_PWM2 - GPIOF5_APWM3_DPWM3_NAME, IOMUXB_PWM3 - */ - -#define PWM_ID 0 -#define PWM_MUX_NAME GPIOF2_APWM0_SEL_NAME -#define PWM_MUX_MODE IOMUXB_PWM0 -#define PWM_EFFECT_VALUE 1 - -static int rk2818_backlight_io_init(void) -{ - rk2818_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE); - return 0; -} - -static int rk2818_backlight_io_deinit(void) -{ - rk2818_mux_api_mode_resume(PWM_MUX_NAME); - return 0; -} -struct rk2818_bl_info rk2818_bl_info = { - .pwm_id = PWM_ID, - .bl_ref = PWM_EFFECT_VALUE, - .io_init = rk2818_backlight_io_init, - .io_deinit = rk2818_backlight_io_deinit, -}; - -#ifdef CONFIG_HEADSET_DET -struct rk2818_headset_data rk2818_headset_info = { - .irq = TCA6424_P22, - .irq_type = IRQF_TRIGGER_FALLING|IRQF_TRIGGER_RISING, - .headset_in_type= HEADSET_IN_HIGH, -}; - -struct platform_device rk28_device_headset = { - .name = "rk2818_headsetdet", - .id = 0, - .dev = { - .platform_data = &rk2818_headset_info, - } -}; -#endif - -/***************************************************************************************** - * nand flash devices - * author: hxy@rock-chips.com - *****************************************************************************************/ -/* -GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1 -GPIOA6_FLASHCS2_SEL_NAME, IOMUXB_FLASH_CS2 -GPIOA7_FLASHCS3_SEL_NAME, IOMUXB_FLASH_CS3 -GPIOE_SPI1_FLASH_SEL1_NAME, IOMUXA_FLASH_CS45 -GPIOE_SPI1_FLASH_SEL_NAME, IOMUXA_FLASH_CS67 -*/ - -#define NAND_CS_MAX_NUM 1 /*form 0 to 8, it is 0 when no nand flash */ - -int rk2818_nand_io_init(void) -{ -#if (NAND_CS_MAX_NUM == 2) - rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1); -#elif (NAND_CS_MAX_NUM == 3) - rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1); - rk2818_mux_api_set(GPIOA6_FLASHCS2_SEL_NAME, IOMUXB_FLASH_CS2); -#elif (NAND_CS_MAX_NUM == 4) - rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1); - rk2818_mux_api_set(GPIOA6_FLASHCS2_SEL_NAME, IOMUXB_FLASH_CS2); - rk2818_mux_api_set(GPIOA7_FLASHCS3_SEL_NAME, IOMUXB_FLASH_CS3); -#elif ((NAND_CS_MAX_NUM == 5) || (NAND_CS_MAX_NUM == 6)) - rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1); - rk2818_mux_api_set(GPIOA6_FLASHCS2_SEL_NAME, IOMUXB_FLASH_CS2); - rk2818_mux_api_set(GPIOA7_FLASHCS3_SEL_NAME, IOMUXB_FLASH_CS3); - rk2818_mux_api_set(GPIOE_SPI1_FLASH_SEL1_NAME, IOMUXA_FLASH_CS45); -#elif ((NAND_CS_MAX_NUM == 7) || (NAND_CS_MAX_NUM == 8)) - rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1); - rk2818_mux_api_set(GPIOA6_FLASHCS2_SEL_NAME, IOMUXB_FLASH_CS2); - rk2818_mux_api_set(GPIOA7_FLASHCS3_SEL_NAME, IOMUXB_FLASH_CS3); - rk2818_mux_api_set(GPIOE_SPI1_FLASH_SEL1_NAME, IOMUXA_FLASH_CS45); - rk2818_mux_api_set(GPIOE_SPI1_FLASH_SEL_NAME, IOMUXA_FLASH_CS67); -#endif - return 0; -} - -struct rk2818_nand_platform_data rk2818_nand_data = { - .width = 1, /* data bus width in bytes */ - .hw_ecc = 1, /* hw ecc 0: soft ecc */ - .num_flash = 1, - .io_init = rk2818_nand_io_init, -}; - - -/******************usb***********************/ -struct usb_mass_storage_platform_data mass_storage_pdata = { - .nluns = 2, - .vendor = "RockChip", - .product = "rk2818 sdk", - .release = 0x0100, -}; - - -static struct platform_device *devices[] __initdata = { -#ifdef CONFIG_UART0_RK2818 - &rk2818_device_uart0, -#endif -#ifdef CONFIG_UART1_RK2818 - &rk2818_device_uart1, -#endif -#ifdef CONFIG_UART2_RK2818 - &rk2818_device_uart2, -#endif -#ifdef CONFIG_I2C0_RK2818 - &rk2818_device_i2c0, -#endif -#ifdef CONFIG_I2C1_RK2818 - &rk2818_device_i2c1, -#endif -#ifdef CONFIG_SDMMC0_RK2818 - &rk2818_device_sdmmc0, -#endif -#ifdef CONFIG_SDMMC1_RK2818 - &rk2818_device_sdmmc1, - &info_wifi_device, -#endif - &info_rfkill, - &rk2818_device_spim, - &rk2818_device_i2s, -#if defined(CONFIG_ANDROID_PMEM) - &rk2818_device_pmem, - &rk2818_device_pmem_dsp, -#endif - &rk2818_device_adc, - &rk2818_device_adckey, - &rk2818_device_battery, - &rk2818_device_fb, - &rk2818_device_backlight, - &rk2818_device_dsp, -#ifdef CONFIG_VIDEO_RK2818 - &rk2818_device_camera, /* ddl@rock-chips.com : camera support */ - &rk2818_soc_camera_pdrv, -#endif -#ifdef CONFIG_MTD_NAND_RK2818 - &rk2818_nand_device, -#endif -#ifdef CONFIG_HEADSET_DET - &rk28_device_headset, -#endif -#ifdef CONFIG_INPUT_JOGBALL - &rk2818_jogball_device, -#endif -#ifdef CONFIG_DWC_OTG - &rk2818_device_dwc_otg, -#endif -#ifdef CONFIG_RK2818_HOST11 - &rk2818_device_host11, -#endif -#ifdef CONFIG_USB_ANDROID - &android_usb_device, - &usb_mass_storage_device, -#endif - -}; - -extern struct sys_timer rk2818_timer; -#define POWER_PIN RK2818_PIN_PH7 -static void rk2818_power_on(void) -{ - int ret; - ret = gpio_request(POWER_PIN, NULL); - if (ret) { - printk("failed to request power_off gpio\n"); - goto err_free_gpio; - } - - gpio_pull_updown(POWER_PIN, GPIOPullUp); - ret = gpio_direction_output(POWER_PIN, GPIO_HIGH); - if (ret) { - printk("failed to set power_off gpio output\n"); - goto err_free_gpio; - } - - gpio_set_value(POWER_PIN, 1);/*power on*/ - -err_free_gpio: - gpio_free(POWER_PIN); -} - -static void rk2818_power_off(void) -{ - printk("shut down system now ...\n"); - gpio_set_value(POWER_PIN, 0);/*power down*/ -} - -// adc ---> key -#define PLAY_ON_PIN RK2818_PIN_PE1 -#define PLAY_ON_LEVEL 0 -static ADC_keyst gAdcValueTab[] = -{ - {0, AD2KEY4}, //home AD2KEY1},///VOLUME_DOWN - {118, AD2KEY5}, //back AD2KEY2},///VOLUME_UP - {408, AD2KEY3},///MENU - {510, AD2KEY2}, ///VOLUME_UP AD2KEY4},///HOME - {612, AD2KEY1}, //VOLUME_DOWN AD2KEY5},///BACK - {816, AD2KEY6},///CALL - {221, KEYSTART},///ENTER - {0,0} -}; - -static unsigned char gInitKeyCode[] = -{ - AD2KEY1,AD2KEY2,AD2KEY3,AD2KEY4,AD2KEY5,AD2KEY6, - ENDCALL,KEYSTART,KEY_WAKEUP, -}; - -struct adc_key_data rk2818_adc_key = { - .pin_playon = PLAY_ON_PIN, - .playon_level = PLAY_ON_LEVEL, - .adc_empty = 900, - .adc_invalid = 20, - .adc_drift = 50, - .adc_chn = 1, - .adc_key_table = gAdcValueTab, - .initKeyCode = gInitKeyCode, - .adc_key_cnt = 9, -}; -struct rk2818_adckey_platform_data rk2818_adckey_platdata = { - .adc_key = &rk2818_adc_key, -}; - -struct jgball_data rk2818_jogball = { - .pin_up = TCA6424_P11, - .pin_down = TCA6424_P06, - .pin_left = TCA6424_P10, - .pin_right = TCA6424_P07, -}; -struct rk2818_jogball_paltform_data rk2818_jogball_platdata = { - .jogball_key = &rk2818_jogball, -}; - - -#if CONFIG_ANDROID_TIMED_GPIO -struct timed_gpio_platform_data rk28_vibrator_info = { - .num_gpios = 0, -}; -#endif - -static void __init machine_rk2818_init_irq(void) -{ - rk2818_init_irq(); - rk2818_gpio_init(rk2818_gpioBank, 8); - rk2818_gpio_irq_setup(); -} - -static void __init machine_rk2818_board_init(void) -{ - rk2818_power_on(); - pm_power_off = rk2818_power_off; -#ifdef CONFIG_I2C0_RK2818 - i2c_register_board_info(default_i2c0_data.bus_num, board_i2c0_devices, - ARRAY_SIZE(board_i2c0_devices)); -#endif -#ifdef CONFIG_I2C1_RK2818 - i2c_register_board_info(default_i2c1_data.bus_num, board_i2c1_devices, - ARRAY_SIZE(board_i2c1_devices)); -#endif - platform_add_devices(devices, ARRAY_SIZE(devices)); - spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices)); -} - -static void __init machine_rk2818_mapio(void) -{ - iotable_init(rk2818_io_desc, ARRAY_SIZE(rk2818_io_desc)); - rk2818_clock_init(); - rk2818_iomux_init(); -} - -MACHINE_START(RK2818, "RK28board") - -/* UART for LL DEBUG */ - .phys_io = 0x18002000, - .io_pg_offst = ((0xFF100000) >> 18) & 0xfffc, - .boot_params = RK2818_SDRAM_PHYS + 0x88000, - .map_io = machine_rk2818_mapio, - .init_irq = machine_rk2818_init_irq, - .init_machine = machine_rk2818_board_init, - .timer = &rk2818_timer, -MACHINE_END - diff --git a/arch/arm/mach-rk2818/board-infosdk-rfkill.c b/arch/arm/mach-rk2818/board-infosdk-rfkill.c deleted file mode 100755 index 0debdc24a9d9..000000000000 --- a/arch/arm/mach-rk2818/board-infosdk-rfkill.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (C) 2010 ROCKCHIP, Inc. - * Author: roger_chen - * - * This program is the bluetooth device bcm4329's driver, - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -//#include -//#include -//#include -//#include -#include -#include -#include -#include -#include -#include - -#if 0 -#define DBG(x...) printk(KERN_INFO x) -#else -#define DBG(x...) -#endif - -#ifdef CONFIG_MACH_RK2818INFO_IT50 -#define INFO_BT_GPIO_POWER_N TCA6424_P01 -#define INFO_BT_GPIO_RESET_N TCA6424_P14 -#else -#define INFO_BT_GPIO_POWER_N TCA6424_P25 -#define INFO_BT_GPIO_RESET_N TCA6424_P22 -#endif -static struct rfkill *bt_rfk; -static const char bt_name[] = "bcm4329"; -extern int info_bt_power_state; -extern int info_wifi_power_state; - -static int bcm4329_set_block(void *data, bool blocked) -{ - DBG("%s---blocked :%d\n", __FUNCTION__, blocked); - - if (false == blocked) { - gpio_set_value(INFO_BT_GPIO_POWER_N, GPIO_HIGH); /* bt power on */ - gpio_set_value(INFO_BT_GPIO_RESET_N, GPIO_HIGH); /* bt reset deactive*/ - mdelay(20); - pr_info("bt turn on power\n"); - } - else { - if (!info_wifi_power_state) { - gpio_set_value(INFO_BT_GPIO_POWER_N, GPIO_LOW); /* bt power off */ - mdelay(20); - pr_info("bt shut off power\n"); - }else { - pr_info("bt shouldn't shut off power, wifi is using it!\n"); - } - - gpio_set_value(INFO_BT_GPIO_RESET_N, GPIO_LOW); /* bt reset active*/ - mdelay(20); - } - - info_bt_power_state = !blocked; - return 0; -} - - -static const struct rfkill_ops bcm4329_rfk_ops = { - .set_block = bcm4329_set_block, -}; - -static int __init bcm4329_rfkill_probe(struct platform_device *pdev) -{ - int rc = 0; - - DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__); - - /* default to bluetooth off */ -// rfkill_switch_all(RFKILL_TYPE_BLUETOOTH, true); - - bt_rfk = rfkill_alloc(bt_name, - NULL, - RFKILL_TYPE_BLUETOOTH, - &bcm4329_rfk_ops, - NULL); - - if (!bt_rfk) - { - printk("fail to rfkill_allocate************\n"); - return -ENOMEM; - } - - rc = rfkill_register(bt_rfk); - if (rc) - rfkill_destroy(bt_rfk); - - printk("rc=0x%x\n", rc); - - return rc; -} - - -static int __devexit bcm4329_rfkill_remove(struct platform_device *pdev) -{ - if (bt_rfk) - rfkill_unregister(bt_rfk); - bt_rfk = NULL; - - platform_set_drvdata(pdev, NULL); - DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__); - return 0; -} - -static struct platform_driver bcm4329_rfkill_driver = { - .probe = bcm4329_rfkill_probe, - .remove = __devexit_p(bcm4329_rfkill_remove), - .driver = { - .name = "info_rfkill", - .owner = THIS_MODULE, - }, -}; - -/* - * Module initialization - */ -static int __init bcm4329_mod_init(void) -{ - int ret; - DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__); - ret = platform_driver_register(&bcm4329_rfkill_driver); - printk("ret=0x%x\n", ret); - return ret; -} - -static void __exit bcm4329_mod_exit(void) -{ - platform_driver_unregister(&bcm4329_rfkill_driver); -} - -module_init(bcm4329_mod_init); -module_exit(bcm4329_mod_exit); -MODULE_DESCRIPTION("bcm4329 Bluetooth driver"); -MODULE_AUTHOR("roger_chen cz@rock-chips.com"); -MODULE_LICENSE("GPL"); - diff --git a/arch/arm/mach-rk2818/board-infosdk.c b/arch/arm/mach-rk2818/board-infosdk.c deleted file mode 100644 index 498610720a97..000000000000 --- a/arch/arm/mach-rk2818/board-infosdk.c +++ /dev/null @@ -1,1727 +0,0 @@ -/* linux/arch/arm/mach-rk2818/board-phonesdk.c - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include /* ddl@rock-chips.com : camera support */ -#include - -#include -#include -#include - -#include /* ddl@rock-chips.com : camera support */ - -#include "devices.h" - -#include - - -#include "../../../drivers/spi/rk2818_spim.h" -#include "../../../drivers/input/touchscreen/xpt2046_ts.h" -#include "../../../drivers/staging/android/timed_gpio.h" -#include "../../../sound/soc/codecs/wm8994.h" -#include "../../../drivers/headset_observe/rk2818_headset.h" - -/* -------------------------------------------------------------------- - * ÉùÃ÷ÁËrk2818_gpioBankÊý×飬²¢¶¨ÒåÁËGPIO¼Ä´æÆ÷×éIDºÍ¼Ä´æÆ÷»ùµØÖ·¡£ - * -------------------------------------------------------------------- */ - -static struct rk2818_gpio_bank rk2818_gpioBank[] = { - { - .id = RK2818_ID_PIOA, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOB, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOC, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOD, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOE, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOF, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOG, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOH, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - } -}; - -//IOÓ³É䷽ʽÃèÊö £¬Ã¿¸öΪһ¶ÎÏßÐÔÁ¬ÐøÓ³Éä -static struct map_desc rk2818_io_desc[] __initdata = { - - { - .virtual = RK2818_MCDMA_BASE, //ÐéÄâµØÖ· - .pfn = __phys_to_pfn(RK2818_MCDMA_PHYS), //ÎïÀíµØÖ·£¬ÐëÓëÒ³±í¶ÔÆë - .length = RK2818_MCDMA_SIZE, //³¤¶È - .type = MT_DEVICE //Ó³É䷽ʽ - }, - - { - .virtual = RK2818_DWDMA_BASE, - .pfn = __phys_to_pfn(RK2818_DWDMA_PHYS), - .length = RK2818_DWDMA_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_INTC_BASE, - .pfn = __phys_to_pfn(RK2818_INTC_PHYS), - .length = RK2818_INTC_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_NANDC_BASE, - .pfn = __phys_to_pfn(RK2818_NANDC_PHYS), - .length = RK2818_NANDC_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_SDRAMC_BASE, - .pfn = __phys_to_pfn(RK2818_SDRAMC_PHYS), - .length = RK2818_SDRAMC_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_ARMDARBITER_BASE, - .pfn = __phys_to_pfn(RK2818_ARMDARBITER_PHYS), - .length = RK2818_ARMDARBITER_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_APB_BASE, - .pfn = __phys_to_pfn(RK2818_APB_PHYS), - .length = 0xa0000, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_WDT_BASE, - .pfn = __phys_to_pfn(RK2818_WDT_PHYS), - .length = 0xa0000, ///apb bus i2s i2c spi no map in this - .type = MT_DEVICE - }, -}; -/***************************************************************************************** - * SDMMC devices - *author: kfx -*****************************************************************************************/ - -static int rk2818_sdmmc0_io_init(void) -{ - rk2818_mux_api_set(GPIOF3_APWM1_MMC0DETN_NAME, IOMUXA_SDMMC1_DETECT_N); - rk2818_mux_api_set(GPIOH_MMC0D_SEL_NAME, IOMUXA_SDMMC0_DATA123); - rk2818_mux_api_set(GPIOH_MMC0_SEL_NAME, IOMUXA_SDMMC0_CMD_DATA0_CLKOUT); - return 0; -} - -static int rk2818_sdmmc1_io_init(void) -{ - rk2818_mux_api_set(GPIOG_MMC1_SEL_NAME, IOMUXA_SDMMC1_CMD_DATA0_CLKOUT); - rk2818_mux_api_set(GPIOG_MMC1D_SEL_NAME, IOMUXA_SDMMC1_DATA123); - - return 0; -} -#define CONFIG_SDMMC0_USE_DMA -#define CONFIG_SDMMC1_USE_DMA -struct rk2818_sdmmc_platform_data default_sdmmc0_data = { - .host_ocr_avail = (MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30| - MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33| - MMC_VDD_33_34|MMC_VDD_34_35| MMC_VDD_35_36), - .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED), - .io_init = rk2818_sdmmc0_io_init, - .no_detect = 0, - .dma_name = "sd_mmc", -#ifdef CONFIG_SDMMC0_USE_DMA - .use_dma = 1, -#else - .use_dma = 0, -#endif -}; - -static int info_wifi_status(struct device *dev); -static int info_wifi_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id); -struct rk2818_sdmmc_platform_data default_sdmmc1_data = { - .host_ocr_avail = (MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29| - MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32| - MMC_VDD_32_33|MMC_VDD_33_34), - .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_SDIO_IRQ| - MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED), - .io_init = rk2818_sdmmc1_io_init, - .no_detect = 1, - .dma_name = "sdio", -#ifdef CONFIG_SDMMC1_USE_DMA - .use_dma = 1, -#else - .use_dma = 0, -#endif - .status = info_wifi_status, - .register_status_notify = info_wifi_status_register, -}; - -static int info_wifi_cd; /* wifi virtual 'card detect' status */ -static void (*wifi_status_cb)(int card_present, void *dev_id); -static void *wifi_status_cb_devid; - -static int info_wifi_status(struct device *dev) -{ - return info_wifi_cd; -} - -static int info_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id) -{ - if(wifi_status_cb) - return -EAGAIN; - wifi_status_cb = callback; - wifi_status_cb_devid = dev_id; - return 0; -} - -#define INFO_WIFI_GPIO_POWER_N TCA6424_P25 -#define INFO_WIFI_GPIO_RESET_N TCA6424_P27 - -int info_wifi_power_state = 0; -int info_bt_power_state = 0; - -static int info_wifi_power(int on) -{ - pr_info("%s: %d\n", __func__, on); - if (on){ - gpio_set_value(INFO_WIFI_GPIO_POWER_N, on); - mdelay(100); - pr_info("wifi turn on power\n"); - }else{ - if (!info_bt_power_state){ - gpio_set_value(INFO_WIFI_GPIO_POWER_N, on); - mdelay(100); - pr_info("wifi shut off power\n"); - }else - { - pr_info("wifi shouldn't shut off power, bt is using it!\n"); - } - - } - - info_wifi_power_state = on; - return 0; -} - -static int info_wifi_reset_state; -static int info_wifi_reset(int on) -{ - pr_info("%s: %d\n", __func__, on); - gpio_set_value(INFO_WIFI_GPIO_RESET_N, on); - mdelay(100); - info_wifi_reset_state = on; - return 0; -} - -static int info_wifi_set_carddetect(int val) -{ - pr_info("%s:%d\n", __func__, val); - info_wifi_cd = val; - if (wifi_status_cb){ - wifi_status_cb(val, wifi_status_cb_devid); - }else { - pr_warning("%s, nobody to notify\n", __func__); - } - return 0; -} - -static struct wifi_platform_data info_wifi_control = { - .set_power = info_wifi_power, - .set_reset = info_wifi_reset, - .set_carddetect = info_wifi_set_carddetect, -}; -static struct platform_device info_wifi_device = { - .name = "bcm4329_wlan", - .id = 1, - .dev = { - .platform_data = &info_wifi_control, - }, -}; - -/* bluetooth rfkill device */ -static struct platform_device info_rfkill = { - .name = "info_rfkill", - .id = -1, -}; - -/***************************************************************************************** - * extern gpio devices - *author: xxx - *****************************************************************************************/ -#if defined (CONFIG_GPIO_PCA9554) -struct rk2818_gpio_expander_info extern_gpio_settinginfo[] = { - { - .gpio_num =RK2818_PIN_PI0, - .pin_type = GPIO_IN, - //.pin_value =GPIO_HIGH, - }, - - { - .gpio_num =RK2818_PIN_PI4,// tp3 - .pin_type = GPIO_IN, - //.pin_value =GPIO_HIGH, - }, - - { - .gpio_num =RK2818_PIN_PI5,//tp4 - .pin_type = GPIO_IN, - //.pin_value =GPIO_HIGH, - }, - { - .gpio_num =RK2818_PIN_PI6,//tp2 - .pin_type = GPIO_OUT, - //.pin_value =GPIO_HIGH, - }, - { - .gpio_num =RK2818_PIN_PI7,//tp1 - .pin_type = GPIO_OUT, - .pin_value =GPIO_HIGH, - }, - - - -}; - -struct pca9554_platform_data rk2818_pca9554_data={ - .gpio_base=GPIO_EXPANDER_BASE, - .gpio_pin_num=CONFIG_EXPANDED_GPIO_NUM, - .gpio_irq_start=NR_AIC_IRQS + 2*NUM_GROUP, - .irq_pin_num=CONFIG_EXPANDED_GPIO_IRQ_NUM, - .pca9954_irq_pin=RK2818_PIN_PE2, - .settinginfo=extern_gpio_settinginfo, - .settinginfolen=ARRAY_SIZE(extern_gpio_settinginfo), -}; -#endif - -#if defined (CONFIG_IOEXTEND_TCA6424) -struct rk2818_gpio_expander_info extgpio_tca6424_settinginfo[] = { - - { - .gpio_num = TCA6424_P01, - .pin_type = GPIO_OUT, - .pin_value = GPIO_LOW, - }, - - { - .gpio_num = TCA6424_P02,// tp3 - .pin_type = GPIO_OUT, - .pin_value = GPIO_LOW, - }, - { - .gpio_num = TCA6424_P03, - .pin_type = GPIO_OUT, - .pin_value = GPIO_LOW, - }, - - { - .gpio_num = TCA6424_P04,// tp3 - .pin_type = GPIO_OUT, - .pin_value = GPIO_LOW, - }, - { - .gpio_num = TCA6424_P05, - .pin_type = GPIO_OUT, - .pin_value = GPIO_LOW, - }, - { - .gpio_num = TCA6424_P11, - .pin_type = GPIO_OUT, - .pin_value = GPIO_HIGH, - }, - { - .gpio_num = TCA6424_P12, - .pin_type = GPIO_IN, - //.pin_value =GPIO_HIGH, - }, - - { - .gpio_num = TCA6424_P13,// tp3 - .pin_type = GPIO_IN, - //.pin_value =GPIO_HIGH, - }, - { - .gpio_num = TCA6424_P14, - .pin_type = GPIO_IN, - //.pin_value =GPIO_HIGH, - }, - - { - .gpio_num = TCA6424_P15,// tp3 - .pin_type = GPIO_IN, - //.pin_value =GPIO_HIGH, - }, - { - .gpio_num = TCA6424_P17,// 3G PowerOn - .pin_type = GPIO_OUT, - .pin_value =GPIO_HIGH, - }, - { - .gpio_num = TCA6424_P25, //wifi reg on - .pin_type = GPIO_OUT, - .pin_value = GPIO_LOW, - }, - { - .gpio_num = TCA6424_P27, //wifi reset - .pin_type = GPIO_OUT, - .pin_value = GPIO_LOW, - }, -}; - -void tca6424_reset_itr(void) -{ - rk2818_mux_api_set(GPIOE_U1IR_I2C1_NAME, IOMUXA_GPIO1_A67); - gpio_request(RK2818_PIN_PE6,NULL); - gpio_request(RK2818_PIN_PE7,NULL); - - gpio_direction_output(RK2818_PIN_PE6,GPIO_HIGH); - gpio_direction_output(RK2818_PIN_PE7,GPIO_LOW); - udelay(3); - gpio_set_value(RK2818_PIN_PE7,GPIO_HIGH); - udelay(1); - - gpio_free(RK2818_PIN_PE6); - gpio_free(RK2818_PIN_PE7); - rk2818_mux_api_set(GPIOE_U1IR_I2C1_NAME, IOMUXA_I2C1); -} - -struct tca6424_platform_data rk2818_tca6424_data={ - .gpio_base=GPIO_EXPANDER_BASE, - .gpio_pin_num=CONFIG_EXPANDED_GPIO_NUM, - .gpio_irq_start=NR_AIC_IRQS + 2*NUM_GROUP + CONFIG_SPI_FPGA_GPIO_IRQ_NUM, - .irq_pin_num=CONFIG_EXPANDED_GPIO_IRQ_NUM, - .tca6424_irq_pin=RK2818_PIN_PA1, - .expand_port_group = 3, - .expand_port_pinnum = 8, - .rk_irq_mode = IRQF_TRIGGER_LOW, - .rk_irq_gpio_pull_up_down = GPIOPullUp, - .settinginfo=extgpio_tca6424_settinginfo, - .settinginfolen=ARRAY_SIZE(extgpio_tca6424_settinginfo), - .reseti2cpin = tca6424_reset_itr, -}; -#endif - -/***************************************************************************************** - * gsensor devices -*****************************************************************************************/ -#define GS_IRQ_PIN RK2818_PIN_PE0 - -struct rk2818_gs_platform_data rk2818_gs_platdata = { - .gsensor_irq_pin = GS_IRQ_PIN, - .swap_xy = 0, -}; - -/***************************************************************************************** - * wm8994 codec - * author: cjq@rock-chips.com - *****************************************************************************************/ -static struct wm8994_platform_data wm8994_data = { - .mic_input = 0, - .micBase_vcc = 0, - .bb_input = 0, - .bb_output = 0, - .frequence = 0, - .enable_pin = 0, - .headset_pin = 0, - .headset_call_vol = 0, - .speaker_call_vol = 0, - .earpiece_call_vol = 0, - .bt_call_vol = 0, -};// must initialize - -/***************************************************************************************** - * i2c devices - * author: kfx@rock-chips.com -*****************************************************************************************/ -static int rk2818_i2c0_io_init(void) -{ - rk2818_mux_api_set(GPIOE_I2C0_SEL_NAME, IOMUXA_I2C0); - return 0; -} - -static int rk2818_i2c1_io_init(void) -{ - rk2818_mux_api_set(GPIOE_U1IR_I2C1_NAME, IOMUXA_I2C1); - return 0; -} -struct rk2818_i2c_platform_data default_i2c0_data = { - .bus_num = 0, - .flags = 0, - .slave_addr = 0xff, - .scl_rate = 400*1000, - .mode = I2C_MODE_IRQ, - .io_init = rk2818_i2c0_io_init, -}; -struct rk2818_i2c_platform_data default_i2c1_data = { -#ifdef CONFIG_I2C0_RK2818 - .bus_num = 1, -#else - .bus_num = 0, -#endif - .flags = 0, - .slave_addr = 0xff, - .scl_rate = 400*1000, - .mode = I2C_MODE_POLL, - .io_init = rk2818_i2c1_io_init, -}; - -struct rk2818_i2c_spi_data default_i2c2_data = { - .bus_num = 2, - .flags = 0, - .slave_addr = 0xff, - .scl_rate = 400*1000, - -}; -struct rk2818_i2c_spi_data default_i2c3_data = { - - .bus_num = 3, - .flags = 0, - .slave_addr = 0xff, - .scl_rate = 400*1000, - -}; -static struct i2c_board_info __initdata board_i2c0_devices[] = { -#if defined (CONFIG_RK1000_CONTROL) - { - .type = "rk1000_control", - .addr = 0x40, - .flags = 0, - }, -#endif - -#if defined (CONFIG_RK1000_TVOUT) - { - .type = "rk1000_tvout", - .addr = 0x42, - .flags = 0, - }, -#endif -#if defined (CONFIG_SND_SOC_RK1000) - { - .type = "rk1000_i2c_codec", - .addr = 0x60, - .flags = 0, - }, -#endif -#if defined (CONFIG_SND_SOC_WM8988) - { - .type = "wm8988", - .addr = 0x1a, - .flags = 0, - } -#endif -#if defined (CONFIG_SND_SOC_WM8994) - { - .type = "wm8994", - .addr = 0x1a, - .flags = 0, - .platform_data = &wm8994_data, - }, -#endif -}; -static struct i2c_board_info __initdata board_i2c1_devices[] = { -#if defined (CONFIG_RTC_HYM8563) - { - .type = "rtc_hym8563", - .addr = 0x51, - .flags = 0, - }, -#endif -#if defined (CONFIG_FM_QN8006) - { - .type = "fm_qn8006", - .addr = 0x2b, - .flags = 0, - }, -#endif -#if defined (CONFIG_GPIO_PCA9554) - { - .type = "extend_gpio_pca9554", - .addr = 0x3c, - .flags = 0, - .platform_data=&rk2818_pca9554_data.gpio_base, - }, -#endif -#if defined (CONFIG_IOEXTEND_TCA6424) - { - .type = "extend_gpio_tca6424", - .addr = 0x23, - .flags = 0, - .platform_data=&rk2818_tca6424_data.gpio_base, - }, -#endif - -#if defined (CONFIG_RK2818_REGULATOR_LP8725) - { - .type = "lp8725", - .addr = 0x79, - .flags = 0, - .platform_data=&rk2818_lp8725_data, - }, -#endif -#if defined (CONFIG_GS_MMA7660) - { - .type = "gs_mma7660", - .addr = 0x4c, - .flags = 0, - .irq = GS_IRQ_PIN, - .platform_data = &rk2818_gs_platdata, - }, -#endif - {}, -}; - - -/***************************************************************************************** - * camera devices - * author: ddl@rock-chips.com - *****************************************************************************************/ -#ifdef CONFIG_VIDEO_RK2818 -#define SENSOR_NAME_0 RK28_CAM_SENSOR_NAME_OV2655 -#define SENSOR_IIC_ADDR_0 0x60 -#define SENSOR_IIC_ADAPTER_ID_0 1 -#define SENSOR_POWER_PIN_0 TCA6424_P16 -#define SENSOR_RESET_PIN_0 INVALID_GPIO -#define SENSOR_POWERACTIVE_LEVEL_0 RK28_CAM_POWERACTIVE_L -#define SENSOR_RESETACTIVE_LEVEL_0 RK28_CAM_RESETACTIVE_L - - -#define SENSOR_NAME_1 NULL -#define SENSOR_IIC_ADDR_1 0x00 -#define SENSOR_IIC_ADAPTER_ID_1 0xff -#define SENSOR_POWER_PIN_1 INVALID_GPIO -#define SENSOR_RESET_PIN_1 INVALID_GPIO -#define SENSOR_POWERACTIVE_LEVEL_1 RK28_CAM_POWERACTIVE_L -#define SENSOR_RESETACTIVE_LEVEL_1 RK28_CAM_RESETACTIVE_L - -static int rk28_sensor_io_init(void); -static int rk28_sensor_io_deinit(void); - -struct rk28camera_platform_data rk28_camera_platform_data = { - .io_init = rk28_sensor_io_init, - .io_deinit = rk28_sensor_io_deinit, - .gpio_res = { - { - .gpio_reset = SENSOR_RESET_PIN_0, - .gpio_power = SENSOR_POWER_PIN_0, - .gpio_flag = (SENSOR_POWERACTIVE_LEVEL_0|SENSOR_RESETACTIVE_LEVEL_0), - .dev_name = SENSOR_NAME_0, - }, { - .gpio_reset = SENSOR_RESET_PIN_1, - .gpio_power = SENSOR_POWER_PIN_1, - .gpio_flag = (SENSOR_POWERACTIVE_LEVEL_1|SENSOR_RESETACTIVE_LEVEL_1), - .dev_name = SENSOR_NAME_1, - } - } -}; - -static int rk28_sensor_io_init(void) -{ - int ret = 0, i; - unsigned int camera_reset = INVALID_GPIO, camera_power = INVALID_GPIO; - unsigned int camera_ioflag; - //printk("\n%s....%d ******** ddl *********\n",__FUNCTION__,__LINE__); - - for (i=0; i<2; i++) { - camera_reset = rk28_camera_platform_data.gpio_res[i].gpio_reset; - camera_power = rk28_camera_platform_data.gpio_res[i].gpio_power; - camera_ioflag = rk28_camera_platform_data.gpio_res[i].gpio_flag; - - if (camera_power != INVALID_GPIO) { - ret = gpio_request(camera_power, "camera power"); - if (ret) - continue; - - gpio_set_value(camera_reset, (((~camera_ioflag)&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - gpio_direction_output(camera_power, (((~camera_ioflag)&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - - //printk("\n%s....%d %x ******** ddl *********\n",__FUNCTION__,__LINE__,(((~camera_ioflag)&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - - } - - if (camera_reset != INVALID_GPIO) { - ret = gpio_request(camera_reset, "camera reset"); - if (ret) { - if (camera_power != INVALID_GPIO) - gpio_free(camera_power); - - continue; - } - - gpio_set_value(camera_reset, ((camera_ioflag&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - gpio_direction_output(camera_reset, ((camera_ioflag&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - - //printk("\n%s....%d %x ******** ddl *********\n",__FUNCTION__,__LINE__,((camera_ioflag&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - - } - } - - return 0; -} - -static int rk28_sensor_io_deinit(void) -{ - unsigned int i; - unsigned int camera_reset = INVALID_GPIO, camera_power = INVALID_GPIO; - - //printk("\n%s....%d ******** ddl *********\n",__FUNCTION__,__LINE__); - - for (i=0; i<2; i++) { - camera_reset = rk28_camera_platform_data.gpio_res[i].gpio_reset; - camera_power = rk28_camera_platform_data.gpio_res[i].gpio_power; - - if (camera_power != INVALID_GPIO){ - gpio_direction_input(camera_power); - gpio_free(camera_power); - } - - if (camera_reset != INVALID_GPIO) { - gpio_direction_input(camera_reset); - gpio_free(camera_reset); - } - } - - return 0; -} - - -static int rk28_sensor_power(struct device *dev, int on) -{ - unsigned int camera_reset = INVALID_GPIO, camera_power = INVALID_GPIO; - unsigned int camera_ioflag; - - if(rk28_camera_platform_data.gpio_res[0].dev_name && (strcmp(rk28_camera_platform_data.gpio_res[0].dev_name, dev_name(dev)) == 0)) { - camera_reset = rk28_camera_platform_data.gpio_res[0].gpio_reset; - camera_power = rk28_camera_platform_data.gpio_res[0].gpio_power; - camera_ioflag = rk28_camera_platform_data.gpio_res[0].gpio_flag; - } else if (rk28_camera_platform_data.gpio_res[1].dev_name && (strcmp(rk28_camera_platform_data.gpio_res[1].dev_name, dev_name(dev)) == 0)) { - camera_reset = rk28_camera_platform_data.gpio_res[1].gpio_reset; - camera_power = rk28_camera_platform_data.gpio_res[1].gpio_power; - camera_ioflag = rk28_camera_platform_data.gpio_res[1].gpio_flag; - } - - if (camera_reset != INVALID_GPIO) { - gpio_set_value(camera_reset, ((camera_ioflag&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - //printk("\n%s..%s..ResetPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev),camera_reset, ((camera_ioflag&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - } - if (camera_power != INVALID_GPIO) { - if (on) { - gpio_set_value(camera_power, ((camera_ioflag&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - //printk("\n%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev), camera_power, ((camera_ioflag&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - } else { - gpio_set_value(camera_power, (((~camera_ioflag)&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - //printk("\n%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev), camera_power, (((~camera_ioflag)&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - } - } - if (camera_reset != INVALID_GPIO) { - msleep(3); /* delay 3 ms */ - gpio_set_value(camera_reset,(((~camera_ioflag)&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - //printk("\n%s..%s..ResetPin= %d..PinLevel = %x \n",__FUNCTION__,dev_name(dev), camera_reset, (((~camera_ioflag)&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - } - return 0; -} - -static struct i2c_board_info rk2818_i2c_cam_info[] = { - { - I2C_BOARD_INFO(SENSOR_NAME_0, SENSOR_IIC_ADDR_0>>1) - }, -}; - -struct soc_camera_link rk2818_iclink = { - .bus_id = RK28_CAM_PLATFORM_DEV_ID, - .power = rk28_sensor_power, - .board_info = &rk2818_i2c_cam_info[0], - .i2c_adapter_id = SENSOR_IIC_ADAPTER_ID_0, - .module_name = SENSOR_NAME_0, -}; - -/*platform_device : soc-camera need */ -struct platform_device rk2818_soc_camera_pdrv = { - .name = "soc-camera-pdrv", - .id = -1, - .dev = { - .init_name = SENSOR_NAME_0, - .platform_data = &rk2818_iclink, - }, -}; -#endif - -/***************************************************************************************** - * battery devices - * author: lw@rock-chips.com - *****************************************************************************************/ -#define CHARGEOK_PIN TCA6424_P07 -struct rk2818_battery_platform_data rk2818_battery_platdata = { - .charge_ok_pin = CHARGEOK_PIN, - .charge_ok_level = 0, -}; -/***************************************************************************************** - * serial devices - * author: lhh@rock-chips.com - *****************************************************************************************/ -static int serial_io_init(void) -{ - int ret; -#if 1 - //cz@rock-chips.com - //20100808 - //UART0µÄËĸö¹Ü½ÅÏÈIOMUX³ÉGPIO - //È»ºó·Ö±ðÉèÖÃÊäÈëÊä³ö/À­¸ßÀ­µÍ´¦Àí - //×îºóÔÙIOMUX³ÉUART - //·ÀÖ¹Ö±½ÓIOMUX³ÉUARTºóËĸö¹Ü½ÅµÄ״̬²»¶Ôʱ - //²Ù×÷UARTµ¼ÖÂUART_USR_BUSYʼÖÕΪ1Ôì³ÉÈçÏÂËÀÑ­»· - //while(rk2818_uart_read(port,UART_USR)&UART_USR_BUSY) - //UARTËĸö¹Ü½ÅÔÚδ´«ÊäʱÕý³£×´Ì¬Ó¦¸ÃΪ£º - //RX/TX£ºHIGH - //CTS/RTS£ºLOW - //×¢Ò⣺CTS/RTSΪµÍÓÐЧ£¬Ó²¼þÉϲ»Ó¦¸ÃÇ¿ÐÐ×öÉÏÀ­ - rk2818_mux_api_set(GPIOG1_UART0_MMC1WPT_NAME, IOMUXA_GPIO1_C1 /*IOMUXA_UART0_SOUT*/); - rk2818_mux_api_set(GPIOG0_UART0_MMC1DET_NAME, IOMUXA_GPIO1_C0 /*IOMUXA_UART0_SIN*/); - - ret = gpio_request(RK2818_PIN_PG0, NULL); - if(ret != 0) - { - gpio_free(RK2818_PIN_PG0); - } - gpio_direction_output(RK2818_PIN_PG0,GPIO_HIGH); - - - ret = gpio_request(RK2818_PIN_PG1, NULL); - if(ret != 0) - { - gpio_free(RK2818_PIN_PG1); - } - gpio_direction_output(RK2818_PIN_PG1,GPIO_HIGH); - - gpio_pull_updown(RK2818_PIN_PG1,GPIOPullUp); - gpio_pull_updown(RK2818_PIN_PG0,GPIOPullUp); - - rk2818_mux_api_set(GPIOG1_UART0_MMC1WPT_NAME, IOMUXA_UART0_SOUT); - rk2818_mux_api_set(GPIOG0_UART0_MMC1DET_NAME, IOMUXA_UART0_SIN); - - rk2818_mux_api_set(GPIOB2_U0CTSN_SEL_NAME, IOMUXB_GPIO0_B2/*IOMUXB_UART0_CTS_N*/); - rk2818_mux_api_set(GPIOB3_U0RTSN_SEL_NAME, IOMUXB_GPIO0_B3/*IOMUXB_UART0_RTS_N*/); - - ret = gpio_request(RK2818_PIN_PB2, NULL); - if(ret != 0) - { - gpio_free(RK2818_PIN_PB2); - } - gpio_direction_input(RK2818_PIN_PB2); - // gpio_direction_output(RK2818_PIN_PB2,GPIO_LOW); - - ret = gpio_request(RK2818_PIN_PB3, NULL); - if(ret != 0) - { - gpio_free(RK2818_PIN_PB3); - } - gpio_direction_output(RK2818_PIN_PB3,GPIO_LOW); -#endif - - rk2818_mux_api_set(GPIOB2_U0CTSN_SEL_NAME, IOMUXB_UART0_CTS_N); - rk2818_mux_api_set(GPIOB3_U0RTSN_SEL_NAME, IOMUXB_UART0_RTS_N); - - return 0; -} - -struct rk2818_serial_platform_data rk2818_serial0_platdata = { - .io_init = serial_io_init, -}; - -/***************************************************************************************** - * i2s devices - * author: lhhrock-chips.com - *****************************************************************************************/ -static int i2s_io_init(void) -{ - /* Configure the I2S pins in correct mode */ - rk2818_mux_api_set(CXGPIO_I2S_SEL_NAME,IOMUXB_I2S_INTERFACE); - return 0; -} - -struct rk2818_i2s_platform_data rk2818_i2s_platdata = { - .io_init = i2s_io_init, -}; -/***************************************************************************************** - * spi devices - * author: lhhrock-chips.com - *****************************************************************************************/ -#define SPI_CHIPSELECT_NUM 2 -struct spi_cs_gpio rk2818_spi_cs_gpios[SPI_CHIPSELECT_NUM] = { - { - .name = "spi cs0", - .cs_gpio = RK2818_PIN_PB4, - .cs_iomux_name = GPIOB4_SPI0CS0_MMC0D4_NAME,//if no iomux,set it NULL - .cs_iomux_mode = IOMUXA_GPIO0_B4, - }, - { - .name = "spi cs1", - .cs_gpio = RK2818_PIN_PB0, - .cs_iomux_name = GPIOB0_SPI0CSN1_MMC1PCA_NAME, - .cs_iomux_mode = IOMUXA_GPIO0_B0, - } - -}; - -static int spi_io_init(struct spi_cs_gpio *cs_gpios, int cs_num) -{ - int i,j,ret; - //clk - rk2818_mux_api_set(GPIOB_SPI0_MMC0_NAME, IOMUXA_SPI0); - //cs - if (cs_gpios) { - for (i=0; i>>>>> lcd cs gpio_request err \n "); - } - } - - rk2818_mux_api_set(LCD_CLK_MUX_NAME, LCD_CLK_MUX_MODE); - if (LCD_CLK_PIN != INVALID_GPIO) { - ret = gpio_request(LCD_CLK_PIN, NULL); - if(ret != 0) - { - goto err2; - printk(">>>>>> lcd clk gpio_request err \n "); - } - } - - rk2818_mux_api_set(LCD_TXD_MUX_NAME, LCD_TXD_MUX_MODE); - if (LCD_TXD_PIN != INVALID_GPIO) { - ret = gpio_request(LCD_TXD_PIN, NULL); - if(ret != 0) - { - goto err3; - printk(">>>>>> lcd txd gpio_request err \n "); - } - } - - return 0; - -err3: - if (LCD_CLK_PIN != INVALID_GPIO) { - gpio_free(LCD_CLK_PIN); - } -err2: - if (LCD_CS_PIN != INVALID_GPIO) { - gpio_free(LCD_CS_PIN); - } -err1: - return ret; -} - -static int rk2818_lcd_io_deinit(void) -{ - int ret = 0; - - gpio_direction_output(LCD_CLK_PIN, 0); - gpio_set_value(LCD_CLK_PIN, GPIO_HIGH); - gpio_direction_output(LCD_TXD_PIN, 0); - gpio_set_value(LCD_TXD_PIN, GPIO_HIGH); - - gpio_free(LCD_CS_PIN); - rk2818_mux_api_mode_resume(LCD_CS_MUX_NAME); - gpio_free(LCD_CLK_PIN); - gpio_free(LCD_TXD_PIN); - rk2818_mux_api_mode_resume(LCD_TXD_MUX_NAME); - rk2818_mux_api_mode_resume(LCD_CLK_MUX_NAME); - - return ret; -} - -struct rk2818lcd_info rk2818_lcd_info = { - .txd_pin = LCD_TXD_PIN, - .clk_pin = LCD_CLK_PIN, - .cs_pin = LCD_CS_PIN, - .io_init = rk2818_lcd_io_init, - .io_deinit = rk2818_lcd_io_deinit, -}; - - -/***************************************************************************************** - * frame buffe devices - * author: zyw@rock-chips.com - *****************************************************************************************/ -#define FB_ID 0 -#define FB_DISPLAY_ON_PIN RK2818_PIN_PB1 -#define FB_LCD_STANDBY_PIN INVALID_GPIO -#define FB_MCU_FMK_PIN INVALID_GPIO - -#define FB_DISPLAY_ON_VALUE GPIO_LOW -#define FB_LCD_STANDBY_VALUE 0 - -#define FB_DISPLAY_ON_MUX_NAME GPIOB1_SMCS1_MMC0PCA_NAME -#define FB_DISPLAY_ON_MUX_MODE IOMUXA_GPIO0_B1 - -#define FB_LCD_STANDBY_MUX_NAME NULL -#define FB_LCD_STANDBY_MUX_MODE 1 - -#define FB_MCU_FMK_PIN_MUX_NAME NULL -#define FB_MCU_FMK_MUX_MODE 0 - -#define FB_DATA0_16_MUX_NAME GPIOC_LCDC16BIT_SEL_NAME -#define FB_DATA0_16_MUX_MODE 1 - -#define FB_DATA17_18_MUX_NAME GPIOC_LCDC18BIT_SEL_NAME -#define FB_DATA17_18_MUX_MODE 1 - -#define FB_DATA19_24_MUX_NAME GPIOC_LCDC24BIT_SEL_NAME -#define FB_DATA19_24_MUX_MODE 1 - -#define FB_DEN_MUX_NAME CXGPIO_LCDDEN_SEL_NAME -#define FB_DEN_MUX_MODE 1 - -#define FB_VSYNC_MUX_NAME CXGPIO_LCDVSYNC_SEL_NAME -#define FB_VSYNC_MUX_MODE 1 - -#define FB_MCU_FMK_MUX_NAME NULL -#define FB_MCU_FMK_MUX_MODE 0 - -static int rk2818_fb_io_init(struct rk2818_fb_setting_info *fb_setting) -{ - int ret = 0; - if(fb_setting->data_num <=16) - rk2818_mux_api_set(FB_DATA0_16_MUX_NAME, FB_DATA0_16_MUX_MODE); - if(fb_setting->data_num >16 && fb_setting->data_num<=18) - rk2818_mux_api_set(FB_DATA17_18_MUX_NAME, FB_DATA17_18_MUX_MODE); - if(fb_setting->data_num >18) - rk2818_mux_api_set(FB_DATA19_24_MUX_NAME, FB_DATA19_24_MUX_MODE); - - if(fb_setting->vsync_en) - rk2818_mux_api_set(FB_VSYNC_MUX_NAME, FB_VSYNC_MUX_MODE); - - if(fb_setting->den_en) - rk2818_mux_api_set(FB_DEN_MUX_NAME, FB_DEN_MUX_MODE); - - if(fb_setting->mcu_fmk_en && FB_MCU_FMK_MUX_NAME && (FB_MCU_FMK_PIN != INVALID_GPIO)) - { - rk2818_mux_api_set(FB_MCU_FMK_MUX_NAME, FB_MCU_FMK_MUX_MODE); - ret = gpio_request(FB_MCU_FMK_PIN, NULL); - if(ret != 0) - { - gpio_free(FB_MCU_FMK_PIN); - printk(">>>>>> FB_MCU_FMK_PIN gpio_request err \n "); - } - gpio_direction_input(FB_MCU_FMK_PIN); - } - - if(fb_setting->disp_on_en && FB_DISPLAY_ON_MUX_NAME && (FB_DISPLAY_ON_PIN != INVALID_GPIO)) - { - rk2818_mux_api_set(FB_DISPLAY_ON_MUX_NAME, FB_DISPLAY_ON_MUX_MODE); - ret = gpio_request(FB_DISPLAY_ON_PIN, NULL); - if(ret != 0) - { - gpio_free(FB_DISPLAY_ON_PIN); - printk(">>>>>> FB_DISPLAY_ON_PIN gpio_request err \n "); - } - } - - if(fb_setting->disp_on_en && FB_LCD_STANDBY_MUX_NAME && (FB_LCD_STANDBY_PIN != INVALID_GPIO)) - { - rk2818_mux_api_set(FB_LCD_STANDBY_MUX_NAME, FB_LCD_STANDBY_MUX_MODE); - ret = gpio_request(FB_LCD_STANDBY_PIN, NULL); - if(ret != 0) - { - gpio_free(FB_LCD_STANDBY_PIN); - printk(">>>>>> FB_LCD_STANDBY_PIN gpio_request err \n "); - } - } - - return ret; -} - -struct rk2818fb_info rk2818_fb_info = { - .fb_id = FB_ID, - .disp_on_pin = FB_DISPLAY_ON_PIN, - .disp_on_value = FB_DISPLAY_ON_VALUE, - .standby_pin = FB_LCD_STANDBY_PIN, - .standby_value = FB_LCD_STANDBY_VALUE, - .mcu_fmk_pin = FB_MCU_FMK_PIN, - .lcd_info = &rk2818_lcd_info, - .io_init = rk2818_fb_io_init, -}; - -/***************************************************************************************** - * backlight devices - * author: nzy@rock-chips.com - *****************************************************************************************/ - /* - GPIOF2_APWM0_SEL_NAME, IOMUXB_PWM0 - GPIOF3_APWM1_MMC0DETN_NAME, IOMUXA_PWM1 - GPIOF4_APWM2_MMC0WPT_NAME, IOMUXA_PWM2 - GPIOF5_APWM3_DPWM3_NAME, IOMUXB_PWM3 - */ - -#define PWM_ID 0 -#define PWM_MUX_NAME GPIOF2_APWM0_SEL_NAME -#define PWM_MUX_MODE IOMUXB_PWM0 -#define PWM_EFFECT_VALUE 0 - - -#define BL_EN_MUX_NAME GPIOF34_UART3_SEL_NAME -#define BL_EN_MUX_MODE IOMUXB_GPIO1_B34 - -#define BL_EN_PIN RK2818_PIN_PF3 -#define BL_EN_VALUE GPIO_HIGH - - - -static int rk2818_backlight_io_init(void) -{ - int ret = 0; - - rk2818_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE); - - rk2818_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE); - - ret = gpio_request(BL_EN_PIN, NULL); - if(ret != 0) - { - gpio_free(BL_EN_PIN); - printk(KERN_ERR ">>>>>> lcd_cs gpio_request err \n "); - } - - gpio_direction_output(BL_EN_PIN, 0); - gpio_set_value(BL_EN_PIN, BL_EN_VALUE); - - return ret; -} - -static int rk2818_backlight_io_deinit(void) -{ - int ret = 0; - - gpio_free(BL_EN_PIN); - - rk2818_mux_api_mode_resume(PWM_MUX_NAME); - - rk2818_mux_api_mode_resume(BL_EN_MUX_NAME); - - return ret; -} -struct rk2818_bl_info rk2818_bl_info = { - .pwm_id = PWM_ID, - .bl_ref = PWM_EFFECT_VALUE, - .io_init = rk2818_backlight_io_init, - .io_deinit = rk2818_backlight_io_deinit, -}; - -/******************************************************** -* dm9000 net work devices -* author:lyx -********************************************************/ -#ifdef CONFIG_DM9000 -/* -GPIOA5_FLASHCS1_SEL_NAME IOMUXB_FLASH_CS1 -GPIOA6_FLASHCS2_SEL_NAME IOMUXB_FLASH_CS2 -GPIOA7_FLASHCS3_SEL_NAME IOMUXB_FLASH_CS3 -GPIOE_SPI1_FLASH_SEL1_NAME IOMUXA_FLASH_CS45 -GPIOE_SPI1_FLASH_SEL_NAME IOMUXA_FLASH_CS67 -*/ -#define DM9000_USE_NAND_CS 1 //cs can be 1,2,3,4,5,6 or 7 -#define DM9000_CS_IOMUX_NAME GPIOA5_FLASHCS1_SEL_NAME -#define DM9000_CS_IOMUX_MODE IOMUXB_FLASH_CS1 -#define DM9000_NET_INT_PIN RK2818_PIN_PA3 -#define DM9000_INT_IOMUX_NAME GPIOA23_UART2_SEL_NAME -#define DM9000_INT_IOMUX_MODE IOMUXB_GPIO0_A23 -#define DM9000_INT_INIT_VALUE GPIOPullDown -#define DM9000_IRQ IRQF_TRIGGER_HIGH -#define DM9000_IO_ADDR (RK2818_NANDC_PHYS + 0x800 + DM9000_USE_NAND_CS*0x100 + 0x8) -#define DM9000_DATA_ADDR (RK2818_NANDC_PHYS + 0x800 + DM9000_USE_NAND_CS*0x100 + 0x4) - -static int dm9k_gpio_set(void) -{ - //cs - rk2818_mux_api_set(DM9000_CS_IOMUX_NAME, DM9000_CS_IOMUX_MODE); - //int - rk2818_mux_api_set(DM9000_INT_IOMUX_NAME, DM9000_INT_IOMUX_MODE); - - return 0; -} -static int dm9k_gpio_free(void) -{ - rk2818_mux_api_mode_resume(DM9000_INT_IOMUX_NAME); - rk2818_mux_api_mode_resume(DM9000_CS_IOMUX_NAME); - return 0; -} - -static struct resource dm9k_resource[] = { - [0] = { - .start = DM9000_IO_ADDR, - .end = DM9000_IO_ADDR + 3, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DM9000_DATA_ADDR, - .end = DM9000_DATA_ADDR + 3, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = DM9000_NET_INT_PIN, - .end = DM9000_NET_INT_PIN, - .flags = IORESOURCE_IRQ | DM9000_IRQ, - } - -}; - -/* for the moment we limit ourselves to 8bit IO until some - * better IO routines can be written and tested -*/ -struct dm9000_plat_data dm9k_platdata = { - .flags = DM9000_PLATF_8BITONLY, - .irq_pin = DM9000_NET_INT_PIN, - .irq_pin_value = DM9000_INT_INIT_VALUE, - .io_init = dm9k_gpio_set, - .io_deinit = dm9k_gpio_free, -}; - -struct platform_device rk2818_device_dm9k = { - .name = "dm9000", - .id = 0, - .num_resources = ARRAY_SIZE(dm9k_resource), - .resource = dm9k_resource, - .dev = { - .platform_data = &dm9k_platdata, - } -}; -#endif - -#ifdef CONFIG_KEYBOARD_MATRIX -/* - * InfoPhone Matrix Keyboard Device - */ -#define KEYOUT0 TCA6424_P01 -#define KEYOUT1 TCA6424_P02 -#define KEYOUT2 TCA6424_P03 -#define KEYOUT3 TCA6424_P04 -#define KEYOUT4 TCA6424_P05 - -#define KEYIN0 TCA6424_P12 -#define KEYIN1 TCA6424_P13 -#define KEYIN2 TCA6424_P14 -#define KEYIN3 TCA6424_P15 - -static const uint32_t rk2818matrix_keymap[] = { - KEY(0, 0, KEY_1), - KEY(1, 0, KEY_2), - KEY(2, 0, KEY_3), - KEY(3, 0, KEY_TAB), - KEY(0, 1, KEY_4), - KEY(1, 1, KEY_5), - KEY(2, 1, KEY_6), - KEY(3, 1, KEY_R), - KEY(0, 2, KEY_7), - KEY(1, 2, KEY_8), - KEY(2, 2, KEY_9), - KEY(3, 2, KEY_Q), - KEY(0, 3, KEY_E), - KEY(1, 3, KEY_0), - KEY(2, 3, KEY_G), - KEY(3, 3, KEY_LEFTCTRL), - KEY(0, 4, KEY_W), - KEY(1, 4, KEY_S), - KEY(2, 4, KEY_F), - KEY(3, 4, KEY_V), -}; - -static struct matrix_keymap_data rk2818matrix_keymap_data = { - .keymap = rk2818matrix_keymap, - .keymap_size = ARRAY_SIZE(rk2818matrix_keymap), -}; - -static const int rk2818matrix_row_gpios[] = - { KEYIN0, KEYIN1, KEYIN2, KEYIN3 }; -static const int rk2818matrix_col_gpios[] = - { KEYOUT0, KEYOUT1, KEYOUT2, KEYOUT3, KEYOUT4 }; - -static struct matrix_keypad_platform_data rk2818matrixkey_pdata = { - .keymap_data = &rk2818matrix_keymap_data, - .row_gpios = rk2818matrix_row_gpios, - .col_gpios = rk2818matrix_col_gpios, - .num_row_gpios = ARRAY_SIZE(rk2818matrix_row_gpios), - .num_col_gpios = ARRAY_SIZE(rk2818matrix_col_gpios), - .col_scan_delay_us = 100, - .debounce_ms = 10, - .wakeup = 1, -}; - -static struct platform_device rk2818_device_matrixkey = { - .name = "matrix-keypad", - .id = -1, - .dev = { - .platform_data = &rk2818matrixkey_pdata, - }, -}; -#endif /* CONFIG_KEYBOARD_MATRIX */ - -#ifdef CONFIG_HEADSET_DET -struct rk2818_headset_data rk2818_headset_info = { - .irq = TCA6424_P23, - .irq_type = IRQF_TRIGGER_FALLING|IRQF_TRIGGER_RISING, - .headset_in_type= HEADSET_IN_HIGH, -}; - -struct platform_device rk28_device_headset = { - .name = "rk2818_headsetdet", - .id = 0, - .dev = { - .platform_data = &rk2818_headset_info, - } -}; -#endif - -/***************************************************************************************** - * nand flash devices - * author: hxy@rock-chips.com - *****************************************************************************************/ -/* -GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1 -GPIOA6_FLASHCS2_SEL_NAME, IOMUXB_FLASH_CS2 -GPIOA7_FLASHCS3_SEL_NAME, IOMUXB_FLASH_CS3 -GPIOE_SPI1_FLASH_SEL1_NAME, IOMUXA_FLASH_CS45 -GPIOE_SPI1_FLASH_SEL_NAME, IOMUXA_FLASH_CS67 -*/ - -#define NAND_CS_MAX_NUM 1 /*form 0 to 8, it is 0 when no nand flash */ - -int rk2818_nand_io_init(void) -{ -#if (NAND_CS_MAX_NUM == 2) - rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1); -#elif (NAND_CS_MAX_NUM == 3) - rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1); - rk2818_mux_api_set(GPIOA6_FLASHCS2_SEL_NAME, IOMUXB_FLASH_CS2); -#elif (NAND_CS_MAX_NUM == 4) - rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1); - rk2818_mux_api_set(GPIOA6_FLASHCS2_SEL_NAME, IOMUXB_FLASH_CS2); - rk2818_mux_api_set(GPIOA7_FLASHCS3_SEL_NAME, IOMUXB_FLASH_CS3); -#elif ((NAND_CS_MAX_NUM == 5) || (NAND_CS_MAX_NUM == 6)) - rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1); - rk2818_mux_api_set(GPIOA6_FLASHCS2_SEL_NAME, IOMUXB_FLASH_CS2); - rk2818_mux_api_set(GPIOA7_FLASHCS3_SEL_NAME, IOMUXB_FLASH_CS3); - rk2818_mux_api_set(GPIOE_SPI1_FLASH_SEL1_NAME, IOMUXA_FLASH_CS45); -#elif ((NAND_CS_MAX_NUM == 7) || (NAND_CS_MAX_NUM == 8)) - rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1); - rk2818_mux_api_set(GPIOA6_FLASHCS2_SEL_NAME, IOMUXB_FLASH_CS2); - rk2818_mux_api_set(GPIOA7_FLASHCS3_SEL_NAME, IOMUXB_FLASH_CS3); - rk2818_mux_api_set(GPIOE_SPI1_FLASH_SEL1_NAME, IOMUXA_FLASH_CS45); - rk2818_mux_api_set(GPIOE_SPI1_FLASH_SEL_NAME, IOMUXA_FLASH_CS67); -#endif - return 0; -} - -struct rk2818_nand_platform_data rk2818_nand_data = { - .width = 1, /* data bus width in bytes */ - .hw_ecc = 1, /* hw ecc 0: soft ecc */ - .num_flash = 1, - .io_init = rk2818_nand_io_init, -}; - - -/******************usb***********************/ -struct usb_mass_storage_platform_data mass_storage_pdata = { - .nluns = 2, - .vendor = "RockChip", - .product = "rk2818 sdk", - .release = 0x0100, -}; - - -static struct platform_device *devices[] __initdata = { -#ifdef CONFIG_UART0_RK2818 - &rk2818_device_uart0, -#endif -#ifdef CONFIG_UART1_RK2818 - &rk2818_device_uart1, -#endif -#ifdef CONFIG_I2C0_RK2818 - &rk2818_device_i2c0, -#endif -#ifdef CONFIG_I2C1_RK2818 - &rk2818_device_i2c1, -#endif -#ifdef CONFIG_SDMMC0_RK2818 - &rk2818_device_sdmmc0, -#endif -#ifdef CONFIG_SDMMC1_RK2818 - &rk2818_device_sdmmc1, - &info_wifi_device, -#endif - &info_rfkill, - &rk2818_device_spim, - &rk2818_device_i2s, -#if defined(CONFIG_ANDROID_PMEM) - &rk2818_device_pmem, - &rk2818_device_pmem_dsp, -#endif - &rk2818_device_adc, - &rk2818_device_adckey, - &rk2818_device_battery, - &rk2818_device_fb, - &rk2818_device_backlight, - &rk2818_device_dsp, -#ifdef CONFIG_VIDEO_RK2818 - &rk2818_device_camera, /* ddl@rock-chips.com : camera support */ - &rk2818_soc_camera_pdrv, -#endif -#ifdef CONFIG_MTD_NAND_RK2818 - &rk2818_nand_device, -#endif -#ifdef CONFIG_DM9000 - &rk2818_device_dm9k, -#endif -#ifdef CONFIG_KEYBOARD_MATRIX - &rk2818_device_matrixkey, -#endif -#ifdef CONFIG_HEADSET_DET - &rk28_device_headset, -#endif -#ifdef CONFIG_DWC_OTG - &rk2818_device_dwc_otg, -#endif -#ifdef CONFIG_RK2818_HOST11 - &rk2818_device_host11, -#endif -#ifdef CONFIG_USB_ANDROID - &android_usb_device, - &usb_mass_storage_device, -#endif - -}; - -extern struct sys_timer rk2818_timer; -#define POWER_PIN RK2818_PIN_PH7 -static void rk2818_power_on(void) -{ - int ret; - ret = gpio_request(POWER_PIN, NULL); - if (ret) { - printk("failed to request power_off gpio\n"); - goto err_free_gpio; - } - - gpio_pull_updown(POWER_PIN, GPIOPullUp); - ret = gpio_direction_output(POWER_PIN, GPIO_HIGH); - if (ret) { - printk("failed to set power_off gpio output\n"); - goto err_free_gpio; - } - - gpio_set_value(POWER_PIN, 1);/*power on*/ - -err_free_gpio: - gpio_free(POWER_PIN); -} - -static void rk2818_power_off(void) -{ - printk("shut down system now ...\n"); - gpio_set_value(POWER_PIN, 0);/*power down*/ -} - -// adc ---> key -#define PLAY_ON_PIN RK2818_PIN_PE1 -#define PLAY_ON_LEVEL 0 -static ADC_keyst gAdcValueTab[] = -{ - {95, AD2KEY1},///VOLUME_DOWN - {249, AD2KEY2},///VOLUME_UP - {408, AD2KEY3},///MENU - {560, AD2KEY4},///HOME - {725, AD2KEY5},///BACK - {816, AD2KEY6},///CALL - {0,0} -}; - -static unsigned char gInitKeyCode[] = -{ - AD2KEY1,AD2KEY2,AD2KEY3,AD2KEY4,AD2KEY5,AD2KEY6, - ENDCALL,KEYSTART,KEY_WAKEUP, -}; - -struct adc_key_data rk2818_adc_key = { - .pin_playon = PLAY_ON_PIN, - .playon_level = PLAY_ON_LEVEL, - .adc_empty = 900, - .adc_invalid = 20, - .adc_drift = 50, - .adc_chn = 1, - .adc_key_table = gAdcValueTab, - .initKeyCode = gInitKeyCode, - .adc_key_cnt = 7, -}; -struct rk2818_adckey_platform_data rk2818_adckey_platdata = { - .adc_key = &rk2818_adc_key, -}; -#if CONFIG_ANDROID_TIMED_GPIO -struct timed_gpio_platform_data rk28_vibrator_info = { - .num_gpios = 0, -}; -#endif - -static void __init machine_rk2818_init_irq(void) -{ - rk2818_init_irq(); - rk2818_gpio_init(rk2818_gpioBank, 8); - rk2818_gpio_irq_setup(); -} - -static void __init machine_rk2818_board_init(void) -{ - rk2818_power_on(); - pm_power_off = rk2818_power_off; -#ifdef CONFIG_I2C0_RK2818 - i2c_register_board_info(default_i2c0_data.bus_num, board_i2c0_devices, - ARRAY_SIZE(board_i2c0_devices)); -#endif -#ifdef CONFIG_I2C1_RK2818 - i2c_register_board_info(default_i2c1_data.bus_num, board_i2c1_devices, - ARRAY_SIZE(board_i2c1_devices)); -#endif - platform_add_devices(devices, ARRAY_SIZE(devices)); - spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices)); -} - -static void __init machine_rk2818_mapio(void) -{ - iotable_init(rk2818_io_desc, ARRAY_SIZE(rk2818_io_desc)); - rk2818_clock_init(); - rk2818_iomux_init(); -} - -MACHINE_START(RK2818, "RK28board") - -/* UART for LL DEBUG */ - .phys_io = 0x18002000, - .io_pg_offst = ((0xFF100000) >> 18) & 0xfffc, - .boot_params = RK2818_SDRAM_PHYS + 0x88000, - .map_io = machine_rk2818_mapio, - .init_irq = machine_rk2818_init_irq, - .init_machine = machine_rk2818_board_init, - .timer = &rk2818_timer, -MACHINE_END - diff --git a/arch/arm/mach-rk2818/board-midsdk.c b/arch/arm/mach-rk2818/board-midsdk.c deleted file mode 100755 index 3913969b5cf5..000000000000 --- a/arch/arm/mach-rk2818/board-midsdk.c +++ /dev/null @@ -1,755 +0,0 @@ -/* linux/arch/arm/mach-rk2818/board-midsdk.c - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "devices.h" - - -/* -------------------------------------------------------------------- - * ÉùÃ÷ÁËrk2818_gpioBankÊý×飬²¢¶¨ÒåÁËGPIO¼Ä´æÆ÷×éIDºÍ¼Ä´æÆ÷»ùµØÖ·¡£ - * -------------------------------------------------------------------- */ - -static struct rk2818_gpio_bank rk2818_gpioBank[] = { - { - .id = RK2818_ID_PIOA, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOB, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOC, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOD, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOE, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOF, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOG, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOH, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - } -}; - -//IOÓ³É䷽ʽÃèÊö £¬Ã¿¸öΪһ¶ÎÏßÐÔÁ¬ÐøÓ³Éä -static struct map_desc rk2818_io_desc[] __initdata = { - - { - .virtual = RK2818_MCDMA_BASE, //ÐéÄâµØÖ· - .pfn = __phys_to_pfn(RK2818_MCDMA_PHYS), //ÎïÀíµØÖ·£¬ÐëÓëÒ³±í¶ÔÆë - .length = RK2818_MCDMA_SIZE, //³¤¶È - .type = MT_DEVICE //Ó³É䷽ʽ - }, - - { - .virtual = RK2818_DWDMA_BASE, - .pfn = __phys_to_pfn(RK2818_DWDMA_PHYS), - .length = RK2818_DWDMA_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_INTC_BASE, - .pfn = __phys_to_pfn(RK2818_INTC_PHYS), - .length = RK2818_INTC_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_NANDC_BASE, - .pfn = __phys_to_pfn(RK2818_NANDC_PHYS), - .length = RK2818_NANDC_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_SDRAMC_BASE, - .pfn = __phys_to_pfn(RK2818_SDRAMC_PHYS), - .length = RK2818_SDRAMC_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_ARMDARBITER_BASE, - .pfn = __phys_to_pfn(RK2818_ARMDARBITER_PHYS), - .length = RK2818_ARMDARBITER_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_APB_BASE, - .pfn = __phys_to_pfn(RK2818_APB_PHYS), - .length = 0xa0000, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_WDT_BASE, - .pfn = __phys_to_pfn(RK2818_WDT_PHYS), - .length = 0xa0000, ///apb bus i2s i2c spi no map in this - .type = MT_DEVICE - }, -}; -/***************************************************************************************** - * SDMMC devices - *author: kfx -*****************************************************************************************/ - void rk2818_sdmmc0_cfg_gpio(struct platform_device *dev) -{ - rk2818_mux_api_set(GPIOF3_APWM1_MMC0DETN_NAME, IOMUXA_SDMMC1_DETECT_N); - rk2818_mux_api_set(GPIOH_MMC0D_SEL_NAME, IOMUXA_SDMMC0_DATA123); - rk2818_mux_api_set(GPIOH_MMC0_SEL_NAME, IOMUXA_SDMMC0_CMD_DATA0_CLKOUT); -} - -void rk2818_sdmmc1_cfg_gpio(struct platform_device *dev) -{ - rk2818_mux_api_set(GPIOG_MMC1_SEL_NAME, IOMUXA_SDMMC1_CMD_DATA0_CLKOUT); - rk2818_mux_api_set(GPIOG_MMC1D_SEL_NAME, IOMUXA_SDMMC1_DATA123); -#if 0 - /* wifi power up (gpio control) */ - rk2818_mux_api_set(GPIOH7_HSADCCLK_SEL_NAME,IOMUXB_GPIO1_D7); - rk2818_mux_api_set(GPIOF5_APWM3_DPWM3_NAME,IOMUXB_GPIO1_B5); - gpio_request(RK2818_PIN_PH7, "sdio"); - gpio_direction_output(RK2818_PIN_PH7,GPIO_HIGH); -#endif - -} -#define CONFIG_SDMMC0_USE_DMA -#define CONFIG_SDMMC1_USE_DMA -struct rk2818_sdmmc_platform_data default_sdmmc0_data = { - .host_ocr_avail = (MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30| - MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33| - MMC_VDD_33_34|MMC_VDD_34_35| MMC_VDD_35_36), - .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED), - .cfg_gpio = rk2818_sdmmc0_cfg_gpio, - .no_detect = 0, - .dma_name = "sd_mmc", -#ifdef CONFIG_SDMMC0_USE_DMA - .use_dma = 1, -#else - .use_dma = 0, -#endif -}; -struct rk2818_sdmmc_platform_data default_sdmmc1_data = { - .host_ocr_avail = (MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29| - MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32| - MMC_VDD_32_33|MMC_VDD_33_34), - .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_SDIO_IRQ| - MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED), - .cfg_gpio = rk2818_sdmmc1_cfg_gpio, - .no_detect = 1, - .dma_name = "sdio", -#ifdef CONFIG_SDMMC1_USE_DMA - .use_dma = 1, -#else - .use_dma = 0, -#endif -}; - -/***************************************************************************************** - * extern gpio devices - *author: xxx - *****************************************************************************************/ -#if defined (CONFIG_GPIO_PCA9554) -struct rk2818_gpio_expander_info extern_gpio_settinginfo[] = { - { - .gpio_num =RK2818_PIN_PI0, - .pin_type = GPIO_IN, - //.pin_value =GPIO_HIGH, - }, - - { - .gpio_num =RK2818_PIN_PI4,// tp3 - .pin_type = GPIO_IN, - //.pin_value =GPIO_HIGH, - }, - - { - .gpio_num =RK2818_PIN_PI5,//tp4 - .pin_type = GPIO_IN, - //.pin_value =GPIO_HIGH, - }, - { - .gpio_num =RK2818_PIN_PI6,//tp2 - .pin_type = GPIO_OUT, - //.pin_value =GPIO_HIGH, - }, - { - .gpio_num =RK2818_PIN_PI7,//tp1 - .pin_type = GPIO_OUT, - .pin_value =GPIO_HIGH, - }, - - - -}; - -struct pca9554_platform_data rk2818_pca9554_data={ - .gpio_base=GPIO_EXPANDER_BASE, - .gpio_pin_num=CONFIG_EXPANDED_GPIO_NUM, - .gpio_irq_start=NR_AIC_IRQS + 2*NUM_GROUP, - .irq_pin_num=CONFIG_EXPANDED_GPIO_IRQ_NUM, - .pca9954_irq_pin=RK2818_PIN_PE2, - .settinginfo=extern_gpio_settinginfo, - .settinginfolen=ARRAY_SIZE(extern_gpio_settinginfo), -}; -#endif - -/***************************************************************************************** - * I2C devices - *author: kfx -*****************************************************************************************/ - void rk2818_i2c0_cfg_gpio(struct platform_device *dev) -{ - rk2818_mux_api_set(GPIOE_I2C0_SEL_NAME, IOMUXA_I2C0); -} - -void rk2818_i2c1_cfg_gpio(struct platform_device *dev) -{ - rk2818_mux_api_set(GPIOE_U1IR_I2C1_NAME, IOMUXA_I2C1); -} -struct rk2818_i2c_platform_data default_i2c0_data = { - .bus_num = 0, - .flags = 0, - .slave_addr = 0xff, - .scl_rate = 400*1000, - .mode = I2C_MODE_IRQ, //I2C_MODE_POLL - .cfg_gpio = rk2818_i2c0_cfg_gpio, -}; -struct rk2818_i2c_platform_data default_i2c1_data = { -#ifdef CONFIG_I2C0_RK2818 - .bus_num = 1, -#else - .bus_num = 0, -#endif - .flags = 0, - .slave_addr = 0xff, - .scl_rate = 400*1000, - .mode = I2C_MODE_IRQ, //I2C_MODE_POLL - .cfg_gpio = rk2818_i2c1_cfg_gpio, -}; - -struct rk2818_i2c_spi_data default_i2c2_data = { - .bus_num = 2, - .flags = 0, - .slave_addr = 0xff, - .scl_rate = 400*1000, - -}; -struct rk2818_i2c_spi_data default_i2c3_data = { - - .bus_num = 3, - .flags = 0, - .slave_addr = 0xff, - .scl_rate = 400*1000, - -}; -static struct i2c_board_info __initdata board_i2c0_devices[] = { -#if defined (CONFIG_RK1000_CONTROL) - { - .type = "rk1000_control", - .addr = 0x40, - .flags = 0, - }, -#endif - -#if defined (CONFIG_RK1000_TVOUT) - { - .type = "rk1000_tvout", - .addr = 0x42, - .flags = 0, - }, -#endif -#if defined (CONFIG_SND_SOC_RK1000) - { - .type = "rk1000_i2c_codec", - .addr = 0x60, - .flags = 0, - }, -#endif -#if defined (CONFIG_SND_SOC_WM8988) - { - .type = "wm8988", - .addr = 0x1a, - .flags = 0, - } -#endif -}; -static struct i2c_board_info __initdata board_i2c1_devices[] = { -#if defined (CONFIG_RTC_HYM8563) - { - .type = "rtc_hym8563", - .addr = 0x51, - .flags = 0, - }, -#endif -#if defined (CONFIG_FM_QN8006) - { - .type = "fm_qn8006", - .addr = 0x2b, - .flags = 0, - }, -#endif -#if defined (CONFIG_GPIO_PCA9554) - { - .type = "extend_gpio_pca9554", - .addr = 0x3c, - .flags = 0, - .platform_data=&rk2818_pca9554_data.gpio_base, - }, -#endif -#if defined (CONFIG_PMIC_LP8725) - { - .type = "lp8725", - .addr = 0x79, - .flags = 0, - }, -#endif - {}, -}; - -static struct i2c_board_info __initdata board_i2c2_devices[] = { - -}; -static struct i2c_board_info __initdata board_i2c3_devices[] = { -#if defined (CONFIG_SND_SOC_WM8994) - { - .type = "wm8994", - .addr = 0x1a, - .flags = 0, - }, -#endif -}; - -/***************************************************************************************** - * SPI devices - *author: lhh - *****************************************************************************************/ -static struct spi_board_info board_spi_devices[] = { -#if defined(CONFIG_SPI_FPGA) - { /* fpga ice65l08xx */ - .modalias = "spi_fpga", - .chip_select = 1, - .max_speed_hz = 8 * 1000 * 1000, - .bus_num = 0, - .mode = SPI_MODE_0, - }, -#endif -#if defined(CONFIG_ENC28J60) - { /* net chip */ - .modalias = "enc28j60", - .chip_select = 1, - .max_speed_hz = 12 * 1000 * 1000, - .bus_num = 0, - .mode = SPI_MODE_0, - }, -#endif -#if defined(CONFIG_TOUCHSCREEN_XPT2046_SPI) || defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI) - { - .modalias = "xpt2046_ts", - .chip_select = 0, - .max_speed_hz = 125 * 1000 * 26,/* (max sample rate @ 3V) * (cmd + data + overhead) */ - .bus_num = 0, - .irq = RK2818_PIN_PE3, - }, -#endif -}; - -/*rk2818_fb gpio information*/ -static struct rk2818_fb_gpio rk2818_fb_gpio_info = { - .display_on = (GPIO_LOW<<16)|RK2818_PIN_PA2, - .lcd_standby = 0, - .mcu_fmk_pin = 0, -}; - -/*rk2818_fb iomux information*/ -static struct rk2818_fb_iomux rk2818_fb_iomux_info = { - .data16 = GPIOC_LCDC16BIT_SEL_NAME, - .data18 = GPIOC_LCDC18BIT_SEL_NAME, - .data24 = GPIOC_LCDC24BIT_SEL_NAME, - .den = CXGPIO_LCDDEN_SEL_NAME, - .vsync = CXGPIO_LCDVSYNC_SEL_NAME, - .mcu_fmk = 0, -}; -/*rk2818_fb*/ -struct rk2818_fb_mach_info rk2818_fb_mach_info = { - .gpio = &rk2818_fb_gpio_info, - .iomux = &rk2818_fb_iomux_info, -}; - -struct rk2818bl_info rk2818_bl_info = { - .pwm_id = 0, - .pw_pin = GPIO_HIGH | (RK2818_PIN_PA3<< 8) , - .bl_ref = 0, - .pw_iomux = GPIOA23_UART2_SEL_NAME, -}; - -/******************************************************** -* dm9000 net work devices -* author:lyx -********************************************************/ -#ifdef CONFIG_DM9000 -/* -GPIOA5_FLASHCS1_SEL_NAME IOMUXB_FLASH_CS1 -GPIOA6_FLASHCS2_SEL_NAME IOMUXB_FLASH_CS2 -GPIOA7_FLASHCS3_SEL_NAME IOMUXB_FLASH_CS3 -GPIOE_SPI1_FLASH_SEL1_NAME IOMUXA_FLASH_CS45 -GPIOE_SPI1_FLASH_SEL_NAME IOMUXA_FLASH_CS67 -*/ -#define DM9000_USE_NAND_CS 1 //cs can be 1,2,3,4,5,6 or 7 -#define DM9000_CS_IOMUX_NAME GPIOA5_FLASHCS1_SEL_NAME -#define DM9000_CS_IOMUX_MODE IOMUXB_FLASH_CS1 -#define DM9000_NET_INT_PIN RK2818_PIN_PE2 -#define DM9000_INT_IOMUX_NAME GPIOE_SPI1_FLASH_SEL1_NAME -#define DM9000_INT_IOMUX_MODE IOMUXA_GPIO1_A12 -#define DM9000_INT_INIT_VALUE GPIOPullDown -#define DM9000_IRQ IRQF_TRIGGER_HIGH -#define DM9000_IO_ADDR (RK2818_NANDC_PHYS + 0x800 + DM9000_USE_NAND_CS*0x100 + 0x8) -#define DM9000_DATA_ADDR (RK2818_NANDC_PHYS + 0x800 + DM9000_USE_NAND_CS*0x100 + 0x4) - -int dm9k_gpio_set(void) -{ - //cs - rk2818_mux_api_set(DM9000_CS_IOMUX_NAME, DM9000_CS_IOMUX_MODE); - - //int - rk2818_mux_api_set(DM9000_INT_IOMUX_NAME, DM9000_INT_IOMUX_MODE); - - if (gpio_request(DM9000_NET_INT_PIN, "dm9000 interrupt")) { - gpio_free(DM9000_NET_INT_PIN); - rk2818_mux_api_mode_resume(DM9000_INT_IOMUX_NAME); - rk2818_mux_api_mode_resume(DM9000_CS_IOMUX_NAME); - printk("[fun:%s line:%d], request gpio for net interrupt fail\n", __func__,__LINE__); - - return -1; - } - gpio_pull_updown(DM9000_NET_INT_PIN, DM9000_INT_INIT_VALUE); - gpio_direction_input(DM9000_NET_INT_PIN); - - return 0; -} -int dm9k_gpio_free(void) -{ - gpio_free(DM9000_NET_INT_PIN); - rk2818_mux_api_mode_resume(DM9000_INT_IOMUX_NAME); - rk2818_mux_api_mode_resume(DM9000_CS_IOMUX_NAME); - return 0; -} -int dm9k_get_gpio_irq(void) -{ - return gpio_to_irq(DM9000_NET_INT_PIN); -} - -static struct resource dm9k_resource[] = { - [0] = { - .start = DM9000_IO_ADDR, - .end = DM9000_IO_ADDR + 3, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DM9000_DATA_ADDR, - .end = DM9000_DATA_ADDR + 3, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = DM9000_NET_INT_PIN, - .end = DM9000_NET_INT_PIN, - .flags = IORESOURCE_IRQ | DM9000_IRQ, - } - -}; - -/* for the moment we limit ourselves to 8bit IO until some - * better IO routines can be written and tested -*/ -struct dm9000_plat_data dm9k_platdata = { - .flags = DM9000_PLATF_8BITONLY, - .io_init = dm9k_gpio_set, - .io_deinit = dm9k_gpio_free, - .get_irq_num = dm9k_get_gpio_irq, -}; - -struct platform_device rk2818_device_dm9k = { - .name = "dm9000", - .id = 0, - .num_resources = ARRAY_SIZE(dm9k_resource), - .resource = dm9k_resource, - .dev = { - .platform_data = &dm9k_platdata, - } -}; -#endif - -static struct platform_device *devices[] __initdata = { -#ifdef CONFIG_UART1_RK2818 - &rk2818_device_uart1, -#endif -#ifdef CONFIG_I2C0_RK2818 - &rk2818_device_i2c0, -#endif -#ifdef CONFIG_I2C1_RK2818 - &rk2818_device_i2c1, -#endif -#ifdef CONFIG_SDMMC0_RK2818 - &rk2818_device_sdmmc0, -#endif -#ifdef CONFIG_SDMMC1_RK2818 - &rk2818_device_sdmmc1, -#endif - &rk2818_device_spim, - &rk2818_device_i2s, -#if defined(CONFIG_ANDROID_PMEM) - &rk2818_device_pmem, - &rk2818_device_pmem_dsp, -#endif - &rk2818_device_adc, - &rk2818_device_adckey, - &rk2818_device_battery, - &rk2818_device_fb, - &rk2818_device_backlight, - &rk2818_device_dsp, -#ifdef CONFIG_MTD_NAND_RK2818 - &rk2818_nand_device, -#endif -#ifdef CONFIG_DM9000 - &rk2818_device_dm9k, -#endif - -#ifdef CONFIG_DWC_OTG - &rk2818_device_dwc_otg, -#endif -#ifdef CONFIG_RK2818_HOST11 - &rk2818_device_host11, -#endif -#ifdef CONFIG_USB_ANDROID - &android_usb_device, - &usb_mass_storage_device, -#endif - -}; - -extern struct sys_timer rk2818_timer; -#define POWER_PIN RK2818_PIN_PA3 -static void rk2818_power_on(void) -{ - int ret; - ret = gpio_request(POWER_PIN, NULL); - if (ret) { - printk("failed to request power_off gpio\n"); - goto err_free_gpio; - } - - gpio_pull_updown(POWER_PIN, GPIOPullUp); - ret = gpio_direction_output(POWER_PIN, GPIO_HIGH); - if (ret) { - printk("failed to set power_off gpio output\n"); - goto err_free_gpio; - } - - gpio_set_value(POWER_PIN, 1);/*power on*/ - -err_free_gpio: - gpio_free(POWER_PIN); -} - -static void rk2818_power_off(void) -{ - printk("shut down system now ...\n"); - gpio_set_value(POWER_PIN, 0);/*power down*/ -} - -void lcd_set_iomux(u8 enable) -{ - int ret=-1; - - if(enable) - { - rk2818_mux_api_set(CXGPIO_HSADC_SEL_NAME, 0); - ret = gpio_request(RK2818_PIN_PA4, NULL); - if(0)//(ret != 0) - { - gpio_free(RK2818_PIN_PA4); - printk(">>>>>> lcd cs gpio_request err \n "); - goto pin_err; - } - - rk2818_mux_api_set(GPIOE_U1IR_I2C1_NAME, 0); - - ret = gpio_request(RK2818_PIN_PE7, NULL); - if(0)//(ret != 0) - { - gpio_free(RK2818_PIN_PE7); - printk(">>>>>> lcd clk gpio_request err \n "); - goto pin_err; - } - - ret = gpio_request(RK2818_PIN_PE6, NULL); - if(0)//(ret != 0) - { - gpio_free(RK2818_PIN_PE6); - printk(">>>>>> lcd txd gpio_request err \n "); - goto pin_err; - } - } - else - { - gpio_free(RK2818_PIN_PA4); - //rk2818_mux_api_set(CXGPIO_HSADC_SEL_NAME, 1); - rk2818_mux_api_mode_resume(CXGPIO_HSADC_SEL_NAME); - - gpio_free(RK2818_PIN_PE7); - gpio_free(RK2818_PIN_PE6); - //rk2818_mux_api_set(GPIOE_U1IR_I2C1_NAME, 2); - rk2818_mux_api_mode_resume(GPIOE_U1IR_I2C1_NAME); - } - return ; -pin_err: - return ; - -} - -struct lcd_td043mgea1_data lcd_td043mgea1 = { - .pin_txd = RK2818_PIN_PE6, - .pin_clk = RK2818_PIN_PE7, - .pin_cs = RK2818_PIN_PA4, - .screen_set_iomux = lcd_set_iomux, -}; - -// adc ---> key -static ADC_keyst gAdcValueTab[] = -{ - {95, AD2KEY1},///VOLUME_DOWN - {192, AD2KEY2},///VOLUME_UP - {280, AD2KEY3},///MENU - {376, AD2KEY4},///HOME - {467, AD2KEY5},///BACK - {560, AD2KEY6},///CALL - {0,0} -}; - -static unsigned char gInitKeyCode[] = -{ - AD2KEY1,AD2KEY2,AD2KEY3,AD2KEY4,AD2KEY5,AD2KEY6, - ENDCALL,KEYSTART,KEY_WAKEUP, -}; - -struct adc_key_data rk2818_adc_key = { - .pin_playon = RK2818_PIN_PA3, - .playon_level = 1, - .adc_empty = 900, - .adc_invalid = 20, - .adc_drift = 50, - .adc_chn = 1, - .adc_key_table = gAdcValueTab, - .initKeyCode = gInitKeyCode, - .adc_key_cnt = 9, -}; - -static void __init machine_rk2818_init_irq(void) -{ - rk2818_init_irq(); - rk2818_gpio_init(rk2818_gpioBank, 8); - rk2818_gpio_irq_setup(); -} - -static void __init machine_rk2818_board_init(void) -{ - rk2818_power_on(); - pm_power_off = rk2818_power_off; -#ifdef CONFIG_I2C0_RK2818 - i2c_register_board_info(default_i2c0_data.bus_num, board_i2c0_devices, - ARRAY_SIZE(board_i2c0_devices)); -#endif -#ifdef CONFIG_I2C1_RK2818 - i2c_register_board_info(default_i2c1_data.bus_num, board_i2c1_devices, - ARRAY_SIZE(board_i2c1_devices)); -#endif -#ifdef CONFIG_SPI_FPGA_I2C - i2c_register_board_info(default_i2c2_data.bus_num, board_i2c2_devices, - ARRAY_SIZE(board_i2c2_devices)); - i2c_register_board_info(default_i2c3_data.bus_num, board_i2c3_devices, - ARRAY_SIZE(board_i2c3_devices)); -#endif - platform_add_devices(devices, ARRAY_SIZE(devices)); - spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices)); - rk2818_mux_api_set(GPIOB4_SPI0CS0_MMC0D4_NAME,IOMUXA_GPIO0_B4); //IOMUXA_SPI0_CSN0);//use for gpio SPI CS0 - rk2818_mux_api_set(GPIOB0_SPI0CSN1_MMC1PCA_NAME,IOMUXA_GPIO0_B0); //IOMUXA_SPI0_CSN1);//use for gpio SPI CS1 - rk2818_mux_api_set(GPIOB_SPI0_MMC0_NAME,IOMUXA_SPI0);//use for SPI CLK SDI SDO -} - -static void __init machine_rk2818_mapio(void) -{ - iotable_init(rk2818_io_desc, ARRAY_SIZE(rk2818_io_desc)); - rk2818_clock_init(); - rk2818_iomux_init(); -} - -MACHINE_START(RK2818, "RK28board") - -/* UART for LL DEBUG */ - .phys_io = 0x18002000, - .io_pg_offst = ((0xFF100000) >> 18) & 0xfffc, - .boot_params = RK2818_SDRAM_PHYS + 0xf8000, - .map_io = machine_rk2818_mapio, - .init_irq = machine_rk2818_init_irq, - .init_machine = machine_rk2818_board_init, - .timer = &rk2818_timer, -MACHINE_END diff --git a/arch/arm/mach-rk2818/board-phonesdk.c b/arch/arm/mach-rk2818/board-phonesdk.c deleted file mode 100755 index 40155489b9e0..000000000000 --- a/arch/arm/mach-rk2818/board-phonesdk.c +++ /dev/null @@ -1,762 +0,0 @@ -/* linux/arch/arm/mach-rk2818/board-phonesdk.c - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "devices.h" - - -/* -------------------------------------------------------------------- - * ÉùÃ÷ÁËrk2818_gpioBankÊý×飬²¢¶¨ÒåÁËGPIO¼Ä´æÆ÷×éIDºÍ¼Ä´æÆ÷»ùµØÖ·¡£ - * -------------------------------------------------------------------- */ - -static struct rk2818_gpio_bank rk2818_gpioBank[] = { - { - .id = RK2818_ID_PIOA, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOB, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOC, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOD, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOE, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOF, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOG, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOH, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - } -}; - -//IOÓ³É䷽ʽÃèÊö £¬Ã¿¸öΪһ¶ÎÏßÐÔÁ¬ÐøÓ³Éä -static struct map_desc rk2818_io_desc[] __initdata = { - - { - .virtual = RK2818_MCDMA_BASE, //ÐéÄâµØÖ· - .pfn = __phys_to_pfn(RK2818_MCDMA_PHYS), //ÎïÀíµØÖ·£¬ÐëÓëÒ³±í¶ÔÆë - .length = RK2818_MCDMA_SIZE, //³¤¶È - .type = MT_DEVICE //Ó³É䷽ʽ - }, - - { - .virtual = RK2818_DWDMA_BASE, - .pfn = __phys_to_pfn(RK2818_DWDMA_PHYS), - .length = RK2818_DWDMA_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_INTC_BASE, - .pfn = __phys_to_pfn(RK2818_INTC_PHYS), - .length = RK2818_INTC_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_NANDC_BASE, - .pfn = __phys_to_pfn(RK2818_NANDC_PHYS), - .length = RK2818_NANDC_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_SDRAMC_BASE, - .pfn = __phys_to_pfn(RK2818_SDRAMC_PHYS), - .length = RK2818_SDRAMC_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_ARMDARBITER_BASE, - .pfn = __phys_to_pfn(RK2818_ARMDARBITER_PHYS), - .length = RK2818_ARMDARBITER_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_APB_BASE, - .pfn = __phys_to_pfn(RK2818_APB_PHYS), - .length = 0xa0000, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_WDT_BASE, - .pfn = __phys_to_pfn(RK2818_WDT_PHYS), - .length = 0xa0000, ///apb bus i2s i2c spi no map in this - .type = MT_DEVICE - }, -}; -/***************************************************************************************** - * SDMMC devices - *author: kfx -*****************************************************************************************/ - void rk2818_sdmmc0_cfg_gpio(struct platform_device *dev) -{ - rk2818_mux_api_set(GPIOF3_APWM1_MMC0DETN_NAME, IOMUXA_SDMMC1_DETECT_N); - rk2818_mux_api_set(GPIOH_MMC0D_SEL_NAME, IOMUXA_SDMMC0_DATA123); - rk2818_mux_api_set(GPIOH_MMC0_SEL_NAME, IOMUXA_SDMMC0_CMD_DATA0_CLKOUT); -} - -void rk2818_sdmmc1_cfg_gpio(struct platform_device *dev) -{ - rk2818_mux_api_set(GPIOG_MMC1_SEL_NAME, IOMUXA_SDMMC1_CMD_DATA0_CLKOUT); - rk2818_mux_api_set(GPIOG_MMC1D_SEL_NAME, IOMUXA_SDMMC1_DATA123); -#if 0 - /* wifi power up (gpio control) */ - rk2818_mux_api_set(GPIOH7_HSADCCLK_SEL_NAME,IOMUXB_GPIO1_D7); - rk2818_mux_api_set(GPIOF5_APWM3_DPWM3_NAME,IOMUXB_GPIO1_B5); - gpio_request(RK2818_PIN_PH7, "sdio"); - gpio_direction_output(RK2818_PIN_PH7,GPIO_HIGH); -#endif - -} -#define CONFIG_SDMMC0_USE_DMA -#define CONFIG_SDMMC1_USE_DMA -struct rk2818_sdmmc_platform_data default_sdmmc0_data = { - .host_ocr_avail = (MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30| - MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33| - MMC_VDD_33_34|MMC_VDD_34_35| MMC_VDD_35_36), - .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED), - .cfg_gpio = rk2818_sdmmc0_cfg_gpio, - .no_detect = 0, - .dma_name = "sd_mmc", -#ifdef CONFIG_SDMMC0_USE_DMA - .use_dma = 1, -#else - .use_dma = 0, -#endif -}; -struct rk2818_sdmmc_platform_data default_sdmmc1_data = { - .host_ocr_avail = (MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29| - MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32| - MMC_VDD_32_33|MMC_VDD_33_34), - .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_SDIO_IRQ| - MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED), - .cfg_gpio = rk2818_sdmmc1_cfg_gpio, - .no_detect = 1, - .dma_name = "sdio", -#ifdef CONFIG_SDMMC1_USE_DMA - .use_dma = 1, -#else - .use_dma = 0, -#endif -}; - -/***************************************************************************************** - * extern gpio devices - *author: xxx - *****************************************************************************************/ -#if defined (CONFIG_GPIO_PCA9554) -struct rk2818_gpio_expander_info extern_gpio_settinginfo[] = { - { - .gpio_num =RK2818_PIN_PI0, - .pin_type = GPIO_IN, - //.pin_value =GPIO_HIGH, - }, - - { - .gpio_num =RK2818_PIN_PI4,// tp3 - .pin_type = GPIO_IN, - //.pin_value =GPIO_HIGH, - }, - - { - .gpio_num =RK2818_PIN_PI5,//tp4 - .pin_type = GPIO_IN, - //.pin_value =GPIO_HIGH, - }, - { - .gpio_num =RK2818_PIN_PI6,//tp2 - .pin_type = GPIO_OUT, - //.pin_value =GPIO_HIGH, - }, - { - .gpio_num =RK2818_PIN_PI7,//tp1 - .pin_type = GPIO_OUT, - .pin_value =GPIO_HIGH, - }, - - - -}; - -struct pca9554_platform_data rk2818_pca9554_data={ - .gpio_base=GPIO_EXPANDER_BASE, - .gpio_pin_num=CONFIG_EXPANDED_GPIO_NUM, - .gpio_irq_start=NR_AIC_IRQS + 2*NUM_GROUP, - .irq_pin_num=CONFIG_EXPANDED_GPIO_IRQ_NUM, - .pca9954_irq_pin=RK2818_PIN_PE2, - .settinginfo=extern_gpio_settinginfo, - .settinginfolen=ARRAY_SIZE(extern_gpio_settinginfo), -}; -#endif - -/***************************************************************************************** - * I2C devices - *author: kfx -*****************************************************************************************/ - void rk2818_i2c0_cfg_gpio(struct platform_device *dev) -{ - rk2818_mux_api_set(GPIOE_I2C0_SEL_NAME, IOMUXA_I2C0); -} - -void rk2818_i2c1_cfg_gpio(struct platform_device *dev) -{ - rk2818_mux_api_set(GPIOE_U1IR_I2C1_NAME, IOMUXA_I2C1); -} -struct rk2818_i2c_platform_data default_i2c0_data = { - .bus_num = 0, - .flags = 0, - .slave_addr = 0xff, - .scl_rate = 400*1000, - .cfg_gpio = rk2818_i2c0_cfg_gpio, -}; -struct rk2818_i2c_platform_data default_i2c1_data = { -#ifdef CONFIG_I2C0_RK2818 - .bus_num = 1, -#else - .bus_num = 0, -#endif - .flags = 0, - .slave_addr = 0xff, - .scl_rate = 400*1000, - .cfg_gpio = rk2818_i2c1_cfg_gpio, -}; - -struct rk2818_i2c_spi_data default_i2c2_data = { - .bus_num = 2, - .flags = 0, - .slave_addr = 0xff, - .scl_rate = 400*1000, - -}; -struct rk2818_i2c_spi_data default_i2c3_data = { - - .bus_num = 3, - .flags = 0, - .slave_addr = 0xff, - .scl_rate = 400*1000, - -}; -static struct i2c_board_info __initdata board_i2c0_devices[] = { -#if defined (CONFIG_RK1000_CONTROL) - { - .type = "rk1000_control", - .addr = 0x40, - .flags = 0, - }, -#endif - -#if defined (CONFIG_RK1000_TVOUT) - { - .type = "rk1000_tvout", - .addr = 0x42, - .flags = 0, - }, -#endif -#if defined (CONFIG_SND_SOC_RK1000) - { - .type = "rk1000_i2c_codec", - .addr = 0x60, - .flags = 0, - }, -#endif -#if defined (CONFIG_SND_SOC_WM8988) - { - .type = "wm8988", - .addr = 0x1a, - .flags = 0, - } -#endif -}; -static struct i2c_board_info __initdata board_i2c1_devices[] = { -#if defined (CONFIG_RTC_HYM8563) - { - .type = "rtc_hym8563", - .addr = 0x51, - .flags = 0, - }, -#endif -#if defined (CONFIG_FM_QN8006) - { - .type = "fm_qn8006", - .addr = 0x2b, - .flags = 0, - }, -#endif -#if defined (CONFIG_GPIO_PCA9554) - { - .type = "extend_gpio_pca9554", - .addr = 0x3c, - .flags = 0, - .platform_data=&rk2818_pca9554_data.gpio_base, - }, -#endif -#if defined (CONFIG_PMIC_LP8725) - { - .type = "lp8725", - .addr = 0x79, - .flags = 0, - }, -#endif -#if defined (CONFIG_GS_MMA7660) - { - .type = "gs_mma7660", - .addr = 0x4c, - .flags = 0, - .irq = RK2818_PIN_PE3, - }, -#endif - {}, -}; - -static struct i2c_board_info __initdata board_i2c2_devices[] = { - -}; -static struct i2c_board_info __initdata board_i2c3_devices[] = { -#if defined (CONFIG_SND_SOC_WM8994) - { - .type = "wm8994", - .addr = 0x1a, - .flags = 0, - }, -#endif -}; - -/***************************************************************************************** - * SPI devices - *author: lhh - *****************************************************************************************/ -static struct spi_board_info board_spi_devices[] = { -#if defined(CONFIG_SPI_FPGA) - { /* fpga ice65l08xx */ - .modalias = "spi_fpga", - .chip_select = 1, - .max_speed_hz = 8 * 1000 * 1000, - .bus_num = 0, - .mode = SPI_MODE_0, - }, -#endif -#if defined(CONFIG_ENC28J60) - { /* net chip */ - .modalias = "enc28j60", - .chip_select = 1, - .max_speed_hz = 12 * 1000 * 1000, - .bus_num = 0, - .mode = SPI_MODE_0, - }, -#endif -#if defined(CONFIG_TOUCHSCREEN_XPT2046_SPI) || defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI) - { - .modalias = "xpt2046_ts", - .chip_select = 0, - .max_speed_hz = 125 * 1000 * 26,/* (max sample rate @ 3V) * (cmd + data + overhead) */ - .bus_num = 0, - .irq = RK2818_PIN_PE3, - }, -#endif -}; - -/*rk2818_fb gpio information*/ -static struct rk2818_fb_gpio rk2818_fb_gpio_info = { - .display_on = (GPIO_LOW<<16)|RK2818_PIN_PA2, - .lcd_standby = 0, - .mcu_fmk_pin = 0, -}; - -/*rk2818_fb iomux information*/ -static struct rk2818_fb_iomux rk2818_fb_iomux_info = { - .data16 = GPIOC_LCDC16BIT_SEL_NAME, - .data18 = GPIOC_LCDC18BIT_SEL_NAME, - .data24 = GPIOC_LCDC24BIT_SEL_NAME, - .den = CXGPIO_LCDDEN_SEL_NAME, - .vsync = CXGPIO_LCDVSYNC_SEL_NAME, - .mcu_fmk = 0, -}; -/*rk2818_fb*/ -struct rk2818_fb_mach_info rk2818_fb_mach_info = { - .gpio = &rk2818_fb_gpio_info, - .iomux = &rk2818_fb_iomux_info, -}; - -struct rk2818bl_info rk2818_bl_info = { - .pwm_id = 0, - .pw_pin = GPIO_HIGH | (RK2818_PIN_PF4<< 8) , - .bl_ref = 0, - .pw_iomux = GPIOF34_UART3_SEL_NAME, -}; - -/******************************************************** -* dm9000 net work devices -* author:lyx -********************************************************/ -#ifdef CONFIG_DM9000 -/* -GPIOA5_FLASHCS1_SEL_NAME IOMUXB_FLASH_CS1 -GPIOA6_FLASHCS2_SEL_NAME IOMUXB_FLASH_CS2 -GPIOA7_FLASHCS3_SEL_NAME IOMUXB_FLASH_CS3 -GPIOE_SPI1_FLASH_SEL1_NAME IOMUXA_FLASH_CS45 -GPIOE_SPI1_FLASH_SEL_NAME IOMUXA_FLASH_CS67 -*/ -#define DM9000_USE_NAND_CS 1 //cs can be 1,2,3,4,5,6 or 7 -#define DM9000_CS_IOMUX_NAME GPIOA5_FLASHCS1_SEL_NAME -#define DM9000_CS_IOMUX_MODE IOMUXB_FLASH_CS1 -#define DM9000_NET_INT_PIN RK2818_PIN_PA1 -#define DM9000_INT_IOMUX_NAME GPIOA1_HOSTDATA17_SEL_NAME -#define DM9000_INT_IOMUX_MODE IOMUXB_GPIO0_A1 -#define DM9000_INT_INIT_VALUE GPIOPullDown -#define DM9000_IRQ IRQF_TRIGGER_HIGH -#define DM9000_IO_ADDR (RK2818_NANDC_PHYS + 0x800 + DM9000_USE_NAND_CS*0x100 + 0x8) -#define DM9000_DATA_ADDR (RK2818_NANDC_PHYS + 0x800 + DM9000_USE_NAND_CS*0x100 + 0x4) - -int dm9k_gpio_set(void) -{ - //cs - rk2818_mux_api_set(DM9000_CS_IOMUX_NAME, DM9000_CS_IOMUX_MODE); - - //int - rk2818_mux_api_set(DM9000_INT_IOMUX_NAME, DM9000_INT_IOMUX_MODE); - - if (gpio_request(DM9000_NET_INT_PIN, "dm9000 interrupt")) { - gpio_free(DM9000_NET_INT_PIN); - rk2818_mux_api_mode_resume(DM9000_INT_IOMUX_NAME); - rk2818_mux_api_mode_resume(DM9000_CS_IOMUX_NAME); - printk("[fun:%s line:%d], request gpio for net interrupt fail\n", __func__,__LINE__); - - return -1; - } - gpio_pull_updown(DM9000_NET_INT_PIN, DM9000_INT_INIT_VALUE); - gpio_direction_input(DM9000_NET_INT_PIN); - - return 0; -} -int dm9k_gpio_free(void) -{ - gpio_free(DM9000_NET_INT_PIN); - rk2818_mux_api_mode_resume(DM9000_INT_IOMUX_NAME); - rk2818_mux_api_mode_resume(DM9000_CS_IOMUX_NAME); - return 0; -} -int dm9k_get_gpio_irq(void) -{ - return gpio_to_irq(DM9000_NET_INT_PIN); -} - -static struct resource dm9k_resource[] = { - [0] = { - .start = DM9000_IO_ADDR, - .end = DM9000_IO_ADDR + 3, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DM9000_DATA_ADDR, - .end = DM9000_DATA_ADDR + 3, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = DM9000_NET_INT_PIN, - .end = DM9000_NET_INT_PIN, - .flags = IORESOURCE_IRQ | DM9000_IRQ, - } - -}; - -/* for the moment we limit ourselves to 8bit IO until some - * better IO routines can be written and tested -*/ -struct dm9000_plat_data dm9k_platdata = { - .flags = DM9000_PLATF_8BITONLY, - .io_init = dm9k_gpio_set, - .io_deinit = dm9k_gpio_free, - .get_irq_num = dm9k_get_gpio_irq, -}; - -struct platform_device rk2818_device_dm9k = { - .name = "dm9000", - .id = 0, - .num_resources = ARRAY_SIZE(dm9k_resource), - .resource = dm9k_resource, - .dev = { - .platform_data = &dm9k_platdata, - } -}; -#endif - -static struct platform_device *devices[] __initdata = { -#ifdef CONFIG_UART1_RK2818 - &rk2818_device_uart1, -#endif -#ifdef CONFIG_I2C0_RK2818 - &rk2818_device_i2c0, -#endif -#ifdef CONFIG_I2C1_RK2818 - &rk2818_device_i2c1, -#endif -#ifdef CONFIG_SDMMC0_RK2818 - &rk2818_device_sdmmc0, -#endif -#ifdef CONFIG_SDMMC1_RK2818 - &rk2818_device_sdmmc1, -#endif - &rk2818_device_spim, - &rk2818_device_i2s, -#if defined(CONFIG_ANDROID_PMEM) - &rk2818_device_pmem, - &rk2818_device_pmem_dsp, -#endif - &rk2818_device_adc, - &rk2818_device_adckey, - &rk2818_device_battery, - &rk2818_device_fb, - &rk2818_device_backlight, - &rk2818_device_dsp, -#ifdef CONFIG_MTD_NAND_RK2818 - &rk2818_nand_device, -#endif -#ifdef CONFIG_DM9000 - &rk2818_device_dm9k, -#endif - -#ifdef CONFIG_DWC_OTG - &rk2818_device_dwc_otg, -#endif -#ifdef CONFIG_RK2818_HOST11 - &rk2818_device_host11, -#endif -#ifdef CONFIG_USB_ANDROID - &android_usb_device, - &usb_mass_storage_device, -#endif - -}; - -extern struct sys_timer rk2818_timer; -#define POWER_PIN RK2818_PIN_PB1 -static void rk2818_power_on(void) -{ - int ret; - ret = gpio_request(POWER_PIN, NULL); - if (ret) { - printk("failed to request power_off gpio\n"); - goto err_free_gpio; - } - - gpio_pull_updown(POWER_PIN, GPIOPullUp); - ret = gpio_direction_output(POWER_PIN, GPIO_HIGH); - if (ret) { - printk("failed to set power_off gpio output\n"); - goto err_free_gpio; - } - - gpio_set_value(POWER_PIN, 1);/*power on*/ - -err_free_gpio: - gpio_free(POWER_PIN); -} - -static void rk2818_power_off(void) -{ - printk("shut down system now ...\n"); - gpio_set_value(POWER_PIN, 0);/*power down*/ -} - -void lcd_set_iomux(u8 enable) -{ - int ret=-1; - - if(enable) - { - rk2818_mux_api_set(CXGPIO_HSADC_SEL_NAME, 0); - ret = gpio_request(RK2818_PIN_PA4, NULL); - if(0)//(ret != 0) - { - gpio_free(RK2818_PIN_PA4); - printk(">>>>>> lcd cs gpio_request err \n "); - goto pin_err; - } - - rk2818_mux_api_set(GPIOE_U1IR_I2C1_NAME, 0); - - ret = gpio_request(RK2818_PIN_PE7, NULL); - if(0)//(ret != 0) - { - gpio_free(RK2818_PIN_PE7); - printk(">>>>>> lcd clk gpio_request err \n "); - goto pin_err; - } - - ret = gpio_request(RK2818_PIN_PE6, NULL); - if(0)//(ret != 0) - { - gpio_free(RK2818_PIN_PE6); - printk(">>>>>> lcd txd gpio_request err \n "); - goto pin_err; - } - } - else - { - gpio_free(RK2818_PIN_PA4); - //rk2818_mux_api_set(CXGPIO_HSADC_SEL_NAME, 1); - rk2818_mux_api_mode_resume(CXGPIO_HSADC_SEL_NAME); - - gpio_free(RK2818_PIN_PE7); - gpio_free(RK2818_PIN_PE6); - //rk2818_mux_api_set(GPIOE_U1IR_I2C1_NAME, 2); - rk2818_mux_api_mode_resume(GPIOE_U1IR_I2C1_NAME); - } - return ; -pin_err: - return ; - -} - -struct lcd_td043mgea1_data lcd_td043mgea1 = { - .pin_txd = RK2818_PIN_PE6, - .pin_clk = RK2818_PIN_PE7, - .pin_cs = RK2818_PIN_PA4, - .screen_set_iomux = lcd_set_iomux, -}; - -// adc ---> key -static ADC_keyst gAdcValueTab[] = -{ - {95, AD2KEY1},///VOLUME_DOWN - {192, AD2KEY2},///VOLUME_UP - {280, AD2KEY3},///MENU - {376, AD2KEY4},///HOME - {467, AD2KEY5},///BACK - {560, AD2KEY6},///CALL - {0,0} -}; - -static unsigned char gInitKeyCode[] = -{ - AD2KEY1,AD2KEY2,AD2KEY3,AD2KEY4,AD2KEY5,AD2KEY6, - ENDCALL,KEYSTART,KEY_WAKEUP, -}; - -struct adc_key_data rk2818_adc_key = { - .pin_playon = RK2818_PIN_PA3, - .playon_level = 1, - .adc_empty = 900, - .adc_invalid = 20, - .adc_drift = 50, - .adc_chn = 1, - .adc_key_table = gAdcValueTab, - .initKeyCode = gInitKeyCode, - .adc_key_cnt = 9, -}; - -static void __init machine_rk2818_init_irq(void) -{ - rk2818_init_irq(); - rk2818_gpio_init(rk2818_gpioBank, 8); - rk2818_gpio_irq_setup(); -} - -static void __init machine_rk2818_board_init(void) -{ - rk2818_power_on(); - pm_power_off = rk2818_power_off; -#ifdef CONFIG_I2C0_RK2818 - i2c_register_board_info(default_i2c0_data.bus_num, board_i2c0_devices, - ARRAY_SIZE(board_i2c0_devices)); -#endif -#ifdef CONFIG_I2C1_RK2818 - i2c_register_board_info(default_i2c1_data.bus_num, board_i2c1_devices, - ARRAY_SIZE(board_i2c1_devices)); -#endif -#ifdef CONFIG_SPI_FPGA_I2C - i2c_register_board_info(default_i2c2_data.bus_num, board_i2c2_devices, - ARRAY_SIZE(board_i2c2_devices)); - i2c_register_board_info(default_i2c3_data.bus_num, board_i2c3_devices, - ARRAY_SIZE(board_i2c3_devices)); -#endif - platform_add_devices(devices, ARRAY_SIZE(devices)); - spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices)); - rk2818_mux_api_set(GPIOB4_SPI0CS0_MMC0D4_NAME,IOMUXA_GPIO0_B4); //IOMUXA_SPI0_CSN0);//use for gpio SPI CS0 - rk2818_mux_api_set(GPIOB0_SPI0CSN1_MMC1PCA_NAME,IOMUXA_GPIO0_B0); //IOMUXA_SPI0_CSN1);//use for gpio SPI CS1 - rk2818_mux_api_set(GPIOB_SPI0_MMC0_NAME,IOMUXA_SPI0);//use for SPI CLK SDI SDO -} - -static void __init machine_rk2818_mapio(void) -{ - iotable_init(rk2818_io_desc, ARRAY_SIZE(rk2818_io_desc)); - rk2818_clock_init(); - rk2818_iomux_init(); -} - -MACHINE_START(RK2818, "RK28board") - -/* UART for LL DEBUG */ - .phys_io = 0x18002000, - .io_pg_offst = ((0xFF100000) >> 18) & 0xfffc, - .boot_params = RK2818_SDRAM_PHYS + 0xf8000, - .map_io = machine_rk2818_mapio, - .init_irq = machine_rk2818_init_irq, - .init_machine = machine_rk2818_board_init, - .timer = &rk2818_timer, -MACHINE_END - diff --git a/arch/arm/mach-rk2818/board-raho-rfkill.c b/arch/arm/mach-rk2818/board-raho-rfkill.c deleted file mode 100755 index 9182d47fb8fc..000000000000 --- a/arch/arm/mach-rk2818/board-raho-rfkill.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (C) 2010 ROCKCHIP, Inc. - * Author: roger_chen - * - * This program is the bluetooth device bcm4329's driver, - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -//#include -//#include -//#include -//#include -#include -#include -#include -#include -#include -#include - -#if 1 -#define DBG(x...) printk(KERN_INFO x) -#else -#define DBG(x...) -#endif - -#define RAHO_BT_GPIO_POWER_N FPGA_PIO1_06 -#define RAHO_BT_GPIO_RESET_N FPGA_PIO1_07 -#define RAHO_BT_GPIO_WAKE_UP_N RK2818_PIN_PC6 - -static struct rfkill *bt_rfk; -static const char bt_name[] = "bcm4329"; -extern int raho_bt_power_state; -extern int raho_wifi_power_state; -#ifdef CONFIG_BT_HCIBCM4325 -int bcm4325_sleep(int bSleep) -{ -// printk("*************bt enter sleep***************\n"); - if (bSleep) - gpio_set_value(RAHO_BT_GPIO_WAKE_UP_N, GPIO_LOW); //low represent bt device may enter sleep - else - gpio_set_value(RAHO_BT_GPIO_WAKE_UP_N, GPIO_HIGH); //high represent bt device must be awake -} -#endif - -static int bcm4329_set_block(void *data, bool blocked) -{ - DBG("%s---blocked :%d\n", __FUNCTION__, blocked); - - if (false == blocked) { - gpio_set_value(RAHO_BT_GPIO_POWER_N, GPIO_HIGH); /* bt power on */ - gpio_set_value(RAHO_BT_GPIO_RESET_N, GPIO_HIGH); /* bt reset deactive*/ - mdelay(20); - pr_info("bt turn on power\n"); - } - else { - if (!raho_wifi_power_state) { - gpio_set_value(RAHO_BT_GPIO_POWER_N, GPIO_LOW); /* bt power off */ - mdelay(20); - pr_info("bt shut off power\n"); - }else { - pr_info("bt shouldn't shut off power, wifi is using it!\n"); - } - - gpio_set_value(RAHO_BT_GPIO_RESET_N, GPIO_LOW); /* bt reset active*/ - mdelay(20); - } - - raho_bt_power_state = !blocked; - return 0; -} - - -static const struct rfkill_ops bcm4329_rfk_ops = { - .set_block = bcm4329_set_block, -}; - -static int __init bcm4329_rfkill_probe(struct platform_device *pdev) -{ - int rc = 0; - bool default_state = true; - - DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__); - - /* default to bluetooth off */ - bcm4329_set_block(NULL, default_state); /* blocked -> bt off */ - - bt_rfk = rfkill_alloc(bt_name, - NULL, - RFKILL_TYPE_BLUETOOTH, - &bcm4329_rfk_ops, - NULL); - - if (!bt_rfk) - { - printk("fail to rfkill_allocate************\n"); - return -ENOMEM; - } - - rfkill_set_states(bt_rfk, default_state, false); - - rc = rfkill_register(bt_rfk); - if (rc) - rfkill_destroy(bt_rfk); - - printk("rc=0x%x\n", rc); - - return rc; -} - - -static int __devexit bcm4329_rfkill_remove(struct platform_device *pdev) -{ - if (bt_rfk) - rfkill_unregister(bt_rfk); - bt_rfk = NULL; - - platform_set_drvdata(pdev, NULL); - DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__); - return 0; -} - -static struct platform_driver bcm4329_rfkill_driver = { - .probe = bcm4329_rfkill_probe, - .remove = __devexit_p(bcm4329_rfkill_remove), - .driver = { - .name = "raho_rfkill", - .owner = THIS_MODULE, - }, -}; - -/* - * Module initialization - */ -static int __init bcm4329_mod_init(void) -{ - int ret; - DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__); - ret = platform_driver_register(&bcm4329_rfkill_driver); - printk("ret=0x%x\n", ret); - return ret; -} - -static void __exit bcm4329_mod_exit(void) -{ - platform_driver_unregister(&bcm4329_rfkill_driver); -} - -module_init(bcm4329_mod_init); -module_exit(bcm4329_mod_exit); -MODULE_DESCRIPTION("bcm4329 Bluetooth driver"); -MODULE_AUTHOR("roger_chen cz@rock-chips.com"); -MODULE_LICENSE("GPL"); - diff --git a/arch/arm/mach-rk2818/board-raho.c b/arch/arm/mach-rk2818/board-raho.c deleted file mode 100755 index 851f115fc540..000000000000 --- a/arch/arm/mach-rk2818/board-raho.c +++ /dev/null @@ -1,2402 +0,0 @@ -/* linux/arch/arm/mach-rk2818/board-phonesdk.c - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include /* ddl@rock-chips.com : camera support */ -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include /* ddl@rock-chips.com : camera support */ - - -#include "devices.h" - -#include "../../../drivers/spi/rk2818_spim.h" -#include -#include "../../../drivers/input/touchscreen/xpt2046_ts.h" -#include "../../../drivers/staging/android/timed_gpio.h" -#include "../../../sound/soc/codecs/wm8994.h" -#include "../../../drivers/headset_observe/rk2818_headset.h" -#include -#include - -#include "../../../drivers/cmmb/siano/smsspiphy.h" -/* -------------------------------------------------------------------- - * ÉùÃ÷ÁËrk2818_gpioBankÊý×飬²¢¶¨ÒåÁËGPIO¼Ä´æÆ÷×éIDºÍ¼Ä´æÆ÷»ùµØÖ·¡£ - * -------------------------------------------------------------------- */ - -static struct rk2818_gpio_bank rk2818_gpioBank[] = { - { - .id = RK2818_ID_PIOA, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOB, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOC, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOD, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOE, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOF, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOG, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOH, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - } -}; - -//IOÓ³É䷽ʽÃèÊö £¬Ã¿¸öΪһ¶ÎÏßÐÔÁ¬ÐøÓ³Éä -static struct map_desc rk2818_io_desc[] __initdata = { - - { - .virtual = RK2818_MCDMA_BASE, //ÐéÄâµØÖ· - .pfn = __phys_to_pfn(RK2818_MCDMA_PHYS), //ÎïÀíµØÖ·£¬ÐëÓëÒ³±í¶ÔÆë - .length = RK2818_MCDMA_SIZE, //³¤¶È - .type = MT_DEVICE //Ó³É䷽ʽ - }, - - { - .virtual = RK2818_DWDMA_BASE, - .pfn = __phys_to_pfn(RK2818_DWDMA_PHYS), - .length = RK2818_DWDMA_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_INTC_BASE, - .pfn = __phys_to_pfn(RK2818_INTC_PHYS), - .length = RK2818_INTC_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_NANDC_BASE, - .pfn = __phys_to_pfn(RK2818_NANDC_PHYS), - .length = RK2818_NANDC_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_SDRAMC_BASE, - .pfn = __phys_to_pfn(RK2818_SDRAMC_PHYS), - .length = RK2818_SDRAMC_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_ARMDARBITER_BASE, - .pfn = __phys_to_pfn(RK2818_ARMDARBITER_PHYS), - .length = RK2818_ARMDARBITER_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_APB_BASE, - .pfn = __phys_to_pfn(RK2818_APB_PHYS), - .length = 0xa0000, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_WDT_BASE, - .pfn = __phys_to_pfn(RK2818_WDT_PHYS), - .length = 0xa0000, ///apb bus i2s i2c spi no map in this - .type = MT_DEVICE - }, -}; - -/***************************************************************************************** - * sd/mmc devices - * author: kfx@rock-chips.com -*****************************************************************************************/ -static int rk2818_sdmmc0_io_init(void) -{ - rk2818_mux_api_set(GPIOH_MMC0D_SEL_NAME, IOMUXA_SDMMC0_DATA123); - rk2818_mux_api_set(GPIOH_MMC0_SEL_NAME, IOMUXA_SDMMC0_CMD_DATA0_CLKOUT); - - return 0; -} - -static int rk2818_sdmmc1_io_init(void) -{ - rk2818_mux_api_set(GPIOG_MMC1_SEL_NAME, IOMUXA_SDMMC1_CMD_DATA0_CLKOUT); - rk2818_mux_api_set(GPIOG_MMC1D_SEL_NAME, IOMUXA_SDMMC1_DATA123); - - return 0; -} -#define CONFIG_SDMMC0_USE_DMA -#define CONFIG_SDMMC1_USE_DMA -struct rk2818_sdmmc_platform_data default_sdmmc0_data = { - .host_ocr_avail = (MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30| - MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33| - MMC_VDD_33_34|MMC_VDD_34_35| MMC_VDD_35_36), - .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED), - .io_init = rk2818_sdmmc0_io_init, - .no_detect = 0, - .dma_name = "sd_mmc", -#ifdef CONFIG_SDMMC0_USE_DMA - .use_dma = 1, -#else - .use_dma = 0, -#endif -}; - -static int raho_wifi_status(struct device *dev); -static int raho_wifi_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id); -struct rk2818_sdmmc_platform_data default_sdmmc1_data = { - .host_ocr_avail = (MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29| - MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32| - MMC_VDD_32_33|MMC_VDD_33_34), - .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_SDIO_IRQ| - MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED), - .io_init = rk2818_sdmmc1_io_init, - .no_detect = 1, - .dma_name = "sdio", -#ifdef CONFIG_SDMMC1_USE_DMA - .use_dma = 1, -#else - .use_dma = 0, -#endif - .status = raho_wifi_status, - .register_status_notify = raho_wifi_status_register, -}; - -static int raho_wifi_cd; /* wifi virtual 'card detect' status */ -static void (*wifi_status_cb)(int card_present, void *dev_id); -static void *wifi_status_cb_devid; - -static int raho_wifi_status(struct device *dev) -{ - return raho_wifi_cd; -} - -static int raho_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id) -{ - if(wifi_status_cb) - return -EAGAIN; - wifi_status_cb = callback; - wifi_status_cb_devid = dev_id; - return 0; -} - -#define RAHO_WIFI_GPIO_POWER_N FPGA_PIO1_06 -#define RAHO_WIFI_GPIO_RESET_N FPGA_PIO1_03 - -int raho_wifi_power_state = 0; -int raho_bt_power_state = 0; - -static int raho_wifi_power(int on) -{ - pr_info("%s: %d\n", __func__, on); - if (on){ - gpio_set_value(RAHO_WIFI_GPIO_POWER_N, on); - mdelay(100); - pr_info("wifi turn on power\n"); - }else{ - if (!raho_bt_power_state){ - gpio_set_value(RAHO_WIFI_GPIO_POWER_N, on); - mdelay(100); - pr_info("wifi shut off power\n"); - }else - { - pr_info("wifi shouldn't shut off power, bt is using it!\n"); - } - - } - - raho_wifi_power_state = on; - return 0; -} - -static int raho_wifi_reset_state; -static int raho_wifi_reset(int on) -{ - pr_info("%s: %d\n", __func__, on); - gpio_set_value(RAHO_WIFI_GPIO_RESET_N, on); - mdelay(100); - raho_wifi_reset_state = on; - return 0; -} - -static int raho_wifi_set_carddetect(int val) -{ - pr_info("%s:%d\n", __func__, val); - raho_wifi_cd = val; - if (wifi_status_cb){ - wifi_status_cb(val, wifi_status_cb_devid); - }else { - pr_warning("%s, nobody to notify\n", __func__); - } - return 0; -} - -static struct wifi_platform_data raho_wifi_control = { - .set_power = raho_wifi_power, - .set_reset = raho_wifi_reset, - .set_carddetect = raho_wifi_set_carddetect, -}; -static struct platform_device raho_wifi_device = { - .name = "bcm4329_wlan", - .id = 1, - .dev = { - .platform_data = &raho_wifi_control, - }, -}; - -/* bluetooth rfkill device */ -static struct platform_device raho_rfkill = { - .name = "raho_rfkill", - .id = -1, -}; - -/***************************************************************************************** - * extern gpio devices - * author: xxx@rock-chips.com - *****************************************************************************************/ -#if defined (CONFIG_GPIO_PCA9554) -struct rk2818_gpio_expander_info extern_gpio_settinginfo[] = { - { - .gpio_num =RK2818_PIN_PI0, - .pin_type = GPIO_IN, - //.pin_value =GPIO_HIGH, - }, - - { - .gpio_num =RK2818_PIN_PI4,// tp3 - .pin_type = GPIO_IN, - //.pin_value =GPIO_HIGH, - }, - - { - .gpio_num =RK2818_PIN_PI5,//tp4 - .pin_type = GPIO_IN, - //.pin_value =GPIO_HIGH, - }, - { - .gpio_num =RK2818_PIN_PI6,//tp2 - .pin_type = GPIO_OUT, - //.pin_value =GPIO_HIGH, - }, - { - .gpio_num =RK2818_PIN_PI7,//tp1 - .pin_type = GPIO_OUT, - .pin_value =GPIO_HIGH, - }, - - - -}; - -struct pca9554_platform_data rk2818_pca9554_data={ - .gpio_base=GPIO_EXPANDER_BASE, - .gpio_pin_num=CONFIG_EXPANDED_GPIO_NUM, - .gpio_irq_start=NR_AIC_IRQS + 2*NUM_GROUP, - .irq_pin_num=CONFIG_EXPANDED_GPIO_IRQ_NUM, - .pca9954_irq_pin=RK2818_PIN_PE2, - .settinginfo=extern_gpio_settinginfo, - .settinginfolen=ARRAY_SIZE(extern_gpio_settinginfo), -}; -#endif - -/***************************************************************************************** - *regulator devices drivers/regulator/rk2818_lp8725.c linux/regulator/rk2818_lp8725.h - *author: cym -*****************************************************************************************/ -#if defined (CONFIG_RK2818_REGULATOR_LP8725) - -/*DVS pin control, make sure it is high level at start.*/ -int rk2818_lp8725_pm_control(void) -{ - rk2818_mux_api_set(GPIOC_LCDC24BIT_SEL_NAME, IOMUXB_GPIO0_C2_7); - gpio_request(RK2818_PIN_PC2,NULL); - gpio_direction_output(RK2818_PIN_PC2,1); - gpio_set_value(RK2818_PIN_PC2,1); - return 0; -} - -/*ldo1 2V8OUT USB2.5V LCD_VCC*/ -static struct regulator_consumer_supply ldo1_consumers[] = { - { - .supply = "ldo1", - } -}; - -static struct regulator_init_data rk2818_lp8725_ldo1_data = { - .constraints = { - .name = "LDO1", - .min_uV = 1200000, - .max_uV = 3300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo1_consumers), - .consumer_supplies = ldo1_consumers, -}; - -/*ldo2 CAMERA_1V8 SD_CARD*/ -static struct regulator_consumer_supply ldo2_consumers[] = { - { - .supply = "ldo2", - } -}; - -static struct regulator_init_data rk2818_lp8725_ldo2_data = { - .constraints = { - .name = "LDO2", - .min_uV = 1200000, - .max_uV = 3300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers), - .consumer_supplies = ldo2_consumers, -}; - -/*ldo3 VCC_NAND WIFI/BT/FM_BCM4325*/ -static struct regulator_consumer_supply ldo3_consumers[] = { - { - .supply = "ldo3", - } -}; - -static struct regulator_init_data rk2818_lp8725_ldo3_data = { - .constraints = { - .name = "LDO3", - .min_uV = 1200000, - .max_uV = 3300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo3_consumers), - .consumer_supplies = ldo3_consumers, -}; - -/*ldo4 VCCA CODEC_WM8994*/ -static struct regulator_consumer_supply ldo4_consumers[] = { - { - .supply = "ldo4", - } -}; - -static struct regulator_init_data rk2818_lp8725_ldo4_data = { - .constraints = { - .name = "LDO4", - .min_uV = 1200000, - .max_uV = 3300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo4_consumers), - .consumer_supplies = ldo4_consumers, -}; - -/*ldo5 AVDD18 CODEC_WM8994*/ -static struct regulator_consumer_supply ldo5_consumers[] = { - { - .supply = "ldo5", - } -}; - -static struct regulator_init_data rk2818_lp8725_ldo5_data = { - .constraints = { - .name = "LDO5", - .min_uV = 1200000, - .max_uV = 3300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo5_consumers), - .consumer_supplies = ldo5_consumers, -}; - -/*lilo1 VCCIO Sensor£¨3M£©*/ -static struct regulator_consumer_supply lilo1_consumers[] = { - { - .supply = "lilo1", - } -}; - -static struct regulator_init_data rk2818_lp8725_lilo1_data = { - .constraints = { - .name = "LILO1", - .min_uV = 800000, - .max_uV = 3300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(lilo1_consumers), - .consumer_supplies = lilo1_consumers -}; - -/*lilo2 VCC33_SD Sensor£¨3M£©*/ -static struct regulator_consumer_supply lilo2_consumers[] = { - { - .supply = "lilo2", - } -}; - -static struct regulator_init_data rk2818_lp8725_lilo2_data = { - .constraints = { - .name = "LILO2", - .min_uV = 800000, - .max_uV = 3300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(lilo2_consumers), - .consumer_supplies = lilo2_consumers -}; - -/*buck1 VDD12 Core*/ -static struct regulator_consumer_supply buck1_consumers[] = { - { - .supply = "vdd12", - } -}; - -static struct regulator_init_data rk2818_lp8725_buck1_data = { - .constraints = { - .name = "VDD12", - .min_uV = 800000, - .max_uV = 1500000, - .apply_uV = 1, - .always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE, - .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL, - }, - .num_consumer_supplies = ARRAY_SIZE(buck1_consumers), - .consumer_supplies = buck1_consumers -}; - -/*buck2 VDDDR MobileDDR VCC*/ -static struct regulator_consumer_supply buck2_consumers[] = { - { - .supply = "vccdr", - } -}; - -static struct regulator_init_data rk2818_lp8725_buck2_data = { - .constraints = { - .name = "VCCDR", - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = 1, - .always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(buck2_consumers), - .consumer_supplies = buck2_consumers -}; - -/*buck1_v2 VDD12 Core*/ -static struct regulator_consumer_supply buck1_v2_consumers[] = { - { - .supply = "vdd12_v2", - } -}; - -static struct regulator_init_data rk2818_lp8725_buck1_v2_data = { - .constraints = { - .name = "VDD12_V2", - .min_uV = 800000, - .max_uV = 1500000, - .apply_uV = 1, - //.always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE, - }, - .num_consumer_supplies = ARRAY_SIZE(buck1_v2_consumers), - .consumer_supplies = buck1_v2_consumers -}; - -/*buck2_v2 VDDDR MobileDDR VCC*/ -static struct regulator_consumer_supply buck2_v2_consumers[] = { - { - .supply = "vccdr_v2", - } -}; - -static struct regulator_init_data rk2818_lp8725_buck2_v2_data = { - .constraints = { - .name = "VCCDR_V2", - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = 1, - //.always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(buck2_v2_consumers), - .consumer_supplies = buck2_v2_consumers -}; - -struct lp8725_regulator_subdev rk2818_lp8725_regulator_subdev[] = { - { - .id=LP8725_LDO1, - .initdata=&rk2818_lp8725_ldo1_data, - }, - - { - .id=LP8725_LDO2, - .initdata=&rk2818_lp8725_ldo2_data, - }, - - { - .id=LP8725_LDO3, - .initdata=&rk2818_lp8725_ldo3_data, - }, - - { - .id=LP8725_LDO4, - .initdata=&rk2818_lp8725_ldo4_data, - }, - - { - .id=LP8725_LDO5, - .initdata=&rk2818_lp8725_ldo5_data, - }, - - { - .id=LP8725_LILO1, - .initdata=&rk2818_lp8725_lilo1_data, - }, - - { - .id=LP8725_LILO2, - .initdata=&rk2818_lp8725_lilo2_data, - }, - - { - .id=LP8725_DCDC1, - .initdata=&rk2818_lp8725_buck1_data, - }, - - { - .id=LP8725_DCDC2, - .initdata=&rk2818_lp8725_buck2_data, - }, - { - .id=LP8725_DCDC1_V2, - .initdata=&rk2818_lp8725_buck1_v2_data, - }, - - { - .id=LP8725_DCDC2_V2, - .initdata=&rk2818_lp8725_buck2_v2_data, - }, -}; - -struct lp8725_platform_data rk2818_lp8725_data={ - .num_regulators=LP8725_NUM_REGULATORS, - .regulators=rk2818_lp8725_regulator_subdev, -}; -#endif - -/***************************************************************************************** - * gsensor devices -*****************************************************************************************/ -#define GS_IRQ_PIN RK2818_PIN_PE3 - -struct rk2818_gs_platform_data rk2818_gs_platdata = { - .gsensor_irq_pin = GS_IRQ_PIN, - .swap_xy = 0, -}; - -/***************************************************************************************** - * wm8994 codec - * author: cjq@rock-chips.com - *****************************************************************************************/ -static struct wm8994_platform_data wm8994_data = { - .mic_input = 0, - .micBase_vcc = 0, - .bb_input = 0, - .bb_output = 0, - .frequence = 0, - .enable_pin = 0, - .headset_pin = 0, - .headset_call_vol = 0, - .speaker_call_vol = 0, - .earpiece_call_vol = 0, - .bt_call_vol = 0, -};// must initialize - -/***************************************************************************************** - * rtc - *****************************************************************************************/ -#define RTC_IRQ_PIN RK2818_PIN_PE2 - -static int rk2818_rtc_io_init(void) -{ - return 0; -} - -static int rk2818_rtc_io_deinit(void) -{ - return 0; -} - -static struct rk2818_rtc_platform_data rtc_data = { - .irq_type = GPIO_LOW,//irq type - .io_init = rk2818_rtc_io_init, - .io_deinit = rk2818_rtc_io_deinit, -}; - -/***************************************************************************************** - * i2c devices - * author: kfx@rock-chips.com -*****************************************************************************************/ -static int rk2818_i2c0_io_init(void) -{ - rk2818_mux_api_set(GPIOE_I2C0_SEL_NAME, IOMUXA_I2C0); - return 0; -} - -static int rk2818_i2c1_io_init(void) -{ - rk2818_mux_api_set(GPIOE_U1IR_I2C1_NAME, IOMUXA_I2C1); - return 0; -} - -struct rk2818_i2c_platform_data default_i2c0_data = { - .bus_num = 0, - .flags = 0, - .slave_addr = 0xff, - .scl_rate = 400*1000, - .mode = I2C_MODE_IRQ, //I2C_MODE_POLL - .io_init = rk2818_i2c0_io_init, -}; -struct rk2818_i2c_platform_data default_i2c1_data = { -#ifdef CONFIG_I2C0_RK2818 - .bus_num = 1, -#else - .bus_num = 0, -#endif - .flags = 0, - .slave_addr = 0xff, - .scl_rate = 400*1000, - .mode = I2C_MODE_POLL, //I2C_MODE_POLL - .io_init = rk2818_i2c1_io_init, -}; - -struct rk2818_i2c_spi_data default_i2c2_data = { - .bus_num = 2, - .flags = 0, - .slave_addr = 0xff, - .scl_rate = 400*1000, - -}; -struct rk2818_i2c_spi_data default_i2c3_data = { - - .bus_num = 3, - .flags = 0, - .slave_addr = 0xff, - .scl_rate = 400*1000, - -}; -static struct i2c_board_info __initdata board_i2c0_devices[] = { -#if defined (CONFIG_RK1000_CONTROL) - { - .type = "rk1000_control", - .addr = 0x40, - .flags = 0, - }, -#endif - -#if defined (CONFIG_RK1000_TVOUT) - { - .type = "rk1000_tvout", - .addr = 0x42, - .flags = 0, - }, -#endif -#if defined (CONFIG_SND_SOC_RK1000) - { - .type = "rk1000_i2c_codec", - .addr = 0x60, - .flags = 0, - }, -#endif -#if defined (CONFIG_SND_SOC_WM8988) - { - .type = "wm8988", - .addr = 0x1a, - .flags = 0, - } -#endif -#if defined (CONFIG_TOUCHSCREEN_IT7250) //add by robert for ctp_it7250 - { - .type = "Ctp_it7250", - .addr = 0x46, - .flags = 0, - .irq = RK2818_PIN_PE1, - }, -#endif //end add -}; -static struct i2c_board_info __initdata board_i2c1_devices[] = { -#if defined (CONFIG_RTC_HYM8563) - { - .type = "rtc_hym8563", - .addr = 0x51, - .flags = 0, - }, -#endif -#if defined (CONFIG_RTC_DRV_S35392A) - { - .type = "rtc-s35392a", - .addr = 0x30, - .flags = 0, - .irq = RTC_IRQ_PIN, - .platform_data = &rtc_data, - }, -#endif -#if defined (CONFIG_FM_QN8006) - { - .type = "fm_qn8006", - .addr = 0x2b, - .flags = 0, - }, -#endif -#if defined (CONFIG_GPIO_PCA9554) - { - .type = "extend_gpio_pca9554", - .addr = 0x3c, - .flags = 0, - .platform_data=&rk2818_pca9554_data.gpio_base, - }, -#endif -#if defined (CONFIG_RK2818_REGULATOR_LP8725) - { - .type = "lp8725", - .addr = 0x79, - .flags = 0, - .platform_data=&rk2818_lp8725_data, - }, -#endif -#if defined (CONFIG_GS_MMA7660) - { - .type = "gs_mma7660", - .addr = 0x4c, - .flags = 0, - .irq = GS_IRQ_PIN, - .platform_data = &rk2818_gs_platdata, - }, -#endif - -}; - -static struct i2c_board_info __initdata board_i2c2_devices[] = { - -}; - -static struct i2c_board_info __initdata board_i2c3_devices[] = { -#if defined (CONFIG_SND_SOC_WM8994) - { - .type = "wm8994", - .addr = 0x1a, - .flags = 0, - .platform_data = &wm8994_data, - }, -#endif -}; - -/* - * External power - */ - -static int power_supply_init(struct device *dev) -{ - return gpio_request(FPGA_PIO2_08, "AC charger detect"); -} - -static int rk2818_is_ac_online(void) -{ - return !gpio_get_value(FPGA_PIO2_08); -} - -static void power_supply_exit(struct device *dev) -{ - gpio_free(FPGA_PIO2_08); -} - -static char *rk2818_supplicant[] = { - "rk2818-battery" -}; - -static struct pda_power_pdata power_supply_info = { - .init = power_supply_init, - .is_ac_online = rk2818_is_ac_online, - .exit = power_supply_exit, - .supplied_to = rk2818_supplicant, - .num_supplicants = ARRAY_SIZE(rk2818_supplicant), -}; - -static struct resource power_supply_resources[] = { - [0] = { - .name = "ac", - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | - IORESOURCE_IRQ_LOWEDGE, - }, - [1] = { - .name = "usb", - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | - IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct platform_device power_supply = { - .name = "pda-power", - .id = -1, - .dev = { - .platform_data = &power_supply_info, - }, - .resource = power_supply_resources, - .num_resources = ARRAY_SIZE(power_supply_resources), -}; - -/* - * USB "Transceiver" - */ - -static struct resource gpio_vbus_resource = { - .flags = IORESOURCE_IRQ, - .start = IRQ_NR_OTG, - .end = IRQ_NR_OTG, -}; - -static struct gpio_vbus_mach_info gpio_vbus_info = { - .gpio_vbus = FPGA_PIO4_06, -}; - -static struct platform_device gpio_vbus = { - .name = "gpio-vbus", - .id = -1, - .num_resources = 1, - .resource = &gpio_vbus_resource, - .dev = { - .platform_data = &gpio_vbus_info, - }, -}; - -/* - * Battery charger - */ - -static struct regulator_consumer_supply rk2818_consumers[] = { - { - .dev=&rk2818_device_battery.dev, - .supply = "battery", - }, - { - .dev = &gpio_vbus.dev, - .supply = "vbus_draw", - }, - { - .dev = &power_supply.dev, - .supply = "ac_draw", - }, -}; - -static struct regulator_init_data charge_init_data = { - .constraints = { - .max_uA = 1200000, - .valid_ops_mask = REGULATOR_CHANGE_CURRENT, - }, - .num_consumer_supplies = ARRAY_SIZE(rk2818_consumers), - .consumer_supplies = rk2818_consumers, -}; - -static struct charge_platform_data charge_current_info = { - .gpio_charge = FPGA_PIO2_08, - .init_data = &charge_init_data, -}; - -static struct platform_device charge_current = { - .name = "charge-regulator", - .id = -1, - .dev = { - .platform_data = &charge_current_info, - }, -}; - -/***************************************************************************************** - * camera devices - * author: ddl@rock-chips.com - *****************************************************************************************/ -#ifdef CONFIG_VIDEO_RK2818 -/* Board-raho camera configuration */ -#define SENSOR_NAME_0 RK28_CAM_SENSOR_NAME_OV2655 -#define SENSOR_IIC_ADDR_0 0x60 -#define SENSOR_IIC_ADAPTER_ID_0 2 -#define SENSOR_POWER_PIN_0 FPGA_PIO1_05 -#define SENSOR_RESET_PIN_0 FPGA_PIO1_14 -#define SENSOR_POWERACTIVE_LEVEL_0 RK28_CAM_POWERACTIVE_L -#define SENSOR_RESETACTIVE_LEVEL_0 RK28_CAM_RESETACTIVE_L - - -#define SENSOR_NAME_1 NULL -#define SENSOR_IIC_ADDR_1 0x00 -#define SENSOR_IIC_ADAPTER_ID_1 0xff -#define SENSOR_POWER_PIN_1 INVALID_GPIO -#define SENSOR_RESET_PIN_1 INVALID_GPIO -#define SENSOR_POWERACTIVE_LEVEL_1 RK28_CAM_POWERACTIVE_L -#define SENSOR_RESETACTIVE_LEVEL_1 RK28_CAM_RESETACTIVE_L - -static int rk28_sensor_io_init(void); -static int rk28_sensor_io_deinit(void); - -struct rk28camera_platform_data rk28_camera_platform_data = { - .io_init = rk28_sensor_io_init, - .io_deinit = rk28_sensor_io_deinit, - .gpio_res = { - { - .gpio_reset = SENSOR_RESET_PIN_0, - .gpio_power = SENSOR_POWER_PIN_0, - .gpio_flag = (SENSOR_POWERACTIVE_LEVEL_0|SENSOR_RESETACTIVE_LEVEL_0), - .dev_name = SENSOR_NAME_0, - }, { - .gpio_reset = SENSOR_RESET_PIN_1, - .gpio_power = SENSOR_POWER_PIN_1, - .gpio_flag = (SENSOR_POWERACTIVE_LEVEL_1|SENSOR_RESETACTIVE_LEVEL_1), - .dev_name = SENSOR_NAME_1, - } - } -}; - -static int rk28_sensor_io_init(void) -{ - int ret = 0, i; - unsigned int camera_reset = INVALID_GPIO, camera_power = INVALID_GPIO; - unsigned int camera_ioflag; - //printk("\n%s....%d ******** ddl *********\n",__FUNCTION__,__LINE__); - - for (i=0; i<2; i++) { - camera_reset = rk28_camera_platform_data.gpio_res[i].gpio_reset; - camera_power = rk28_camera_platform_data.gpio_res[i].gpio_power; - camera_ioflag = rk28_camera_platform_data.gpio_res[i].gpio_flag; - - if (camera_power != INVALID_GPIO) { - ret = gpio_request(camera_power, "camera power"); - if (ret) - continue; - - gpio_set_value(camera_reset, (((~camera_ioflag)&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - gpio_direction_output(camera_power, (((~camera_ioflag)&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - - //printk("\n%s....%d %x ******** ddl *********\n",__FUNCTION__,__LINE__,(((~camera_ioflag)&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - - } - - if (camera_reset != INVALID_GPIO) { - ret = gpio_request(camera_reset, "camera reset"); - if (ret) { - if (camera_power != INVALID_GPIO) - gpio_free(camera_power); - - continue; - } - - gpio_set_value(camera_reset, ((camera_ioflag&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - gpio_direction_output(camera_reset, ((camera_ioflag&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - - //printk("\n%s....%d %x ******** ddl *********\n",__FUNCTION__,__LINE__,((camera_ioflag&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - - } - } - - return 0; -} - -static int rk28_sensor_io_deinit(void) -{ - unsigned int i; - unsigned int camera_reset = INVALID_GPIO, camera_power = INVALID_GPIO; - - //printk("\n%s....%d ******** ddl *********\n",__FUNCTION__,__LINE__); - - for (i=0; i<2; i++) { - camera_reset = rk28_camera_platform_data.gpio_res[i].gpio_reset; - camera_power = rk28_camera_platform_data.gpio_res[i].gpio_power; - - if (camera_power != INVALID_GPIO){ - gpio_direction_input(camera_power); - gpio_free(camera_power); - } - - if (camera_reset != INVALID_GPIO) { - gpio_direction_input(camera_reset); - gpio_free(camera_reset); - } - } - - return 0; -} - - -static int rk28_sensor_power(struct device *dev, int on) -{ - unsigned int camera_reset = INVALID_GPIO, camera_power = INVALID_GPIO; - unsigned int camera_ioflag; - - if(rk28_camera_platform_data.gpio_res[0].dev_name && (strcmp(rk28_camera_platform_data.gpio_res[0].dev_name, dev_name(dev)) == 0)) { - camera_reset = rk28_camera_platform_data.gpio_res[0].gpio_reset; - camera_power = rk28_camera_platform_data.gpio_res[0].gpio_power; - camera_ioflag = rk28_camera_platform_data.gpio_res[0].gpio_flag; - } else if (rk28_camera_platform_data.gpio_res[1].dev_name && (strcmp(rk28_camera_platform_data.gpio_res[1].dev_name, dev_name(dev)) == 0)) { - camera_reset = rk28_camera_platform_data.gpio_res[1].gpio_reset; - camera_power = rk28_camera_platform_data.gpio_res[1].gpio_power; - camera_ioflag = rk28_camera_platform_data.gpio_res[1].gpio_flag; - } - - if (camera_reset != INVALID_GPIO) { - gpio_set_value(camera_reset, ((camera_ioflag&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - //printk("\n%s..%s..ResetPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev),camera_reset, ((camera_ioflag&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - } - if (camera_power != INVALID_GPIO) { - if (on) { - gpio_set_value(camera_power, ((camera_ioflag&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - //printk("\n%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev), camera_power, ((camera_ioflag&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - } else { - gpio_set_value(camera_power, (((~camera_ioflag)&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - //printk("\n%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev), camera_power, (((~camera_ioflag)&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - } - } - if (camera_reset != INVALID_GPIO) { - msleep(3); /* delay 3 ms */ - gpio_set_value(camera_reset,(((~camera_ioflag)&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - //printk("\n%s..%s..ResetPin= %d..PinLevel = %x \n",__FUNCTION__,dev_name(dev), camera_reset, (((~camera_ioflag)&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - } - return 0; -} - -static struct i2c_board_info rk2818_i2c_cam_info[] = { - { - I2C_BOARD_INFO(SENSOR_NAME_0, SENSOR_IIC_ADDR_0>>1) - }, -}; - -struct soc_camera_link rk2818_iclink = { - .bus_id = RK28_CAM_PLATFORM_DEV_ID, - .power = rk28_sensor_power, - .board_info = &rk2818_i2c_cam_info[0], - .i2c_adapter_id = SENSOR_IIC_ADAPTER_ID_0, - .module_name = SENSOR_NAME_0, -}; - -/*platform_device : soc-camera need */ -struct platform_device rk2818_soc_camera_pdrv = { - .name = "soc-camera-pdrv", - .id = -1, - .dev = { - .init_name = SENSOR_NAME_0, - .platform_data = &rk2818_iclink, - }, -}; -#endif -/***************************************************************************************** - * battery devices - * author: lw@rock-chips.com - *****************************************************************************************/ -#define CHARGEOK_PIN FPGA_PIO0_06 -struct rk2818_battery_platform_data rk2818_battery_platdata = { - .charge_ok_pin = CHARGEOK_PIN, - .charge_ok_level = 0, -}; - - -/***************************************************************************************** - * serial devices - * author: lhh@rock-chips.com - *****************************************************************************************/ -static int serial_io_init(void) -{ - int ret; -#if 1 - //cz@rock-chips.com - //20100808 - //UART0µÄËĸö¹Ü½ÅÏÈIOMUX³ÉGPIO - //È»ºó·Ö±ðÉèÖÃÊäÈëÊä³ö/À­¸ßÀ­µÍ´¦Àí - //×îºóÔÙIOMUX³ÉUART - //·ÀÖ¹Ö±½ÓIOMUX³ÉUARTºóËĸö¹Ü½ÅµÄ״̬²»¶Ôʱ - //²Ù×÷UARTµ¼ÖÂUART_USR_BUSYʼÖÕΪ1Ôì³ÉÈçÏÂËÀÑ­»· - //while(rk2818_uart_read(port,UART_USR)&UART_USR_BUSY) - //UARTËĸö¹Ü½ÅÔÚδ´«ÊäʱÕý³£×´Ì¬Ó¦¸ÃΪ£º - //RX/TX£ºHIGH - //CTS/RTS£ºLOW - //×¢Ò⣺CTS/RTSΪµÍÓÐЧ£¬Ó²¼þÉϲ»Ó¦¸ÃÇ¿ÐÐ×öÉÏÀ­ - rk2818_mux_api_set(GPIOG1_UART0_MMC1WPT_NAME, IOMUXA_GPIO1_C1 /*IOMUXA_UART0_SOUT*/); - rk2818_mux_api_set(GPIOG0_UART0_MMC1DET_NAME, IOMUXA_GPIO1_C0 /*IOMUXA_UART0_SIN*/); - - ret = gpio_request(RK2818_PIN_PG0, NULL); - if(ret != 0) - { - gpio_free(RK2818_PIN_PG0); - } - gpio_direction_output(RK2818_PIN_PG0,GPIO_HIGH); - - - ret = gpio_request(RK2818_PIN_PG1, NULL); - if(ret != 0) - { - gpio_free(RK2818_PIN_PG1); - } - gpio_direction_output(RK2818_PIN_PG1,GPIO_HIGH); - - gpio_pull_updown(RK2818_PIN_PG1,GPIOPullUp); - gpio_pull_updown(RK2818_PIN_PG0,GPIOPullUp); - - rk2818_mux_api_set(GPIOG1_UART0_MMC1WPT_NAME, IOMUXA_UART0_SOUT); - rk2818_mux_api_set(GPIOG0_UART0_MMC1DET_NAME, IOMUXA_UART0_SIN); - - rk2818_mux_api_set(GPIOB2_U0CTSN_SEL_NAME, IOMUXB_GPIO0_B2/*IOMUXB_UART0_CTS_N*/); - rk2818_mux_api_set(GPIOB3_U0RTSN_SEL_NAME, IOMUXB_GPIO0_B3/*IOMUXB_UART0_RTS_N*/); - - ret = gpio_request(RK2818_PIN_PB2, NULL); - if(ret != 0) - { - gpio_free(RK2818_PIN_PB2); - } - gpio_direction_input(RK2818_PIN_PB2); - // gpio_direction_output(RK2818_PIN_PB2,GPIO_LOW); - - ret = gpio_request(RK2818_PIN_PB3, NULL); - if(ret != 0) - { - gpio_free(RK2818_PIN_PB3); - } - gpio_direction_output(RK2818_PIN_PB3,GPIO_LOW); -#endif - - rk2818_mux_api_set(GPIOB2_U0CTSN_SEL_NAME, IOMUXB_UART0_CTS_N); - rk2818_mux_api_set(GPIOB3_U0RTSN_SEL_NAME, IOMUXB_UART0_RTS_N); - - return 0; -} - -struct rk2818_serial_platform_data rk2818_serial0_platdata = { - .io_init = serial_io_init, -}; - -/***************************************************************************************** - * i2s devices - * author: lhhrock-chips.com - *****************************************************************************************/ -static int i2s_io_init(void) -{ - /* Configure the I2S pins in correct mode */ - rk2818_mux_api_set(CXGPIO_I2S_SEL_NAME,IOMUXB_I2S_INTERFACE); - return 0; -} - -struct rk2818_i2s_platform_data rk2818_i2s_platdata = { - .io_init = i2s_io_init, -}; - - -/***************************************************************************************** - * spi devices - * author: lhhrock-chips.com - *****************************************************************************************/ -#define SPI_CHIPSELECT_NUM 3 -struct spi_cs_gpio rk2818_spi_cs_gpios[SPI_CHIPSELECT_NUM] = { - { - .name = "spi cs0", - .cs_gpio = RK2818_PIN_PB4, - .cs_iomux_name = GPIOB4_SPI0CS0_MMC0D4_NAME,//if no iomux,set it NULL - .cs_iomux_mode = IOMUXA_GPIO0_B4, - }, - { - .name = "spi cs1", - .cs_gpio = RK2818_PIN_PB0, - .cs_iomux_name = GPIOB0_SPI0CSN1_MMC1PCA_NAME, - .cs_iomux_mode = IOMUXA_GPIO0_B0, - }, - { - .name = "spi cs2", - .cs_gpio = RK2818_PIN_PF5, - .cs_iomux_name = GPIOF5_APWM3_DPWM3_NAME, - .cs_iomux_mode = IOMUXB_GPIO1_B5, - } -}; - -static int spi_io_init(struct spi_cs_gpio *cs_gpios, int cs_num) -{ - int i,j,ret; - //clk - rk2818_mux_api_set(GPIOB_SPI0_MMC0_NAME, IOMUXA_SPI0); - //cs - if (cs_gpios) { - for (i=0; i>>>>> lcd cs gpio_request err \n "); - } - } - - rk2818_mux_api_set(LCD_CLK_MUX_NAME, LCD_CLK_MUX_MODE); - if (LCD_CLK_PIN != INVALID_GPIO) { - ret = gpio_request(LCD_CLK_PIN, NULL); - if(ret != 0) - { - goto err2; - printk(">>>>>> lcd clk gpio_request err \n "); - } - } - - rk2818_mux_api_set(LCD_TXD_MUX_NAME, LCD_TXD_MUX_MODE); - if (LCD_TXD_PIN != INVALID_GPIO) { - ret = gpio_request(LCD_TXD_PIN, NULL); - if(ret != 0) - { - goto err3; - printk(">>>>>> lcd txd gpio_request err \n "); - } - } - - return 0; - -err3: - if (LCD_CLK_PIN != INVALID_GPIO) { - gpio_free(LCD_CLK_PIN); - } -err2: - if (LCD_CS_PIN != INVALID_GPIO) { - gpio_free(LCD_CS_PIN); - } -err1: - return ret; -} - -static int rk2818_lcd_io_deinit(void) -{ - int ret = 0; - - gpio_direction_output(LCD_CLK_PIN, 0); - gpio_set_value(LCD_CLK_PIN, GPIO_HIGH); - gpio_direction_output(LCD_TXD_PIN, 0); - gpio_set_value(LCD_TXD_PIN, GPIO_HIGH); - - gpio_free(LCD_CS_PIN); - rk2818_mux_api_mode_resume(LCD_CS_MUX_NAME); - gpio_free(LCD_CLK_PIN); - gpio_free(LCD_TXD_PIN); - rk2818_mux_api_mode_resume(LCD_TXD_MUX_NAME); - rk2818_mux_api_mode_resume(LCD_CLK_MUX_NAME); - - return ret; -} - -static int rk2818_lcd_reset(void) -{ - int ret; - rk2818_mux_api_set(LCD_RESET_IOMUX_NAME, LCD_RESET_IOMUX_VALUE); - ret = gpio_request(LCD_RESET_PIN, "lcd reset"); - if(ret != 0) - { - gpio_free(LCD_RESET_PIN); - rk2818_mux_api_mode_resume(LCD_RESET_IOMUX_NAME); - printk(">>>>>> lcd gpio_request err \n "); - return -1; - } - gpio_set_value(LCD_RESET_PIN, GPIO_LOW); - gpio_direction_output(LCD_RESET_PIN, GPIO_LOW); - mdelay(3); - gpio_set_value(LCD_RESET_PIN, GPIO_HIGH); - gpio_direction_output(LCD_RESET_PIN, GPIO_HIGH); - - printk(">>>>>> lcd reset ok \n "); - - return 0; -} - -struct rk2818lcd_info rk2818_lcd_info = { - .txd_pin = LCD_TXD_PIN, - .clk_pin = LCD_CLK_PIN, - .cs_pin = LCD_CS_PIN, - .io_init = rk2818_lcd_io_init, - .io_deinit = rk2818_lcd_io_deinit, -}; - - -/***************************************************************************************** - * frame buffe devices - * author: zyw@rock-chips.com - *****************************************************************************************/ -#define FB_ID 0 -#define FB_DISPLAY_ON_PIN INVALID_GPIO -#define FB_LCD_STANDBY_PIN INVALID_GPIO -#define FB_MCU_FMK_PIN INVALID_GPIO - -#define FB_DISPLAY_ON_VALUE GPIO_LOW -#define FB_LCD_STANDBY_VALUE 0 - -#define FB_DISPLAY_ON_MUX_NAME NULL -#define FB_DISPLAY_ON_MUX_MODE 0 - -#define FB_LCD_STANDBY_MUX_NAME NULL -#define FB_LCD_STANDBY_MUX_MODE 1 - -#define FB_MCU_FMK_PIN_MUX_NAME NULL -#define FB_MCU_FMK_MUX_MODE 0 - -#define FB_DATA0_16_MUX_NAME GPIOC_LCDC16BIT_SEL_NAME -#define FB_DATA0_16_MUX_MODE 1 - -#define FB_DATA17_18_MUX_NAME GPIOC_LCDC18BIT_SEL_NAME -#define FB_DATA17_18_MUX_MODE 1 - -#define FB_DATA19_24_MUX_NAME GPIOC_LCDC24BIT_SEL_NAME -#define FB_DATA19_24_MUX_MODE 1 - -#define FB_DEN_MUX_NAME CXGPIO_LCDDEN_SEL_NAME -#define FB_DEN_MUX_MODE 1 - -#define FB_VSYNC_MUX_NAME CXGPIO_LCDVSYNC_SEL_NAME -#define FB_VSYNC_MUX_MODE 1 - -#define FB_MCU_FMK_MUX_NAME NULL -#define FB_MCU_FMK_MUX_MODE 0 - -static int rk2818_fb_io_init(struct rk2818_fb_setting_info *fb_setting) -{ - int ret = 0; - if(fb_setting->data_num <=16) - rk2818_mux_api_set(FB_DATA0_16_MUX_NAME, FB_DATA0_16_MUX_MODE); - if(fb_setting->data_num >16 && fb_setting->data_num<=18) - rk2818_mux_api_set(FB_DATA17_18_MUX_NAME, FB_DATA17_18_MUX_MODE); - if(fb_setting->data_num >18) - rk2818_mux_api_set(FB_DATA19_24_MUX_NAME, FB_DATA19_24_MUX_MODE); - - if(fb_setting->vsync_en) - rk2818_mux_api_set(FB_VSYNC_MUX_NAME, FB_VSYNC_MUX_MODE); - - if(fb_setting->den_en) - rk2818_mux_api_set(FB_DEN_MUX_NAME, FB_DEN_MUX_MODE); - - if(fb_setting->mcu_fmk_en && FB_MCU_FMK_MUX_NAME && (FB_MCU_FMK_PIN != INVALID_GPIO)) - { - rk2818_mux_api_set(FB_MCU_FMK_MUX_NAME, FB_MCU_FMK_MUX_MODE); - ret = gpio_request(FB_MCU_FMK_PIN, NULL); - if(ret != 0) - { - gpio_free(FB_MCU_FMK_PIN); - printk(">>>>>> FB_MCU_FMK_PIN gpio_request err \n "); - } - gpio_direction_input(FB_MCU_FMK_PIN); - } - - if(fb_setting->disp_on_en && FB_DISPLAY_ON_MUX_NAME && (FB_DISPLAY_ON_PIN != INVALID_GPIO)) - { - rk2818_mux_api_set(FB_DISPLAY_ON_MUX_NAME, FB_DISPLAY_ON_MUX_MODE); - ret = gpio_request(FB_DISPLAY_ON_PIN, NULL); - if(ret != 0) - { - gpio_free(FB_DISPLAY_ON_PIN); - printk(">>>>>> FB_DISPLAY_ON_PIN gpio_request err \n "); - } - } - - if(fb_setting->disp_on_en && FB_LCD_STANDBY_MUX_NAME && (FB_LCD_STANDBY_PIN != INVALID_GPIO)) - { - rk2818_mux_api_set(FB_LCD_STANDBY_MUX_NAME, FB_LCD_STANDBY_MUX_MODE); - ret = gpio_request(FB_LCD_STANDBY_PIN, NULL); - if(ret != 0) - { - gpio_free(FB_LCD_STANDBY_PIN); - printk(">>>>>> FB_LCD_STANDBY_PIN gpio_request err \n "); - } - } - - return ret; -} - -struct rk2818fb_info rk2818_fb_info = { - .fb_id = FB_ID, - .disp_on_pin = FB_DISPLAY_ON_PIN, - .disp_on_value = FB_DISPLAY_ON_VALUE, - .standby_pin = FB_LCD_STANDBY_PIN, - .standby_value = FB_LCD_STANDBY_VALUE, - .mcu_fmk_pin = FB_MCU_FMK_PIN, - .lcd_info = &rk2818_lcd_info, - .io_init = rk2818_fb_io_init, -}; - -/***************************************************************************************** - * backlight devices - * author: nzy@rock-chips.com - *****************************************************************************************/ - /* - GPIOF2_APWM0_SEL_NAME, IOMUXB_PWM0 - GPIOF3_APWM1_MMC0DETN_NAME, IOMUXA_PWM1 - GPIOF4_APWM2_MMC0WPT_NAME, IOMUXA_PWM2 - GPIOF5_APWM3_DPWM3_NAME, IOMUXB_PWM3 - */ - -#define PWM_ID 0 -#define PWM_MUX_NAME GPIOF2_APWM0_SEL_NAME -#define PWM_MUX_MODE IOMUXB_PWM0 -#define PWM_EFFECT_VALUE 0 - - -#define BL_EN_MUX_NAME GPIOF34_UART3_SEL_NAME -#define BL_EN_MUX_MODE IOMUXB_GPIO1_B34 - -#define BL_EN_PIN RK2818_PIN_PF3 -#define BL_EN_VALUE GPIO_HIGH - - - -static int rk2818_backlight_io_init(void) -{ - int ret = 0; - - rk2818_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE); - - rk2818_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE); - - ret = gpio_request(BL_EN_PIN, NULL); - if(ret != 0) - { - gpio_free(BL_EN_PIN); - printk(KERN_ERR ">>>>>> lcd_cs gpio_request err \n "); - } - - gpio_direction_output(BL_EN_PIN, 0); - gpio_set_value(BL_EN_PIN, BL_EN_VALUE); - - return ret; -} - -static int rk2818_backlight_io_deinit(void) -{ - int ret = 0; - - gpio_free(BL_EN_PIN); - - rk2818_mux_api_mode_resume(PWM_MUX_NAME); - - rk2818_mux_api_mode_resume(BL_EN_MUX_NAME); - - return ret; -} - -struct rk2818_bl_info rk2818_bl_info = { - .pwm_id = PWM_ID, - .bl_ref = PWM_EFFECT_VALUE, - .io_init = rk2818_backlight_io_init, - .io_deinit = rk2818_backlight_io_deinit, -}; - - -/***************************************************************************************** - * netcard devices - * author: lyx@rock-chips.com - *****************************************************************************************/ -#ifdef CONFIG_DM9000 -/* -GPIOA5_FLASHCS1_SEL_NAME IOMUXB_FLASH_CS1 -GPIOA6_FLASHCS2_SEL_NAME IOMUXB_FLASH_CS2 -GPIOA7_FLASHCS3_SEL_NAME IOMUXB_FLASH_CS3 -GPIOE_SPI1_FLASH_SEL1_NAME IOMUXA_FLASH_CS45 -GPIOE_SPI1_FLASH_SEL_NAME IOMUXA_FLASH_CS67 -*/ -#define DM9000_USE_NAND_CS 1 //cs can be 1,2,3,4,5,6 or 7 -#define DM9000_CS_IOMUX_NAME GPIOA5_FLASHCS1_SEL_NAME -#define DM9000_CS_IOMUX_MODE IOMUXB_FLASH_CS1 -#define DM9000_NET_INT_PIN RK2818_PIN_PA1 -#define DM9000_INT_IOMUX_NAME GPIOA1_HOSTDATA17_SEL_NAME -#define DM9000_INT_IOMUX_MODE IOMUXB_GPIO0_A1 -#define DM9000_INT_INIT_VALUE GPIOPullDown -#define DM9000_IRQ IRQF_TRIGGER_HIGH -#define DM9000_IO_ADDR (RK2818_NANDC_PHYS + 0x800 + DM9000_USE_NAND_CS*0x100 + 0x8) -#define DM9000_DATA_ADDR (RK2818_NANDC_PHYS + 0x800 + DM9000_USE_NAND_CS*0x100 + 0x4) - -static int dm9k_gpio_set(void) -{ - //cs - rk2818_mux_api_set(DM9000_CS_IOMUX_NAME, DM9000_CS_IOMUX_MODE); - //int - rk2818_mux_api_set(DM9000_INT_IOMUX_NAME, DM9000_INT_IOMUX_MODE); - - return 0; -} -static int dm9k_gpio_free(void) -{ - rk2818_mux_api_mode_resume(DM9000_INT_IOMUX_NAME); - rk2818_mux_api_mode_resume(DM9000_CS_IOMUX_NAME); - return 0; -} - -static struct resource dm9k_resource[] = { - [0] = { - .start = DM9000_IO_ADDR, - .end = DM9000_IO_ADDR + 3, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DM9000_DATA_ADDR, - .end = DM9000_DATA_ADDR + 3, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = DM9000_NET_INT_PIN, - .end = DM9000_NET_INT_PIN, - .flags = IORESOURCE_IRQ | DM9000_IRQ, - } - -}; - -/* for the moment we limit ourselves to 8bit IO until some - * better IO routines can be written and tested -*/ -struct dm9000_plat_data dm9k_platdata = { - .flags = DM9000_PLATF_8BITONLY, - .irq_pin = DM9000_NET_INT_PIN, - .irq_pin_value = DM9000_INT_INIT_VALUE, - .io_init = dm9k_gpio_set, - .io_deinit = dm9k_gpio_free, -}; - -struct platform_device rk2818_device_dm9k = { - .name = "dm9000", - .id = 0, - .num_resources = ARRAY_SIZE(dm9k_resource), - .resource = dm9k_resource, - .dev = { - .platform_data = &dm9k_platdata, - } -}; -#endif - -#ifdef CONFIG_STE -struct platform_device rk2818_device_ste = { - .name = "ste", - .id = -1, - }; -#endif - -#ifdef CONFIG_HEADSET_DET -struct rk2818_headset_data rk2818_headset_info = { - .irq = FPGA_PIO0_00, - .irq_type = IRQF_TRIGGER_FALLING, - .headset_in_type= HEADSET_IN_HIGH, -}; - -struct platform_device rk28_device_headset = { - .name = "rk2818_headsetdet", - .id = 0, - .dev = { - .platform_data = &rk2818_headset_info, - } -}; -#endif - -// adc ---> key -#define PLAY_ON_PIN RK2818_PIN_PA3 -#define PLAY_ON_LEVEL 1 -static ADC_keyst gAdcValueTab[] = -{ - {0x65, AD2KEY2},///VOLUME_DOWN - {0xd3, AD2KEY1},///VOLUME_UP - {0x130, AD2KEY3},///MENU - {0x19d, AD2KEY4},///HOME - {0x202, AD2KEY5},///BACK - {0x2d0, AD2KEY6},///CALL - {0x267, AD2KEY7},///SEARCH - {0, 0}///table end -}; - -static unsigned char gInitKeyCode[] = -{ - AD2KEY1,AD2KEY2,AD2KEY3,AD2KEY4,AD2KEY5,AD2KEY6,AD2KEY7, - ENDCALL,KEYSTART,KEY_WAKEUP, -}; - -struct adc_key_data rk2818_adc_key = { - .pin_playon = PLAY_ON_PIN, - .playon_level = PLAY_ON_LEVEL, - .adc_empty = 1000, - .adc_invalid = 20, - .adc_drift = 50, - .adc_chn = 1, - .adc_key_table = gAdcValueTab, - .initKeyCode = gInitKeyCode, - .adc_key_cnt = 10, -}; - -struct rk2818_adckey_platform_data rk2818_adckey_platdata = { - .adc_key = &rk2818_adc_key, -}; - -//headset key -#ifdef CONFIG_HEADSET_KEY -static ADC_keyst gHskeyValueTab[] = -{ - {0, KEY_HEADSETHOOK}, - {0, 0}///table end -}; - -static unsigned char gInitHsKeyCode[] = -{ - KEY_HEADSETHOOK, -}; - -struct adc_key_data rk2818_hs_key = { - .pin_playon = 0, - .playon_level = 0, - .adc_empty = 0, - .adc_invalid = 0, - .adc_drift = 50, - .adc_chn = 2, - .adc_key_table = gHskeyValueTab, - .initKeyCode = gInitHsKeyCode, - .adc_key_cnt = 1, -}; - -struct rk2818_adckey_platform_data rk2818_hskey_platdata = { - .adc_key = &rk2818_hs_key, -}; - -struct platform_device rk2818_device_hskey = { - .name = "rk2818-hskey", - .id = -1, - .dev = { - .platform_data = &rk2818_hskey_platdata, - } -}; -#endif - -#ifdef CONFIG_INPUT_LPSENSOR_CM3602 -static int capella_cm3602_power(int on); - -static struct capella_cm3602_platform_data capella_cm3602_pdata = { - .power = capella_cm3602_power, - .irq_pin = FPGA_PIO0_04, - .pwd_out_pin = FPGA_PIO4_07, - .ps_shutdown_pin = FPGA_PIO5_00, - //.p_out = MAHIMAHI_GPIO_PROXIMITY_INT_N - }; - -static int capella_cm3602_power(int on) -{ /* TODO eolsen Add Voltage reg control */ - if (on) { - printk("[%s]:on---\n",__FUNCTION__); - gpio_direction_output(capella_cm3602_pdata.pwd_out_pin, SPI_GPIO_LOW); - gpio_direction_output(capella_cm3602_pdata.ps_shutdown_pin, SPI_GPIO_LOW); - } - else { - printk("[%s]:off---\n",__FUNCTION__); - gpio_direction_output(capella_cm3602_pdata.pwd_out_pin, SPI_GPIO_HIGH); - gpio_direction_output(capella_cm3602_pdata.ps_shutdown_pin, SPI_GPIO_HIGH); - } - return 0; -} - -struct platform_device rk2818_device_cm3605 = { - .name = CAPELLA_CM3602, - .id = -1, - .dev = { - .platform_data = &capella_cm3602_pdata - } - }; -#endif - -/***************************************************************************************** - * nand flash devices - * author: hxy@rock-chips.com - *****************************************************************************************/ -/* -GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1 -GPIOA6_FLASHCS2_SEL_NAME, IOMUXB_FLASH_CS2 -GPIOA7_FLASHCS3_SEL_NAME, IOMUXB_FLASH_CS3 -GPIOE_SPI1_FLASH_SEL1_NAME, IOMUXA_FLASH_CS45 -GPIOE_SPI1_FLASH_SEL_NAME, IOMUXA_FLASH_CS67 -*/ - -#define NAND_CS_MAX_NUM 1 /*form 0 to 8, it is 0 when no nand flash */ - -int rk2818_nand_io_init(void) -{ -#if (NAND_CS_MAX_NUM == 2) - rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1); -#elif (NAND_CS_MAX_NUM == 3) - rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1); - rk2818_mux_api_set(GPIOA6_FLASHCS2_SEL_NAME, IOMUXB_FLASH_CS2); -#elif (NAND_CS_MAX_NUM == 4) - rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1); - rk2818_mux_api_set(GPIOA6_FLASHCS2_SEL_NAME, IOMUXB_FLASH_CS2); - rk2818_mux_api_set(GPIOA7_FLASHCS3_SEL_NAME, IOMUXB_FLASH_CS3); -#elif ((NAND_CS_MAX_NUM == 5) || (NAND_CS_MAX_NUM == 6)) - rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1); - rk2818_mux_api_set(GPIOA6_FLASHCS2_SEL_NAME, IOMUXB_FLASH_CS2); - rk2818_mux_api_set(GPIOA7_FLASHCS3_SEL_NAME, IOMUXB_FLASH_CS3); - rk2818_mux_api_set(GPIOE_SPI1_FLASH_SEL1_NAME, IOMUXA_FLASH_CS45); -#elif ((NAND_CS_MAX_NUM == 7) || (NAND_CS_MAX_NUM == 8)) - rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1); - rk2818_mux_api_set(GPIOA6_FLASHCS2_SEL_NAME, IOMUXB_FLASH_CS2); - rk2818_mux_api_set(GPIOA7_FLASHCS3_SEL_NAME, IOMUXB_FLASH_CS3); - rk2818_mux_api_set(GPIOE_SPI1_FLASH_SEL1_NAME, IOMUXA_FLASH_CS45); - rk2818_mux_api_set(GPIOE_SPI1_FLASH_SEL_NAME, IOMUXA_FLASH_CS67); -#endif - return 0; -} - -struct rk2818_nand_platform_data rk2818_nand_data = { - .width = 1, /* data bus width in bytes */ - .hw_ecc = 1, /* hw ecc 0: soft ecc */ - .num_flash = 1, - .io_init = rk2818_nand_io_init, -}; - - -/********************usb*********************/ -struct usb_mass_storage_platform_data mass_storage_pdata = { - .nluns = 1, - .vendor = "RockChip", - .product = "rk2818 sdk", - .release = 0x0100, -}; - - - -static struct platform_device *devices[] __initdata = { -#ifdef CONFIG_BT - &raho_rfkill, -#endif -#ifdef CONFIG_UART0_RK2818 - &rk2818_device_uart0, -#endif -#ifdef CONFIG_UART1_RK2818 - &rk2818_device_uart1, -#endif -#ifdef CONFIG_I2C0_RK2818 - &rk2818_device_i2c0, -#endif -#ifdef CONFIG_I2C1_RK2818 - &rk2818_device_i2c1, -#endif -#ifdef CONFIG_SDMMC0_RK2818 - &rk2818_device_sdmmc0, -#endif -#ifdef CONFIG_SDMMC1_RK2818 - &rk2818_device_sdmmc1, -#endif - &raho_wifi_device, - &rk2818_device_spim, - &rk2818_device_i2s, -#if defined(CONFIG_ANDROID_PMEM) - &rk2818_device_pmem, - &rk2818_device_pmem_dsp, -#endif - &rk2818_device_adc, - &rk2818_device_adckey, -#if defined(CONFIG_RK2818_REGULATOR_CHARGE) - &power_supply, - &charge_current, -#endif - &rk2818_device_battery, - &rk2818_device_fb, - &rk2818_device_backlight, - &rk2818_device_dsp, - -#ifdef CONFIG_VIDEO_RK2818 - &rk2818_device_camera, /* ddl@rock-chips.com : camera support */ - &rk2818_soc_camera_pdrv, - #endif - -#ifdef CONFIG_MTD_NAND_RK2818 - &rk2818_nand_device, -#endif -#ifdef CONFIG_DM9000 - &rk2818_device_dm9k, -#endif -#ifdef CONFIG_INPUT_LPSENSOR_CM3602 - &rk2818_device_cm3605, -#endif -#ifdef CONFIG_HEADSET_DET - &rk28_device_headset, -#endif -#ifdef CONFIG_HEADSET_KEY - &rk2818_device_hskey, -#endif -#ifdef CONFIG_DWC_OTG - &rk2818_device_dwc_otg, -#endif -#ifdef CONFIG_RK2818_HOST11 - &rk2818_device_host11, -#endif -#ifdef CONFIG_USB_ANDROID - &android_usb_device, - &usb_mass_storage_device, -#endif -#ifdef CONFIG_STE - &rk2818_device_ste, -#endif -#ifdef CONFIG_ANDROID_TIMED_GPIO - &rk28_device_vibrator, -#endif -}; - -extern struct sys_timer rk2818_timer; -#define POWER_PIN RK2818_PIN_PB1 -static void rk2818_power_on(void) -{ - int ret; - ret = gpio_request(POWER_PIN, NULL); - if (ret) { - printk("failed to request power_off gpio\n"); - goto err_free_gpio; - } - - gpio_pull_updown(POWER_PIN, GPIOPullUp); - ret = gpio_direction_output(POWER_PIN, GPIO_HIGH); - if (ret) { - printk("failed to set power_off gpio output\n"); - goto err_free_gpio; - } - - gpio_set_value(POWER_PIN, 1);/*power on*/ - -err_free_gpio: - gpio_free(POWER_PIN); -} - -static void rk2818_power_off(void) -{ - printk("shut down system now ...\n"); - gpio_set_value(POWER_PIN, 0);/*power down*/ -} - -#if defined(CONFIG_ANDROID_TIMED_GPIO) -static struct timed_gpio timed_gpios[] = { - { - .name = "vibrator", - .gpio = FPGA_PIO1_12, - .max_timeout = 1000, - .active_low = 0, - }, -}; - -struct timed_gpio_platform_data rk28_vibrator_info = { - .num_gpios = 1, - .gpios = timed_gpios, -}; -#endif -#if defined (CONFIG_RK2818_SOC_PM) -void __tcmfunc rk2818_pm_scu_suspend(unsigned int *reg,int regoff) -{ - - switch(regoff) - { - case PM_SCU_CLKGATE0_CON: - { - } - - - } - -} - - - -void __tcmfunc rk2818_soc_general_reg_suspend(void) -{ - struct rk2818_pm_soc_st *general=rk2818_soc_pm.general; - - unsigned int *general_reg_addr=general->reg_base_addr; - #if 1 - general->reg_ctrbit|=(0x1<reg_ctrbit|=(0x1<reg_ctrbit|=(0x1<reg_ctrbit|=(0x1<reg_ctrbit|=(0x1<reg_ctrbit|=(0x1<> 18) & 0xfffc, - .boot_params = RK2818_SDRAM_PHYS + 0xf8000, - .map_io = machine_rk2818_mapio, - .init_irq = machine_rk2818_init_irq, - .init_machine = machine_rk2818_board_init, - .timer = &rk2818_timer, -MACHINE_END - diff --git a/arch/arm/mach-rk2818/board-rahosdk-rfkill.c b/arch/arm/mach-rk2818/board-rahosdk-rfkill.c deleted file mode 100755 index 2b0001cfdb49..000000000000 --- a/arch/arm/mach-rk2818/board-rahosdk-rfkill.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright (C) 2010 ROCKCHIP, Inc. - * Author: roger_chen - * - * This program is the bluetooth device bcm4329's driver, - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -//#include -//#include -//#include -//#include -#include -#include -#include -#include -#include -#include - -#if 1 -#define DBG(x...) printk(KERN_INFO x) -#else -#define DBG(x...) -#endif - -#define RAHO_BT_GPIO_POWER_N FPGA_PIO1_06 -#define RAHO_BT_GPIO_RESET_N FPGA_PIO1_07 - -static struct rfkill *bt_rfk; -static const char bt_name[] = "bcm4329"; -extern int raho_bt_power_state; -extern int raho_wifi_power_state; - -static int bcm4329_set_block(void *data, bool blocked) -{ - DBG("%s---blocked :%d\n", __FUNCTION__, blocked); - - if (false == blocked) { - gpio_set_value(RAHO_BT_GPIO_POWER_N, GPIO_HIGH); /* bt power on */ - gpio_set_value(RAHO_BT_GPIO_RESET_N, GPIO_HIGH); /* bt reset deactive*/ - mdelay(20); - pr_info("bt turn on power\n"); - } - else { - if (!raho_wifi_power_state) { - gpio_set_value(RAHO_BT_GPIO_POWER_N, GPIO_LOW); /* bt power off */ - mdelay(20); - pr_info("bt shut off power\n"); - }else { - pr_info("bt shouldn't shut off power, wifi is using it!\n"); - } - - gpio_set_value(RAHO_BT_GPIO_RESET_N, GPIO_LOW); /* bt reset active*/ - mdelay(20); - } - - raho_bt_power_state = !blocked; - return 0; -} - - -static const struct rfkill_ops bcm4329_rfk_ops = { - .set_block = bcm4329_set_block, -}; - -static int __init bcm4329_rfkill_probe(struct platform_device *pdev) -{ - int rc = 0; - bool default_state = true; - - DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__); - - /* default to bluetooth off */ - bcm4329_set_block(NULL, default_state); /* blocked -> bt off */ - - bt_rfk = rfkill_alloc(bt_name, - NULL, - RFKILL_TYPE_BLUETOOTH, - &bcm4329_rfk_ops, - NULL); - - if (!bt_rfk) - { - printk("fail to rfkill_allocate************\n"); - return -ENOMEM; - } - - rfkill_set_states(bt_rfk, default_state, false); - - rc = rfkill_register(bt_rfk); - if (rc) - rfkill_destroy(bt_rfk); - - printk("rc=0x%x\n", rc); - - return rc; -} - - -static int __devexit bcm4329_rfkill_remove(struct platform_device *pdev) -{ - if (bt_rfk) - rfkill_unregister(bt_rfk); - bt_rfk = NULL; - - platform_set_drvdata(pdev, NULL); - DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__); - return 0; -} - -static struct platform_driver bcm4329_rfkill_driver = { - .probe = bcm4329_rfkill_probe, - .remove = __devexit_p(bcm4329_rfkill_remove), - .driver = { - .name = "raho_rfkill", - .owner = THIS_MODULE, - }, -}; - -/* - * Module initialization - */ -static int __init bcm4329_mod_init(void) -{ - int ret; - DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__); - ret = platform_driver_register(&bcm4329_rfkill_driver); - printk("ret=0x%x\n", ret); - return ret; -} - -static void __exit bcm4329_mod_exit(void) -{ - platform_driver_unregister(&bcm4329_rfkill_driver); -} - -module_init(bcm4329_mod_init); -module_exit(bcm4329_mod_exit); -MODULE_DESCRIPTION("bcm4329 Bluetooth driver"); -MODULE_AUTHOR("roger_chen cz@rock-chips.com"); -MODULE_LICENSE("GPL"); - diff --git a/arch/arm/mach-rk2818/board-rahosdk.c b/arch/arm/mach-rk2818/board-rahosdk.c deleted file mode 100755 index a242a5c3de89..000000000000 --- a/arch/arm/mach-rk2818/board-rahosdk.c +++ /dev/null @@ -1,2322 +0,0 @@ -/* linux/arch/arm/mach-rk2818/board-phonesdk.c - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include /* ddl@rock-chips.com : camera support */ -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include /* ddl@rock-chips.com : camera support */ - - -#include "devices.h" - -#include "../../../drivers/spi/rk2818_spim.h" -#include -#include "../../../drivers/input/touchscreen/xpt2046_ts.h" -#include "../../../drivers/staging/android/timed_gpio.h" -#include "../../../sound/soc/codecs/wm8994.h" -#include "../../../drivers/headset_observe/rk2818_headset.h" -#include -#include - -#include "../../../drivers/cmmb/siano/smsspiphy.h" -/* -------------------------------------------------------------------- - * ÉùÃ÷ÁËrk2818_gpioBankÊý×飬²¢¶¨ÒåÁËGPIO¼Ä´æÆ÷×éIDºÍ¼Ä´æÆ÷»ùµØÖ·¡£ - * -------------------------------------------------------------------- */ - -static struct rk2818_gpio_bank rk2818_gpioBank[] = { - { - .id = RK2818_ID_PIOA, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOB, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOC, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOD, - .offset = RK2818_GPIO0_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOE, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOF, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOG, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - }, - { - .id = RK2818_ID_PIOH, - .offset = RK2818_GPIO1_BASE, - .clock = NULL, - } -}; - -//IOÓ³É䷽ʽÃèÊö £¬Ã¿¸öΪһ¶ÎÏßÐÔÁ¬ÐøÓ³Éä -static struct map_desc rk2818_io_desc[] __initdata = { - - { - .virtual = RK2818_MCDMA_BASE, //ÐéÄâµØÖ· - .pfn = __phys_to_pfn(RK2818_MCDMA_PHYS), //ÎïÀíµØÖ·£¬ÐëÓëÒ³±í¶ÔÆë - .length = RK2818_MCDMA_SIZE, //³¤¶È - .type = MT_DEVICE //Ó³É䷽ʽ - }, - - { - .virtual = RK2818_DWDMA_BASE, - .pfn = __phys_to_pfn(RK2818_DWDMA_PHYS), - .length = RK2818_DWDMA_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_INTC_BASE, - .pfn = __phys_to_pfn(RK2818_INTC_PHYS), - .length = RK2818_INTC_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_NANDC_BASE, - .pfn = __phys_to_pfn(RK2818_NANDC_PHYS), - .length = RK2818_NANDC_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_SDRAMC_BASE, - .pfn = __phys_to_pfn(RK2818_SDRAMC_PHYS), - .length = RK2818_SDRAMC_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_ARMDARBITER_BASE, - .pfn = __phys_to_pfn(RK2818_ARMDARBITER_PHYS), - .length = RK2818_ARMDARBITER_SIZE, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_APB_BASE, - .pfn = __phys_to_pfn(RK2818_APB_PHYS), - .length = 0xa0000, - .type = MT_DEVICE - }, - - { - .virtual = RK2818_WDT_BASE, - .pfn = __phys_to_pfn(RK2818_WDT_PHYS), - .length = 0xa0000, ///apb bus i2s i2c spi no map in this - .type = MT_DEVICE - }, -}; - -/***************************************************************************************** - * sd/mmc devices - * author: kfx@rock-chips.com -*****************************************************************************************/ -static int rk2818_sdmmc0_io_init(void) -{ - rk2818_mux_api_set(GPIOH_MMC0D_SEL_NAME, IOMUXA_SDMMC0_DATA123); - rk2818_mux_api_set(GPIOH_MMC0_SEL_NAME, IOMUXA_SDMMC0_CMD_DATA0_CLKOUT); - - return 0; -} - -static int rk2818_sdmmc1_io_init(void) -{ - rk2818_mux_api_set(GPIOG_MMC1_SEL_NAME, IOMUXA_SDMMC1_CMD_DATA0_CLKOUT); - rk2818_mux_api_set(GPIOG_MMC1D_SEL_NAME, IOMUXA_SDMMC1_DATA123); - - return 0; -} -#define CONFIG_SDMMC0_USE_DMA -#define CONFIG_SDMMC1_USE_DMA -struct rk2818_sdmmc_platform_data default_sdmmc0_data = { - .host_ocr_avail = (MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30| - MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33| - MMC_VDD_33_34|MMC_VDD_34_35| MMC_VDD_35_36), - .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED), - .io_init = rk2818_sdmmc0_io_init, - .no_detect = 0, - .dma_name = "sd_mmc", -#ifdef CONFIG_SDMMC0_USE_DMA - .use_dma = 1, -#else - .use_dma = 0, -#endif -}; - -static int raho_wifi_status(struct device *dev); -static int raho_wifi_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id); -struct rk2818_sdmmc_platform_data default_sdmmc1_data = { - .host_ocr_avail = (MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29| - MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32| - MMC_VDD_32_33|MMC_VDD_33_34), - .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_SDIO_IRQ| - MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED), - .io_init = rk2818_sdmmc1_io_init, - .no_detect = 1, - .dma_name = "sdio", -#ifdef CONFIG_SDMMC1_USE_DMA - .use_dma = 1, -#else - .use_dma = 0, -#endif - .status = raho_wifi_status, - .register_status_notify = raho_wifi_status_register, -}; - -static int raho_wifi_cd; /* wifi virtual 'card detect' status */ -static void (*wifi_status_cb)(int card_present, void *dev_id); -static void *wifi_status_cb_devid; - -static int raho_wifi_status(struct device *dev) -{ - return raho_wifi_cd; -} - -static int raho_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id) -{ - if(wifi_status_cb) - return -EAGAIN; - wifi_status_cb = callback; - wifi_status_cb_devid = dev_id; - return 0; -} - -#define RAHO_WIFI_GPIO_POWER_N FPGA_PIO1_06 -#define RAHO_WIFI_GPIO_RESET_N FPGA_PIO1_03 - -int raho_wifi_power_state = 0; -int raho_bt_power_state = 0; - -static int raho_wifi_power(int on) -{ - pr_info("%s: %d\n", __func__, on); - if (on){ - gpio_set_value(RAHO_WIFI_GPIO_POWER_N, on); - mdelay(100); - pr_info("wifi turn on power\n"); - }else{ - if (!raho_bt_power_state){ - gpio_set_value(RAHO_WIFI_GPIO_POWER_N, on); - mdelay(100); - pr_info("wifi shut off power\n"); - }else - { - pr_info("wifi shouldn't shut off power, bt is using it!\n"); - } - - } - - raho_wifi_power_state = on; - return 0; -} - -static int raho_wifi_reset_state; -static int raho_wifi_reset(int on) -{ - pr_info("%s: %d\n", __func__, on); - gpio_set_value(RAHO_WIFI_GPIO_RESET_N, on); - mdelay(100); - raho_wifi_reset_state = on; - return 0; -} - -static int raho_wifi_set_carddetect(int val) -{ - pr_info("%s:%d\n", __func__, val); - raho_wifi_cd = val; - if (wifi_status_cb){ - wifi_status_cb(val, wifi_status_cb_devid); - }else { - pr_warning("%s, nobody to notify\n", __func__); - } - return 0; -} - -static struct wifi_platform_data raho_wifi_control = { - .set_power = raho_wifi_power, - .set_reset = raho_wifi_reset, - .set_carddetect = raho_wifi_set_carddetect, -}; -static struct platform_device raho_wifi_device = { - .name = "bcm4329_wlan", - .id = 1, - .dev = { - .platform_data = &raho_wifi_control, - }, -}; - -/* bluetooth rfkill device */ -static struct platform_device raho_rfkill = { - .name = "raho_rfkill", - .id = -1, -}; - -/***************************************************************************************** - * extern gpio devices - * author: xxx@rock-chips.com - *****************************************************************************************/ -#if defined (CONFIG_GPIO_PCA9554) -struct rk2818_gpio_expander_info extern_gpio_settinginfo[] = { - { - .gpio_num =RK2818_PIN_PI0, - .pin_type = GPIO_IN, - //.pin_value =GPIO_HIGH, - }, - - { - .gpio_num =RK2818_PIN_PI4,// tp3 - .pin_type = GPIO_IN, - //.pin_value =GPIO_HIGH, - }, - - { - .gpio_num =RK2818_PIN_PI5,//tp4 - .pin_type = GPIO_IN, - //.pin_value =GPIO_HIGH, - }, - { - .gpio_num =RK2818_PIN_PI6,//tp2 - .pin_type = GPIO_OUT, - //.pin_value =GPIO_HIGH, - }, - { - .gpio_num =RK2818_PIN_PI7,//tp1 - .pin_type = GPIO_OUT, - .pin_value =GPIO_HIGH, - }, - - - -}; - -struct pca9554_platform_data rk2818_pca9554_data={ - .gpio_base=GPIO_EXPANDER_BASE, - .gpio_pin_num=CONFIG_EXPANDED_GPIO_NUM, - .gpio_irq_start=NR_AIC_IRQS + 2*NUM_GROUP, - .irq_pin_num=CONFIG_EXPANDED_GPIO_IRQ_NUM, - .pca9954_irq_pin=RK2818_PIN_PE2, - .settinginfo=extern_gpio_settinginfo, - .settinginfolen=ARRAY_SIZE(extern_gpio_settinginfo), -}; -#endif - -/***************************************************************************************** - *regulator devices drivers/regulator/rk2818_lp8725.c linux/regulator/rk2818_lp8725.h - *author: cym -*****************************************************************************************/ -#if defined (CONFIG_RK2818_REGULATOR_LP8725) - -/*DVS pin control, make sure it is high level at start.*/ -int rk2818_lp8725_pm_control(void) -{ - rk2818_mux_api_set(GPIOC_LCDC24BIT_SEL_NAME, IOMUXB_GPIO0_C2_7); - gpio_request(RK2818_PIN_PC2,NULL); - gpio_direction_output(RK2818_PIN_PC2,1); - gpio_set_value(RK2818_PIN_PC2,1); - return 0; -} - -/*ldo1 2V8OUT USB2.5V LCD_VCC*/ -static struct regulator_consumer_supply ldo1_consumers[] = { - { - .supply = "ldo1", - } -}; - -static struct regulator_init_data rk2818_lp8725_ldo1_data = { - .constraints = { - .name = "LDO1", - .min_uV = 1200000, - .max_uV = 3300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo1_consumers), - .consumer_supplies = ldo1_consumers, -}; - -/*ldo2 CAMERA_1V8 SD_CARD*/ -static struct regulator_consumer_supply ldo2_consumers[] = { - { - .supply = "ldo2", - } -}; - -static struct regulator_init_data rk2818_lp8725_ldo2_data = { - .constraints = { - .name = "LDO2", - .min_uV = 1200000, - .max_uV = 3300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers), - .consumer_supplies = ldo2_consumers, -}; - -/*ldo3 VCC_NAND WIFI/BT/FM_BCM4325*/ -static struct regulator_consumer_supply ldo3_consumers[] = { - { - .supply = "ldo3", - } -}; - -static struct regulator_init_data rk2818_lp8725_ldo3_data = { - .constraints = { - .name = "LDO3", - .min_uV = 1200000, - .max_uV = 3300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo3_consumers), - .consumer_supplies = ldo3_consumers, -}; - -/*ldo4 VCCA CODEC_WM8994*/ -static struct regulator_consumer_supply ldo4_consumers[] = { - { - .supply = "ldo4", - } -}; - -static struct regulator_init_data rk2818_lp8725_ldo4_data = { - .constraints = { - .name = "LDO4", - .min_uV = 1200000, - .max_uV = 3300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo4_consumers), - .consumer_supplies = ldo4_consumers, -}; - -/*ldo5 AVDD18 CODEC_WM8994*/ -static struct regulator_consumer_supply ldo5_consumers[] = { - { - .supply = "ldo5", - } -}; - -static struct regulator_init_data rk2818_lp8725_ldo5_data = { - .constraints = { - .name = "LDO5", - .min_uV = 1200000, - .max_uV = 3300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo5_consumers), - .consumer_supplies = ldo5_consumers, -}; - -/*lilo1 VCCIO Sensor£¨3M£©*/ -static struct regulator_consumer_supply lilo1_consumers[] = { - { - .supply = "lilo1", - } -}; - -static struct regulator_init_data rk2818_lp8725_lilo1_data = { - .constraints = { - .name = "LILO1", - .min_uV = 800000, - .max_uV = 3300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(lilo1_consumers), - .consumer_supplies = lilo1_consumers -}; - -/*lilo2 VCC33_SD Sensor£¨3M£©*/ -static struct regulator_consumer_supply lilo2_consumers[] = { - { - .supply = "lilo2", - } -}; - -static struct regulator_init_data rk2818_lp8725_lilo2_data = { - .constraints = { - .name = "LILO2", - .min_uV = 800000, - .max_uV = 3300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(lilo2_consumers), - .consumer_supplies = lilo2_consumers -}; - -/*buck1 VDD12 Core*/ -static struct regulator_consumer_supply buck1_consumers[] = { - { - .supply = "vdd12", - } -}; - -static struct regulator_init_data rk2818_lp8725_buck1_data = { - .constraints = { - .name = "VDD12", - .min_uV = 800000, - .max_uV = 1500000, - .apply_uV = 1, - .always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE, - .valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL, - }, - .num_consumer_supplies = ARRAY_SIZE(buck1_consumers), - .consumer_supplies = buck1_consumers -}; - -/*buck2 VDDDR MobileDDR VCC*/ -static struct regulator_consumer_supply buck2_consumers[] = { - { - .supply = "vccdr", - } -}; - -static struct regulator_init_data rk2818_lp8725_buck2_data = { - .constraints = { - .name = "VCCDR", - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = 1, - .always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(buck2_consumers), - .consumer_supplies = buck2_consumers -}; - -/*buck1_v2 VDD12 Core*/ -static struct regulator_consumer_supply buck1_v2_consumers[] = { - { - .supply = "vdd12_v2", - } -}; - -static struct regulator_init_data rk2818_lp8725_buck1_v2_data = { - .constraints = { - .name = "VDD12_V2", - .min_uV = 800000, - .max_uV = 1500000, - .apply_uV = 1, - //.always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE, - }, - .num_consumer_supplies = ARRAY_SIZE(buck1_v2_consumers), - .consumer_supplies = buck1_v2_consumers -}; - -/*buck2_v2 VDDDR MobileDDR VCC*/ -static struct regulator_consumer_supply buck2_v2_consumers[] = { - { - .supply = "vccdr_v2", - } -}; - -static struct regulator_init_data rk2818_lp8725_buck2_v2_data = { - .constraints = { - .name = "VCCDR_V2", - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = 1, - //.always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(buck2_v2_consumers), - .consumer_supplies = buck2_v2_consumers -}; - -struct lp8725_regulator_subdev rk2818_lp8725_regulator_subdev[] = { - { - .id=LP8725_LDO1, - .initdata=&rk2818_lp8725_ldo1_data, - }, - - { - .id=LP8725_LDO2, - .initdata=&rk2818_lp8725_ldo2_data, - }, - - { - .id=LP8725_LDO3, - .initdata=&rk2818_lp8725_ldo3_data, - }, - - { - .id=LP8725_LDO4, - .initdata=&rk2818_lp8725_ldo4_data, - }, - - { - .id=LP8725_LDO5, - .initdata=&rk2818_lp8725_ldo5_data, - }, - - { - .id=LP8725_LILO1, - .initdata=&rk2818_lp8725_lilo1_data, - }, - - { - .id=LP8725_LILO2, - .initdata=&rk2818_lp8725_lilo2_data, - }, - - { - .id=LP8725_DCDC1, - .initdata=&rk2818_lp8725_buck1_data, - }, - - { - .id=LP8725_DCDC2, - .initdata=&rk2818_lp8725_buck2_data, - }, - { - .id=LP8725_DCDC1_V2, - .initdata=&rk2818_lp8725_buck1_v2_data, - }, - - { - .id=LP8725_DCDC2_V2, - .initdata=&rk2818_lp8725_buck2_v2_data, - }, -}; - -struct lp8725_platform_data rk2818_lp8725_data={ - .num_regulators=LP8725_NUM_REGULATORS, - .regulators=rk2818_lp8725_regulator_subdev, -}; -#endif - -/***************************************************************************************** - * gsensor devices -*****************************************************************************************/ -#define GS_IRQ_PIN RK2818_PIN_PE3 - -struct rk2818_gs_platform_data rk2818_gs_platdata = { - .gsensor_irq_pin = GS_IRQ_PIN, - .swap_xy = 0, -}; - -/***************************************************************************************** - * wm8994 codec - * author: cjq@rock-chips.com - *****************************************************************************************/ -static struct wm8994_platform_data wm8994_data = { - .mic_input = 0, - .micBase_vcc = 0, - .bb_input = 0, - .bb_output = 0, - .frequence = 0, - .enable_pin = 0, - .headset_pin = 0, - .headset_call_vol = 0, - .speaker_call_vol = 0, - .earpiece_call_vol = 0, - .bt_call_vol = 0, -};// must initialize - -/***************************************************************************************** - * rtc - *****************************************************************************************/ -#define RTC_IRQ_PIN RK2818_PIN_PE2 - -static int rk2818_rtc_io_init(void) -{ - return 0; -} - -static int rk2818_rtc_io_deinit(void) -{ - return 0; -} - -static struct rk2818_rtc_platform_data rtc_data = { - .irq_type = GPIO_HIGH,//irq type - .io_init = rk2818_rtc_io_init, - .io_deinit = rk2818_rtc_io_deinit, -}; - -/***************************************************************************************** - * i2c devices - * author: kfx@rock-chips.com -*****************************************************************************************/ -static int rk2818_i2c0_io_init(void) -{ - rk2818_mux_api_set(GPIOE_I2C0_SEL_NAME, IOMUXA_I2C0); - return 0; -} - -static int rk2818_i2c1_io_init(void) -{ - rk2818_mux_api_set(GPIOE_U1IR_I2C1_NAME, IOMUXA_I2C1); - return 0; -} - -struct rk2818_i2c_platform_data default_i2c0_data = { - .bus_num = 0, - .flags = 0, - .slave_addr = 0xff, - .scl_rate = 400*1000, - .mode = I2C_MODE_IRQ, //I2C_MODE_POLL - .io_init = rk2818_i2c0_io_init, -}; -struct rk2818_i2c_platform_data default_i2c1_data = { -#ifdef CONFIG_I2C0_RK2818 - .bus_num = 1, -#else - .bus_num = 0, -#endif - .flags = 0, - .slave_addr = 0xff, - .scl_rate = 400*1000, - .mode = I2C_MODE_POLL, //I2C_MODE_POLL - .io_init = rk2818_i2c1_io_init, -}; - -struct rk2818_i2c_spi_data default_i2c2_data = { - .bus_num = 2, - .flags = 0, - .slave_addr = 0xff, - .scl_rate = 400*1000, - -}; -struct rk2818_i2c_spi_data default_i2c3_data = { - - .bus_num = 3, - .flags = 0, - .slave_addr = 0xff, - .scl_rate = 400*1000, - -}; -static struct i2c_board_info __initdata board_i2c0_devices[] = { -#if defined (CONFIG_RK1000_CONTROL) - { - .type = "rk1000_control", - .addr = 0x40, - .flags = 0, - }, -#endif - -#if defined (CONFIG_RK1000_TVOUT) - { - .type = "rk1000_tvout", - .addr = 0x42, - .flags = 0, - }, -#endif -#if defined (CONFIG_SND_SOC_RK1000) - { - .type = "rk1000_i2c_codec", - .addr = 0x60, - .flags = 0, - }, -#endif -#if defined (CONFIG_SND_SOC_WM8988) - { - .type = "wm8988", - .addr = 0x1a, - .flags = 0, - } -#endif -#if defined (CONFIG_TOUCHSCREEN_IT7250) //add by robert for ctp_it7250 - { - .type = "Ctp_it7250", - .addr = 0x46, - .flags = 0, - .irq = RK2818_PIN_PE1, - }, -#endif //end add -}; -static struct i2c_board_info __initdata board_i2c1_devices[] = { -#if defined (CONFIG_RTC_HYM8563) - { - .type = "rtc_hym8563", - .addr = 0x51, - .flags = 0, - }, -#endif -#if defined (CONFIG_RTC_DRV_S35392A) - { - .type = "rtc-s35392a", - .addr = 0x30, - .flags = 0, - .irq = RTC_IRQ_PIN, - .platform_data = &rtc_data, - }, -#endif -#if defined (CONFIG_FM_QN8006) - { - .type = "fm_qn8006", - .addr = 0x2b, - .flags = 0, - }, -#endif -#if defined (CONFIG_GPIO_PCA9554) - { - .type = "extend_gpio_pca9554", - .addr = 0x3c, - .flags = 0, - .platform_data=&rk2818_pca9554_data.gpio_base, - }, -#endif -#if defined (CONFIG_RK2818_REGULATOR_LP8725) - { - .type = "lp8725", - .addr = 0x79, - .flags = 0, - .platform_data=&rk2818_lp8725_data, - }, -#endif -#if defined (CONFIG_GS_MMA7660) - { - .type = "gs_mma7660", - .addr = 0x4c, - .flags = 0, - .irq = GS_IRQ_PIN, - .platform_data = &rk2818_gs_platdata, - }, -#endif - -}; - -static struct i2c_board_info __initdata board_i2c2_devices[] = { - -}; - -static struct i2c_board_info __initdata board_i2c3_devices[] = { -#if defined (CONFIG_SND_SOC_WM8994) - { - .type = "wm8994", - .addr = 0x1a, - .flags = 0, - .platform_data = &wm8994_data, - }, -#endif -}; - -/* - * External power - */ - -static int power_supply_init(struct device *dev) -{ - return gpio_request(FPGA_PIO2_08, "AC charger detect"); -} - -static int rk2818_is_ac_online(void) -{ - return !gpio_get_value(FPGA_PIO2_08); -} - -static void power_supply_exit(struct device *dev) -{ - gpio_free(FPGA_PIO2_08); -} - -static char *rk2818_supplicant[] = { - "rk2818-battery" -}; - -static struct pda_power_pdata power_supply_info = { - .init = power_supply_init, - .is_ac_online = rk2818_is_ac_online, - .exit = power_supply_exit, - .supplied_to = rk2818_supplicant, - .num_supplicants = ARRAY_SIZE(rk2818_supplicant), -}; - -static struct resource power_supply_resources[] = { - [0] = { - .name = "ac", - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | - IORESOURCE_IRQ_LOWEDGE, - }, - [1] = { - .name = "usb", - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | - IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct platform_device power_supply = { - .name = "pda-power", - .id = -1, - .dev = { - .platform_data = &power_supply_info, - }, - .resource = power_supply_resources, - .num_resources = ARRAY_SIZE(power_supply_resources), -}; - -/* - * USB "Transceiver" - */ - -static struct resource gpio_vbus_resource = { - .flags = IORESOURCE_IRQ, - .start = IRQ_NR_OTG, - .end = IRQ_NR_OTG, -}; - -static struct gpio_vbus_mach_info gpio_vbus_info = { - .gpio_vbus = FPGA_PIO4_06, -}; - -static struct platform_device gpio_vbus = { - .name = "gpio-vbus", - .id = -1, - .num_resources = 1, - .resource = &gpio_vbus_resource, - .dev = { - .platform_data = &gpio_vbus_info, - }, -}; - -/* - * Battery charger - */ - -static struct regulator_consumer_supply rk2818_consumers[] = { - { - .dev=&rk2818_device_battery.dev, - .supply = "battery", - }, - { - .dev = &gpio_vbus.dev, - .supply = "vbus_draw", - }, - { - .dev = &power_supply.dev, - .supply = "ac_draw", - }, -}; - -static struct regulator_init_data charge_init_data = { - .constraints = { - .max_uA = 1200000, - .valid_ops_mask = REGULATOR_CHANGE_CURRENT, - }, - .num_consumer_supplies = ARRAY_SIZE(rk2818_consumers), - .consumer_supplies = rk2818_consumers, -}; - -static struct charge_platform_data charge_current_info = { - .gpio_charge = FPGA_PIO2_08, - .init_data = &charge_init_data, -}; - -static struct platform_device charge_current = { - .name = "charge-regulator", - .id = -1, - .dev = { - .platform_data = &charge_current_info, - }, -}; - -/***************************************************************************************** - * camera devices - * author: ddl@rock-chips.com - *****************************************************************************************/ -#ifdef CONFIG_VIDEO_RK2818 -/* Board-raho camera configuration */ -#define SENSOR_NAME_0 RK28_CAM_SENSOR_NAME_OV2655 -#define SENSOR_IIC_ADDR_0 0x60 -#define SENSOR_IIC_ADAPTER_ID_0 2 -#define SENSOR_POWER_PIN_0 FPGA_PIO1_05 -#define SENSOR_RESET_PIN_0 FPGA_PIO1_14 -#define SENSOR_POWERACTIVE_LEVEL_0 RK28_CAM_POWERACTIVE_L -#define SENSOR_RESETACTIVE_LEVEL_0 RK28_CAM_RESETACTIVE_L - - -#define SENSOR_NAME_1 NULL -#define SENSOR_IIC_ADDR_1 0x00 -#define SENSOR_IIC_ADAPTER_ID_1 0xff -#define SENSOR_POWER_PIN_1 INVALID_GPIO -#define SENSOR_RESET_PIN_1 INVALID_GPIO -#define SENSOR_POWERACTIVE_LEVEL_1 RK28_CAM_POWERACTIVE_L -#define SENSOR_RESETACTIVE_LEVEL_1 RK28_CAM_RESETACTIVE_L - -static int rk28_sensor_io_init(void); -static int rk28_sensor_io_deinit(void); - -struct rk28camera_platform_data rk28_camera_platform_data = { - .io_init = rk28_sensor_io_init, - .io_deinit = rk28_sensor_io_deinit, - .gpio_res = { - { - .gpio_reset = SENSOR_RESET_PIN_0, - .gpio_power = SENSOR_POWER_PIN_0, - .gpio_flag = (SENSOR_POWERACTIVE_LEVEL_0|SENSOR_RESETACTIVE_LEVEL_0), - .dev_name = SENSOR_NAME_0, - }, { - .gpio_reset = SENSOR_RESET_PIN_1, - .gpio_power = SENSOR_POWER_PIN_1, - .gpio_flag = (SENSOR_POWERACTIVE_LEVEL_1|SENSOR_RESETACTIVE_LEVEL_1), - .dev_name = SENSOR_NAME_1, - } - } -}; - -static int rk28_sensor_io_init(void) -{ - int ret = 0, i; - unsigned int camera_reset = INVALID_GPIO, camera_power = INVALID_GPIO; - unsigned int camera_ioflag; - //printk("\n%s....%d ******** ddl *********\n",__FUNCTION__,__LINE__); - - for (i=0; i<2; i++) { - camera_reset = rk28_camera_platform_data.gpio_res[i].gpio_reset; - camera_power = rk28_camera_platform_data.gpio_res[i].gpio_power; - camera_ioflag = rk28_camera_platform_data.gpio_res[i].gpio_flag; - - if (camera_power != INVALID_GPIO) { - ret = gpio_request(camera_power, "camera power"); - if (ret) - continue; - - gpio_set_value(camera_reset, (((~camera_ioflag)&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - gpio_direction_output(camera_power, (((~camera_ioflag)&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - - //printk("\n%s....%d %x ******** ddl *********\n",__FUNCTION__,__LINE__,(((~camera_ioflag)&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - - } - - if (camera_reset != INVALID_GPIO) { - ret = gpio_request(camera_reset, "camera reset"); - if (ret) { - if (camera_power != INVALID_GPIO) - gpio_free(camera_power); - - continue; - } - - gpio_set_value(camera_reset, ((camera_ioflag&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - gpio_direction_output(camera_reset, ((camera_ioflag&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - - //printk("\n%s....%d %x ******** ddl *********\n",__FUNCTION__,__LINE__,((camera_ioflag&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - - } - } - - return 0; -} - -static int rk28_sensor_io_deinit(void) -{ - unsigned int i; - unsigned int camera_reset = INVALID_GPIO, camera_power = INVALID_GPIO; - - //printk("\n%s....%d ******** ddl *********\n",__FUNCTION__,__LINE__); - - for (i=0; i<2; i++) { - camera_reset = rk28_camera_platform_data.gpio_res[i].gpio_reset; - camera_power = rk28_camera_platform_data.gpio_res[i].gpio_power; - - if (camera_power != INVALID_GPIO){ - gpio_direction_input(camera_power); - gpio_free(camera_power); - } - - if (camera_reset != INVALID_GPIO) { - gpio_direction_input(camera_reset); - gpio_free(camera_reset); - } - } - - return 0; -} - - -static int rk28_sensor_power(struct device *dev, int on) -{ - unsigned int camera_reset = INVALID_GPIO, camera_power = INVALID_GPIO; - unsigned int camera_ioflag; - - if(rk28_camera_platform_data.gpio_res[0].dev_name && (strcmp(rk28_camera_platform_data.gpio_res[0].dev_name, dev_name(dev)) == 0)) { - camera_reset = rk28_camera_platform_data.gpio_res[0].gpio_reset; - camera_power = rk28_camera_platform_data.gpio_res[0].gpio_power; - camera_ioflag = rk28_camera_platform_data.gpio_res[0].gpio_flag; - } else if (rk28_camera_platform_data.gpio_res[1].dev_name && (strcmp(rk28_camera_platform_data.gpio_res[1].dev_name, dev_name(dev)) == 0)) { - camera_reset = rk28_camera_platform_data.gpio_res[1].gpio_reset; - camera_power = rk28_camera_platform_data.gpio_res[1].gpio_power; - camera_ioflag = rk28_camera_platform_data.gpio_res[1].gpio_flag; - } - - if (camera_reset != INVALID_GPIO) { - gpio_set_value(camera_reset, ((camera_ioflag&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - //printk("\n%s..%s..ResetPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev),camera_reset, ((camera_ioflag&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - } - if (camera_power != INVALID_GPIO) { - if (on) { - gpio_set_value(camera_power, ((camera_ioflag&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - //printk("\n%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev), camera_power, ((camera_ioflag&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - } else { - gpio_set_value(camera_power, (((~camera_ioflag)&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - //printk("\n%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev), camera_power, (((~camera_ioflag)&RK28_CAM_POWERACTIVE_MASK)>>RK28_CAM_POWERACTIVE_BITPOS)); - } - } - if (camera_reset != INVALID_GPIO) { - msleep(3); /* delay 3 ms */ - gpio_set_value(camera_reset,(((~camera_ioflag)&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - //printk("\n%s..%s..ResetPin= %d..PinLevel = %x \n",__FUNCTION__,dev_name(dev), camera_reset, (((~camera_ioflag)&RK28_CAM_RESETACTIVE_MASK)>>RK28_CAM_RESETACTIVE_BITPOS)); - } - return 0; -} - -static struct i2c_board_info rk2818_i2c_cam_info[] = { - { - I2C_BOARD_INFO(SENSOR_NAME_0, SENSOR_IIC_ADDR_0>>1) - }, -}; - -struct soc_camera_link rk2818_iclink = { - .bus_id = RK28_CAM_PLATFORM_DEV_ID, - .power = rk28_sensor_power, - .board_info = &rk2818_i2c_cam_info[0], - .i2c_adapter_id = SENSOR_IIC_ADAPTER_ID_0, - .module_name = SENSOR_NAME_0, -}; - -/*platform_device : soc-camera need */ -struct platform_device rk2818_soc_camera_pdrv = { - .name = "soc-camera-pdrv", - .id = -1, - .dev = { - .init_name = SENSOR_NAME_0, - .platform_data = &rk2818_iclink, - }, -}; -#endif -/***************************************************************************************** - * battery devices - * author: lw@rock-chips.com - *****************************************************************************************/ -#define CHARGEOK_PIN FPGA_PIO0_06 -struct rk2818_battery_platform_data rk2818_battery_platdata = { - .charge_ok_pin = CHARGEOK_PIN, - .charge_ok_level = 0, -}; - - -/***************************************************************************************** - * serial devices - * author: lhh@rock-chips.com - *****************************************************************************************/ -static int serial_io_init(void) -{ - int ret; -#if 1 - //cz@rock-chips.com - //20100808 - //UART0µÄËĸö¹Ü½ÅÏÈIOMUX³ÉGPIO - //È»ºó·Ö±ðÉèÖÃÊäÈëÊä³ö/À­¸ßÀ­µÍ´¦Àí - //×îºóÔÙIOMUX³ÉUART - //·ÀÖ¹Ö±½ÓIOMUX³ÉUARTºóËĸö¹Ü½ÅµÄ״̬²»¶Ôʱ - //²Ù×÷UARTµ¼ÖÂUART_USR_BUSYʼÖÕΪ1Ôì³ÉÈçÏÂËÀÑ­»· - //while(rk2818_uart_read(port,UART_USR)&UART_USR_BUSY) - //UARTËĸö¹Ü½ÅÔÚδ´«ÊäʱÕý³£×´Ì¬Ó¦¸ÃΪ£º - //RX/TX£ºHIGH - //CTS/RTS£ºLOW - //×¢Ò⣺CTS/RTSΪµÍÓÐЧ£¬Ó²¼þÉϲ»Ó¦¸ÃÇ¿ÐÐ×öÉÏÀ­ - rk2818_mux_api_set(GPIOG1_UART0_MMC1WPT_NAME, IOMUXA_GPIO1_C1 /*IOMUXA_UART0_SOUT*/); - rk2818_mux_api_set(GPIOG0_UART0_MMC1DET_NAME, IOMUXA_GPIO1_C0 /*IOMUXA_UART0_SIN*/); - - ret = gpio_request(RK2818_PIN_PG0, NULL); - if(ret != 0) - { - gpio_free(RK2818_PIN_PG0); - } - gpio_direction_output(RK2818_PIN_PG0,GPIO_HIGH); - - - ret = gpio_request(RK2818_PIN_PG1, NULL); - if(ret != 0) - { - gpio_free(RK2818_PIN_PG1); - } - gpio_direction_output(RK2818_PIN_PG1,GPIO_HIGH); - - gpio_pull_updown(RK2818_PIN_PG1,GPIOPullUp); - gpio_pull_updown(RK2818_PIN_PG0,GPIOPullUp); - - rk2818_mux_api_set(GPIOG1_UART0_MMC1WPT_NAME, IOMUXA_UART0_SOUT); - rk2818_mux_api_set(GPIOG0_UART0_MMC1DET_NAME, IOMUXA_UART0_SIN); - - rk2818_mux_api_set(GPIOB2_U0CTSN_SEL_NAME, IOMUXB_GPIO0_B2/*IOMUXB_UART0_CTS_N*/); - rk2818_mux_api_set(GPIOB3_U0RTSN_SEL_NAME, IOMUXB_GPIO0_B3/*IOMUXB_UART0_RTS_N*/); - - ret = gpio_request(RK2818_PIN_PB2, NULL); - if(ret != 0) - { - gpio_free(RK2818_PIN_PB2); - } - gpio_direction_input(RK2818_PIN_PB2); - // gpio_direction_output(RK2818_PIN_PB2,GPIO_LOW); - - ret = gpio_request(RK2818_PIN_PB3, NULL); - if(ret != 0) - { - gpio_free(RK2818_PIN_PB3); - } - gpio_direction_output(RK2818_PIN_PB3,GPIO_LOW); -#endif - - rk2818_mux_api_set(GPIOB2_U0CTSN_SEL_NAME, IOMUXB_UART0_CTS_N); - rk2818_mux_api_set(GPIOB3_U0RTSN_SEL_NAME, IOMUXB_UART0_RTS_N); - - return 0; -} - -struct rk2818_serial_platform_data rk2818_serial0_platdata = { - .io_init = serial_io_init, -}; - -/***************************************************************************************** - * i2s devices - * author: lhhrock-chips.com - *****************************************************************************************/ -static int i2s_io_init(void) -{ - /* Configure the I2S pins in correct mode */ - rk2818_mux_api_set(CXGPIO_I2S_SEL_NAME,IOMUXB_I2S_INTERFACE); - return 0; -} - -struct rk2818_i2s_platform_data rk2818_i2s_platdata = { - .io_init = i2s_io_init, -}; - - -/***************************************************************************************** - * spi devices - * author: lhhrock-chips.com - *****************************************************************************************/ -#define SPI_CHIPSELECT_NUM 3 -struct spi_cs_gpio rk2818_spi_cs_gpios[SPI_CHIPSELECT_NUM] = { - { - .name = "spi cs0", - .cs_gpio = RK2818_PIN_PB4, - .cs_iomux_name = GPIOB4_SPI0CS0_MMC0D4_NAME,//if no iomux,set it NULL - .cs_iomux_mode = IOMUXA_GPIO0_B4, - }, - { - .name = "spi cs1", - .cs_gpio = RK2818_PIN_PB0, - .cs_iomux_name = GPIOB0_SPI0CSN1_MMC1PCA_NAME, - .cs_iomux_mode = IOMUXA_GPIO0_B0, - }, - { - .name = "spi cs2", - .cs_gpio = RK2818_PIN_PF5, - .cs_iomux_name = GPIOF5_APWM3_DPWM3_NAME, - .cs_iomux_mode = IOMUXB_GPIO1_B5, - } -}; - -static int spi_io_init(struct spi_cs_gpio *cs_gpios, int cs_num) -{ - int i,j,ret; - //clk - rk2818_mux_api_set(GPIOB_SPI0_MMC0_NAME, IOMUXA_SPI0); - //cs - if (cs_gpios) { - for (i=0; i>>>>> lcd cs gpio_request err \n "); - } - } - - rk2818_mux_api_set(LCD_CLK_MUX_NAME, LCD_CLK_MUX_MODE); - if (LCD_CLK_PIN != INVALID_GPIO) { - ret = gpio_request(LCD_CLK_PIN, NULL); - if(ret != 0) - { - goto err2; - printk(">>>>>> lcd clk gpio_request err \n "); - } - } - - rk2818_mux_api_set(LCD_TXD_MUX_NAME, LCD_TXD_MUX_MODE); - if (LCD_TXD_PIN != INVALID_GPIO) { - ret = gpio_request(LCD_TXD_PIN, NULL); - if(ret != 0) - { - goto err3; - printk(">>>>>> lcd txd gpio_request err \n "); - } - } - - return 0; - -err3: - if (LCD_CLK_PIN != INVALID_GPIO) { - gpio_free(LCD_CLK_PIN); - } -err2: - if (LCD_CS_PIN != INVALID_GPIO) { - gpio_free(LCD_CS_PIN); - } -err1: - return ret; -} - -static int rk2818_lcd_io_deinit(void) -{ - int ret = 0; - - gpio_direction_output(LCD_CLK_PIN, 0); - gpio_set_value(LCD_CLK_PIN, GPIO_HIGH); - gpio_direction_output(LCD_TXD_PIN, 0); - gpio_set_value(LCD_TXD_PIN, GPIO_HIGH); - - gpio_free(LCD_CS_PIN); - rk2818_mux_api_mode_resume(LCD_CS_MUX_NAME); - gpio_free(LCD_CLK_PIN); - gpio_free(LCD_TXD_PIN); - rk2818_mux_api_mode_resume(LCD_TXD_MUX_NAME); - rk2818_mux_api_mode_resume(LCD_CLK_MUX_NAME); - - return ret; -} - -struct rk2818lcd_info rk2818_lcd_info = { - .txd_pin = LCD_TXD_PIN, - .clk_pin = LCD_CLK_PIN, - .cs_pin = LCD_CS_PIN, - .io_init = rk2818_lcd_io_init, - .io_deinit = rk2818_lcd_io_deinit, -}; - - -/***************************************************************************************** - * frame buffe devices - * author: zyw@rock-chips.com - *****************************************************************************************/ -#define FB_ID 0 -#define FB_DISPLAY_ON_PIN INVALID_GPIO -#define FB_LCD_STANDBY_PIN INVALID_GPIO -#define FB_MCU_FMK_PIN INVALID_GPIO - -#define FB_DISPLAY_ON_VALUE GPIO_LOW -#define FB_LCD_STANDBY_VALUE 0 - -#define FB_DISPLAY_ON_MUX_NAME NULL -#define FB_DISPLAY_ON_MUX_MODE 0 - -#define FB_LCD_STANDBY_MUX_NAME NULL -#define FB_LCD_STANDBY_MUX_MODE 1 - -#define FB_MCU_FMK_PIN_MUX_NAME NULL -#define FB_MCU_FMK_MUX_MODE 0 - -#define FB_DATA0_16_MUX_NAME GPIOC_LCDC16BIT_SEL_NAME -#define FB_DATA0_16_MUX_MODE 1 - -#define FB_DATA17_18_MUX_NAME GPIOC_LCDC18BIT_SEL_NAME -#define FB_DATA17_18_MUX_MODE 1 - -#define FB_DATA19_24_MUX_NAME GPIOC_LCDC24BIT_SEL_NAME -#define FB_DATA19_24_MUX_MODE 1 - -#define FB_DEN_MUX_NAME CXGPIO_LCDDEN_SEL_NAME -#define FB_DEN_MUX_MODE 1 - -#define FB_VSYNC_MUX_NAME CXGPIO_LCDVSYNC_SEL_NAME -#define FB_VSYNC_MUX_MODE 1 - -#define FB_MCU_FMK_MUX_NAME NULL -#define FB_MCU_FMK_MUX_MODE 0 - -static int rk2818_fb_io_init(struct rk2818_fb_setting_info *fb_setting) -{ - int ret = 0; - if(fb_setting->data_num <=16) - rk2818_mux_api_set(FB_DATA0_16_MUX_NAME, FB_DATA0_16_MUX_MODE); - if(fb_setting->data_num >16 && fb_setting->data_num<=18) - rk2818_mux_api_set(FB_DATA17_18_MUX_NAME, FB_DATA17_18_MUX_MODE); - if(fb_setting->data_num >18) - rk2818_mux_api_set(FB_DATA19_24_MUX_NAME, FB_DATA19_24_MUX_MODE); - - if(fb_setting->vsync_en) - rk2818_mux_api_set(FB_VSYNC_MUX_NAME, FB_VSYNC_MUX_MODE); - - if(fb_setting->den_en) - rk2818_mux_api_set(FB_DEN_MUX_NAME, FB_DEN_MUX_MODE); - - if(fb_setting->mcu_fmk_en && FB_MCU_FMK_MUX_NAME && (FB_MCU_FMK_PIN != INVALID_GPIO)) - { - rk2818_mux_api_set(FB_MCU_FMK_MUX_NAME, FB_MCU_FMK_MUX_MODE); - ret = gpio_request(FB_MCU_FMK_PIN, NULL); - if(ret != 0) - { - gpio_free(FB_MCU_FMK_PIN); - printk(">>>>>> FB_MCU_FMK_PIN gpio_request err \n "); - } - gpio_direction_input(FB_MCU_FMK_PIN); - } - - if(fb_setting->disp_on_en && FB_DISPLAY_ON_MUX_NAME && (FB_DISPLAY_ON_PIN != INVALID_GPIO)) - { - rk2818_mux_api_set(FB_DISPLAY_ON_MUX_NAME, FB_DISPLAY_ON_MUX_MODE); - ret = gpio_request(FB_DISPLAY_ON_PIN, NULL); - if(ret != 0) - { - gpio_free(FB_DISPLAY_ON_PIN); - printk(">>>>>> FB_DISPLAY_ON_PIN gpio_request err \n "); - } - } - - if(fb_setting->disp_on_en && FB_LCD_STANDBY_MUX_NAME && (FB_LCD_STANDBY_PIN != INVALID_GPIO)) - { - rk2818_mux_api_set(FB_LCD_STANDBY_MUX_NAME, FB_LCD_STANDBY_MUX_MODE); - ret = gpio_request(FB_LCD_STANDBY_PIN, NULL); - if(ret != 0) - { - gpio_free(FB_LCD_STANDBY_PIN); - printk(">>>>>> FB_LCD_STANDBY_PIN gpio_request err \n "); - } - } - - return ret; -} - -struct rk2818fb_info rk2818_fb_info = { - .fb_id = FB_ID, - .disp_on_pin = FB_DISPLAY_ON_PIN, - .disp_on_value = FB_DISPLAY_ON_VALUE, - .standby_pin = FB_LCD_STANDBY_PIN, - .standby_value = FB_LCD_STANDBY_VALUE, - .mcu_fmk_pin = FB_MCU_FMK_PIN, - .lcd_info = &rk2818_lcd_info, - .io_init = rk2818_fb_io_init, -}; - -/***************************************************************************************** - * backlight devices - * author: nzy@rock-chips.com - *****************************************************************************************/ - /* - GPIOF2_APWM0_SEL_NAME, IOMUXB_PWM0 - GPIOF3_APWM1_MMC0DETN_NAME, IOMUXA_PWM1 - GPIOF4_APWM2_MMC0WPT_NAME, IOMUXA_PWM2 - GPIOF5_APWM3_DPWM3_NAME, IOMUXB_PWM3 - */ - -#define PWM_ID 0 -#define PWM_MUX_NAME GPIOF2_APWM0_SEL_NAME -#define PWM_MUX_MODE IOMUXB_PWM0 -#define PWM_EFFECT_VALUE 0 - - -#define BL_EN_MUX_NAME GPIOF34_UART3_SEL_NAME -#define BL_EN_MUX_MODE IOMUXB_GPIO1_B34 - -#define BL_EN_PIN RK2818_PIN_PF3 -#define BL_EN_VALUE GPIO_HIGH - - - -static int rk2818_backlight_io_init(void) -{ - int ret = 0; - - rk2818_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE); - - rk2818_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE); - - ret = gpio_request(BL_EN_PIN, NULL); - if(ret != 0) - { - gpio_free(BL_EN_PIN); - printk(KERN_ERR ">>>>>> lcd_cs gpio_request err \n "); - } - - gpio_direction_output(BL_EN_PIN, 0); - gpio_set_value(BL_EN_PIN, BL_EN_VALUE); - - return ret; -} - -static int rk2818_backlight_io_deinit(void) -{ - int ret = 0; - - gpio_free(BL_EN_PIN); - - rk2818_mux_api_mode_resume(PWM_MUX_NAME); - - rk2818_mux_api_mode_resume(BL_EN_MUX_NAME); - - return ret; -} - -struct rk2818_bl_info rk2818_bl_info = { - .pwm_id = PWM_ID, - .bl_ref = PWM_EFFECT_VALUE, - .io_init = rk2818_backlight_io_init, - .io_deinit = rk2818_backlight_io_deinit, -}; - - -/***************************************************************************************** - * netcard devices - * author: lyx@rock-chips.com - *****************************************************************************************/ -#ifdef CONFIG_DM9000 -/* -GPIOA5_FLASHCS1_SEL_NAME IOMUXB_FLASH_CS1 -GPIOA6_FLASHCS2_SEL_NAME IOMUXB_FLASH_CS2 -GPIOA7_FLASHCS3_SEL_NAME IOMUXB_FLASH_CS3 -GPIOE_SPI1_FLASH_SEL1_NAME IOMUXA_FLASH_CS45 -GPIOE_SPI1_FLASH_SEL_NAME IOMUXA_FLASH_CS67 -*/ -#define DM9000_USE_NAND_CS 1 //cs can be 1,2,3,4,5,6 or 7 -#define DM9000_CS_IOMUX_NAME GPIOA5_FLASHCS1_SEL_NAME -#define DM9000_CS_IOMUX_MODE IOMUXB_FLASH_CS1 -#define DM9000_NET_INT_PIN RK2818_PIN_PA1 -#define DM9000_INT_IOMUX_NAME GPIOA1_HOSTDATA17_SEL_NAME -#define DM9000_INT_IOMUX_MODE IOMUXB_GPIO0_A1 -#define DM9000_INT_INIT_VALUE GPIOPullDown -#define DM9000_IRQ IRQF_TRIGGER_HIGH -#define DM9000_IO_ADDR (RK2818_NANDC_PHYS + 0x800 + DM9000_USE_NAND_CS*0x100 + 0x8) -#define DM9000_DATA_ADDR (RK2818_NANDC_PHYS + 0x800 + DM9000_USE_NAND_CS*0x100 + 0x4) - -static int dm9k_gpio_set(void) -{ - //cs - rk2818_mux_api_set(DM9000_CS_IOMUX_NAME, DM9000_CS_IOMUX_MODE); - //int - rk2818_mux_api_set(DM9000_INT_IOMUX_NAME, DM9000_INT_IOMUX_MODE); - - return 0; -} -static int dm9k_gpio_free(void) -{ - rk2818_mux_api_mode_resume(DM9000_INT_IOMUX_NAME); - rk2818_mux_api_mode_resume(DM9000_CS_IOMUX_NAME); - return 0; -} - -static struct resource dm9k_resource[] = { - [0] = { - .start = DM9000_IO_ADDR, - .end = DM9000_IO_ADDR + 3, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DM9000_DATA_ADDR, - .end = DM9000_DATA_ADDR + 3, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = DM9000_NET_INT_PIN, - .end = DM9000_NET_INT_PIN, - .flags = IORESOURCE_IRQ | DM9000_IRQ, - } - -}; - -/* for the moment we limit ourselves to 8bit IO until some - * better IO routines can be written and tested -*/ -struct dm9000_plat_data dm9k_platdata = { - .flags = DM9000_PLATF_8BITONLY, - .irq_pin = DM9000_NET_INT_PIN, - .irq_pin_value = DM9000_INT_INIT_VALUE, - .io_init = dm9k_gpio_set, - .io_deinit = dm9k_gpio_free, -}; - -struct platform_device rk2818_device_dm9k = { - .name = "dm9000", - .id = 0, - .num_resources = ARRAY_SIZE(dm9k_resource), - .resource = dm9k_resource, - .dev = { - .platform_data = &dm9k_platdata, - } -}; -#endif - -#ifdef CONFIG_HEADSET_DET -struct rk2818_headset_data rk2818_headset_info = { - .irq = FPGA_PIO0_00, - .irq_type = IRQF_TRIGGER_FALLING, - .headset_in_type= HEADSET_IN_HIGH, -}; - -struct platform_device rk28_device_headset = { - .name = "rk2818_headsetdet", - .id = 0, - .dev = { - .platform_data = &rk2818_headset_info, - } -}; -#endif - -#ifdef CONFIG_INPUT_LPSENSOR_CM3602 -static int capella_cm3602_power(int on); - -static struct capella_cm3602_platform_data capella_cm3602_pdata = { - .power = capella_cm3602_power, - .irq_pin = FPGA_PIO0_04, - .pwd_out_pin = FPGA_PIO4_07, - .ps_shutdown_pin = FPGA_PIO5_00, - //.p_out = MAHIMAHI_GPIO_PROXIMITY_INT_N - }; - -static int capella_cm3602_power(int on) -{ /* TODO eolsen Add Voltage reg control */ - if (on) { - printk("[%s]:on---\n",__FUNCTION__); - gpio_direction_output(capella_cm3602_pdata.pwd_out_pin, SPI_GPIO_LOW); - gpio_direction_output(capella_cm3602_pdata.ps_shutdown_pin, SPI_GPIO_LOW); - } - else { - printk("[%s]:off---\n",__FUNCTION__); - gpio_direction_output(capella_cm3602_pdata.pwd_out_pin, SPI_GPIO_HIGH); - gpio_direction_output(capella_cm3602_pdata.ps_shutdown_pin, SPI_GPIO_HIGH); - } - return 0; -} - -struct platform_device rk2818_device_cm3605 = { - .name = CAPELLA_CM3602, - .id = -1, - .dev = { - .platform_data = &capella_cm3602_pdata - } - }; -#endif - -/***************************************************************************************** - * nand flash devices - * author: hxy@rock-chips.com - *****************************************************************************************/ -/* -GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1 -GPIOA6_FLASHCS2_SEL_NAME, IOMUXB_FLASH_CS2 -GPIOA7_FLASHCS3_SEL_NAME, IOMUXB_FLASH_CS3 -GPIOE_SPI1_FLASH_SEL1_NAME, IOMUXA_FLASH_CS45 -GPIOE_SPI1_FLASH_SEL_NAME, IOMUXA_FLASH_CS67 -*/ - -#define NAND_CS_MAX_NUM 1 /*form 0 to 8, it is 0 when no nand flash */ - -int rk2818_nand_io_init(void) -{ -#if (NAND_CS_MAX_NUM == 2) - rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1); -#elif (NAND_CS_MAX_NUM == 3) - rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1); - rk2818_mux_api_set(GPIOA6_FLASHCS2_SEL_NAME, IOMUXB_FLASH_CS2); -#elif (NAND_CS_MAX_NUM == 4) - rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1); - rk2818_mux_api_set(GPIOA6_FLASHCS2_SEL_NAME, IOMUXB_FLASH_CS2); - rk2818_mux_api_set(GPIOA7_FLASHCS3_SEL_NAME, IOMUXB_FLASH_CS3); -#elif ((NAND_CS_MAX_NUM == 5) || (NAND_CS_MAX_NUM == 6)) - rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1); - rk2818_mux_api_set(GPIOA6_FLASHCS2_SEL_NAME, IOMUXB_FLASH_CS2); - rk2818_mux_api_set(GPIOA7_FLASHCS3_SEL_NAME, IOMUXB_FLASH_CS3); - rk2818_mux_api_set(GPIOE_SPI1_FLASH_SEL1_NAME, IOMUXA_FLASH_CS45); -#elif ((NAND_CS_MAX_NUM == 7) || (NAND_CS_MAX_NUM == 8)) - rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1); - rk2818_mux_api_set(GPIOA6_FLASHCS2_SEL_NAME, IOMUXB_FLASH_CS2); - rk2818_mux_api_set(GPIOA7_FLASHCS3_SEL_NAME, IOMUXB_FLASH_CS3); - rk2818_mux_api_set(GPIOE_SPI1_FLASH_SEL1_NAME, IOMUXA_FLASH_CS45); - rk2818_mux_api_set(GPIOE_SPI1_FLASH_SEL_NAME, IOMUXA_FLASH_CS67); -#endif - return 0; -} - -struct rk2818_nand_platform_data rk2818_nand_data = { - .width = 1, /* data bus width in bytes */ - .hw_ecc = 1, /* hw ecc 0: soft ecc */ - .num_flash = 1, - .io_init = rk2818_nand_io_init, -}; - - -/********************usb*********************/ -struct usb_mass_storage_platform_data mass_storage_pdata = { - .nluns = 1, - .vendor = "RockChip", - .product = "rk2818 sdk", - .release = 0x0100, -}; - - -static struct platform_device *devices[] __initdata = { -#ifdef CONFIG_BT - &raho_rfkill, -#endif -#ifdef CONFIG_UART0_RK2818 - &rk2818_device_uart0, -#endif -#ifdef CONFIG_UART1_RK2818 - &rk2818_device_uart1, -#endif -#ifdef CONFIG_I2C0_RK2818 - &rk2818_device_i2c0, -#endif -#ifdef CONFIG_I2C1_RK2818 - &rk2818_device_i2c1, -#endif -#ifdef CONFIG_SDMMC0_RK2818 - &rk2818_device_sdmmc0, -#endif -#ifdef CONFIG_SDMMC1_RK2818 - &rk2818_device_sdmmc1, -#endif - &raho_wifi_device, - &rk2818_device_spim, - &rk2818_device_i2s, -#if defined(CONFIG_ANDROID_PMEM) - &rk2818_device_pmem, - &rk2818_device_pmem_dsp, -#endif - &rk2818_device_adc, - &rk2818_device_adckey, -#if defined(CONFIG_RK2818_REGULATOR_CHARGE) - &power_supply, - &charge_current, -#endif - &rk2818_device_battery, - &rk2818_device_fb, - &rk2818_device_backlight, - &rk2818_device_dsp, - -#ifdef CONFIG_VIDEO_RK2818 - &rk2818_device_camera, /* ddl@rock-chips.com : camera support */ - &rk2818_soc_camera_pdrv, - #endif - -#ifdef CONFIG_MTD_NAND_RK2818 - &rk2818_nand_device, -#endif -#ifdef CONFIG_DM9000 - &rk2818_device_dm9k, -#endif -#ifdef CONFIG_INPUT_LPSENSOR_CM3602 - &rk2818_device_cm3605, -#endif -#ifdef CONFIG_HEADSET_DET - &rk28_device_headset, -#endif -#ifdef CONFIG_DWC_OTG - &rk2818_device_dwc_otg, -#endif -#ifdef CONFIG_RK2818_HOST11 - &rk2818_device_host11, -#endif -#ifdef CONFIG_USB_ANDROID - &android_usb_device, - &usb_mass_storage_device, -#endif -#ifdef CONFIG_ANDROID_TIMED_GPIO - &rk28_device_vibrator, -#endif -}; - -extern struct sys_timer rk2818_timer; -#define POWER_PIN RK2818_PIN_PB1 -static void rk2818_power_on(void) -{ - int ret; - ret = gpio_request(POWER_PIN, NULL); - if (ret) { - printk("failed to request power_off gpio\n"); - goto err_free_gpio; - } - - gpio_pull_updown(POWER_PIN, GPIOPullUp); - ret = gpio_direction_output(POWER_PIN, GPIO_HIGH); - if (ret) { - printk("failed to set power_off gpio output\n"); - goto err_free_gpio; - } - - gpio_set_value(POWER_PIN, 1);/*power on*/ - -err_free_gpio: - gpio_free(POWER_PIN); -} - -static void rk2818_power_off(void) -{ - printk("shut down system now ...\n"); - gpio_set_value(POWER_PIN, 0);/*power down*/ -} - -// adc ---> key -#define PLAY_ON_PIN RK2818_PIN_PA3 -#define PLAY_ON_LEVEL 1 -static ADC_keyst gAdcValueTab[] = -{ - {0x65, AD2KEY1},///VOLUME_DOWN - {0xd3, AD2KEY2},///VOLUME_UP - {0x130, AD2KEY3},///MENU - {0x19d, AD2KEY4},///HOME - {0x202, AD2KEY5},///BACK - {0x2d0, AD2KEY6},///CALL - {0x267, AD2KEY7},///SEARCH - {0, 0}///table end -}; - -static unsigned char gInitKeyCode[] = -{ - AD2KEY1,AD2KEY2,AD2KEY3,AD2KEY4,AD2KEY5,AD2KEY6,AD2KEY7, - ENDCALL,KEYSTART,KEY_WAKEUP, -}; - -static struct adc_key_data rk2818_adc_key = { - .pin_playon = PLAY_ON_PIN, - .playon_level = PLAY_ON_LEVEL, - .adc_empty = 1000, - .adc_invalid = 20, - .adc_drift = 50, - .adc_chn = 1, - .adc_key_table = gAdcValueTab, - .initKeyCode = gInitKeyCode, - .adc_key_cnt = 10, -}; - -struct rk2818_adckey_platform_data rk2818_adckey_platdata = { - .adc_key = &rk2818_adc_key, - .name = "raho-keypad", -}; - -#if CONFIG_ANDROID_TIMED_GPIO -static struct timed_gpio timed_gpios[] = { - { - .name = "vibrator", - .gpio = SPI_GPIO_P1_12, - .max_timeout = 1000, - .active_low = 1, - }, -}; - -struct timed_gpio_platform_data rk28_vibrator_info = { - .num_gpios = 1, - .gpios = timed_gpios, -}; -#endif -#if defined (CONFIG_RK2818_SOC_PM) -void __tcmfunc rk2818_pm_scu_suspend(unsigned int *reg,int regoff) -{ - - switch(regoff) - { - case PM_SCU_CLKGATE0_CON: - { - } - - - } - -} - - - -void __tcmfunc rk2818_soc_general_reg_suspend(void) -{ - struct rk2818_pm_soc_st *general=rk2818_soc_pm.general; - - unsigned int *general_reg_addr=general->reg_base_addr; - #if 1 - general->reg_ctrbit|=(0x1<reg_ctrbit|=(0x1<reg_ctrbit|=(0x1<reg_ctrbit|=(0x1<reg_ctrbit|=(0x1<reg_ctrbit|=(0x1<> 18) & 0xfffc, - .boot_params = RK2818_SDRAM_PHYS + 0xf8000, - .map_io = machine_rk2818_mapio, - .init_irq = machine_rk2818_init_irq, - .init_machine = machine_rk2818_board_init, - .timer = &rk2818_timer, -MACHINE_END - diff --git a/arch/arm/mach-rk2818/clock.c b/arch/arm/mach-rk2818/clock.c deleted file mode 100644 index 6305d4881826..000000000000 --- a/arch/arm/mach-rk2818/clock.c +++ /dev/null @@ -1,1806 +0,0 @@ -/* arch/arm/mach-rk2818/clock.c - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -//#define DEBUG -#define pr_fmt(fmt) "clock: %s: " fmt, __func__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include // CPU_APB_REG0 - -#define CLKSEL0_REG (u32 __iomem *)(RK2818_SCU_BASE + SCU_CLKSEL0_CON) -#define CLKSEL1_REG (u32 __iomem *)(RK2818_SCU_BASE + SCU_CLKSEL1_CON) -#define CLKSEL2_REG (u32 __iomem *)(RK2818_SCU_BASE + SCU_CLKSEL2_CON) - -/* SCU PLL CON */ -#define PLL_TEST (0x01u<<25) -#define PLL_SAT (0x01u<<24) -#define PLL_FAST (0x01u<<23) -#define PLL_PD (0x01u<<22) -#define PLL_CLKR(i) (((i)&0x3f)<<16) -#define PLL_CLKF(i) (((i)&0x0fff)<<4) -#define PLL_CLKOD(i) (((i)&0x07)<<1) -#define PLL_BYPASS (0X01) - -/* SCU MODE CON */ -#define SCU_CPUMODE_MASK (0x03u << 2) -#define SCU_CPUMODE_SLOW (0x00u << 2) -#define SCU_CPUMODE_NORMAL (0x01u << 2) -#define SCU_CPUMODE_DSLOW (0x02u << 2) - -#define SCU_DSPMODE_MASK 0x03u -#define SCU_DSPMODE_SLOW 0x00u -#define SCU_DSPMODE_NORMAL 0x01u -#define SCU_DSPMODE_DSLOW 0x02u - -/* SCU CLK SEL0 CON */ -#define CLK_DDR_REG CLKSEL0_REG -#define CLK_DDR_SRC_MASK (3 << 28) -#define CLK_DDR_CODPLL (0 << 28) -#define CLK_DDR_ARMPLL (1 << 28) -#define CLK_DDR_DSPPLL (2 << 28) - -#define CLK_SENSOR_REG CLKSEL0_REG -#define CLK_SENSOR_SRC_MASK (3 << 23) -#define CLK_SENSOR_24M (0 << 23) -#define CLK_SENSOR_27M (1 << 23) -#define CLK_SENSOR_48M (2 << 23) - -#define CLK_USBPHY_REG CLKSEL0_REG -#define CLK_USBPHY_SRC_MASK (3 << 18) -#define CLK_USBPHY_24M (0 << 18) -#define CLK_USBPHY_12M (1 << 18) -#define CLK_USBPHY_48M (2 << 18) - -#define CLK_LCDC_REG CLKSEL0_REG -#define CLK_LCDC_DIV_SRC_MASK (3 << 16) -#define CLK_LCDC_ARMPLL (0 << 16) -#define CLK_LCDC_DSPPLL (1 << 16) -#define CLK_LCDC_CODPLL (2 << 16) -#define CLK_LCDC_SRC_MASK (1 << 7) -#define CLK_LCDC_DIVOUT (0 << 7) -#define CLK_LCDC_27M (1 << 7) - -/* SCU CLKSEL1 CON */ -#define CLK_UART_REG CLKSEL1_REG -#define CLK_UART_SRC_MASK (1 << 31) -#define CLK_UART_24M (0 << 31) -#define CLK_UART_48M (1 << 31) - -#define CLK_DEMOD_REG CLKSEL1_REG -#define CLK_DEMOD_SRC_MASK (1 << 26) -#define CLK_DEMOD_DIVOUT (0 << 26) -#define CLK_DEMOD_27M (1 << 26) -#define CLK_DEMOD_DIV_SRC_MASK (3 << 24) -#define CLK_DEMOD_CODPLL (0 << 24) -#define CLK_DEMOD_ARMPLL (1 << 24) -#define CLK_DEMOD_DSPPLL (2 << 24) - -#define CLK_CODEC_REG CLKSEL1_REG -#define CLK_CODEC_SRC_MASK (1 << 2) -#define CLK_CODEC_CPLLCLK (0 << 2) -#define CLK_CODEC_12M (1 << 2) - -#define CLK_CPLL_MASK 0x03u -#define CLK_CPLL_SLOW 0x00u -#define CLK_CPLL_NORMAL 0x01u -#define CLK_CPLL_DSLOW 0x02u - -/* Clock flags */ -/* bit 0 is free */ -#define RATE_FIXED (1 << 1) /* Fixed clock rate */ -#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ -#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ - -#define regfile_readl(offset) readl(RK2818_REGFILE_BASE + offset) - -#define scu_readl(offset) readl(RK2818_SCU_BASE + offset) -#define scu_writel(v, offset) writel(v, RK2818_SCU_BASE + offset) -#define scu_writel_force(v, offset) do { u32 _v = v; u32 _count = 5; do { scu_writel(_v, offset); } while (scu_readl(offset) != _v && _count--); } while (0) /* huangtao: when write SCU_xPLL_CON, first time may failed, so try again. unknown why. */ - -#define CLK_GATE_INVALID -1 - -#define SCU_CLK_MHZ (1000*1000) - -#define ARM_PLL_DELAY 800 // loop.ARM run at 24M, -// 20100719,HSL@RK , from (200*200) to 300*200 for change ddr failed. -#define OTHER_PLL_DELAY (300*200) // loop .ARM run at normal. - -#define MAYCHG_VDD 0 - -struct rockchip_pll_set { - u32 clk_hz; - u32 pll_con; - - u8 clk48m_div : 4; - u8 ahb_div : 2; - u8 apb_div : 2; - - u32 flags; -}; - -struct clk { - struct list_head node; - const char *name; - struct clk *parent; - struct list_head children; - struct list_head sibling; /* node for children */ - unsigned long rate; - u32 flags; - int (*mode)(struct clk *clk, int on); - unsigned long (*recalc)(struct clk *); - int (*set_rate)(struct clk *, unsigned long); - long (*round_rate)(struct clk *, unsigned long); - struct clk* (*get_parent)(struct clk *); /* get clk's parent from the hardware */ - int (*set_parent)(struct clk *, struct clk *); - s16 usecount; - u8 gate_idx; - u8 pll_idx; - u32 __iomem *clksel_reg; - u32 clksel_mask; - u8 clksel_shift; - u8 clksel_maxdiv; -}; - -int __tcmdata ddr_disabled = 0; - -static void __clk_disable(struct clk *clk); -static void clk_reparent(struct clk *child, struct clk *parent); -static void propagate_rate(struct clk *tclk); - -/* Used for clocks that always have same value as the parent clock */ -static unsigned long followparent_recalc(struct clk *clk) -{ - return clk->parent->rate; -} - -static unsigned long clksel_recalc(struct clk *clk) -{ - u32 div = ((readl(clk->clksel_reg) & clk->clksel_mask) >> clk->clksel_shift) + 1; - unsigned long rate = clk->parent->rate / div; - pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div); - return rate; -} - -static unsigned long clksel_recalc_shift(struct clk *clk) -{ - u32 shift = (readl(clk->clksel_reg) & clk->clksel_mask) >> clk->clksel_shift; - unsigned long rate = clk->parent->rate >> shift; - pr_debug("%s new clock rate is %ld (shift %d)\n", clk->name, rate, shift); - return rate; -} - -static int clksel_set_rate(struct clk *clk, unsigned long rate) -{ - u32 div; - - for (div = 1; div <= clk->clksel_maxdiv; div++) { - u32 new_rate = clk->parent->rate / div; - if (new_rate <= rate) { - u32 *reg = clk->clksel_reg; - u32 v = readl(reg); - v &= ~clk->clksel_mask; - v |= (div - 1) << clk->clksel_shift; - writel(v, reg); - clk->rate = new_rate; - pr_debug("clksel_set_rate for clock %s to rate %ld (div %d)\n", clk->name, rate, div); - return 0; - } - } - - return -ENOENT; -} - -static int clksel_set_rate_shift(struct clk *clk, unsigned long rate) -{ - u32 shift; - - for (shift = 0; (1 << shift) <= clk->clksel_maxdiv; shift++) { - u32 new_rate = clk->parent->rate >> shift; - if (new_rate <= rate) { - u32 *reg = clk->clksel_reg; - u32 v = readl(reg); - v &= ~clk->clksel_mask; - v |= shift << clk->clksel_shift; - writel(v, reg); - clk->rate = new_rate; - pr_debug("clksel_set_rate for clock %s to rate %ld (shift %d)\n", clk->name, rate, shift); - return 0; - } - } - - return -ENOENT; -} - -static struct clk xin24m = { - .name = "xin24m", - .rate = 24000000, - .flags = RATE_FIXED, - .gate_idx = CLK_GATE_INVALID, -}; - -static struct clk clk12m = { - .name = "clk12m", - .rate = 12000000, - .parent = &xin24m, - .flags = RATE_FIXED, - .gate_idx = CLK_GATE_INVALID, -}; - -static struct clk extclk = { - .name = "extclk", - .rate = 27000000, - .flags = RATE_FIXED, - .gate_idx = CLK_GATE_INVALID, -}; - -static unsigned long arm_pll_clk_recalc(struct clk *clk) -{ - unsigned long rate; - - if ((scu_readl(SCU_MODE_CON) & SCU_CPUMODE_MASK) == SCU_CPUMODE_NORMAL) { - u32 v = scu_readl(SCU_APLL_CON); - u32 OD = ((v >> 1) & 0x7) + 1; - u32 NF = ((v >> 4) & 0xfff) + 1; - u32 NR = ((v >> 16) & 0x3f) + 1; - rate = clk->parent->rate / NR * NF / OD; - pr_debug("%s new clock rate is %ld NR %d NF %d OD %d\n", clk->name, rate, NR, NF, OD); - } else { - rate = clk->parent->rate; - pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate); - } - - return rate; -} - -static struct clk arm_pll_clk = { - .name = "arm_pll", - .parent = &xin24m, - .recalc = arm_pll_clk_recalc, - .gate_idx = CLK_GATE_INVALID, -}; - -#define ASM_LOOP_INSTRUCTION_NUM 8 - -void __tcmfunc tcm_udelay(unsigned long usecs, unsigned long arm_freq_mhz) -{ - unsigned int cycle; - - cycle = usecs * arm_freq_mhz / ASM_LOOP_INSTRUCTION_NUM; - - while (cycle--) { - nop(); - nop(); - nop(); - barrier(); - } -} - -#define ARM_PLL_IDX 0 -#define DSP_PLL_IDX 1 -#define CODEC_PLL_IDX 2 - - -static void scu_hw_pll_wait_lock(int pll_idx, int delay) -{ - u32 bit = 0x80u << pll_idx; - while (delay > 0) { - if (regfile_readl(CPU_APB_REG0) & bit) - break; - delay--; - } - if (delay == 0 && !ddr_disabled) { - pr_warning("wait pll bit 0x%x time out!\n", bit); - } -} - -static void arm_pll_clk_slow_mode(int enter) -{ - scu_writel((scu_readl(SCU_MODE_CON) & ~SCU_CPUMODE_MASK) | (enter ? SCU_CPUMODE_SLOW : SCU_CPUMODE_NORMAL), SCU_MODE_CON); -} - -#define CLK_HCLK_PCLK_11 0 -#define CLK_HCLK_PCLK_21 1 -#define CLK_HCLK_PCLK_41 2 - -#define CLK_ARM_HCLK_11 0 -#define CLK_ARM_HCLK_21 1 -#define CLK_ARM_HCLK_31 2 -#define CLK_ARM_HCLK_41 3 - -static void scu_hw_set_ahb_apb_div(int ahb_div, int apb_div) -{ - u32 reg_val; - reg_val = scu_readl(SCU_CLKSEL0_CON) & ~0xF; - reg_val |= ((apb_div & 0x3) << 2) | ahb_div; -// pr_debug("set ahb = %s, apb = %s, clksel0 0x%x\n", ahb_div == 0 ? "1:1" : ahb_div == 1 ? "2:1" : ahb_div == 2 ? "3:1" : "4:1", apb_div == 0 ? "1:1" : apb_div == 1 ? "2:1" : apb_div == 2 ? "4:1" : "bad", reg_val); - scu_writel(reg_val, SCU_CLKSEL0_CON); - tcm_udelay(1, 24); /* huangtao: unknown why, but if no delay, system will unstable. */ -} - -static void scu_hw_set_clk48m_div(int clk48m_div) -{ - u32 reg_val = scu_readl(SCU_CLKSEL2_CON) & ~(0xF << 4); - reg_val |= ((clk48m_div & 0xF) << 4); - scu_writel(reg_val, SCU_CLKSEL2_CON); -} - -static int rockchip_scu_set_arm_pllclk_hw(const struct rockchip_pll_set *ps) -{ - const int delay = ARM_PLL_DELAY; - - if (ps->clk_hz == 24 * SCU_CLK_MHZ) { - arm_pll_clk_slow_mode(1); - /* 20100615,HSL@RK,when power down,set pll out=300 M. */ - scu_writel_force(ps->pll_con, SCU_APLL_CON); - pr_debug("set 24M clk, arm power down\n"); - __udelay(delay); - scu_writel_force(scu_readl(SCU_APLL_CON) | PLL_PD, SCU_APLL_CON); - scu_hw_set_ahb_apb_div(ps->ahb_div, ps->apb_div); - } else { - u32 reg_val; - unsigned long flags; - - local_irq_save(flags); - /*20100726,HSL@RK,close irq for change ahb = ahb =1. */ - arm_pll_clk_slow_mode(1); - /* if change arm pll,we change vdd core and ahb,apb div. */ - scu_hw_set_ahb_apb_div(CLK_ARM_HCLK_11, CLK_HCLK_PCLK_11); - local_irq_restore(flags); - - local_irq_save(flags); - reg_val = scu_readl(SCU_APLL_CON); - if (reg_val & PLL_PD) { - scu_writel_force(reg_val & ~PLL_PD, SCU_APLL_CON); - pr_debug("arm pll power on, set to %d, delay = %d\n", ps->clk_hz, delay); - scu_hw_pll_wait_lock(ARM_PLL_IDX, delay * 2); - } - local_irq_restore(flags); - - /* XXX:delay for pll state , for 0.3ms , clkf will lock clkf */ - /* 可能屏幕会倒动,如果不修改 clkr和clkf则不用进入slow mode . */ - local_irq_save(flags); - scu_writel_force(ps->pll_con, SCU_APLL_CON); - scu_hw_pll_wait_lock(ARM_PLL_IDX, delay); - - scu_hw_set_ahb_apb_div(ps->ahb_div, ps->apb_div); - scu_hw_set_clk48m_div(ps->clk48m_div); - - arm_pll_clk_slow_mode(0); - local_irq_restore(flags); - } - - return 0; -} - -#define ARM_PLL(_clk_hz, nr, nf, od, _clk48m_div, _ahb_div, _apb_div, _flags) \ -{ \ - .clk_hz = _clk_hz, \ - .pll_con = PLL_SAT | PLL_FAST | PLL_CLKR(nr-1) | PLL_CLKF(nf-1) | PLL_CLKOD(od-1), \ - .clk48m_div = _clk48m_div - 1, \ - .ahb_div = CLK_ARM_HCLK_##_ahb_div, \ - .apb_div = CLK_HCLK_PCLK_##_apb_div, \ - .flags = _flags, \ -} - -static const struct rockchip_pll_set arm_pll[] = { -// clk_hz = 24*clkf/(clkr*clkod) clkr clkf clkod hdiv pdiv flags (pdiv=1,2,4,no 3!!) - ARM_PLL(576 * SCU_CLK_MHZ, 4, 96, 1, 12, 31, 41, 1), - ARM_PLL(384 * SCU_CLK_MHZ, 3, 96, 2, 8, 21, 41, 1), - ARM_PLL(192 * SCU_CLK_MHZ, 4, 96, 3, 4, 11, 41, 1), - // last item, pll power down. set real clk == SCU_ARM_MID_CLK - ARM_PLL( 24 * SCU_CLK_MHZ, 4, 48, 1, 6, 31, 21, 0), // POWER down -}; - -static int arm_clk_set_rate(struct clk *clk, unsigned long rate) -{ - const struct rockchip_pll_set *ps, *pt; - - /* found the rockchip_pll_set we want. */ - ps = pt = &arm_pll[0]; - while (1) { - if (pt->clk_hz == rate) { - ps = pt; - break; - } - // special clk ,exact match. - if (pt->flags & 1) { - pt++; - continue; - } - // we are sorted,and ps->clk_hz > pt->clk_hz. - if ((pt->clk_hz > rate || (rate - pt->clk_hz < ps->clk_hz - rate))) - ps = pt; - if (pt->clk_hz < rate || pt->clk_hz == 24 * SCU_CLK_MHZ) - break; - pt++; - } - - if (ps->clk_hz == clk->rate) - return 0; - - pr_debug("set arm to %d Hz, cur clk = %ld Hz\n", ps->clk_hz, clk->rate); - - if (ps->clk_hz > clk->rate) { - // increase freq. - int i; - for (i = ARRAY_SIZE(arm_pll) - 2; i >= 0; i--) { - if (ps->clk_hz > arm_pll[i].clk_hz && arm_pll[i].clk_hz > clk->rate) { - rockchip_scu_set_arm_pllclk_hw(&arm_pll[i]); - } - } - } else { - // decrease freq. - int i; - for (i = 1; i < ARRAY_SIZE(arm_pll); i++) { - if (ps->clk_hz < arm_pll[i].clk_hz && arm_pll[i].clk_hz < clk->rate) { - rockchip_scu_set_arm_pllclk_hw(&arm_pll[i]); - } - } - } - - rockchip_scu_set_arm_pllclk_hw(ps); - - /* adjust arm_pll_clk and arm_pll_clk other children's rate */ - arm_pll_clk.rate = arm_pll_clk.recalc(&arm_pll_clk); - { - struct clk *clkp; - - list_for_each_entry(clkp, &arm_pll_clk.children, sibling) { - if (clkp == clk) - continue; - if (clkp->recalc) - clkp->rate = clkp->recalc(clkp); - propagate_rate(clkp); - } - } - - return 0; -} - -static struct clk arm_clk = { - .name = "arm", - .parent = &arm_pll_clk, - .recalc = clksel_recalc, - .set_rate = arm_clk_set_rate, - .gate_idx = CLK_GATE_INVALID, - .clksel_reg = CLKSEL2_REG, - .clksel_mask = 0xF, - .clksel_maxdiv = 16, -}; - -static struct clk arm_hclk = { - .name = "arm_hclk", - .parent = &arm_clk, - .recalc = clksel_recalc, - .gate_idx = CLK_GATE_INVALID, - .clksel_reg = CLKSEL0_REG, - .clksel_mask = 0x3, - .clksel_maxdiv = 4, -}; - -static struct clk clk48m = { - .name = "clk48m", - .parent = &arm_clk, - .flags = RATE_FIXED, - .recalc = clksel_recalc, - .gate_idx = CLK_GATE_INVALID, - .clksel_reg = CLKSEL2_REG, - .clksel_mask = 0xF << 4, - .clksel_shift = 4, -}; - -static struct clk arm_pclk = { - .name = "arm_pclk", - .parent = &arm_hclk, - .flags = ENABLE_ON_INIT, - .recalc = clksel_recalc_shift, - .set_rate = clksel_set_rate_shift, - .gate_idx = CLK_GATE_INVALID, - .clksel_reg = CLKSEL0_REG, - .clksel_mask = 0x3 << 2, - .clksel_shift = 2, - .clksel_maxdiv = 4, -}; - -static unsigned long dsp_pll_clk_recalc(struct clk *clk) -{ - unsigned long rate; - - if ((scu_readl(SCU_MODE_CON) & SCU_DSPMODE_MASK) == SCU_DSPMODE_NORMAL) { - u32 v = scu_readl(SCU_DPLL_CON); - u32 OD = ((v >> 1) & 0x7) + 1; - u32 NF = ((v >> 4) & 0xfff) + 1; - u32 NR = ((v >> 16) & 0x3f) + 1; - rate = clk->parent->rate / NR * NF / OD; - pr_debug("%s new clock rate is %ld NR %d NF %d OD %d\n", clk->name, rate, NR, NF, OD); - } else { - rate = clk->parent->rate; - pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate); - } - - return rate; -} - -static void dsp_pll_clk_slow_mode(int enter) -{ - scu_writel((scu_readl(SCU_MODE_CON) & ~SCU_DSPMODE_MASK) | (enter ? SCU_DSPMODE_SLOW : SCU_DSPMODE_NORMAL), SCU_MODE_CON); -} - -static int rockchip_scu_set_dsp_pllclk_hw(const struct rockchip_pll_set *ps) -{ - const int delay = OTHER_PLL_DELAY; - - if (ps->clk_hz == 24 * SCU_CLK_MHZ) { - dsp_pll_clk_slow_mode(1); - /* 20100615,HSL@RK,when power down,set pll out=300 M. */ - scu_writel_force(ps->pll_con, SCU_DPLL_CON); - pr_debug("set 24M clk, dsp power down\n"); - tcm_udelay(1, 600); - scu_writel_force(scu_readl(SCU_DPLL_CON) | PLL_PD, SCU_DPLL_CON); - } else { - u32 reg_val; - - dsp_pll_clk_slow_mode(1); - - reg_val = scu_readl(SCU_DPLL_CON); - if (reg_val & PLL_PD) { - scu_writel_force(reg_val & ~PLL_PD, SCU_DPLL_CON); - pr_debug("dsp pll power on, set to %d, delay = %d\n", ps->clk_hz, delay); - scu_hw_pll_wait_lock(DSP_PLL_IDX, delay * 2); - } - - /* XXX:delay for pll state , for 0.3ms , clkf will lock clkf */ - /* 可能屏幕会倒动,如果不修改 clkr和clkf则不用进入slow mode . */ - scu_writel_force(ps->pll_con, SCU_DPLL_CON); - scu_hw_pll_wait_lock(DSP_PLL_IDX, delay); - - dsp_pll_clk_slow_mode(0); - } - - return 0; -} - -static int rockchip_scu_set_codec_pllclk_hw(const struct rockchip_pll_set *ps) -{ - const int delay = OTHER_PLL_DELAY; - - if (ps->clk_hz == 24 * SCU_CLK_MHZ) { -// dsp_pll_clk_slow_mode(1); - /* 20100615,HSL@RK,when power down,set pll out=300 M. */ - scu_writel_force(ps->pll_con, SCU_CPLL_CON); - pr_debug("codec power down\n"); - tcm_udelay(1, 600); - scu_writel_force(scu_readl(SCU_CPLL_CON) | PLL_PD, SCU_CPLL_CON); - } else { - u32 reg_val; - -// dsp_pll_clk_slow_mode(1); - - reg_val = scu_readl(SCU_CPLL_CON); - if (reg_val & PLL_PD) { - scu_writel_force(reg_val & ~PLL_PD, SCU_CPLL_CON); - pr_debug("codec pll power on, set to %d, delay = %d\n", ps->clk_hz, delay); - scu_hw_pll_wait_lock(CODEC_PLL_IDX, delay * 2); - } - - /* XXX:delay for pll state , for 0.3ms , clkf will lock clkf */ - /* 鍙兘灞忓箷浼氬€掑姩,濡傛灉涓嶄慨鏀?clkr鍜宑lkf鍒欎笉鐢ㄨ繘鍏low mode . */ - scu_writel_force(ps->pll_con, SCU_CPLL_CON); - scu_hw_pll_wait_lock(CODEC_PLL_IDX, delay); - -// dsp_pll_clk_slow_mode(0); - } - - return 0; -} - -#define CODEC_PLL(_clk_hz, nr, nf, od) \ -{ \ - .clk_hz = _clk_hz, \ - .pll_con = PLL_SAT | PLL_FAST | PLL_CLKR(nr-1) | PLL_CLKF(nf-1) | PLL_CLKOD(od-1), \ -} - -static const struct rockchip_pll_set codec_pll[] = { -// clk_hz = 24*clkf/(clkr*clkod) clkr clkf clkod - CODEC_PLL(600 * SCU_CLK_MHZ, 6, 150, 1), - CODEC_PLL(560 * SCU_CLK_MHZ, 6, 140, 1), -// CODEC_PLL(500 * SCU_CLK_MHZ, 6, 125, 1), -// CODEC_PLL(450 * SCU_CLK_MHZ, 4, 75, 1), -// CODEC_PLL(400 * SCU_CLK_MHZ, 6, 100, 1), -#if MAYCHG_VDD - CODEC_PLL(364 * SCU_CLK_MHZ, 6, 91, 1), // VDD_110 for ddr 364M will crash. -#endif - // pll power down. - CODEC_PLL( 136 * SCU_CLK_MHZ, 6, 34*2,2), - CODEC_PLL( 24 * SCU_CLK_MHZ, 4, 50, 1), // POWER down,by the real clk = 300M -}; - -#define DSP_PLL(_clk_hz, nr, nf, od) \ -{ \ - .clk_hz = _clk_hz, \ - .pll_con = PLL_SAT | PLL_FAST | PLL_CLKR(nr-1) | PLL_CLKF(nf-1) | PLL_CLKOD(od-1), \ -} - -static const struct rockchip_pll_set dsp_pll[] = { -// clk_hz = 24*clkf/(clkr*clkod) clkr clkf clkod - DSP_PLL(600 * SCU_CLK_MHZ, 6, 150, 1), - DSP_PLL(560 * SCU_CLK_MHZ, 6, 140, 1), - DSP_PLL(500 * SCU_CLK_MHZ, 6, 125, 1), - DSP_PLL(450 * SCU_CLK_MHZ, 4, 75, 1), - DSP_PLL(400 * SCU_CLK_MHZ, 6, 100, 1), -#if MAYCHG_VDD - DSP_PLL(364 * SCU_CLK_MHZ, 6, 91, 1), // VDD_110 for ddr 364M will crash. -#endif - // pll power down. - DSP_PLL( 24 * SCU_CLK_MHZ, 4, 50, 1), // POWER down,by the real clk = 300M -}; - -static int dsp_pll_clk_set_rate(struct clk *clk, unsigned long rate) -{ - const struct rockchip_pll_set *ps, *pt; - static const struct rockchip_pll_set mid_pll = DSP_PLL(300 * SCU_CLK_MHZ, 4, 50, 1); - - /* found the rockchip_pll_set we want. */ - ps = pt = &dsp_pll[0]; - while (1) { - if (pt->clk_hz == rate) { - ps = pt; - break; - } - // we are sorted,and ps->clk_hz > pt->clk_hz. - if (pt->clk_hz > rate || (rate - pt->clk_hz < ps->clk_hz - rate)) - ps = pt; - if (pt->clk_hz < rate || pt->clk_hz == 24 * SCU_CLK_MHZ) - break; - pt++; - } - - if (ps->clk_hz == clk->rate) - return 0; - - pr_debug("set dsp to %d Hz, cur clk = %ld Hz\n", ps->clk_hz, clk->rate); - - if ((rate > mid_pll.clk_hz && mid_pll.clk_hz > clk->rate) || - (rate < mid_pll.clk_hz && mid_pll.clk_hz < clk->rate)) - rockchip_scu_set_dsp_pllclk_hw(&mid_pll); - rockchip_scu_set_dsp_pllclk_hw(ps); - - return 0; -} - -static struct clk dsp_pll_clk = { - .name = "dsp_pll", - .parent = &xin24m, - .recalc = dsp_pll_clk_recalc, - .set_rate = dsp_pll_clk_set_rate, - .gate_idx = CLK_GATE_INVALID, -}; - -static unsigned long codec_pll_clk_recalc(struct clk *clk) -{ - unsigned long rate; - - if ((scu_readl(SCU_CLKSEL1_CON) & CLK_CPLL_MASK) == CLK_CPLL_NORMAL) { - u32 v = scu_readl(SCU_CPLL_CON); - u32 OD = ((v >> 1) & 0x7) + 1; - u32 NF = ((v >> 4) & 0xfff) + 1; - u32 NR = ((v >> 16) & 0x3f) + 1; - rate = clk->parent->rate / NR * NF / OD; - pr_debug("%s new clock rate is %ld NR %d NF %d OD %d\n", clk->name, rate, NR, NF, OD); - } else { - rate = clk->parent->rate; - pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate); - } - - return rate; -} - -#if 0 -static void codec_pll_clk_slow_mode(int enter) -{ - scu_writel((scu_readl(SCU_CLKSEL1_CON) & ~CLK_CPLL_MASK) | (enter ? CLK_CPLL_SLOW : CLK_CPLL_NORMAL), SCU_CLKSEL1_CON); -} -#endif - -static struct clk codec_pll_clk = { - .name = "codec_pll", - .parent = &xin24m, - .recalc = codec_pll_clk_recalc, - .gate_idx = CLK_GATE_INVALID, -}; - -static struct clk* demod_divider_clk_get_parent(struct clk *clk) -{ - u32 r = readl(CLK_DEMOD_REG) & CLK_DEMOD_DIV_SRC_MASK; - return (r == CLK_DEMOD_CODPLL) ? &codec_pll_clk : (r == CLK_DEMOD_ARMPLL) ? &arm_pll_clk : (r == CLK_DEMOD_DSPPLL) ? &dsp_pll_clk : clk->parent; -} - -static int demod_divider_clk_set_parent(struct clk *clk, struct clk *parent) -{ - u32 r = readl(CLK_DEMOD_REG) & ~CLK_DEMOD_DIV_SRC_MASK; - - if (parent == &codec_pll_clk) { - r |= CLK_DEMOD_CODPLL; - } else if (parent == &arm_pll_clk) { - r |= CLK_DEMOD_ARMPLL; - } else if (parent == &dsp_pll_clk) { - r |= CLK_DEMOD_DSPPLL; - } else { - return -EINVAL; - } - writel(r, CLK_DEMOD_REG); - - return 0; -} - -static struct clk demod_divider_clk = { - .name = "demod_divider", - .parent = &codec_pll_clk, - .recalc = clksel_recalc, - .set_rate = clksel_set_rate, - .get_parent = demod_divider_clk_get_parent, - .set_parent = demod_divider_clk_set_parent, - .gate_idx = CLK_GATE_INVALID, - .clksel_reg = CLKSEL1_REG, - .clksel_mask = 0xFF << 16, - .clksel_shift = 16, - .clksel_maxdiv = 128, -}; - -static struct clk* demod_clk_get_parent(struct clk *clk) -{ - u32 r = readl(CLK_DEMOD_REG) & CLK_DEMOD_SRC_MASK; - return (r == CLK_DEMOD_DIVOUT) ? &demod_divider_clk : &extclk; -} - -static int demod_clk_set_parent(struct clk *clk, struct clk *parent) -{ - u32 r = readl(CLK_DEMOD_REG) & ~CLK_DEMOD_SRC_MASK; - - if (parent == &extclk) { - r |= CLK_DEMOD_27M; - } else if (parent == &demod_divider_clk) { - r |= CLK_DEMOD_DIVOUT; - } else { - return -EINVAL; - } - writel(r, CLK_DEMOD_REG); - - return 0; -} - -static struct clk demod_clk = { - .name = "demod", - .parent = &demod_divider_clk, - .recalc = followparent_recalc, - .get_parent = demod_clk_get_parent, - .set_parent = demod_clk_set_parent, - .gate_idx = CLK_GATE_INVALID, -}; - -static struct clk codec_clk = { - .name = "codec", - .parent = &codec_pll_clk, - .recalc = clksel_recalc, - .set_rate = clksel_set_rate, - .gate_idx = CLK_GATE_INVALID, - .clksel_reg = CLKSEL1_REG, - .clksel_mask = 0x1F << 3, - .clksel_shift = 3, - .clksel_maxdiv = 32, -}; - -static struct clk* lcdc_divider_clk_get_parent(struct clk *clk) -{ - u32 r = readl(CLK_LCDC_REG) & CLK_LCDC_DIV_SRC_MASK; - return (r == CLK_LCDC_ARMPLL) ? &arm_pll_clk : (r == CLK_LCDC_DSPPLL) ? &dsp_pll_clk : (r == CLK_LCDC_CODPLL) ? &codec_pll_clk : clk->parent; -} - -static int lcdc_divider_clk_set_parent(struct clk *clk, struct clk *parent) -{ - u32 r = readl(CLK_LCDC_REG) & ~CLK_LCDC_DIV_SRC_MASK; - - if (parent == &arm_pll_clk) { - r |= CLK_LCDC_ARMPLL; - } else if (parent == &dsp_pll_clk) { - r |= CLK_LCDC_DSPPLL; - } else if (parent == &codec_pll_clk) { - r |= CLK_LCDC_CODPLL; - } else { - return -EINVAL; - } - writel(r, CLK_LCDC_REG); - - return 0; -} - -static struct clk lcdc_divider_clk = { - .name = "lcdc_divider", - .parent = &arm_pll_clk, - .recalc = clksel_recalc, - .set_rate = clksel_set_rate, - .get_parent = lcdc_divider_clk_get_parent, - .set_parent = lcdc_divider_clk_set_parent, - .gate_idx = CLK_GATE_INVALID, - .clksel_reg = CLKSEL0_REG, - .clksel_mask = 0xFF << 8, - .clksel_shift = 8, - .clksel_maxdiv = 128, -}; - -static struct clk* otgphy_clk_get_parent(struct clk *clk) -{ - u32 r = readl(CLK_USBPHY_REG) & CLK_USBPHY_SRC_MASK; - return (r == CLK_USBPHY_24M) ? &xin24m : (r == CLK_USBPHY_12M) ? &clk12m : (r == CLK_USBPHY_48M) ? &clk48m : clk->parent; -} - -static int otgphy_clk_set_parent(struct clk *clk, struct clk *parent) -{ - u32 r = readl(CLK_USBPHY_REG) & ~CLK_USBPHY_SRC_MASK; - - if (parent == &xin24m) { - r |= CLK_USBPHY_24M; - } else if (parent == &clk12m) { - r |= CLK_USBPHY_12M; - } else if (parent == &clk48m) { - r |= CLK_USBPHY_48M; - } else { - return -EINVAL; - } - writel(r, CLK_USBPHY_REG); - - return 0; -} - -static struct clk* lcdc_clk_get_parent(struct clk *clk) -{ - u32 r = readl(CLK_LCDC_REG) & CLK_LCDC_SRC_MASK; - return (r == CLK_LCDC_DIVOUT) ? &lcdc_divider_clk : &extclk; -} - -static int lcdc_clk_set_parent(struct clk *clk, struct clk *parent) -{ - u32 r = readl(CLK_LCDC_REG) & ~CLK_LCDC_SRC_MASK; - - if (parent == &lcdc_divider_clk) { - r |= CLK_LCDC_DIVOUT; - } else if (parent == &extclk) { - r |= CLK_LCDC_27M; - } else { - return -EINVAL; - } - writel(r, CLK_LCDC_REG); - - return 0; -} - -static struct clk* vip_clk_get_parent(struct clk *clk) -{ - u32 r = readl(CLK_SENSOR_REG) & CLK_SENSOR_SRC_MASK; - return (r == CLK_SENSOR_24M) ? &xin24m : (r == CLK_SENSOR_27M) ? &extclk : (r == CLK_SENSOR_48M) ? &clk48m : clk->parent; -} - -static int vip_clk_set_parent(struct clk *clk, struct clk *parent) -{ - u32 r = readl(CLK_SENSOR_REG) & ~CLK_SENSOR_SRC_MASK; - - if (parent == &xin24m) { - r |= CLK_SENSOR_24M; - } else if (parent == &extclk) { - r |= CLK_SENSOR_27M; - } else if (parent == &clk48m) { - r |= CLK_SENSOR_48M; - } else { - return -EINVAL; - } - writel(r, CLK_SENSOR_REG); - - return 0; -} - -static struct clk* ddr_clk_get_parent(struct clk *clk) -{ - u32 r = readl(CLK_DDR_REG) & CLK_DDR_SRC_MASK; - return (r == CLK_DDR_CODPLL) ? &codec_pll_clk : (r == CLK_DDR_ARMPLL) ? &arm_pll_clk : (r == CLK_DDR_DSPPLL) ? &dsp_pll_clk : clk->parent; -} - -static int ddr_clk_set_parent(struct clk *clk, struct clk *parent) -{ - u32 r = readl(CLK_DDR_REG) & ~CLK_DDR_SRC_MASK; - - if (parent == &codec_pll_clk) { - r |= CLK_DDR_CODPLL; - } else if (parent == &arm_pll_clk) { - r |= CLK_DDR_ARMPLL; - } else if (parent == &dsp_pll_clk) { - r |= CLK_DDR_DSPPLL; - } else { - return -EINVAL; - } - writel(r, CLK_DDR_REG); - - return 0; -} - -static struct clk* i2s_clk_get_parent(struct clk *clk) -{ - u32 r = readl(CLK_CODEC_REG) & CLK_CODEC_SRC_MASK; - return (r == CLK_CODEC_CPLLCLK) ? &codec_clk : &clk12m; -} - -static int i2s_clk_set_parent(struct clk *clk, struct clk *parent) -{ - u32 r = readl(CLK_CODEC_REG) & ~CLK_CODEC_SRC_MASK; - - if (parent == &codec_clk) { - r |= CLK_CODEC_CPLLCLK; - } else if (parent == &clk12m) { - r |= CLK_CODEC_12M; - } else { - return -EINVAL; - } - writel(r, CLK_CODEC_REG); - - return 0; -} - -static int gate_mode(struct clk *clk, int on) -{ - u32 reg; - int idx = clk->gate_idx; - u32 v; - - if (idx >= CLK_GATE_MAX) - return -EINVAL; - - reg = SCU_CLKGATE0_CON; - reg += (idx >> 5) << 2; - idx &= 0x1F; - - v = scu_readl(reg); - if (on) { - v &= ~(1 << idx); // clear bit - } else { - v |= (1 << idx); // set bit - } - scu_writel(v, reg); - - return 0; -} - -static struct clk* uart_clk_get_parent(struct clk *clk) -{ - u32 r = readl(CLK_UART_REG) & CLK_UART_SRC_MASK; - return (r == CLK_UART_24M) ? &xin24m : &clk48m; -} - -static int uart_clk_set_parent(struct clk *clk, struct clk *parent) -{ - u32 r = readl(CLK_UART_REG) & ~CLK_UART_SRC_MASK; - - if (parent == &xin24m) { - r |= CLK_UART_24M; - } else if (parent == &clk48m) { - r |= CLK_UART_48M; - } else { - return -EINVAL; - } - writel(r, CLK_UART_REG); - - return 0; -} - -#define UART_CLK(n) \ -static struct clk uart##n##_clk = { \ - .name = "uart"#n, \ - .parent = &xin24m, \ - .mode = gate_mode, \ - .recalc = followparent_recalc, \ - .get_parent = uart_clk_get_parent, \ - .set_parent = uart_clk_set_parent, \ - .gate_idx = CLK_GATE_UART##n, \ -} - -#define GATE_CLK(NAME,PARENT,ID) \ -static struct clk NAME##_clk = { \ - .name = #NAME, \ - .parent = &PARENT, \ - .mode = gate_mode, \ - .recalc = followparent_recalc, \ - .gate_idx = CLK_GATE_##ID, \ -} - -GATE_CLK(arm_core, arm_clk, ARM); -GATE_CLK(dma, arm_hclk, DMA); -GATE_CLK(sramarm, arm_hclk, SRAMARM); -GATE_CLK(sramdsp, arm_hclk, SRAMDSP); -GATE_CLK(hif, arm_hclk, HIF); -GATE_CLK(otgbus, arm_hclk, OTGBUS); -static struct clk otgphy_clk = { - .name = "otgphy", - .parent = &xin24m, - .mode = gate_mode, - .recalc = followparent_recalc, - .get_parent = otgphy_clk_get_parent, - .set_parent = otgphy_clk_set_parent, - .gate_idx = CLK_GATE_OTGPHY, -}; -GATE_CLK(nandc, arm_hclk, NANDC); -GATE_CLK(intc, arm_hclk, INTC); -GATE_CLK(deblocking_rv, arm_hclk, DEBLK); -static struct clk lcdc_clk = { - .name = "lcdc", - .parent = &lcdc_divider_clk, - .mode = gate_mode, - .recalc = followparent_recalc, - .get_parent = lcdc_clk_get_parent, - .set_parent = lcdc_clk_set_parent, - .gate_idx = CLK_GATE_LCDC, -}; -static struct clk vip_clk = { - .name = "vip", - .parent = &xin24m, - .mode = gate_mode, - .recalc = followparent_recalc, - .get_parent = vip_clk_get_parent, - .set_parent = vip_clk_set_parent, - .gate_idx = CLK_GATE_VIP, -}; -static struct clk i2s_clk = { - .name = "i2s", - .parent = &clk12m, - .mode = gate_mode, - .recalc = followparent_recalc, - .get_parent = i2s_clk_get_parent, - .set_parent = i2s_clk_set_parent, - .gate_idx = CLK_GATE_I2S, -}; -static struct clk sdmmc0_clk = { - .name = "sdmmc0", - .parent = &arm_hclk, - .mode = gate_mode, - .recalc = clksel_recalc, - .set_rate = clksel_set_rate, - .gate_idx = CLK_GATE_SDMMC0, - .clksel_reg = CLKSEL0_REG, - .clksel_mask = 7 << 4, - .clksel_shift = 4, - .clksel_maxdiv = 8, -}; - -GATE_CLK(ebrom, arm_hclk, EBROM); -GATE_CLK(gpio0, arm_pclk, GPIO0); -GATE_CLK(gpio1, arm_pclk, GPIO1); -UART_CLK(0); -UART_CLK(1); -GATE_CLK(i2c0, arm_pclk, I2C0); -GATE_CLK(i2c1, arm_pclk, I2C1); -GATE_CLK(spi0, arm_pclk, SPI0); -GATE_CLK(spi1, arm_pclk, SPI1); -GATE_CLK(pwm, arm_pclk, PWM); -GATE_CLK(timer, arm_pclk, TIMER); -GATE_CLK(wdt, arm_pclk, WDT); -GATE_CLK(rtc, arm_pclk, RTC); -static struct clk lsadc_clk = { - .name = "lsadc", - .parent = &arm_pclk, - .mode = gate_mode, - .recalc = clksel_recalc, - .set_rate = clksel_set_rate, - .gate_idx = CLK_GATE_LSADC, - .clksel_reg = CLKSEL1_REG, - .clksel_mask = 0xFF << 8, - .clksel_shift = 8, - .clksel_maxdiv = 128, -}; -UART_CLK(2); -UART_CLK(3); -static struct clk sdmmc1_clk = { - .name = "sdmmc1", - .parent = &arm_hclk, - .mode = gate_mode, - .recalc = clksel_recalc, - .set_rate = clksel_set_rate, - .gate_idx = CLK_GATE_SDMMC1, - .clksel_reg = CLKSEL2_REG, - .clksel_mask = 7 << 8, - .clksel_shift = 8, - .clksel_maxdiv = 8, -}; - -static unsigned long hsadc_clk_recalc(struct clk *clk) -{ - return clk->parent->rate >> 1; -} - -static struct clk hsadc_clk = { - .name = "hsadc", - .parent = &demod_clk, - .mode = gate_mode, - .recalc = hsadc_clk_recalc, - .gate_idx = CLK_GATE_HSADC, -}; -GATE_CLK(sdram_common, arm_hclk, SDRAM_COMMON); -GATE_CLK(sdram_controller, arm_hclk, SDRAM_CONTROLLER); -GATE_CLK(mobile_sdram_controller, arm_hclk, MOBILE_SDRAM_CONTROLLER); -GATE_CLK(lcdc_share_memory, arm_hclk, LCDC_SHARE_MEMORY); -GATE_CLK(lcdc_hclk, arm_hclk, LCDC_HCLK); -GATE_CLK(deblocking_h264, arm_hclk, DEBLK_H264); -GATE_CLK(gpu, arm_hclk, GPU); -GATE_CLK(ddr_hclk, arm_hclk, DDR_HCLK); -static struct clk ddr_clk = { - .name = "ddr", - .parent = &codec_pll_clk, - .mode = gate_mode, - .recalc = clksel_recalc_shift, - .set_rate = clksel_set_rate_shift, - .get_parent = ddr_clk_get_parent, - .set_parent = ddr_clk_set_parent, - .gate_idx = CLK_GATE_DDR, - .clksel_reg = CLKSEL0_REG, - .clksel_mask = 0x3 << 30, - .clksel_shift = 30, - .clksel_maxdiv = 8, -}; -GATE_CLK(customized_sdram_controller, arm_hclk, CUSTOMIZED_SDRAM_CONTROLLER); -GATE_CLK(mcdma, arm_hclk, MCDMA); -GATE_CLK(sdram, arm_hclk, SDRAM); -GATE_CLK(ddr_axi, arm_hclk, DDR_AXI); -GATE_CLK(dsp_timer, arm_hclk, DSP_TIMER); -GATE_CLK(dsp_slave, arm_hclk, DSP_SLAVE); -GATE_CLK(dsp_master, arm_hclk, DSP_MASTER); -GATE_CLK(usb_host, clk48m, USB_HOST); - -GATE_CLK(armibus, arm_hclk, ARMIBUS); -GATE_CLK(armdbus, arm_hclk, ARMDBUS); -GATE_CLK(dspbus, arm_hclk, DSPBUS); -GATE_CLK(expbus, arm_hclk, EXPBUS); -GATE_CLK(apbbus, arm_hclk, APBBUS); -GATE_CLK(efuse, arm_pclk, EFUSE); -GATE_CLK(dtcm1, arm_clk, DTCM1); -GATE_CLK(dtcm0, arm_clk, DTCM0); -GATE_CLK(itcm, arm_clk, ITCM); -GATE_CLK(videobus, arm_hclk, VIDEOBUS); - -#define CLK(dev, con, ck) \ - { \ - .dev_id = dev, \ - .con_id = con, \ - .clk = ck, \ - } - -#define CLK1(name) \ - { \ - .dev_id = NULL, \ - .con_id = #name, \ - .clk = &name##_clk, \ - } - -static struct clk_lookup clks[] = { - CLK(NULL, "xin24m", &xin24m), - CLK(NULL, "extclk", &extclk), - - CLK(NULL, "clk12m", &clk12m), - CLK1(arm_pll), - CLK1(dsp_pll), - CLK1(codec_pll), - CLK1(arm), - CLK(NULL, "arm_hclk", &arm_hclk), - CLK(NULL, "clk48m", &clk48m), - CLK(NULL, "arm_pclk", &arm_pclk), - CLK1(demod_divider), - CLK1(demod), - CLK1(codec), - CLK1(lcdc_divider), - - CLK1(arm_core), - CLK1(dma), - CLK1(sramarm), - CLK1(sramdsp), - CLK1(hif), - CLK1(otgbus), - CLK1(otgphy), - CLK1(nandc), - CLK1(intc), - CLK1(deblocking_rv), - CLK1(lcdc), - CLK1(vip), - CLK("rk2818_i2s","i2s",&i2s_clk), - CLK("rk2818_sdmmc.0", "sdmmc", &sdmmc0_clk), - CLK1(ebrom), - CLK1(gpio0), - CLK1(gpio1), - CLK("rk2818_serial.0", "uart", &uart0_clk), - CLK("rk2818_serial.1", "uart", &uart1_clk), - CLK("rk2818_i2c.0", "i2c", &i2c0_clk), - CLK("rk2818_i2c.1", "i2c", &i2c1_clk), - CLK("rk2818_spim.0", "spi", &spi0_clk), - CLK1(spi1), - CLK1(pwm), - CLK1(timer), - CLK1(wdt), - CLK1(rtc), - CLK1(lsadc), - CLK("rk2818_serial.2", "uart", &uart2_clk), - CLK("rk2818_serial.3", "uart", &uart3_clk), - CLK("rk2818_sdmmc.1", "sdmmc", &sdmmc1_clk), - - CLK1(hsadc), - CLK1(sdram_common), - CLK1(sdram_controller), - CLK1(mobile_sdram_controller), - CLK1(lcdc_share_memory), - CLK1(lcdc_hclk), - CLK1(deblocking_h264), - CLK1(gpu), - CLK1(ddr_hclk), - CLK1(ddr), - CLK1(customized_sdram_controller), - CLK1(mcdma), - CLK1(sdram), - CLK1(ddr_axi), - CLK1(dsp_timer), - CLK1(dsp_slave), - CLK1(dsp_master), - CLK1(usb_host), - - CLK1(armibus), - CLK1(armdbus), - CLK1(dspbus), - CLK1(expbus), - CLK1(apbbus), - CLK1(efuse), - CLK1(dtcm1), - CLK1(dtcm0), - CLK1(itcm), - CLK1(videobus), -}; - -static LIST_HEAD(clocks); -static DEFINE_MUTEX(clocks_mutex); -static DEFINE_SPINLOCK(clockfw_lock); -#define LOCK() do { WARN_ON(in_irq()); if (!irqs_disabled()) spin_lock_bh(&clockfw_lock); } while (0) -#define UNLOCK() do { if (!irqs_disabled()) spin_unlock_bh(&clockfw_lock); } while (0) - -static int __clk_enable(struct clk *clk) -{ - int ret = 0; - - if (clk->usecount == 0) { - if (clk->parent) { - ret = __clk_enable(clk->parent); - if (ret) - return ret; - } - - if (clk->mode) { - ret = clk->mode(clk, 1); - if (ret) { - if (clk->parent) - __clk_disable(clk->parent); - return ret; - } - } - pr_debug("%s enabled\n", clk->name); - } - clk->usecount++; - - return ret; -} - -int clk_enable(struct clk *clk) -{ - int ret = 0; - - if (clk == NULL || IS_ERR(clk)) - return -EINVAL; - - LOCK(); - ret = __clk_enable(clk); - UNLOCK(); - - return ret; -} -EXPORT_SYMBOL(clk_enable); - -static void __clk_disable(struct clk *clk) -{ - if (--clk->usecount == 0) { - if (clk->mode) - clk->mode(clk, 0); - pr_debug("%s disabled\n", clk->name); - if (clk->parent) - __clk_disable(clk->parent); - } -} - -void clk_disable(struct clk *clk) -{ - if (clk == NULL || IS_ERR(clk)) - return; - - LOCK(); - if (clk->usecount == 0) { - printk(KERN_ERR "Trying disable clock %s with 0 usecount\n", clk->name); - WARN_ON(1); - goto out; - } - - __clk_disable(clk); - -out: - UNLOCK(); -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - if (clk == NULL || IS_ERR(clk)) - return 0; - - return clk->rate; -} -EXPORT_SYMBOL(clk_get_rate); - -/*------------------------------------------------------------------------- - * Optional clock functions defined in include/linux/clk.h - *-------------------------------------------------------------------------*/ - -/* Given a clock and a rate apply a clock specific rounding function */ -static long __clk_round_rate(struct clk *clk, unsigned long rate) -{ - if (clk->round_rate) - return clk->round_rate(clk, rate); - - if (clk->flags & RATE_FIXED) - printk(KERN_ERR "clock: clk_round_rate called on fixed-rate clock %s\n", clk->name); - - return clk->rate; -} - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - long ret = 0; - - if (clk == NULL || IS_ERR(clk)) - return ret; - - LOCK(); - ret = __clk_round_rate(clk, rate); - UNLOCK(); - - return ret; -} -EXPORT_SYMBOL(clk_round_rate); - -/* Set the clock rate for a clock source */ -static int __clk_set_rate(struct clk *clk, unsigned long rate) -{ - int ret = -EINVAL; - - pr_debug("set_rate for clock %s to rate %ld\n", clk->name, rate); - - if (clk->flags & CONFIG_PARTICIPANT) - return -EINVAL; - - if (clk->set_rate) - ret = clk->set_rate(clk, rate); - - return ret; -} - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - int ret = -EINVAL; - - if (clk == NULL || IS_ERR(clk)) - return ret; - - LOCK(); - if (rate == clk->rate) { - ret = 0; - goto out; - } - ret = __clk_set_rate(clk, rate); - if (ret == 0) { - if (clk->recalc) - clk->rate = clk->recalc(clk); - propagate_rate(clk); - } -out: - UNLOCK(); - - return ret; -} -EXPORT_SYMBOL(clk_set_rate); - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - int ret = -EINVAL; - - if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent)) - return ret; - - if (clk->set_parent == NULL) - return ret; - - LOCK(); - if (clk->usecount == 0) { - ret = clk->set_parent(clk, parent); - if (ret == 0) { - clk_reparent(clk, parent); - if (clk->recalc) - clk->rate = clk->recalc(clk); - propagate_rate(clk); - } - } else - ret = -EBUSY; - UNLOCK(); - - return ret; -} -EXPORT_SYMBOL(clk_set_parent); - -struct clk *clk_get_parent(struct clk *clk) -{ - return clk->parent; -} -EXPORT_SYMBOL(clk_get_parent); - -static void clk_reparent(struct clk *child, struct clk *parent) -{ - if (child->parent == parent) - return; - pr_debug("%s reparent to %s (was %s)\n", child->name, parent->name, ((child->parent) ? child->parent->name : "NULL")); - - list_del_init(&child->sibling); - if (parent) - list_add(&child->sibling, &parent->children); - child->parent = parent; -} - -/* Propagate rate to children */ -static void propagate_rate(struct clk *tclk) -{ - struct clk *clkp; - - list_for_each_entry(clkp, &tclk->children, sibling) { - if (clkp->recalc) - clkp->rate = clkp->recalc(clkp); - propagate_rate(clkp); - } -} - -static LIST_HEAD(root_clks); - -/** - * recalculate_root_clocks - recalculate and propagate all root clocks - * - * Recalculates all root clocks (clocks with no parent), which if the - * clock's .recalc is set correctly, should also propagate their rates. - * Called at init. - */ -static void recalculate_root_clocks(void) -{ - struct clk *clkp; - - list_for_each_entry(clkp, &root_clks, sibling) { - if (clkp->recalc) - clkp->rate = clkp->recalc(clkp); - propagate_rate(clkp); - } -} - -void clk_recalculate_root_clocks(void) -{ - LOCK(); - recalculate_root_clocks(); - UNLOCK(); -} - - - - -static int register_show (void) -{ - printk("SCU_APLL_CON : 0x%08x\n", scu_readl(SCU_APLL_CON)); - printk("SCU_DPLL_CON : 0x%08x\n", scu_readl(SCU_DPLL_CON)); - printk("SCU_CPLL_CON : 0x%08x\n", scu_readl(SCU_CPLL_CON)); - printk("SCU_MODE_CON : 0x%08x\n", scu_readl(SCU_MODE_CON)); - printk("SCU_PMU_CON : 0x%08x\n", scu_readl(SCU_PMU_CON)); - printk("SCU_CLKSEL0_CON : 0x%08x\n", scu_readl(SCU_CLKSEL0_CON)); - printk("SCU_CLKSEL1_CON : 0x%08x\n", scu_readl(SCU_CLKSEL1_CON)); - printk("SCU_CLKGATE0_CON : 0x%08x\n", scu_readl(SCU_CLKGATE0_CON)); - printk("SCU_CLKGATE1_CON : 0x%08x\n", scu_readl(SCU_CLKGATE1_CON)); - printk("SCU_CLKGATE2_CON : 0x%08x\n", scu_readl(SCU_CLKGATE2_CON)); - printk("SCU_SOFTRST_CON : 0x%08x\n", scu_readl(SCU_SOFTRST_CON)); - printk("SCU_CHIPCFG_CON : 0x%08x\n", scu_readl(SCU_CHIPCFG_CON)); - printk("SCU_CPUPD : 0x%08x\n", scu_readl(SCU_CPUPD)); - printk("SCU_CLKSEL2_CON : 0x%08x\n", scu_readl(SCU_CLKSEL2_CON)); -} - - - -static void scu_ddr_early_suspend(void) -{ - static const struct rockchip_pll_set arm_tmp_pll =ARM_PLL(192 * SCU_CLK_MHZ, 4, 96, 3, 4, 11, 41, 1); - static const struct rockchip_pll_set arm_tmp_pll2 =ARM_PLL( 24 * SCU_CLK_MHZ, 4, 48, 1, 6, 11, 21, 0); - -// register_show(); - - rockchip_scu_set_arm_pllclk_hw(&arm_tmp_pll); - - ddr_change_mode(0 ); - - scu_writel_force(scu_readl(SCU_CLKGATE0_CON)&~(0x1<<11), SCU_CLKGATE0_CON); - scu_writel_force(scu_readl(SCU_CLKGATE1_CON)&~(0x1<<19), SCU_CLKGATE1_CON); - scu_writel_force(((scu_readl(SCU_CLKSEL0_CON)&~(0xff<<8))|(0x05<<8)), SCU_CLKSEL0_CON); - - change_ddr_freq(136); - - rockchip_scu_set_arm_pllclk_hw(&arm_tmp_pll2); - -// register_show(); -} - - -void scu_set_clk_for_reboot( void) -{ - // scu_unlock_arm_force(); /* for force change freq. */ - scu_ddr_early_suspend( ); - //ddr_change_mode( 1 ); - // rockchip_clk_set_arm( 24 ) ; /* for loader , maskrom , AHB 1:1--do it at rk281x_reboot */ -} - - -/** - * clk_preinit - initialize any fields in the struct clk before clk init - * @clk: struct clk * to initialize - * - * Initialize any struct clk fields needed before normal clk initialization - * can run. No return value. - */ -static void clk_preinit(struct clk *clk) -{ - INIT_LIST_HEAD(&clk->children); -} - -static int clk_register(struct clk *clk) -{ - if (clk == NULL || IS_ERR(clk)) - return -EINVAL; - - /* - * trap out already registered clocks - */ - if (clk->node.next || clk->node.prev) - return 0; - - mutex_lock(&clocks_mutex); - - if (clk->get_parent) - clk->parent = clk->get_parent(clk); - - if (clk->parent) - list_add(&clk->sibling, &clk->parent->children); - else - list_add(&clk->sibling, &root_clks); - - list_add(&clk->node, &clocks); - - mutex_unlock(&clocks_mutex); - - return 0; -} - -static void clk_enable_init_clocks(void) -{ - struct clk *clkp; - - list_for_each_entry(clkp, &clocks, node) { - if (clkp->flags & ENABLE_ON_INIT) - clk_enable(clkp); - } -} - -static unsigned int __initdata armclk = 576000000; - -/* - * You can override arm_clk rate with armclk= cmdline option. - */ -static int __init armclk_setup(char *str) -{ - get_option(&str, &armclk); - - if (!armclk) - return 1; - - if (armclk < 1000) - armclk *= 1000000; - - return 1; -} -__setup("armclk=", armclk_setup); - -extern void rk2818_timer_update_mult(void); - -/* - * Switch the arm_clk rate if specified on cmdline. - * We cannot do this early until cmdline is parsed. - */ -static int __init rk2818_clk_arch_init(void) -{ - if (!armclk) - return -EINVAL; - - if (clk_set_rate(&arm_clk, armclk)) - pr_err("*** Unable to set arm_clk rate\n"); - - printk(KERN_INFO "Switched to new clocking rate (pll/arm/hclk/pclk): " - "%ld/%ld/%ld/%ld MHz\n", - arm_pll_clk.rate / 1000000, arm_clk.rate / 1000000, - arm_hclk.rate / 1000000, arm_pclk.rate / 1000000); - - /* cpufreq is not active now, so change timer_mult and loops_per_jiffy manually */ - rk2818_timer_update_mult(); - calibrate_delay(); - printk(KERN_INFO "%lu.%02lu BogoMIPS (lpj=%lu)\n", loops_per_jiffy/(500000/HZ), (loops_per_jiffy/(5000/HZ)) % 100, loops_per_jiffy); - - return 0; -} -core_initcall_sync(rk2818_clk_arch_init); - -void __init rk2818_clock_init(void) -{ - struct clk_lookup *lk; - - for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) - clk_preinit(lk->clk); - - for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) { - clkdev_add(lk); - clk_register(lk->clk); - } - - recalculate_root_clocks(); - - printk(KERN_INFO "Clocking rate (pll/arm/hclk/pclk): " - "%ld/%ld/%ld/%ld MHz\n", - arm_pll_clk.rate / 1000000, arm_clk.rate / 1000000, - arm_hclk.rate / 1000000, arm_pclk.rate / 1000000); - - /* - * Only enable those clocks we will need, let the drivers - * enable other clocks as necessary - */ - clk_enable_init_clocks(); -} - -#ifdef CONFIG_PROC_FS -#include -#include - -static void dump_clock(struct seq_file *s, struct clk *clk, int deep) -{ - struct clk* ck; - int i; - unsigned long rate = clk->rate; - - for (i = 0; i < deep; i++) - seq_printf(s, " "); - - seq_printf(s, "%-9s ", clk->name); - - if (clk->gate_idx < CLK_GATE_MAX) { - u32 reg; - int idx = clk->gate_idx; - u32 v; - - reg = SCU_CLKGATE0_CON; - reg += (idx >> 5) << 2; - idx &= 0x1F; - - v = scu_readl(reg) & (1 << idx); - - seq_printf(s, "%s ", v ? "off" : "on "); - } else - seq_printf(s, "%s ", clk->usecount ? "on " : "off"); - - if (rate >= 1000000) { - if (rate % 1000000) - seq_printf(s, "%ld.%06ld MHz", rate / 1000000, rate % 1000000); - else - seq_printf(s, "%ld MHz", rate / 1000000); - } else if (rate >= 1000) { - if (rate % 1000) - seq_printf(s, "%ld.%03ld KHz", rate / 1000, rate % 1000); - else - seq_printf(s, "%ld KHz", rate / 1000); - } else { - seq_printf(s, "%ld Hz", rate); - } - - seq_printf(s, " usecount = %d", clk->usecount); - - seq_printf(s, " parent = %s\n", clk->parent ? clk->parent->name : "NULL"); - - list_for_each_entry(ck, &clocks, node) { - if (ck->parent == clk) - dump_clock(s, ck, deep + 1); - } -} - -static int proc_clk_show(struct seq_file *s, void *v) -{ - struct clk* clk; - - mutex_lock(&clocks_mutex); - list_for_each_entry(clk, &clocks, node) { - if (!clk->parent) - dump_clock(s, clk, 0); - } - mutex_unlock(&clocks_mutex); - - seq_printf(s, "\nRegisters:\n"); - seq_printf(s, "SCU_APLL_CON : 0x%08x\n", scu_readl(SCU_APLL_CON)); - seq_printf(s, "SCU_DPLL_CON : 0x%08x\n", scu_readl(SCU_DPLL_CON)); - seq_printf(s, "SCU_CPLL_CON : 0x%08x\n", scu_readl(SCU_CPLL_CON)); - seq_printf(s, "SCU_MODE_CON : 0x%08x\n", scu_readl(SCU_MODE_CON)); - seq_printf(s, "SCU_PMU_CON : 0x%08x\n", scu_readl(SCU_PMU_CON)); - seq_printf(s, "SCU_CLKSEL0_CON : 0x%08x\n", scu_readl(SCU_CLKSEL0_CON)); - seq_printf(s, "SCU_CLKSEL1_CON : 0x%08x\n", scu_readl(SCU_CLKSEL1_CON)); - seq_printf(s, "SCU_CLKGATE0_CON : 0x%08x\n", scu_readl(SCU_CLKGATE0_CON)); - seq_printf(s, "SCU_CLKGATE1_CON : 0x%08x\n", scu_readl(SCU_CLKGATE1_CON)); - seq_printf(s, "SCU_CLKGATE2_CON : 0x%08x\n", scu_readl(SCU_CLKGATE2_CON)); - seq_printf(s, "SCU_CLKSEL2_CON : 0x%08x\n", scu_readl(SCU_CLKSEL2_CON)); - - return 0; -} - -static int proc_clk_open(struct inode *inode, struct file *file) -{ - return single_open(file, proc_clk_show, NULL); -} - -static const struct file_operations proc_clk_fops = { - .open = proc_clk_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int __init clk_proc_init(void) -{ - proc_create("clocks", 0, NULL, &proc_clk_fops); - return 0; - -} -late_initcall(clk_proc_init); -#endif /* CONFIG_PROC_FS */ - diff --git a/arch/arm/mach-rk2818/cpufreq.c b/arch/arm/mach-rk2818/cpufreq.c deleted file mode 100755 index 081531ec8f55..000000000000 --- a/arch/arm/mach-rk2818/cpufreq.c +++ /dev/null @@ -1,107 +0,0 @@ -/* arch/arm/mach-rk2818/cpufreq.c - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include - -static struct cpufreq_frequency_table freq_table[] = { - { .frequency = 192000 }, - { .frequency = 576000 }, - { .frequency = CPUFREQ_TABLE_END }, -}; -static struct clk *arm_clk; - -static int rk2818_cpufreq_verify(struct cpufreq_policy *policy) -{ - return cpufreq_frequency_table_verify(policy, freq_table); -} - -static int rk2818_cpufreq_target(struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation) -{ - int index; - struct cpufreq_freqs freqs; - - if (policy->cpu != 0) - return -EINVAL; - if (cpufreq_frequency_table_target(policy, freq_table, target_freq, relation, &index)) { - pr_err("cpufreq: invalid target_freq: %d\n", target_freq); - return -EINVAL; - } - - if (policy->cur == freq_table[index].frequency) - return 0; - -#ifdef CONFIG_CPU_FREQ_DEBUG - printk(KERN_DEBUG "%s %d r %d (%d-%d) selected %d\n", __func__, target_freq, relation, policy->min, policy->max, freq_table[index].frequency); -#endif - freqs.old = policy->cur; - freqs.new = freq_table[index].frequency; - freqs.cpu = 0; - cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); - clk_set_rate(arm_clk, freqs.new * 1000); - cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); - - return 0; -} - -extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table); - -static int __init rk2818_cpufreq_init(struct cpufreq_policy *policy) -{ - arm_clk = clk_get(NULL, "arm"); - if (IS_ERR(arm_clk)) - return PTR_ERR(arm_clk); - - if (policy->cpu != 0) - return -EINVAL; - - BUG_ON(cpufreq_frequency_table_cpuinfo(policy, freq_table)); - cpufreq_frequency_table_get_attr(freq_table, policy->cpu); - policy->cur = clk_get_rate(arm_clk) / 1000; - policy->cpuinfo.transition_latency = 300 * NSEC_PER_USEC; // FIXME: 0.3ms? - - return 0; -} - -static int rk2818_cpufreq_exit(struct cpufreq_policy *policy) -{ - clk_put(arm_clk); - return 0; -} - -static struct freq_attr *rk2818_cpufreq_attr[] = { - &cpufreq_freq_attr_scaling_available_freqs, - NULL, -}; - -static struct cpufreq_driver rk2818_cpufreq_driver = { - .flags = CPUFREQ_STICKY, - .init = rk2818_cpufreq_init, - .exit = rk2818_cpufreq_exit, - .verify = rk2818_cpufreq_verify, - .target = rk2818_cpufreq_target, - .name = "rk2818", - .attr = rk2818_cpufreq_attr, -}; - -static int __init rk2818_cpufreq_register(void) -{ - return cpufreq_register_driver(&rk2818_cpufreq_driver); -} - -device_initcall(rk2818_cpufreq_register); - diff --git a/arch/arm/mach-rk2818/ddr.c b/arch/arm/mach-rk2818/ddr.c deleted file mode 100644 index 83671c539cae..000000000000 --- a/arch/arm/mach-rk2818/ddr.c +++ /dev/null @@ -1,2171 +0,0 @@ -/**************************************************************** -// CopyRight(C) 2008 by Rock-Chip Fuzhou -// All Rights Reserved -//ÎļþÃû:hw_sdram.c -//ÃèÊö:sdram driver implement -//×÷Õß:hcy -//´´½¨ÈÕÆÚ:2008-11-08 -//¸ü¸Ä¼Ç¼: -$Log: hw_sdram.c,v $ -Revision 1.1.1.1 2009/12/15 01:46:27 zjd -20091215 ÑîÓÀÖÒÌá½»³õʼ°æ±¾ - -Revision 1.1.1.1 2009/09/25 08:00:32 zjd -20090925 »ÆµÂʤÌá½» V1.3.1 - -Revision 1.1.1.1 2009/08/18 06:43:26 Administrator -no message - -Revision 1.1.1.1 2009/08/14 08:02:00 Administrator -no message - -Revision 1.4 2009/04/02 03:03:37 hcy -¸üÐÂSDRAMʱÐòÅäÖã¬Ö»¿¼ÂÇ-6£¬-75ϵÁÐSDRAM - -Revision 1.3 2009/03/19 13:38:39 hxy -hcyÈ¥µôSDRAM±£ÊØʱÐò,±£ÊØʱÐò²»¶Ô,µ¼ÖÂMP3²¥·Åʱ½çÃ涶¶¯ - -Revision 1.2 2009/03/19 12:21:18 hxy -hcyÔö¼ÓSDRAM±£ÊØʱÐò¹©²âÊÔ - -Revision 1.1.1.1 2009/03/16 01:34:06 zjd -20090316 µËѵ½ðÌṩ³õʼSDK°æ±¾ - -Revision 1.2 2009/03/07 07:30:18 yk -(yk)¸üÐÂSCUÄ£¿é¸÷ƵÂÊÉèÖã¬Íê³ÉËùÓк¯Êý¼°´úÂ룬¸üгõʼ»¯ÉèÖ㬠-¸üÐÂÒ£¿ØÆ÷´úÂ룬ɾ³ýFPGA_BOARDºê¡£ -(hcy)SDRAMÇý¶¯¸Ä³É28µÄ - -//µ±Ç°°æ±¾:1.00 -****************************************************************/ -#define DRIVERS_DDRAM - - -#ifdef DRIVERS_DDRAM -#include -#include -#include -#include -#include - -#include - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32)) -#include -#include -#include -#include -#include -#include -#else -#include -#include -#include -#endif -#include -#include - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32)) -#undef SCU_APLL_CON -#undef SCU_DPLL_CON -#undef SCU_CPLL_CON -#undef SCU_MODE_CON -#undef SCU_PMU_CON -#undef SCU_CLKSEL0_CON -#undef SCU_CLKSEL1_CON -#undef SCU_CLKGATE0_CON -#undef SCU_CLKGATE1_CON -#undef SCU_CLKGATE2_CON -#undef SCU_SOFTRST_CON -#undef SCU_CHIPCFG_CON -#undef SCU_CPUPD -#undef SCU_CLKSEL2_CON -#undef CPU_APB_REG0 -#undef CPU_APB_REG1 -#undef CPU_APB_REG0 -#undef CPU_APB_REG1 -#undef CPU_APB_REG2 -#undef CPU_APB_REG3 -#undef CPU_APB_REG4 -#undef CPU_APB_REG5 -#undef CPU_APB_REG6 -#undef CPU_APB_REG7 -#undef IOMUX_A_CON -#undef IOMUX_B_CON -#undef GPIO0_AB_PU_CON -#undef GPIO0_CD_PU_CON -#undef GPIO1_AB_PU_CON -#undef GPIO1_CD_PU_CON -#undef OTGPHY_CON0 -#undef OTGPHY_CON1 -typedef volatile struct tagGRF_REG -{ - unsigned int CPU_APB_REG0; - unsigned int CPU_APB_REG1; - unsigned int CPU_APB_REG2; - unsigned int CPU_APB_REG3; - unsigned int CPU_APB_REG4; - unsigned int CPU_APB_REG5; - unsigned int CPU_APB_REG6; - unsigned int CPU_APB_REG7; - unsigned int IOMUX_A_CON; - unsigned int IOMUX_B_CON; - unsigned int GPIO0_AB_PU_CON; - unsigned int GPIO0_CD_PU_CON; - unsigned int GPIO1_AB_PU_CON; - unsigned int GPIO1_CD_PU_CON; - unsigned int OTGPHY_CON0; - unsigned int OTGPHY_CON1; -}GRF_REG, *pGRF_REG,*pAPB_REG; - -/*intc*/ -typedef volatile struct tagINTC_REG -{ /*offset 0x00~0x30*/ - unsigned int IRQ_INTEN_L; //IRQ interrupt source enable register (low) - unsigned int IRQ_INTEN_H; //IRQ interrupt source enable register (high) - unsigned int IRQ_INTMASK_L; //IRQ interrupt source mask register (low). - unsigned int IRQ_INTMASK_H; //IRQ interrupt source mask register (high). - unsigned int IRQ_INTFORCE_L; //IRQ interrupt force register - unsigned int IRQ_INTFORCE_H; // - unsigned int IRQ_RAWSTATUS_L; //IRQ raw status register - unsigned int IRQ_RAWSTATUS_H; // - unsigned int IRQ_STATUS_L; //IRQ status register - unsigned int IRQ_STATUS_H; // - unsigned int IRQ_MASKSTATUS_L; //IRQ interrupt mask status register - unsigned int IRQ_MASKSTATUS_H; // - unsigned int IRQ_FINALSTATUS_L;//IRQ interrupt final status - unsigned int IRQ_FINALSTATUS_H; - unsigned int reserved0[(0xC0-0x38)/4]; - - /*offset 0xc0~0xd8*/ - unsigned int FIQ_INTEN; //Fast interrupt enable register - unsigned int FIQ_INTMASK; //Fast interrupt mask register - unsigned int FIQ_INTFORCE; //Fast interrupt force register - unsigned int FIQ_RAWSTATUS; //Fast interrupt source raw status register - unsigned int FIQ_STATUS; //Fast interrupt status register - unsigned int FIQ_FINALSTATUS; //Fast interrupt final status register - unsigned int IRQ_PLEVEL; //IRQ System Priority Level Register - unsigned int reserved1[(0xe8-0xdc)/4]; - - /*offset 0xe8~0xe8+39*4*/ - unsigned int IRQ_PN_OFFSET[40];//Interrupt N priority level register(s), - // where N is from 0 to 15 - unsigned int reserved2[(0x3f0-0x188)/4]; - - /*offset 0x3f0~0x3fc*/ - unsigned int ICTL_COMP_PARAMS_2; //Component Parameter Register 2 - unsigned int ICTL_COMP_PARAMS_1; //Component Parameter Register 1 - unsigned int AHB_ICTL_COMP_VERSION;//Version register - unsigned int ICTL_COMP_TYPE; //Component Type Register -}INTC_REG, *pINTC_REG; - -typedef u32 uint32; -#define SCU_BASE_ADDR_VA RK2818_SCU_BASE -#define SDRAMC_BASE_ADDR_VA RK2818_SDRAMC_BASE -#define REG_FILE_BASE_ADDR_VA RK2818_REGFILE_BASE -#define INTC_BASE_ADDR_VA RK2818_INTC_BASE -#define UART0_BASE_ADDR_VA RK2818_UART0_BASE - -static inline int rockchip_clk_get_ahb(void) -{ - struct clk *arm_hclk = clk_get(NULL, "arm_hclk"); - int ahb = clk_get_rate(arm_hclk) / 1000; - clk_put(arm_hclk); - return ahb; -} - -extern void clk_recalculate_root_clocks(void); - -#define S_INFO(msg...) -#define S_WARN(msg...) printk(KERN_WARNING msg) - -#define rockchip_mux_api_set rk2818_mux_api_set - -#define PMW3_PRESCALE 25 // out put clk = pclk / (PMW3_PRESCALE*2) -#define VDD_095 (100/(100/PMW3_PRESCALE)) // io , out 1 -#define VDD_140 (0/(100/PMW3_PRESCALE)) // io , out 0. -#define VDD_130 (20/(100/PMW3_PRESCALE)) -#define VDD_125 (32/(100/PMW3_PRESCALE)) // io , int. -#define VDD_120 (40/(100/PMW3_PRESCALE)) -#define VDD_115 (52/(100/PMW3_PRESCALE)) -#define VDD_110 (60/(100/PMW3_PRESCALE)) -#define VDD_105 (68/(100/PMW3_PRESCALE)) -#define VDD_END (PMW3_PRESCALE*2) - -static int __tcmlocalfunc rk28_change_vdd( int vdd ) -{ - return 0; -} - -#include -static void __tcmlocalfunc __rk28_halt_here(void) -{ - asm volatile ( - "mov r0, #0\n" - "mrc p15, 0, r1, c1, c0, 0 @ Read control register\n" - "mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer\n" - "bic r2, r1, #1 << 12\n" - "mrs r3, cpsr @ Disable FIQs while Icache\n" - "orr ip, r3, %0 @ is disabled\n" - "msr cpsr_c, ip\n" - "mcr p15, 0, r2, c1, c0, 0 @ Disable I cache\n" - "mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt\n" - "nop @20091221,flush cpu line\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable\n" - "msr cpsr_c, r3 @ Restore FIQ state\n" - "mov pc, lr\n" - ::"I" (PSR_F_BIT)); -} -#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32) */ - -/*APB reg file*/ -#if 0 /*xxm replace by iomux.h*/ -typedef volatile struct tagGRF_REG -{ - unsigned int CPU_APB_REG0; - unsigned int CPU_APB_REG1; - unsigned int CPU_APB_REG2; - unsigned int CPU_APB_REG3; - unsigned int CPU_APB_REG4; - unsigned int CPU_APB_REG5; - unsigned int CPU_APB_REG6; - unsigned int CPU_APB_REG7; - unsigned int IOMUX_A_CON; - unsigned int IOMUX_B_CON; - unsigned int GPIO0_AB_PU_CON; - unsigned int GPIO0_CD_PU_CON; - unsigned int GPIO1_AB_PU_CON; - unsigned int GPIO1_CD_PU_CON; - unsigned int OTGPHY_CON0; - unsigned int OTGPHY_CON1; -}GRF_REG, *pGRF_REG,*pAPB_REG; -#endif -/*scu*/ -typedef volatile struct tagSCU_REG -{ - unsigned int SCU_APLL_CON;//[3];//0:arm 1:dsp 2:codec - unsigned int SCU_DPLL_CON; - unsigned int SCU_CPLL_CON; - unsigned int SCU_MODE_CON; - unsigned int SCU_PMU_CON; - unsigned int SCU_CLKSEL0_CON; - unsigned int SCU_CLKSEL1_CON; - unsigned int SCU_CLKGATE0_CON; - unsigned int SCU_CLKGATE1_CON; - unsigned int SCU_CLKGATE2_CON; - unsigned int SCU_SOFTRST_CON; - unsigned int SCU_CHIPCFG_CON; - unsigned int SCU_CPUPD; - unsigned int SCU_CLKSEL2_CON; -}SCU_REG,*pSCU_REG; - -#define SDRAM_REG_BASE (SDRAMC_BASE_ADDR_VA) -#define DDR_REG_BASE (SDRAMC_BASE_ADDR_VA) - -/* CPU_APB_REG4 */ -#define MSDR_1_8V_ENABLE (0x1 << 24) -#define READ_PIPE_ENABLE (0x1 << 22) -#define EXIT_SELF_REFRESH (0x1 << 21) - -/* CPU_APB_REG5 */ -#define MEMTYPEMASK (0x3 << 11) -#define SDRAM (0x0 << 11) -#define Mobile_SDRAM (0x1 << 11) -#define DDRII (0x2 << 11) -#define Mobile_DDR (0x3 << 11) - -/* SDRAM Config Register */ -#define DATA_WIDTH_16 (0x0 << 13) -#define DATA_WIDTH_32 (0x1 << 13) -#define DATA_WIDTH_64 (0x2 << 13) -#define DATA_WIDTH_128 (0x3 << 13) - -#define COL(n) ((n-1) << 9) -#define ROW(n) ((n-1) << 5) - -#define BANK_2 (0 << 3) -#define BANK_4 (1 << 3) -#define BANK_8 (2 << 3) -#define BANK_16 (3 << 3) - -/* SDRAM Timing Register0 */ -#define T_RC_SHIFT (22) -#define T_RC_MAX (0xF) -#define T_XSR_MSB_SHIFT (27) -#define T_XSR_MSB_MASK (0x1F) -#define T_XSR_LSB_SHIFT (18) -#define T_XSR_LSB_MASK (0xF) -#define T_RCAR_SHIFT (14) -#define T_RCAR_MAX (0xF) -#define T_WR_SHIFT (12) -#define T_WR_MAX (0x3) -#define T_RP_SHIFT (9) -#define T_RP_MAX (0x7) -#define T_RCD_SHIFT (6) -#define T_RCD_MAX (0x7) -#define T_RAS_SHIFT (2) -#define T_RAS_MASK (0xF) - -#define CL_1 (0) -#define CL_2 (1) -#define CL_3 (2) -#define CL_4 (3) - -/* SDRAM Timing Register1 */ -#define AR_COUNT_SHIFT (16) - -/* SDRAM Control Regitster */ -#define MSD_DEEP_POWERDOWN (1 << 20) -#define UPDATE_EMRS (1 << 18) -#define OPEN_BANK_COUNT_SHIFT (12) -#define SR_MODE (1 << 11) -#define UPDATE_MRS (1 << 9) -#define READ_PIPE_SHIFT (6) -#define REFRESH_ALL_ROW_A (1 << 5) -#define REFRESH_ALL_ROW_B (1 << 4) -#define DELAY_PRECHARGE (1 << 3) -#define SDR_POWERDOWN (1 << 2) -#define ENTER_SELF_REFRESH (1 << 1) -#define SDR_INIT (1 << 0) - -/* Extended Mode Register */ -#define DS_FULL (0 << 5) -#define DS_1_2 (1 << 5) -#define DS_1_4 (2 << 5) -#define DS_1_8 (3 << 5) - -#define TCSR_70 (0 << 3) -#define TCSR_45 (1 << 3) -#define TCSR_15 (2 << 3) -#define TCSR_85 (3 << 3) - -#define PASR_4_BANK (0) -#define PASR_2_BANK (1) -#define PASR_1_BANK (2) -#define PASR_1_2_BANK (5) -#define PASR_1_4_BANK (6) - -/* SDRAM Controller register struct */ -typedef volatile struct TagSDRAMC_REG -{ - volatile uint32 MSDR_SCONR; //SDRAM configuration register - volatile uint32 MSDR_STMG0R; //SDRAM timing register0 - volatile uint32 MSDR_STMG1R; //SDRAM timing register1 - volatile uint32 MSDR_SCTLR; //SDRAM control register - volatile uint32 MSDR_SREFR; //SDRAM refresh register - volatile uint32 MSDR_SCSLR0_LOW; //Chip select register0(lower 32bits) - volatile uint32 MSDR_SCSLR1_LOW; //Chip select register1(lower 32bits) - volatile uint32 MSDR_SCSLR2_LOW; //Chip select register2(lower 32bits) - uint32 reserved0[(0x54-0x1c)/4 - 1]; - volatile uint32 MSDR_SMSKR0; //Mask register 0 - volatile uint32 MSDR_SMSKR1; //Mask register 1 - volatile uint32 MSDR_SMSKR2; //Mask register 2 - uint32 reserved1[(0x84-0x5c)/4 - 1]; - volatile uint32 MSDR_CSREMAP0_LOW; //Remap register for chip select0(lower 32 bits) - uint32 reserved2[(0x94-0x84)/4 - 1]; - volatile uint32 MSDR_SMTMGR_SET0; //Static memory timing register Set0 - volatile uint32 MSDR_SMTMGR_SET1; //Static memory timing register Set1 - volatile uint32 MSDR_SMTMGR_SET2; //Static memory timing register Set2 - volatile uint32 MSDR_FLASH_TRPDR; //FLASH memory tRPD timing register - volatile uint32 MSDR_SMCTLR; //Static memory control register - uint32 reserved4; - volatile uint32 MSDR_EXN_MODE_REG; //Extended Mode Register -}SDRAMC_REG_T,*pSDRAMC_REG_T; - - -#define pSDR_Reg ((pSDRAMC_REG_T)SDRAM_REG_BASE) -#define pDDR_Reg ((pDDRC_REG_T)DDR_REG_BASE) -#define pSCU_Reg ((pSCU_REG)SCU_BASE_ADDR_VA) -#define pGRF_Reg ((pGRF_REG)REG_FILE_BASE_ADDR_VA) -#define pUART_Reg ((pUART_REG)UART0_BASE_ADDR_VA) - - -#define DDR_MEM_TYPE() (pGRF_Reg->CPU_APB_REG0 & MEMTYPEMASK) -#define DDR_ENABLE_SLEEP() do{pDDR_Reg->CTRL_REG_36 = 0x1F1F;}while(0) - -#define ODT_DIS (0x0) -#define ODT_75 (0x8) -#define ODT_150 (0x40) -#define ODT_50 (0x48) - -/* CTRL_REG_01 */ -#define EXP_BDW_OVFLOW (0x1 << 24) //port 3 -#define LCDC_BDW_OVFLOW (0x1 << 16) //port 2 - -/* CTRL_REG_02 */ -#define VIDEO_BDW_OVFLOW (0x1 << 24) //port 7 -#define CEVA_BDW_OVFLOW (0x1 << 16) //port 6 -#define ARMI_BDW_OVFLOW (0x1 << 8) //port 5 -#define ARMD_BDW_OVFLOW (0x1 << 0) //port 4 - -/* CTR_REG_03 */ -#define CONCURRENTAP (0x1 << 16) - -/* CTRL_REG_04 */ -#define SINGLE_ENDED_DQS (0x0 << 24) -#define DIFFERENTIAL_DQS (0x1 << 24) -#define DLL_BYPASS_EN (0x1 << 16) - -/* CTR_REG_05 */ -#define CS1_BANK_4 (0x0 << 16) -#define CS1_BANK_8 (0x1 << 16) -#define CS0_BANK_4 (0x0 << 8) -#define CS0_BANK_8 (0x1 << 8) - -/* CTR_REG_07 */ -#define ODT_CL_3 (0x1 << 8) - -/* CTR_REG_08 */ -#define BUS_16BIT (0x1 << 16) -#define BUS_32BIT (0x0 << 16) - -/* CTR_REG_10 */ -#define EN_TRAS_LOCKOUT (0x1 << 24) -#define DIS_TRAS_LOCKOUT (0x0 << 24) - -/* CTR_REG_12 */ -#define AXI_MC_ASYNC (0x0) -#define AXI_MC_2_1 (0x1) -#define AXI_MC_1_2 (0x2) -#define AXI_MC_SYNC (0x3) - -/* CTR_REG_13 */ -#define LCDC_WR_PRIO(n) ((n) << 24) -#define LCDC_RD_PRIO(n) ((n) << 16) - -/* CTR_REG_14 */ -#define EXP_WR_PRIO(n) ((n) << 16) -#define EXP_RD_PRIO(n) ((n) << 8) - -/* CTR_REG_15 */ -#define ARMD_WR_PRIO(n) ((n) << 8) -#define ARMD_RD_PRIO(n) (n) -#define ARMI_RD_PRIO(n) ((n) << 24) - -/* CTR_REG_16 */ -#define ARMI_WR_PRIO(n) (n) -#define CEVA_WR_PRIO(n) ((n) << 24) -#define CEVA_RD_PRIO(n) ((n) << 16) - -/* CTR_REG_17 */ -#define VIDEO_WR_PRIO(n) ((n) << 16) -#define VIDEO_RD_PRIO(n) ((n) << 8) -#define CS_MAP(n) ((n) << 24) - -/* CTR_REG_18 */ -#define CS0_RD_ODT_MASK (0x3 << 24) -#define CS0_RD_ODT(n) (0x1 << (24+(n))) -#define CS0_LOW_POWER_REF_EN (0x0 << 8) -#define CS0_LOW_POWER_REF_DIS (0x1 << 8) -#define CS1_LOW_POWER_REF_EN (0x0 << 9) -#define CS1_LOW_POWER_REF_DIS (0x1 << 9) - -/* CTR_REG_19 */ -#define CS0_ROW(n) ((n) << 24) -#define CS1_WR_ODT_MASK (0x3 << 16) -#define CS1_WR_ODT(n) (0x1 << (16+(n))) -#define CS0_WR_ODT_MASK (0x3 << 8) -#define CS0_WR_ODT(n) (0x1 << (8+(n))) -#define CS1_RD_ODT_MASK (0x3) -#define CS1_RD_ODT(n) (0x1 << (n)) - -/* CTR_REG_20 */ -#define CS1_ROW(n) (n) -#define CL(n) (((n)&0x7) << 16) - -/* CTR_REG_21 */ -#define CS0_COL(n) (n) -#define CS1_COL(n) ((n) << 8) - -/* CTR_REG_23 */ -#define TRRD(n) (((n)&0x7) << 24) -#define TCKE(n) (((n)&0x7) << 8) - -/* CTR_REG_24 */ -#define TWTR_CK(n) (((n)&0x7) << 16) -#define TRTP(n) ((n)&0x7) - -/* CTR_REG_29 */ -//CAS latency linear value -#define CL_L_1_0 (2) -#define CL_L_1_5 (3) -#define CL_L_2_0 (4) -#define CL_L_2_5 (5) -#define CL_L_3_0 (6) -#define CL_L_3_5 (7) -#define CL_L_4_0 (8) -#define CL_L_4_5 (9) -#define CL_L_5_0 (0xA) -#define CL_L_5_5 (0xB) -#define CL_L_6_0 (0xC) -#define CL_L_6_5 (0xD) -#define CL_L_7_0 (0xE) -#define CL_L_7_5 (0xF) - -/* CTR_REG_34 */ -#define CS0_TRP_ALL(n) (((n)&0xF) << 24) -#define TRP(n) (((n)&0xF) << 16) - -/* CTR_REG_35 */ -#define WL(n) ((((n)&0xF) << 16) | (((n)&0xF) << 24)) -#define TWTR(n) (((n)&0xF) << 8) -#define CS1_TRP_ALL(n) ((n)&0xF) - -/* CTR_REG_37 */ -#define TMRD(n) ((n) << 24) -#define TDAL(n) ((n) << 16) -#define TCKESR(n) ((n) << 8) -#define TCCD(n) (n) - -/* CTR_REG_38 */ -#define TRC(n) ((n) << 24) -#define TFAW(n) ((n) << 16) -#define TWR(n) (n) - -/* CTR_REG_40 */ -#define EXP_BW_PER(n) ((n) << 16) -#define LCDC_BW_PER(n) (n) - -/* CTR_REG_41 */ -#define ARMI_BW_PER(n) ((n) << 16) -#define ARMD_BW_PER(n) (n) - -/* CTR_REG_42 */ -#define VIDEO_BW_PER(n) ((n) << 16) -#define CEVA_BW_PER(n) (n) - -/* CTR_REG_43 */ -#define TMOD(n) (((n)&0xFF) << 24) - -/* CTR_REG_44 */ -#define TRFC(n) ((n) << 16) -#define TRCD(n) ((n) << 8) -#define TRAS_MIN(n) (n) - -/* CTR_REG_48 */ -#define TPHYUPD_RESP(n) (((n)&0x3FFF) << 16) -#define TCTRLUPD_MAX(n) ((n)&0x3FFF) - -/* CTR_REG_51 */ -#define CS0_MR(n) ((((n) & 0xFEF0) | 0x2) << 16) -#define TREF(n) (n) - -/* CTR_REG_52 */ -#define CS0_EMRS_1(n) (((n)&0xFFC7) << 16) -#define CS1_MR(n) (((n) & 0xFEF0) | 0x2) - -/* CTR_REG_53 */ -#define CS0_EMRS_2(n) ((n) << 16) -#define CS0_EMR(n) ((n) << 16) -#define CS1_EMRS_1(n) ((n)&0xFFC7) - -/* CTR_REG_54 */ -#define CS0_EMRS_3(n) ((n) << 16) -#define CS1_EMRS_2(n) (n) -#define CS1_EMR(n) (n) - -/* CTR_REG_55 */ -#define CS1_EMRS_3(n) (n) - -/* CTR_REG_59 */ -#define CS_MSK_0(n) (((n)&0xFFFF) << 16) - -/* CTR_REG_60 */ -#define CS_VAL_0(n) (((n)&0xFFFF) << 16) -#define CS_MSK_1(n) ((n)&0xFFFF) - -/* CTR_REG_61 */ -#define CS_VAL_1(n) ((n)&0xFFFF) - -/* CTR_REG_62 */ -#define MODE5_CNT(n) (((n)&0xFFFF) << 16) -#define MODE4_CNT(n) ((n)&0xFFFF) - -/* CTR_REG_63 */ -#define MODE1_2_CNT(n) ((n)&0xFFFF) - -/* CTR_REG_64 */ -#define TCPD(n) ((n) << 16) -#define MODE3_CNT(n) (n) - -/* CTR_REG_65 */ -#define TPDEX(n) ((n) << 16) -#define TDLL(n) (n) - -/* CTR_REG_66 */ -#define TXSNR(n) ((n) << 16) -#define TRAS_MAX(n) (n) - -/* CTR_REG_67 */ -#define TXSR(n) (n) - -/* CTR_REG_68 */ -#define TINIT(n) (n) - - -/* DDR Controller register struct */ -typedef volatile struct TagDDRC_REG -{ - volatile uint32 CTRL_REG_00; - volatile uint32 CTRL_REG_01; - volatile uint32 CTRL_REG_02; - volatile uint32 CTRL_REG_03; - volatile uint32 CTRL_REG_04; - volatile uint32 CTRL_REG_05; - volatile uint32 CTRL_REG_06; - volatile uint32 CTRL_REG_07; - volatile uint32 CTRL_REG_08; - volatile uint32 CTRL_REG_09; - volatile uint32 CTRL_REG_10; - volatile uint32 CTRL_REG_11; - volatile uint32 CTRL_REG_12; - volatile uint32 CTRL_REG_13; - volatile uint32 CTRL_REG_14; - volatile uint32 CTRL_REG_15; - volatile uint32 CTRL_REG_16; - volatile uint32 CTRL_REG_17; - volatile uint32 CTRL_REG_18; - volatile uint32 CTRL_REG_19; - volatile uint32 CTRL_REG_20; - volatile uint32 CTRL_REG_21; - volatile uint32 CTRL_REG_22; - volatile uint32 CTRL_REG_23; - volatile uint32 CTRL_REG_24; - volatile uint32 CTRL_REG_25; - volatile uint32 CTRL_REG_26; - volatile uint32 CTRL_REG_27; - volatile uint32 CTRL_REG_28; - volatile uint32 CTRL_REG_29; - volatile uint32 CTRL_REG_30; - volatile uint32 CTRL_REG_31; - volatile uint32 CTRL_REG_32; - volatile uint32 CTRL_REG_33; - volatile uint32 CTRL_REG_34; - volatile uint32 CTRL_REG_35; - volatile uint32 CTRL_REG_36; - volatile uint32 CTRL_REG_37; - volatile uint32 CTRL_REG_38; - volatile uint32 CTRL_REG_39; - volatile uint32 CTRL_REG_40; - volatile uint32 CTRL_REG_41; - volatile uint32 CTRL_REG_42; - volatile uint32 CTRL_REG_43; - volatile uint32 CTRL_REG_44; - volatile uint32 CTRL_REG_45; - volatile uint32 CTRL_REG_46; - volatile uint32 CTRL_REG_47; - volatile uint32 CTRL_REG_48; - volatile uint32 CTRL_REG_49; - volatile uint32 CTRL_REG_50; - volatile uint32 CTRL_REG_51; - volatile uint32 CTRL_REG_52; - volatile uint32 CTRL_REG_53; - volatile uint32 CTRL_REG_54; - volatile uint32 CTRL_REG_55; - volatile uint32 CTRL_REG_56; - volatile uint32 CTRL_REG_57; - volatile uint32 CTRL_REG_58; - volatile uint32 CTRL_REG_59; - volatile uint32 CTRL_REG_60; - volatile uint32 CTRL_REG_61; - volatile uint32 CTRL_REG_62; - volatile uint32 CTRL_REG_63; - volatile uint32 CTRL_REG_64; - volatile uint32 CTRL_REG_65; - volatile uint32 CTRL_REG_66; - volatile uint32 CTRL_REG_67; - volatile uint32 CTRL_REG_68; - volatile uint32 CTRL_REG_69; - volatile uint32 CTRL_REG_70; - volatile uint32 CTRL_REG_71; - volatile uint32 CTRL_REG_72; - volatile uint32 CTRL_REG_73; - volatile uint32 CTRL_REG_74; - volatile uint32 CTRL_REG_75; - volatile uint32 CTRL_REG_76; - volatile uint32 CTRL_REG_77; - volatile uint32 CTRL_REG_78; - volatile uint32 CTRL_REG_79; - volatile uint32 CTRL_REG_80; - volatile uint32 CTRL_REG_81; - volatile uint32 CTRL_REG_82; - volatile uint32 CTRL_REG_83; - volatile uint32 CTRL_REG_84; - volatile uint32 CTRL_REG_85; - volatile uint32 CTRL_REG_86; - volatile uint32 CTRL_REG_87; - volatile uint32 CTRL_REG_88; - volatile uint32 CTRL_REG_89; - volatile uint32 CTRL_REG_90; - volatile uint32 CTRL_REG_91; - volatile uint32 CTRL_REG_92; - volatile uint32 CTRL_REG_93; - volatile uint32 CTRL_REG_94; - volatile uint32 CTRL_REG_95; - volatile uint32 CTRL_REG_96; - volatile uint32 CTRL_REG_97; - volatile uint32 CTRL_REG_98; - volatile uint32 CTRL_REG_99; - volatile uint32 CTRL_REG_100; - volatile uint32 CTRL_REG_101; - volatile uint32 CTRL_REG_102; - volatile uint32 CTRL_REG_103; - volatile uint32 CTRL_REG_104; - volatile uint32 CTRL_REG_105; - volatile uint32 CTRL_REG_106; - volatile uint32 CTRL_REG_107; - volatile uint32 CTRL_REG_108; - volatile uint32 CTRL_REG_109; - volatile uint32 CTRL_REG_110; - volatile uint32 CTRL_REG_111; - volatile uint32 CTRL_REG_112; - volatile uint32 CTRL_REG_113; - volatile uint32 CTRL_REG_114; - volatile uint32 CTRL_REG_115; - volatile uint32 CTRL_REG_116; - volatile uint32 CTRL_REG_117; - volatile uint32 CTRL_REG_118; - volatile uint32 CTRL_REG_119; - volatile uint32 CTRL_REG_120; - volatile uint32 CTRL_REG_121; - volatile uint32 CTRL_REG_122; - volatile uint32 CTRL_REG_123; - volatile uint32 CTRL_REG_124; - volatile uint32 CTRL_REG_125; - volatile uint32 CTRL_REG_126; - volatile uint32 CTRL_REG_127; - volatile uint32 CTRL_REG_128; - volatile uint32 CTRL_REG_129; - volatile uint32 CTRL_REG_130; - volatile uint32 CTRL_REG_131; - volatile uint32 CTRL_REG_132; - volatile uint32 CTRL_REG_133; - volatile uint32 CTRL_REG_134; - volatile uint32 CTRL_REG_135; - volatile uint32 CTRL_REG_136; - volatile uint32 CTRL_REG_137; - volatile uint32 CTRL_REG_138; - volatile uint32 CTRL_REG_139; - volatile uint32 CTRL_REG_140; - volatile uint32 CTRL_REG_141; - volatile uint32 CTRL_REG_142; - volatile uint32 CTRL_REG_143; - volatile uint32 CTRL_REG_144; - volatile uint32 CTRL_REG_145; - volatile uint32 CTRL_REG_146; - volatile uint32 CTRL_REG_147; - volatile uint32 CTRL_REG_148; - volatile uint32 CTRL_REG_149; - volatile uint32 CTRL_REG_150; - volatile uint32 CTRL_REG_151; - volatile uint32 CTRL_REG_152; - volatile uint32 CTRL_REG_153; - volatile uint32 CTRL_REG_154; - volatile uint32 CTRL_REG_155; - volatile uint32 CTRL_REG_156; - volatile uint32 CTRL_REG_157; - volatile uint32 CTRL_REG_158; - volatile uint32 CTRL_REG_159; -}DDRC_REG_T,*pDDRC_REG_T; - -typedef volatile struct tagUART_STRUCT -{ - unsigned int UART_RBR; - unsigned int UART_DLH; - unsigned int UART_IIR; - unsigned int UART_LCR; - unsigned int UART_MCR; - unsigned int UART_LSR; - unsigned int UART_MSR; - unsigned int UART_SCR; - unsigned int RESERVED1[(0x30-0x20)/4]; - unsigned int UART_SRBR[(0x70-0x30)/4]; - unsigned int UART_FAR; - unsigned int UART_TFR; - unsigned int UART_RFW; - unsigned int UART_USR; - unsigned int UART_TFL; - unsigned int UART_RFL; - unsigned int UART_SRR; - unsigned int UART_SRTS; - unsigned int UART_SBCR; - unsigned int UART_SDMAM; - unsigned int UART_SFE; - unsigned int UART_SRT; - unsigned int UART_STET; - unsigned int UART_HTX; - unsigned int UART_DMASA; - unsigned int RESERVED2[(0xf4-0xac)/4]; - unsigned int UART_CPR; - unsigned int UART_UCV; - unsigned int UART_CTR; -} UART_REG, *pUART_REG; - -//#define pSDR_Reg ((pSDRAMC_REG_T)SDRAM_REG_BASE) -//#define pDDR_Reg ((pDDRC_REG_T)DDR_REG_BASE) -//#define pSCU_Reg ((pSCU_REG)SCU_BASE_ADDR_VA) -//#define pGRF_Reg ((pGRF_REG)REG_FILE_BASE_ADDR_VA) - -#define read32(address) (*((uint32 volatile*)(address))) -#define write32(address, value) (*((uint32 volatile*)(address)) = value) - -static volatile int __tcmdata rk28_debugs = 1; -unsigned long save_sp; - -static uint32 __tcmdata telement; -static uint32 __tcmdata capability; //µ¥¸öCSµÄÈÝÁ¿ -static uint32 __tcmdata SDRAMnewKHz = 150000; -// uint32 __tcmdata DDRnewKHz = 400000 ; //266000; -static uint32 __tcmdata SDRAMoldKHz = 66000; - //uint32 __tcmdata DDRoldKHz = 200000; -static unsigned int __tcmdata ddr_reg[8] ; - -static __tcmdata uint32 bFreqRaise; -static __tcmdata uint32 elementCnt; -static __tcmdata uint32 ddrSREF; -static __tcmdata uint32 ddrRASMAX; -static __tcmdata uint32 ddrCTRL_REG_23; -static __tcmdata uint32 ddrCTRL_REG_24; -static __tcmdata uint32 ddrCTRL_REG_34; -static __tcmdata uint32 ddrCTRL_REG_35; -static __tcmdata uint32 ddrCTRL_REG_37; -static __tcmdata uint32 ddrCTRL_REG_38; -static __tcmdata uint32 ddrCTRL_REG_43; -static __tcmdata uint32 ddrCTRL_REG_44; -static __tcmdata uint32 ddrCTRL_REG_64; -static __tcmdata uint32 ddrCTRL_REG_65; -static __tcmdata uint32 ddrCTRL_REG_66; -static __tcmdata uint32 ddrCTRL_REG_67; -static __tcmdata uint32 ddrCTRL_REG_68; - - -static void __tcmfunc DLLBypass(void) -{ - - volatile uint32 value = 0; - - value = pDDR_Reg->CTRL_REG_04; - pDDR_Reg->CTRL_REG_04 = value | DLL_BYPASS_EN; - - - pDDR_Reg->CTRL_REG_70 = 0x10002117 | (elementCnt << 15); - pDDR_Reg->CTRL_REG_71 = 0x10002117 | (elementCnt << 15); - pDDR_Reg->CTRL_REG_72 = 0x10002117 | (elementCnt << 15); - pDDR_Reg->CTRL_REG_73 = 0x10002117 | (elementCnt << 15); - pDDR_Reg->CTRL_REG_74 = 0x00002104 | (elementCnt << 15); - pDDR_Reg->CTRL_REG_75 = 0x00002104 | (elementCnt << 15); - pDDR_Reg->CTRL_REG_76 = 0x00002104 | (elementCnt << 15); - pDDR_Reg->CTRL_REG_77 = 0x00002104 | (elementCnt << 15); -} - -static void SDRAMUpdateRef(uint32 kHz) -{ - if(capability <= 0x2000000) // <= SDRAM_2x32x4 - { - // 64Mb and 128Mb SDRAM's auto refresh cycle 15.6us or a burst of 4096 auto refresh cycles once in 64ms - pSDR_Reg->MSDR_SREFR = (((125*kHz)/1000) >> 3) & 0xFFFF; // 125/8 = 15.625us - } - else - { - // 256Mb and 512Mb SDRAM's auto refresh cycle 7.8us or a burst of 8192 auto refresh cycles once in 64ms - pSDR_Reg->MSDR_SREFR = (((62*kHz)/1000) >> 3) & 0xFFFF; // 62/8 = 7.75us - } -} - -static void SDRAMUpdateTiming(uint32 kHz) -{ - uint32 value =0; - uint32 tmp = 0; - - value = pSDR_Reg->MSDR_STMG0R; - value &= 0xFC3C003F; - //t_rc = 15ns - tmp = (15*kHz/1000000) + ((((15*kHz)%1000000) > 0) ? 1:0); - tmp = (tmp > 0) ? (tmp - 1) : 0; - tmp = (tmp > T_RC_MAX) ? T_RC_MAX : tmp; - value |= tmp << T_RC_SHIFT; - //t_rcar = 80ns - tmp = (80*kHz/1000000) + ((((80*kHz)%1000000) > 0) ? 1:0); - tmp = (tmp > 0) ? (tmp - 1) : 0; - tmp = (tmp > T_RCAR_MAX) ? T_RCAR_MAX : tmp; - value |= tmp << T_RCAR_SHIFT; - //t_wr ¹Ì¶¨Îª2¸öclk - value |= 1 << T_WR_SHIFT; - //t_rp = 20ns - tmp = (20*kHz/1000000) + ((((20*kHz)%1000000) > 0) ? 1:0); - tmp = (tmp > 0) ? (tmp - 1) : 0; - tmp = (tmp > T_RP_MAX) ? T_RP_MAX : tmp; - value |= tmp << T_RP_SHIFT; - //t_rcd = 20ns - tmp = (20*kHz/1000000) + ((((20*kHz)%1000000) > 0) ? 1:0); - tmp = (tmp > 0) ? (tmp - 1) : 0; - tmp = (tmp > T_RCD_MAX) ? T_RCD_MAX : tmp; - value |= tmp << T_RCD_SHIFT; - pSDR_Reg->MSDR_STMG0R = value; - #if 0 - if(newKHz >= 90000) //´óÓÚ90M£¬¿ªÆôread pipe - { - value = *pSDR_SUB_Reg; - value |= READ_PIPE_ENABLE; - *pSDR_SUB_Reg = value; - value = pSDR_Reg->MSDR_SCTLR; - value &= ~(0x7 << READ_PIPE_SHIFT); - value |= (0x1 << READ_PIPE_SHIFT); - pSDR_Reg->MSDR_SCTLR = value; - } - else - { - value = *pSDR_SUB_Reg; - value &= ~(READ_PIPE_ENABLE); - *pSDR_SUB_Reg = value; - } - #endif -} - -#if 0 -static uint32 __tcmfunc DDR_debug_byte(char byte) -{ - uint32 uartTimeOut; -#define UART_THR UART_RBR - pUART_REG g_UART =((pUART_REG)(( UART1_BASE_ADDR_VA))); - if( byte == '\n' ) - DDR_debug_byte(0x0d); - uartTimeOut = 0xffff; - while((g_UART->UART_USR & (1<<1)) != (1<<1)) - { - if(uartTimeOut == 0) - { - return (1); - } - uartTimeOut--; - } - g_UART->UART_THR = byte; - return (0); -} -static uint32 __tcmfunc DDR_debug_string(char *s) -{ - while(*s){ - DDR_debug_byte(*s); - s++; - } - return 0; -} -#else -#define DDR_debug_string( a ) do{ }while(0) -#endif - -static void DDRPreUpdateRef(uint32 MHz) -{ - uint32 tmp; - - ddrSREF = ((62*MHz) >> 3) & 0x3FFF; // 62/8 = 7.75us - - ddrRASMAX = (70*MHz); - ddrRASMAX = (ddrRASMAX > 0xFFFF) ? 0xFFFF : ddrRASMAX; - - //tMOD = 12ns - tmp = (12*MHz/1000); - tmp = (tmp > 0xFF) ? 0xFF : tmp; - ddrCTRL_REG_43 = TMOD(tmp); -} - -static void __tcmfunc DDRUpdateRef(void) -{ - volatile uint32 value = 0; - - value = pDDR_Reg->CTRL_REG_51; - value &= ~(0x3FFF); - pDDR_Reg->CTRL_REG_51 = value|ddrSREF; - pDDR_Reg->CTRL_REG_48 = TPHYUPD_RESP(ddrSREF) | TCTRLUPD_MAX(ddrSREF); - - //tXSNR =ûÕâ¸öÃû×ÖµÄʱ¼ä£¬°´DDRII£¬Ò²ÈÃÆäµÈÓÚ = tRFC + 10ns, tRAS_max = 70000ns - value = pDDR_Reg->CTRL_REG_66; - value &= ~(0xFFFF); - pDDR_Reg->CTRL_REG_66 = value | TRAS_MAX(ddrRASMAX); - - pDDR_Reg->CTRL_REG_43 = ddrCTRL_REG_43; -} - - -static uint32 PLLGetDDRFreq(void) -{ - -#define DIV1 (0x00 << 30) -#define DIV2 (0x01 << 30) -#define DIV4 (0x02 << 30) -#define DIV8 (0x03 << 30) -#define EXT_OSC_CLK 24 -#define LOADER_DDR_FREQ_MHZ 133 - uint32 codecfrqMHz,ddrfrqMHz,codecpll_nf,codecpll_nr,codecpll_od,ddrclk_div; - codecpll_nr = ((pSCU_Reg->SCU_CPLL_CON & 0x003f0000) >> 16 ) + 1; /*NR = CLKR[5:0] + 1*/ - codecpll_nf = ((pSCU_Reg->SCU_CPLL_CON & 0x0000fff0) >> 4 ) + 1; /*NF = CLKF[11:0] + 1*/ - codecpll_od = ((pSCU_Reg->SCU_CPLL_CON & 0x0000000e) >> 1 ) + 1; /*OD = CLKOD[2:0] + 1*/ - ddrclk_div =(pSCU_Reg->SCU_CLKSEL0_CON & 0xc0000000); - switch(ddrclk_div) - { - case DIV1 : - ddrclk_div = 1; - //printk("%s-ddr clk div =%d->%d\n",__FUNCTION__,ddrclk_div,__LINE__); - break; - case DIV2 : - ddrclk_div = 2; - //printk("%s-ddr clk div =%d->%d\n",__FUNCTION__,ddrclk_div,__LINE__); - break; - case DIV4 : - ddrclk_div = 4; - //printk("%s-ddr clk div =%d->%d\n",__FUNCTION__,ddrclk_div,__LINE__); - break; - case DIV8 : - ddrclk_div = 8; - //printk("%s-ddr clk div =%d->%d\n",__FUNCTION__,ddrclk_div,__LINE__); - break; - default : - ddrclk_div = 1; - break; - } - #if 0 - if((armpll_nr == 0)||(armpll_od == 0)) - //printk("codec current clk error !! flag armpll_nr ==%d armpll_od==%d\n",armpll_nr,armpll_od); - if(((EXT_OSC_CLK/armpll_nr) < 9 ) && ((EXT_OSC_CLK/armpll_nr) > 800)) - //printk(" codec current freq/nr range error\n"); - if(((EXT_OSC_CLK/armpll_nr)*armpll_nf < 160 ) && ((EXT_OSC_CLK/armpll_nr)*armpll_nf > 800)) - //printk(" codec current freq/nr*nf range error\n"); - #endif - /*the output frequency Fout = EXT_OSC_CLK * armpll_nf/armpll_nr/armpll_od */ - codecfrqMHz = EXT_OSC_CLK * codecpll_nf; - codecfrqMHz = codecfrqMHz/codecpll_nr; - codecfrqMHz = codecfrqMHz/codecpll_od; - ddrfrqMHz = codecfrqMHz/ddrclk_div; /*calculate DDR current frquency*/ - //printk("SCU_CPLL_CON ==%x codecpll_nr == %d codecpll_nf == %d codecpll_od ==%d\n",pSCU_Reg->SCU_CPLL_CON,armpll_nr,armpll_nf,armpll_od); - //printk("get current freq codecfrqkhz==%d ddfrqkHz==%d\n",armfrqkHz,ddrfrqkHz); - if(ddrfrqMHz == 0) - return LOADER_DDR_FREQ_MHZ; - return ddrfrqMHz; -} - -static uint32 GetDDRCL(uint32 newMHz) -{ - uint32 memType = DDR_MEM_TYPE(); - - if(memType == DDRII) - { - if(newMHz <= 266) - { - return 4; - } - else if((newMHz > 266) && (newMHz <= 333)) - { - return 5; - } - else if((newMHz > 333) && (newMHz <= 400)) - { - return 6; - } - else // > 400MHz - { - return 6; - } - } - else - { - return 3; - } -} - -static void DDRPreUpdateTiming(uint32 MHz) -{ - uint32 tmp; - uint32 tmp2; - uint32 tmp3; - uint32 cl; - uint32 memType = DDR_MEM_TYPE();// (read32(CPU_APB_REG0) >> 11) & 0x3; - - cl = GetDDRCL(MHz); - //ʱÐò - if(memType == DDRII) - { - // tRRD = 10ns, tCKE = 3 tCK - tmp = (10*MHz/1000) + ((((10*MHz)%1000) > 0) ? 1:0); - tmp = (tmp > 7) ? 7 : tmp; - ddrCTRL_REG_23 = TRRD(tmp) | TCKE(3) | 0x2; - // tRTP = 7.5ns - tmp = (8*MHz/1000) + ((((8*MHz)%1000) > 0) ? 1:0); - tmp = (tmp > 7) ? 7 : tmp; - ddrCTRL_REG_24 = TRTP(tmp) | TWTR_CK(1) | 0x01000100; - //tRP_ALL = tRP + 1 tCK, tWTR = 10ns(DDR2-400), 7.5ns (DDR2-533/667/800) - if(MHz <= 200) - { - tmp2 = (10*MHz/1000) + ((((10*MHz)%1000) > 0) ? 1:0); - } - else - { - tmp2 = (8*MHz/1000) + ((((8*MHz)%1000) > 0) ? 1:0); - } - tmp2 = (tmp2 > 0xF) ? 0xF : tmp2; - ddrCTRL_REG_35 = CS1_TRP_ALL(cl+1) | TWTR(tmp2); - //tRP_ALL = tRP + 1 tCK, tRP = CL - ddrCTRL_REG_34 = CS0_TRP_ALL(cl+1) | TRP(cl) | 0x200; - // tMRD = 2 tCK, tDAL = tWR + tRP = 15ns + CL, tCCD = 2 tCK, DDR2: tCKESR=tCKE=3 tCK, mobile DDR: tCKESR=tRFC - tmp = (15*MHz/1000) + ((((15*MHz)%1000) > 0) ? 1:0); - tmp += cl; - tmp = (tmp > 0x1F) ? 0x1F : tmp; - ddrCTRL_REG_37 = TMRD(2) | TDAL(tmp) | TCKESR(3) | TCCD(2); - if(MHz <= 200) //tRC = 65ns - { - tmp = (65*MHz/1000) + ((((65*MHz)%1000) > 0) ? 1:0); - } - else //tRC = 60ns - { - tmp = (60*MHz/1000) + ((((60*MHz)%1000) > 0) ? 1:0); - } - //tFAW = 50ns, tWR = 15ns - tmp = (tmp > 0x3F) ? 0x3F : tmp; - tmp2 = (50*MHz/1000) + ((((50*MHz)%1000) > 0) ? 1:0); - tmp2 = (tmp2 > 0x3F) ? 0x3F : tmp2; - tmp3 = (15*MHz/1000) + ((((15*MHz)%1000) > 0) ? 1:0); - tmp3 = (tmp3 > 0x1F) ? 0x1F : tmp3; - ddrCTRL_REG_38 = TRC(tmp) | TFAW(tmp2) | TWR(tmp3); - if(capability <= 0x2000000) // 256Mb - { - tmp = (75*MHz/1000) + ((((75*MHz)%1000) > 0) ? 1:0); - tmp = (tmp > 0xFF) ? 0xFF : tmp; - //tXSNR = tRFC + 10ns, tRAS_max = 70000ns - tmp3 = (85*MHz/1000) + ((((85*MHz)%1000) > 0) ? 1:0); - tmp3 = (tmp3 > 0xFFFF) ? 0xFFFF : tmp3; - ddrCTRL_REG_66 = TXSNR(tmp3); - } - else if(capability <= 0x4000000) // 512Mb - { - tmp = (105*MHz/1000) + ((((105*MHz)%1000) > 0) ? 1:0); - tmp = (tmp > 0xFF) ? 0xFF : tmp; - //tXSNR = tRFC + 10ns, tRAS_max = 70000ns - tmp3 = (115*MHz/1000) + ((((115*MHz)%1000) > 0) ? 1:0); - tmp3 = (tmp3 > 0xFFFF) ? 0xFFFF : tmp3; - ddrCTRL_REG_66 = TXSNR(tmp3); - } - else if(capability <= 0x8000000) // 1Gb - { - tmp = (128*MHz/1000) + ((((128*MHz)%1000) > 0) ? 1:0); - tmp = (tmp > 0xFF) ? 0xFF : tmp; - //tXSNR = tRFC + 10ns, tRAS_max = 70000ns - tmp3 = (138*MHz/1000) + ((((138*MHz)%1000) > 0) ? 1:0); - tmp3 = (tmp3 > 0xFFFF) ? 0xFFFF : tmp3; - ddrCTRL_REG_66 = TXSNR(tmp3); - } - else // 4Gb - { - tmp = (328*MHz/1000) + ((((328*MHz)%1000) > 0) ? 1:0); - tmp = (tmp > 0xFF) ? 0xFF : tmp; - //tXSNR = tRFC + 10ns, tRAS_max = 70000ns - tmp3 = (338*MHz/1000) + ((((338*MHz)%1000) > 0) ? 1:0); - tmp3 = (tmp3 > 0xFFFF) ? 0xFFFF : tmp3; - ddrCTRL_REG_66 = TXSNR(tmp3); - } - //tRFC = 75ns(256Mb)/105ns(512Mb)/127.5ns(1Gb)/327.5ns(4Gb), tRCD = CL, tRAS_min = 45ns - tmp3 = (45*MHz/1000) + ((((45*MHz)%1000) > 0) ? 1:0); - tmp3 = (tmp3 > 0xFF) ? 0xFF : tmp3; - ddrCTRL_REG_44 = TRFC(tmp) | TRCD(cl) | TRAS_MIN(tmp3); - //tPDEX=ûÕÒµ½£¬Ó¦¸ÃµÈÓÚ=tXPºÍtXARDÖеÄ×î´óÕß - ddrCTRL_REG_65 = TPDEX(0x2) | TDLL(200); - //tXSR = tXSRD = 200 tCK - ddrCTRL_REG_67 = TXSR(200); - } - else - { - // tRTP = 0ns - ddrCTRL_REG_24 = TRTP(0) | TWTR_CK(1) | 0x01000100; - //tWTR = 1 tCK - ddrCTRL_REG_35 = CS1_TRP_ALL(cl) | TWTR(1); - //tRP_ALL = ûÕÒµ½ = tRP, tRP = CL - ddrCTRL_REG_34 = CS0_TRP_ALL(cl) | TRP(cl) | 0x200; - if(MHz <= 100) //tRC = 80ns - { - tmp = (80*MHz/1000) + ((((80*MHz)%1000) > 0) ? 1:0); - } - else //tRC = 75ns - { - tmp = (75*MHz/1000) + ((((75*MHz)%1000) > 0) ? 1:0); - } - //tFAW = ûÓÐÕâ¸öʱ¼ä, tWR = 15ns - tmp = (tmp > 0x3F) ? 0x3F : tmp; - tmp3 = (15*MHz/1000) + ((((15*MHz)%1000) > 0) ? 1:0); - tmp3 = (tmp3 > 0x1F) ? 0x1F : tmp3; - ddrCTRL_REG_38 = TRC(tmp) | TFAW(0) | TWR(tmp3); - if(capability <= 0x2000000) // 128Mb,256Mb - { - // 128Mb,256Mb tRFC=80ns - tmp = (80*MHz/1000) + ((((80*MHz)%1000) > 0) ? 1:0); - tmp = (tmp > 0x1F) ? 0x1F : tmp; - // tMRD = 2 tCK, tDAL = tWR + tRP = 15ns + CL, tCCD = 2 tCK, DDR2: tCKESR=tCKE=3 tCK, mobile DDR: tCKESR=tRFC - tmp2 = (15*MHz/1000) + ((((15*MHz)%1000) > 0) ? 1:0); - tmp2 += cl; - tmp2 = (tmp2 > 0x1F) ? 0x1F : tmp2; - ddrCTRL_REG_37 = TMRD(2) | TDAL(tmp2) | TCKESR(tmp) | TCCD(2); - tmp = (80*MHz/1000) + ((((80*MHz)%1000) > 0) ? 1:0); - tmp = (tmp > 0xFF) ? 0xFF : tmp; - //tXSNR = tRFC + 10ns, tRAS_max = 70000ns - tmp3 = (90*MHz/1000) + ((((90*MHz)%1000) > 0) ? 1:0); - tmp3 = (tmp3 > 0xFFFF) ? 0xFFFF : tmp3; - ddrCTRL_REG_66 = TXSNR(tmp3); - } - else if(capability <= 0x4000000) // 512Mb - { - // 512Mb tRFC=110ns - tmp = (110*MHz/1000) + ((((110*MHz)%1000) > 0) ? 1:0); - tmp = (tmp > 0x1F) ? 0x1F : tmp; - // tMRD = 2 tCK, tDAL = tWR + tRP = 15ns + CL, tCCD = 2 tCK, DDR2: tCKESR=tCKE=3 tCK, mobile DDR: tCKESR=tRFC - tmp2 = (15*MHz/1000) + ((((15*MHz)%1000) > 0) ? 1:0); - tmp2 += cl; - tmp2 = (tmp2 > 0x1F) ? 0x1F : tmp2; - ddrCTRL_REG_37 = TMRD(2) | TDAL(tmp2) | TCKESR(tmp) | TCCD(2); - tmp = (110*MHz/1000) + ((((110*MHz)%1000) > 0) ? 1:0); - tmp = (tmp > 0xFF) ? 0xFF : tmp; - //tXSNR = tRFC + 10ns, tRAS_max = 70000ns - tmp3 = (120*MHz/1000) + ((((120*MHz)%1000) > 0) ? 1:0); - tmp3 = (tmp3 > 0xFFFF) ? 0xFFFF : tmp3; - ddrCTRL_REG_66 = TXSNR(tmp3); - } - else if(capability <= 0x8000000) // 1Gb - { - // 1Gb tRFC=140ns - tmp = (140*MHz/1000) + ((((140*MHz)%1000) > 0) ? 1:0); - tmp = (tmp > 0x1F) ? 0x1F : tmp; - // tMRD = 2 tCK, tDAL = tWR + tRP = 15ns + CL, tCCD = 2 tCK, DDR2: tCKESR=tCKE=3 tCK, mobile DDR: tCKESR=tRFC - tmp2 = (15*MHz/1000) + ((((15*MHz)%1000) > 0) ? 1:0); - tmp2 += cl; - tmp2 = (tmp2 > 0x1F) ? 0x1F : tmp2; - ddrCTRL_REG_37 = TMRD(2) | TDAL(tmp2) | TCKESR(tmp) | TCCD(2); - tmp = (140*MHz/1000) + ((((140*MHz)%1000) > 0) ? 1:0); - tmp = (tmp > 0xFF) ? 0xFF : tmp; - //tXSNR = tRFC + 10ns, tRAS_max = 70000ns - tmp3 = (150*MHz/1000) + ((((150*MHz)%1000) > 0) ? 1:0); - tmp3 = (tmp3 > 0xFFFF) ? 0xFFFF : tmp3; - ddrCTRL_REG_66 = TXSNR(tmp3); - } - else // 4Gb - { - // ´óÓÚ1GbûÕÒµ½£¬°´DDR2µÄ tRFC=328ns - tmp = (328*MHz/1000) + ((((328*MHz)%1000) > 0) ? 1:0); - tmp = (tmp > 0x1F) ? 0x1F : tmp; - // tMRD = 2 tCK, tDAL = tWR + tRP = 15ns + CL, tCCD = 2 tCK, DDR2: tCKESR=tCKE=3 tCK, mobile DDR: tCKESR=tRFC - tmp2 = (15*MHz/1000) + ((((15*MHz)%1000) > 0) ? 1:0); - tmp2 += cl; - tmp2 = (tmp2 > 0x1F) ? 0x1F : tmp2; - ddrCTRL_REG_37 = TMRD(2) | TDAL(tmp2) | TCKESR(tmp) | TCCD(2); - tmp = (328*MHz/1000) + ((((328*MHz)%1000) > 0) ? 1:0); - tmp = (tmp > 0xFF) ? 0xFF : tmp; - //tXSNR = tRFC + 10ns, tRAS_max = 70000ns - tmp3 = (338*MHz/1000) + ((((338*MHz)%1000) > 0) ? 1:0); - tmp3 = (tmp3 > 0xFFFF) ? 0xFFFF : tmp3; - ddrCTRL_REG_66 = TXSNR(tmp3); - } - //tRFC = 80ns(128Mb,256Mb)/110ns(512Mb)/140ns(1Gb), tRCD = CL - if(MHz <= 100) //tRAS_min = 50ns - { - tmp3 = (50*MHz/1000) + ((((50*MHz)%1000) > 0) ? 1:0); - } - else //tRAS_min = 45ns - { - tmp3 = (45*MHz/1000) + ((((45*MHz)%1000) > 0) ? 1:0); - } - tmp3 = (tmp3 > 0xFF) ? 0xFF : tmp3; - ddrCTRL_REG_44 = TRFC(tmp) | TRCD(cl) | TRAS_MIN(tmp3); - //tPDEX=ûÕÒµ½£¬Ó¦¸ÃµÈÓÚ=tXP=25ns - tmp = (25*MHz/1000) + ((((25*MHz)%1000) > 0) ? 1:0); - tmp = (tmp > 0xFFFF) ? 0xFFFF : tmp; - ddrCTRL_REG_65 = TPDEX(tmp) | TDLL(200); - // tRRD = 15ns, tCKE = 2 tCK - tmp2 = (15*MHz/1000) + ((((15*MHz)%1000) > 0) ? 1:0); - tmp2 = (tmp2 > 7) ? 7 : tmp2; - tmp = (tmp <= 1) ? 2 : (tmp + 1); - tmp = (tmp > 7) ? 7 : tmp; - ddrCTRL_REG_23 = TRRD(tmp2) | TCKE(tmp) | 0x2; - //tXSR = 200 ns - tmp = (200*MHz/1000) + ((((200*MHz)%1000) > 0) ? 1:0); - tmp = (tmp > 0xFFFF) ? 0xFFFF : tmp; - ddrCTRL_REG_67 = TXSR(tmp); - } - //tCPD = 400ns - tmp = (400*MHz/1000) + ((((400*MHz)%1000) > 0) ? 1:0); - tmp = (tmp > 0xFFFF) ? 0xFFFF : tmp; - ddrCTRL_REG_64 = TCPD(tmp) | MODE3_CNT(0x1FF); - //tINIT = 200us - tmp = (200000*MHz/1000) + ((((200000*MHz)%1000) > 0) ? 1:0); - tmp = (tmp > 0xFFFFFF) ? 0xFFFFFF : tmp; - ddrCTRL_REG_68 = TINIT(tmp); -} - -static void __tcmfunc DDRUpdateTiming(void) -{ - uint32 value; - value = pDDR_Reg->CTRL_REG_35; - value &= ~(0xF0F); - pDDR_Reg->CTRL_REG_35 = value | ddrCTRL_REG_35; - pDDR_Reg->CTRL_REG_23 = ddrCTRL_REG_23; - pDDR_Reg->CTRL_REG_24 = ddrCTRL_REG_24; - pDDR_Reg->CTRL_REG_37 = ddrCTRL_REG_37; - pDDR_Reg->CTRL_REG_34 = ddrCTRL_REG_34; - pDDR_Reg->CTRL_REG_38 = ddrCTRL_REG_38; - pDDR_Reg->CTRL_REG_44 = ddrCTRL_REG_44; - pDDR_Reg->CTRL_REG_64 = ddrCTRL_REG_64; - pDDR_Reg->CTRL_REG_65 = ddrCTRL_REG_65; - value = pDDR_Reg->CTRL_REG_66; - value &= ~(0xFFFF0000); - pDDR_Reg->CTRL_REG_66 = ddrCTRL_REG_66 | value; - pDDR_Reg->CTRL_REG_67 = ddrCTRL_REG_67; - pDDR_Reg->CTRL_REG_68 = ddrCTRL_REG_68; -} - -/* we avoid to use stack and global var. six instr in one cycle.*/ -#if 0 -volatile uint32 __tcmdata for_ddr_delay; -void __tcmfunc ddr_pll_delay( int loops ) -{ - for_ddr_delay = loops; - for( ; for_ddr_delay > 0 ; for_ddr_delay-- ){ - ; - } -} -#else -asm( -" .section \".tcm.text\",\"ax\"\n" -" .align\n" -" .type ddr_pll_delay, #function\n" -" .global ddr_pll_delay\n" -"ddr_pll_delay:\n" -" cmp r0,#0\n" -" movle pc , lr\n" -"1: sub r0,r0,#1\n" -" mov r1,r1\n" -" mov r1,r1\n" -" mov r1,r1\n" -" mov r2,r2\n" -" mov r2,r2\n" -" cmp r0,#0\n" -" bgt 1b\n" -" mov pc,lr\n" -" .previous" -); -#endif -/****************************************************************/ -//º¯ÊýÃû:SDRAM_BeforeUpdateFreq -//ÃèÊö:µ÷ÕûSDRAM/DDRƵÂÊÇ°µ÷Óõĺ¯Êý£¬ÓÃÓÚµ÷ÕûSDRAM/DDRʱÐò²ÎÊý -//²ÎÊý˵Ã÷:SDRAMnewKHz ÊäÈë²ÎÊý SDRAM½«Òªµ÷Õûµ½µÄƵÂÊ£¬µ¥Î»KHz -// DDRnewKHz ÊäÈë²ÎÊý DDR½«Òªµ÷Õûµ½µÄƵÂÊ£¬µ¥Î»KHz -//·µ»ØÖµ: -//Ïà¹ØÈ«¾Ö±äÁ¿: -//×¢Òâ:Õâ¸öº¯ÊýÖ»ÐÞ¸ÄMSDR_STMG0R£¬MSDR_SREFR£¬MSDR_SCTLRµÄÖµ -/****************************************************************/ -static void __tcmfunc SDRAM_BeforeUpdateFreq(uint32 SDRAMnewKHz, uint32 DDRnewMHz) -{ - uint32 MHz; - uint32 memType = DDR_MEM_TYPE();// (pGRF_Reg->CPU_APB_REG0) & MEMTYPEMASK; - uint32 tmp; - uint32 cl; - volatile uint32 *p_ddr = (volatile uint32 *)0xc0080000; - //uint32 *ddr_reg = 0xff401c00; - ddr_reg[0] = pGRF_Reg->CPU_APB_REG0; - ddr_reg[1] = pGRF_Reg->CPU_APB_REG1; - - - ddr_reg[4] = pDDR_Reg->CTRL_REG_10; - - ddr_reg[6] = pDDR_Reg->CTRL_REG_78; - switch(memType) - { - case Mobile_SDRAM: - case SDRAM: - printk("%s:erroe memtype=0x%x\n" ,__func__, memType); - #if 0 - KHz = PLLGetAHBFreq(); - if(KHz < SDRAMnewKHz) //ÉýƵ - { - SDRAMUpdateTiming(SDRAMnewKHz); - bFreqRaise = 1; - } - else //½µÆµ - { - SDRAMUpdateRef(SDRAMnewKHz); - bFreqRaise = 0; - } - #endif - break; - case DDRII: - case Mobile_DDR: - MHz = PLLGetDDRFreq(); - if(telement) - { - elementCnt = 250000/(DDRnewMHz*telement); - if(elementCnt > 156) - { - elementCnt = 156; - } - } - else - { - elementCnt = 2778/DDRnewMHz; // 90psËã - if(elementCnt > 156) - { - elementCnt = 156; - } - } - DDRPreUpdateRef(DDRnewMHz); - DDRPreUpdateTiming(DDRnewMHz); - - while(pGRF_Reg->CPU_APB_REG1 & 0x100); - tmp = *p_ddr; //read to wakeup - pDDR_Reg->CTRL_REG_36 &= ~(0x1F << 8); - while(pDDR_Reg->CTRL_REG_03 & 0x100) - { - tmp = *p_ddr; //read to wakeup - } - while(pGRF_Reg->CPU_APB_REG1 & 0x100); - printk("%s::just befor ddr refresh.ahb=%d,new ddr=%d\n" , __func__ , SDRAMnewKHz , DDRnewMHz); - //WAIT_ME(); - if(memType == DDRII) - { - cl = GetDDRCL(DDRnewMHz); - pDDR_Reg->CTRL_REG_00 |= (0x1 << 16); //refresh to close all bank - ddr_pll_delay(10); - //set mode register cl - pDDR_Reg->CTRL_REG_51 = (pDDR_Reg->CTRL_REG_51 & (~(0x7FFF << 16))) | (((cl << 4) | ((cl -1) << 9) | 0x2) << 16); - pDDR_Reg->CTRL_REG_52 = (((cl << 4) | ((cl -1) << 9) | 0x2)) | ((0x1 << 6) << 16); - pDDR_Reg->CTRL_REG_53 = (0x1 << 6); - pDDR_Reg->CTRL_REG_11 |= (0x1 << 16); - //set controller register cl - pDDR_Reg->CTRL_REG_20 = (pDDR_Reg->CTRL_REG_20 & (~(0x7 << 16))) | (cl << 16); - pDDR_Reg->CTRL_REG_29 = (pDDR_Reg->CTRL_REG_29 & (~(0xF << 24))) | ((cl << 1) << 24); - pDDR_Reg->CTRL_REG_30 = (pDDR_Reg->CTRL_REG_30 & (~0xF)) | (cl << 1); - pDDR_Reg->CTRL_REG_32 = (pDDR_Reg->CTRL_REG_32 & (~(0xF << 8))) | (cl << 8); - pDDR_Reg->CTRL_REG_35 = (pDDR_Reg->CTRL_REG_35 & (~(0xF0F << 16))) | ((cl - 1) << 16) | ((cl-1) << 24); - } - pDDR_Reg->CTRL_REG_09 |= (0x1 << 24); // after this on,ddr enter refresh,no access valid!! - //WAIT_ME(); - while(!(pDDR_Reg->CTRL_REG_03 & 0x100)); - pDDR_Reg->CTRL_REG_10 &= ~(0x1); - if(MHz < DDRnewMHz) //ÉýƵ - { - DDRUpdateTiming(); - bFreqRaise = 1; - } - else //½µÆµ - { - DDRUpdateRef(); - bFreqRaise = 0; - } - break; - } -} - -/****************************************************************/ -//º¯ÊýÃû:SDRAM_AfterUpdateFreq -//ÃèÊö:SDRAM/DDRƵÂʵ÷Õûºó£¬µ÷ÓÃÕâ¸öº¯Êý£¬Íê³Éµ÷ƵºóµÄÉƺó¹¤×÷ -//²ÎÊý˵Ã÷:SDRAMoldKHz ÊäÈë²ÎÊý SDRAMµ÷ÕûÇ°µÄƵÂÊ£¬µ¥Î»KHz -// DDRoldKHz ÊäÈë²ÎÊý SDRAMµ÷ÕûÇ°µÄƵÂÊ£¬µ¥Î»KHz -//·µ»ØÖµ: -//Ïà¹ØÈ«¾Ö±äÁ¿: -//×¢Òâ:Õâ¸öº¯ÊýÖ»ÐÞ¸ÄMSDR_STMG0R£¬MSDR_SREFR£¬MSDR_SCTLRµÄÖµ -/****************************************************************/ - -static void __tcmfunc SDRAM_AfterUpdateFreq(uint32 SDRAMoldKHz, uint32 DDRnewMHz) -{ - uint32 value =0; - //uint32 tmp = 0; - uint32 ddrMHz; - //uint32 ahbKHz; - uint32 memType = DDR_MEM_TYPE();// (pGRF_Reg->CPU_APB_REG0) & MEMTYPEMASK; - DDR_debug_string("21\n"); - switch(memType) - { - case Mobile_SDRAM: - case SDRAM: - printk("%s:erroe memtype=0x%x\n" ,__func__, memType); - #if 0 - // ahbKHz = PLLGetAHBFreq(); - if(ahbKHz > SDRAMoldKHz) //ÉýƵ - { - // SDRAMUpdateRef(ahbKHz); - } - else //½µÆµ - { - // SDRAMUpdateTiming(ahbKHz); - } - #endif - break; - case DDRII: - case Mobile_DDR: - if(bFreqRaise) //ÉýƵ - { - DDRUpdateRef(); - } - else //½µÆµ - { - DDRUpdateTiming(); - } - ddrMHz = DDRnewMHz; - pDDR_Reg->CTRL_REG_10 |= 0x1; - value = 1000; - while(value) - { - if(pDDR_Reg->CTRL_REG_04 & 0x100) - { - break; - } - value--; - } - if(!(value)) - { - DLLBypass(); - pDDR_Reg->CTRL_REG_10 |= 0x1; - while(!(pDDR_Reg->CTRL_REG_04 & 0x100)); - } - pDDR_Reg->CTRL_REG_09 &= ~(0x1 << 24); - while(pDDR_Reg->CTRL_REG_03 & 0x100); // exit - // printk("exit ddr refresh,"); - //Í˳ö×Ôˢкó£¬ÔÙËãelementµÄÖµ - //ddrKHz = PLLGetDDRFreq(); - ddrMHz = DDRnewMHz; - //printk("new ddr kHz=%ld\n" , ddrKHz); - if(110 < ddrMHz) - { - value = pDDR_Reg->CTRL_REG_78; - if(value & 0x1) - { - value = value >> 1; - if( value == 0 ){ - S_WARN("%s::value = 0!\n" , __func__ ); - } else - telement = 1000000/(ddrMHz*value); - } - } - // 20100714,HSL@RK,use DDR_ENABLE_SLEEP instead!! - //pDDR_Reg->CTRL_REG_36 = (0x1F1F); // 20100608,YK@RK. - DDR_ENABLE_SLEEP(); - break; - } -} - -static void __tcmfunc ddr_put_char( char c ) -{ - pUART_Reg->UART_RBR = c; - pUART_Reg->UART_RBR = 0x0d; - ddr_pll_delay( 800 ); -} - -asm( -" .section \".tcm.text\",\"ax\"\n" -" .align\n" -" .type ddr_save_sp, #function\n" -" .global ddr_save_sp\n" -"ddr_save_sp:\n" -" mov r1,sp\n" -" mov sp,r0\n" -" mov r0,r1\n" -" mov pc,lr\n" -" .previous" -); -/*SCU PLL CON , 20100518,copy from rk28_scu_hw.c -*/ -#define PLL_TEST (0x01u<<25) -#define PLL_SAT (0x01u<<24) -#define PLL_FAST (0x01u<<23) -#define PLL_PD (0x01u<<22) -#define PLL_CLKR(i) (((i)&0x3f)<<16) -#define PLL_CLKF(i) (((i)&0x0fff)<<4) -#define PLL_CLKOD(i) (((i)&0x07)<<1) -#define PLL_BYPASS (0X01) - -#define DDR_CLK_NORMAL 300 -#define DDR_CLK_LOWPW 128 -/* 20100609,HSL@RK, dtcm --> sram,when dsp close,sram clk will be close,so - * we use itcm as tmp stack. -*/ - -/**************************************************************** -* º¯ÊýÃû:disable_DDR_Sleep -* ÃèÊö:½ûÖ¹×Ô¶¯sleepģʽ -* ²ÎÊý˵Ã÷: -* ·µ»ØÖµ: -* Ïà¹ØÈ«¾Ö±äÁ¿: -****************************************************************/ -static void __tcmfunc disable_DDR_Sleep(void) -{ - volatile uint32 *p_ddr = (volatile uint32 *)0xc0080000; - unsigned int tmp; - while(pGRF_Reg->CPU_APB_REG1 & 0x100); - tmp = *p_ddr; //read to wakeup - pDDR_Reg->CTRL_REG_36 &= ~(0x1F << 8); - while(pDDR_Reg->CTRL_REG_03 & 0x100) - { - tmp = *p_ddr; //read to wakeup - } - while(pGRF_Reg->CPU_APB_REG1 & 0x100); -} - -/****************************************************************/ -//º¯ÊýÃû:SDRAM_EnterSelfRefresh -//ÃèÊö:SDRAM½øÈë×ÔË¢ÐÂģʽ -//²ÎÊý˵Ã÷: -//·µ»ØÖµ: -//Ïà¹ØÈ«¾Ö±äÁ¿: -//×¢Òâ:(1)ϵͳÍêÈ«idleºó²ÅÄܽøÈë×ÔË¢ÐÂģʽ£¬½øÈë×Ôˢкó²»ÄÜÔÙ·ÃÎÊSDRAM -// (2)Òª½øÈë×ÔË¢ÐÂģʽ£¬±ØÐë±£Ö¤ÔËÐÐʱÕâ¸öº¯ÊýËùµ÷Óõ½µÄËùÓдúÂë²»ÔÚSDRAMÉÏ -/****************************************************************/ -static void __tcmfunc rk28_ddr_enter_self_refresh(void) -{ - uint32 memType = DDR_MEM_TYPE(); - - switch(memType) - { - case DDRII: - case Mobile_DDR: - disable_DDR_Sleep(); - pDDR_Reg->CTRL_REG_62 = (pDDR_Reg->CTRL_REG_62 & - (~(0xFFFF<<16))) | MODE5_CNT(0x1); - DDR_ENABLE_SLEEP(); - ddr_pll_delay( 100 ); - pSCU_Reg->SCU_CLKGATE1_CON |= 0x00c00001; - ddr_pll_delay( 10 ); - pSCU_Reg->SCU_CPLL_CON |= ((1<<22)|1); - ddr_pll_delay( 10 ); - break; - default: - break; - } -} - -/****************************************************************/ -//º¯ÊýÃû:SDRAM_ExitSelfRefresh -//ÃèÊö:SDRAMÍ˳ö×ÔË¢ÐÂģʽ -//²ÎÊý˵Ã÷: -//·µ»ØÖµ: -//Ïà¹ØÈ«¾Ö±äÁ¿: -//×¢Òâ:(1)SDRAMÔÚ×ÔË¢ÐÂģʽºó²»Äܱ»·ÃÎÊ£¬±ØÐëÏÈÍ˳ö×ÔË¢ÐÂģʽ -// (2)±ØÐë±£Ö¤ÔËÐÐʱÕâ¸öº¯ÊýµÄ´úÂë²»ÔÚSDRAMÉÏ -/****************************************************************/ -static void __tcmfunc rk28_ddr_exit_self_refresh(void) -{ - uint32 memType = DDR_MEM_TYPE(); - - switch(memType) - { - case DDRII: - case Mobile_DDR: - pSCU_Reg->SCU_CPLL_CON &= ~((1<<22)|1); - ddr_pll_delay( 3000 ); - pSCU_Reg->SCU_CLKGATE1_CON &= ~0x00c00000; - ddr_pll_delay( 100 ); - - disable_DDR_Sleep(); - #if 1 // scrn failed - pDDR_Reg->CTRL_REG_62 = (pDDR_Reg->CTRL_REG_62 & (~(0xFFFF<<16)) - )| MODE5_CNT(0x64); - #else - pDDR_Reg->CTRL_REG_62 = (pDDR_Reg->CTRL_REG_62 & (~(0xFFFF<<16)) - )| MODE5_CNT(0xFFFF); - #endif - DDR_ENABLE_SLEEP(); - ddr_pll_delay( 1000 ); - break; - default: - break; - } - -} - -static uint32 scu_clk_gate[3]; -static uint32 scu_pmu_con; - -static void scu_reg_save(void) -{ - // bit 31: 1.1host phy. bit 2: 2.0host. - //pGRF_Reg->OTGPHY_CON1 = 0x80000004; - pGRF_Reg->OTGPHY_CON1 |= 0x80000000; - scu_clk_gate[0] = pSCU_Reg->SCU_CLKGATE0_CON; - scu_clk_gate[1] = pSCU_Reg->SCU_CLKGATE1_CON; - scu_clk_gate[2] = pSCU_Reg->SCU_CLKGATE2_CON; - // open uart0,1(bit 18,19,for debug), open gpio0,1(bit16,17) and arm,arm core. - // XXX:open pwm(bit24) for ctrl vdd core??. - // open timer (bit 25) for usb detect and mono timer. - // open sdmmc0 clk for wakeup. - pSCU_Reg->SCU_CLKGATE0_CON = 0xfdf0bff6; //0xfefcfff6 ;// arm core clock - // - pSCU_Reg->SCU_CLKGATE1_CON = 0xff3f8001; //sdram clock 0xe7fff - pSCU_Reg->SCU_CLKGATE2_CON = 0x24; //ahb, apb clock - - scu_pmu_con = pSCU_Reg->SCU_PMU_CON; - - // XXX:close LCDC power domain(bit 3) need to reset lcdc ctrl regs when wake up. - // about 1ma vdd core. - //pSCU_Reg->SCU_PMU_CON = 0x09;//power down lcdc & dsp power domain - pSCU_Reg->SCU_PMU_CON = 0x01;//power downdsp power domain -} -static void scu_reg_restore(void) -{ - pSCU_Reg->SCU_PMU_CON = scu_pmu_con;//power down lcdc & dsp power domain - - pSCU_Reg->SCU_CLKGATE0_CON = scu_clk_gate[0]; - pSCU_Reg->SCU_CLKGATE1_CON = scu_clk_gate[1]; - pSCU_Reg->SCU_CLKGATE2_CON = scu_clk_gate[2]; - -} - -#if 1 // 20100702,HSL@RK,PUT at SCU. -static void __tcmfunc ddr_change_freq( int freq_MHZ ) -{ - int arm_clk = 540*1000; //KHZ - uint32 DDRnewMHz = freq_MHZ; - //printk("%s::ahb clk=%d KHZ\n",__func__ , ahb ); - SDRAM_BeforeUpdateFreq( arm_clk, DDRnewMHz); - pSCU_Reg->SCU_CLKSEL1_CON &= ~(0X03); - if( freq_MHZ >= 200 ) { - pSCU_Reg->SCU_CPLL_CON = PLL_SAT|PLL_FAST - |(PLL_CLKR(6-1))|(PLL_CLKF(freq_MHZ/4-1)); - } else { - pSCU_Reg->SCU_CPLL_CON = PLL_SAT|PLL_FAST - |(PLL_CLKR(6-1))|(PLL_CLKF(freq_MHZ/2-1)) - |(PLL_CLKOD(2 - 1)); - } - ddr_pll_delay( arm_clk ); - pSCU_Reg->SCU_CLKSEL1_CON |= 0X01; - SDRAM_AfterUpdateFreq( arm_clk, DDRnewMHz); -} -void change_ddr_freq(int freq_MHZ) -{ - -#if 0 - g_intcReg->FIQ_INTEN &= 0x0; - g_intcReg->IRQ_INTEN_H &= 0x0; - g_intcReg->IRQ_INTEN_L &= 0x0; - g_intcReg->IRQ_INTMASK_L &= 0x0; - g_intcReg->IRQ_INTMASK_H &= 0x0; -#endif -#if 0 - uint32 i; - uint32 *p; - for(i=0;i<93; i++) - { - p = (uint32 *)(DDR_REG_BASE + (4*i)); - printk("DDR Reg[%d]=0x%x\n", i, *p); - } -#endif - - unsigned long flags; - local_irq_save(flags); - DDR_SAVE_SP; - ddr_change_freq( freq_MHZ ); // DDR CLK! - DDR_RESTORE_SP; - local_irq_restore(flags); -} -#else -#define change_ddr_freq( mhz ) -#endif - -/* change ddr to mode :1:performance , 0:power save*/ -/* 20100909,HSL@RK,exchange performance and power save */ -void ddr_change_mode( int performance ) -{ - if( performance ){ - pDDR_Reg->CTRL_REG_63 = 0x0000ffff; - } else { - pDDR_Reg->CTRL_REG_63 = 200 ; // 0x64; - } -} - - -/****************************************************************/ -//º¯ÊýÃû:SDRAM_Init -//ÃèÊö:SDRAM³õʼ»¯ -//²ÎÊý˵Ã÷: -//·µ»ØÖµ: -//Ïà¹ØÈ«¾Ö±äÁ¿: -//×¢Òâ: -/****************************************************************/ -static void SDRAM_DDR_Init(void) -{ - uint32 value; - uint32 MHz; - uint32 memType = DDR_MEM_TYPE();// (pGRF_Reg->CPU_APB_REG0) & MEMTYPEMASK; - - telement = 0; - if(memType != DDRII) - { - pDDR_Reg->CTRL_REG_11 = 0x101; - } - /* 20100609,HSL@RK,disable ddr interrupt .*/ - pDDR_Reg->CTRL_REG_45 = 0x07ff03ff; - //tPDEX=ûÕÒµ½£¬Ó¦¸ÃµÈÓÚ=tXP=25ns -#if 1 // scrn failed - pDDR_Reg->CTRL_REG_63 = 0x64; - pDDR_Reg->CTRL_REG_62 = 0x00100008; - //pDDR_Reg->CTRL_REG_36 = 0x1f1f; // use DDR_ENABLE_SLEEP instead!! -#else - pDDR_Reg->CTRL_REG_63 &= 0x0000ffff; // scrn ok -#endif - //¶Á²Ù×÷ʱ¶Ë¿ÚÓÅÏȼ¶ÊÇ:LCDC(port 2) > CEVA(port 6) > VIDEO(port 7) > ARMI(port 5) > ARMD(port 4) > EXP(port3) - //д²Ù×÷ʱ¶Ë¿ÚÓÅÏȼ¶ÊÇ:CEVA(port 6) > ARMD(port 4) > EXP(port3) > LCDC(port 2) > VIDEO(port 7) > ARMI(port 5) - pDDR_Reg->CTRL_REG_13 = (AXI_MC_ASYNC << 8) | LCDC_WR_PRIO(3) | LCDC_RD_PRIO(0); - pDDR_Reg->CTRL_REG_14 = (AXI_MC_ASYNC << 24) | (AXI_MC_ASYNC) | EXP_WR_PRIO(2) | EXP_RD_PRIO(3); - pDDR_Reg->CTRL_REG_15 = (AXI_MC_ASYNC << 16) | ARMD_WR_PRIO(1) | ARMD_RD_PRIO(3) | ARMI_RD_PRIO(3); - pDDR_Reg->CTRL_REG_16 = (AXI_MC_ASYNC << 8) | CEVA_WR_PRIO(0) | CEVA_RD_PRIO(1) | ARMI_WR_PRIO(3); - value = pDDR_Reg->CTRL_REG_17; - value &= ~(0x3FFFF); - value |= (AXI_MC_ASYNC) | VIDEO_RD_PRIO(2) | VIDEO_WR_PRIO(3); - pDDR_Reg->CTRL_REG_17 = value; - capability = (0x1 << ((0x2 >> ((pDDR_Reg->CTRL_REG_08 >> 16) & 0x1)) //bus width - + (13 - (pDDR_Reg->CTRL_REG_21 & 0x7)) //col - + (2 + ((pDDR_Reg->CTRL_REG_05 >> 8) & 0x1)) //bank - + (15 - ((pDDR_Reg->CTRL_REG_19 >> 24) & 0x7)))); //row - if(((pDDR_Reg->CTRL_REG_17 >> 24) & 0x3) == 0x3) - { - if(capability < (0x1 << ((0x2 >> ((pDDR_Reg->CTRL_REG_08 >> 16) & 0x1)) //bus width - + (13 - ((pDDR_Reg->CTRL_REG_21 >> 8) & 0x7)) //col - + (2 + ((pDDR_Reg->CTRL_REG_05 >> 16) & 0x1)) //bank - + (15 - (pDDR_Reg->CTRL_REG_20 & 0x7))))) //row - { - capability = (0x1 << ((0x2 >> ((pDDR_Reg->CTRL_REG_08 >> 16) & 0x1)) //bus width - + (13 - ((pDDR_Reg->CTRL_REG_21 >> 8) & 0x7)) //col - + (2 + ((pDDR_Reg->CTRL_REG_05 >> 16) & 0x1)) //bank - + (15 - (pDDR_Reg->CTRL_REG_20 & 0x7)))); //row - } - } - MHz = PLLGetDDRFreq(); - printk("PLLGetDDRFreq=%d MHZ\n" , MHz); - if(110 > MHz) - { - if(telement) - { - elementCnt = 250000/(MHz*telement); - if(elementCnt > 156) - { - elementCnt = 156; - } - } - else - { - elementCnt = 2778/MHz; // 90psËã - if(elementCnt > 156) - { - elementCnt = 156; - } - } - DLLBypass(); - } - else - { - value = pDDR_Reg->CTRL_REG_78; - if(value & 0x1) - { - value = value >> 1; - telement = 1000000/(MHz*value); - } - } - DDRPreUpdateRef(MHz); - DDRPreUpdateTiming(MHz); - DDRUpdateRef(); - DDRUpdateTiming(); - DDR_ENABLE_SLEEP(); - - { - unsigned long flags; - local_irq_save(flags); - ddr_change_freq( memType == DDRII ? 300 : 168 ); // DDR CLK! - local_irq_restore(flags); - } -} - -#if 1 // 20100713,test funciton . -/* reg: 0..159, v: reg value */ -int rk28_read_ddr( int reg ) -{ - volatile uint32 *reg0 = (volatile uint32 *)(SDRAMC_BASE_ADDR_VA); - printk("reg%d=0x%lx\n" ,reg , *(reg0+reg)); - return reg; -} - -int rk28_write_ddr( int reg , unsigned int v ) -{ - unsigned long flags; - volatile uint32 *reg0 = (volatile uint32 *)(SDRAMC_BASE_ADDR_VA); - local_irq_save(flags); - *(reg0+reg) = v ; - local_irq_restore(flags); - printk("set reg%d=0x%x\n",reg , v ); - return reg; -} -#endif -extern void __rk28_halt_here( void ); -static void __tcmlocalfunc rk28_do_halt( void ) -{ - ddr_put_char('$'); // close uart clk ,can not print. - scu_reg_save(); - ddr_disabled = 1; - rk28_ddr_enter_self_refresh(); // and close ddr clk.codec pll. - rk28_change_vdd( VDD_095 ); // not change vdd for test. - ddr_put_char('%'); // close uart clk ,can not print. - __rk28_halt_here(); - ddr_put_char('&'); - //rk28_change_vdd( VDD_110 ); // use tow step to raise vdd for impact. - //ddr_pll_delay( 4000*10 ); // 6 instr. 24M. 4000 for 1 ms.total 10 ms. - rk28_change_vdd( VDD_125 ); // set vdd120 here for write ddr ctrl reg. - ddr_pll_delay( 4000*10 ); // 6 instr. 24M. 4000 for 1 ms.total 10 ms. - rk28_ddr_exit_self_refresh(); // and open codec pll. - scu_reg_restore(); - ddr_disabled = 0; - ddr_put_char('@'); -} -void __tcmfunc rk28_halt_at_tcm( void ) -{ - flush_cache_all(); // 20100615,HSL@RK. - __cpuc_flush_user_all(); - DDR_SAVE_SP; - rk28_do_halt(); - DDR_RESTORE_SP; -} - -static void __tcmlocalfunc rk2818_reduce_armfrq(void) -{ -#define pSCU_Reg ((pSCU_REG)SCU_BASE_ADDR_VA) -#define ARM_FRQ_48MHz 0x018502F6 -#define ARM_PLL_PWD (0x1<<22) - pSCU_Reg->SCU_MODE_CON &= (~(0x3<<2)); // arm slow mod - udelay(100); - pSCU_Reg->SCU_CLKSEL0_CON &= (~(0xf<<0)); //arm:ahb:apb=1:1:1 - udelay(100); - pSCU_Reg->SCU_APLL_CON = ARM_FRQ_48MHz; - udelay(100); - pSCU_Reg->SCU_APLL_CON |=ARM_PLL_PWD; - udelay(100); -} -static void __tcmfunc rk281x_reboot( void ) -{ - uint32 i; - uint32 *p; -#define pSCU_Reg ((pSCU_REG)SCU_BASE_ADDR_VA) -#define g_intcReg ((pINTC_REG)(INTC_BASE_ADDR_VA)) -#if 0 - g_intcReg->FIQ_INTEN &= 0x0; - g_intcReg->IRQ_INTEN_H &= 0x0; - g_intcReg->IRQ_INTEN_L &= 0x0; - g_intcReg->IRQ_INTMASK_L &= 0x0; - g_intcReg->IRQ_INTMASK_H &= 0x0; -#endif - //rk2818_reduce_armfrq(); - //printk("disable DDR sleep!!!\n"); - //disable_DDR_Sleep(); - printk("start reboot!!!\n"); - #if 0 - for(i=0;i<93; i++) - { - p = (uint32 *)(DDR_REG_BASE + (4*i)); - printk("DDR Reg[%d]=0x%x\n", i, *p); - } - #else - //WAIT_ME(); - #endif - asm( - "ldr r6,=0x18018000 @ get scu reg base first.\n" - "ldr r7,=0x10002FF8 @load sram for stack.\n" - "mov r0,#0\n" - "MCR p15, 0, r0, c7, c7, 0 @flush I-cache & D-cache\n" - "MRC p15,0,r0,c1,c0,0\n" - "BIC r0,r0,#(1<<2) @ disable Dcache \n" - "BIC r0,r0,#(1<<12) @ disable Icache \n" - "MCR p15,0,r0,c1,c0,0\n" - - "MRC p15,0,r0,c1,c0,0\n" - "BIC r0,r0,#(1<<0) @disable mmu\n" - "BIC r0,r0,#(1<<13) @set vector to 0x00000000\n" - "MCR p15,0,r0,c1,c0,0\n" - "mov r1,r1\n" - "mov r1,r1\n" - "mov r1,r1\n" - - "mov sp , r7\n" // set SP for call other functions at itcm. - // print char '0' - //"mov r0,#0x30\n" - //"bl ddr_put_char\n" - - //"ldr r2,=0x18018000 @ enable sram arm dsp clock\n" - //"mov r2,r6\n" - "ldr r3,[r6,#0x1c]\n" - "bic r3,r3,#(1<<3)\n" - "bic r3,r3,#(1<<4)\n" - "str r3,[r6,#0x1c]\n" - - - // print char 'A' - //"mov r0,#0x41\n" - //"bl ddr_put_char\n" - - "ldr r3,[r6,#0x1c] @ITCM not map to address 0, it is right in linux system\n" - "bic r3,r3,#(1<<15) @maskrom clock enable\n" - "bic r3,r3,#(1<<8) @nandc clock enable\n" - "bic r3,r3,#(1<<22) @spi0 clock enable\n" - "bic r3,r3,#(1<<18) @uart0 clock enable\n" - "bic r3,r3,#(1<<6) @usb clock enable\n" - "bic r3,r3,#(1<<7)\n" - "bic r3,r3,#(1<<9) @intc clock enable\n" - "bic r3,r3,#(1<<5) @hif clock enable\n" - "str r3,[r6,#0x1c]\n" - - // print char '1' - //"mov r0,#0x31\n" - //"bl ddr_put_char\n" - - "ldr r2,=0x10040804 @usb soft disconnect.\n" - " mov r3,#2\n" - "str r3,[r2,#0]\n" - - "ldr r2,=0x100AE00C @ BCH reset.\n" - " mov r3,#1\n" - "str r3,[r2,#0]\n" - - "ldr r3,[r6,#0x14] @ARM:AHB=1:1, AHB:APB=2:1\n" - "bic r3,r3,#0xF\n" - "orr r3,r3,#0x4\n" - "str r3,[r6,#0x14]\n" - - // print char 'B' - //"mov r0,#0x42\n" - //"bl ddr_put_char\n" - - "ldr r3,[r6,#0x28] @reset nandc\n" - "orr r3,r3,#(1<<3)\n" - "orr r3,r3,#(1<<0)\n" - "orr r3,r3,#(1<<11)\n" - "orr r3,r3,#(1<<12)\n" - //"orr r3,r3,#(1<<14) @reset uart1\n" - "orr r3,r3,#(1<<15)\n" - "str r3,[r6,#0x28]\n" - - "mov r0,#1000\n" - "bl ddr_pll_delay\n" - - //"ldr r2,=0x18018000\n" - "ldr r3,[r6,#0x28]\n" - "bic r3,r3,#(1<<3)\n" - "bic r3,r3,#(1<<0)\n" - "bic r3,r3,#(1<<11)\n" - "bic r3,r3,#(1<<12)\n" - "bic r3,r3,#(1<<14)\n" - "bic r3,r3,#(1<<15)\n" - "str r3,[r6,#0x28]\n" - - "mov r0,#100\n" - "bl ddr_pll_delay\n" - - // print char '2' - //"mov r0,#0x32\n" - //"bl ddr_put_char\n" - - //"ldr r2,=0x18018000\n" - "ldr r3,[r6,#0x18] @uart0 use 24MHz clock\n" - "bic r3,r3,#(1<<31)\n" - "str r3,[r6,#0x18]\n" - - "ldr r6,=0x18019000 @ DisableRemap\n" - "ldr r3,[r6,#0x14]\n" - "bic r3,r3,#(1<<0)\n" - "bic r3,r3,#(1<<1)\n" - "str r3,[r6,#0x14]\n" - - "ldr r3,[r6,#0x10] @hif interface enable\n" - "orr r3,r3,#(1<<27)\n" - "str r3,[r6,#0x10]\n" - - // print char '3' - //"mov r0,#0x33\n" - //"bl ddr_put_char\n" - -#if 0 - "ldr r2,=0x18009000 @rk2818_reduce_corevoltage\n" - "ldr r3,[r2,#0x24]\n" - "bic r3,#(1<<6)\n" - "str r3,[r2,#0x24]\n" - "ldr r3,[r2,#0x28]\n" - "bic r3,#(1<<6)\n" - "str r3,[r2,#0x28]\n" - #endif - "mov r12,#0\n" - "mov pc ,r12\n" - ); -} - -void(*rk2818_reboot)(void )= (void(*)(void ))rk281x_reboot; -static int __init update_frq(void) -{ - int chip_type; /*xxm*/ - //printk(">>>>>%s-->%d\n",__FUNCTION__,__LINE__); - int *reg = (int *)(SCU_BASE_ADDR_VA); - #if 0 - ddr_reg[0] = pGRF_Reg->CPU_APB_REG0; - ddr_reg[1] = pGRF_Reg->CPU_APB_REG1; - ddr_reg[2] = pDDR_Reg->CTRL_REG_03; - ddr_reg[3] = pDDR_Reg->CTRL_REG_09; - ddr_reg[4] = pDDR_Reg->CTRL_REG_10; - ddr_reg[5] = pDDR_Reg->CTRL_REG_36; - ddr_reg[6] = pDDR_Reg->CTRL_REG_78; - printk(" before 0x%08x 0x%08x 0x%08x 0x%08x\n" - "0x%08x 0x%08x 0x%08x \n" - // "0x%08x 0x%08x 0x%08x 0x%08x\n" , - ,ddr_reg[0],ddr_reg[1],ddr_reg[2],ddr_reg[3], - ddr_reg[4],ddr_reg[5],ddr_reg[6]); - #endif - //local_irq_disable(); - //printk("wait for jtag...\n"); - //WAIT_ME(); - /*xxm*/ - rockchip_mux_api_set(GPIOG_MMC1_SEL_NAME,IOMUXA_GPIO1_C237); -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 32)) - GPIOSetPinLevel(GPIOPortG_Pin7,GPIO_HIGH); - while(!(chip_type = GPIOGetPinLevel(GPIOPortG_Pin7))); -#else -// gpio_direction_output(RK2818_PIN_PG7,GPIO_HIGH); -// gpio_direction_input(RK2818_PIN_PG7); -// while(!(chip_type = gpio_get_value(RK2818_PIN_PG7))); -#endif - #if 0 - { - printk("[xxm]~~~~~~~~~~~chip_type is %d,you are forbiden,sorry~~~~~~\r\n",chip_type); - *p = 'n'; - } - #endif - SDRAM_DDR_Init(); - #if 0 - printk("after SDRAM_DDR_Init\n"); - //local_irq_enable(); - ddr_reg[0] = pGRF_Reg->CPU_APB_REG0; - ddr_reg[1] = pGRF_Reg->CPU_APB_REG1; - ddr_reg[2] = pDDR_Reg->CTRL_REG_03; - ddr_reg[3] = pDDR_Reg->CTRL_REG_09; - ddr_reg[4] = pDDR_Reg->CTRL_REG_10; - ddr_reg[5] = pDDR_Reg->CTRL_REG_36; - ddr_reg[6] = pDDR_Reg->CTRL_REG_78; - printk("after 0x%08x 0x%08x 0x%08x 0x%08x\n" - "0x%08x 0x%08x 0x%08x \n" - // "0x%08x 0x%08x 0x%08x 0x%08x\n" , - ,ddr_reg[0],ddr_reg[1],ddr_reg[2],ddr_reg[3], - ddr_reg[4],ddr_reg[5],ddr_reg[6]); - #endif - S_INFO("scu after frq%s::\n0x%08x 0x%08x 0x%08x 0x%08x\n" - "0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n" - "0x%08x 0x%08x 0x%08x 0x%08x\n" - // "0x%08x 0x%08x 0x%08x 0x%08x\n" , - ,__func__, - reg[0],reg[1],reg[2],reg[3], - reg[4],reg[5],reg[6],reg[7], reg[8], - reg[9], reg[10],reg[11], reg[12]); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32)) - clk_recalculate_root_clocks(); -#endif - return 0; -} -core_initcall_sync(update_frq); - -#endif //endi of #ifdef DRIVERS_SDRAM - diff --git a/arch/arm/mach-rk2818/devices.c b/arch/arm/mach-rk2818/devices.c deleted file mode 100755 index b9132b80f863..000000000000 --- a/arch/arm/mach-rk2818/devices.c +++ /dev/null @@ -1,654 +0,0 @@ -/* arch/arm/mach-rk2818/devices.c - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "devices.h" - -#include -#include -#include - -#include -#include -#include -#include /* ddl@rock-chips.com : camera support */ -#include -#include -#include -#include -#include -#include "../../../drivers/staging/android/timed_gpio.h" -static struct resource resources_sdmmc0[] = { - { - .start = IRQ_NR_SDMMC0, - .end = IRQ_NR_SDMMC0, - .flags = IORESOURCE_IRQ, - }, - { - .start = RK2818_SDMMC0_PHYS, - .end = RK2818_SDMMC0_PHYS + SZ_8K -1, - .flags = IORESOURCE_MEM, - } -}; -static struct resource resources_sdmmc1[] = { - { - .start = IRQ_NR_SDMMC1, - .end = IRQ_NR_SDMMC1, - .flags = IORESOURCE_IRQ, - }, - { - .start = RK2818_SDMMC1_PHYS, - .end = RK2818_SDMMC1_PHYS + SZ_8K -1, - .flags = IORESOURCE_MEM, - } -}; - - -static struct resource resources_i2c0[] = { - { - .start = IRQ_NR_I2C0, - .end = IRQ_NR_I2C0, - .flags = IORESOURCE_IRQ, - }, - { - .start = RK2818_I2C0_PHYS, - .end = RK2818_I2C0_PHYS + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; -static struct resource resources_i2c1[] = { - { - .start = IRQ_NR_I2C1, - .end = IRQ_NR_I2C1, - .flags = IORESOURCE_IRQ, - }, - { - .start = RK2818_I2C1_PHYS, - .end = RK2818_I2C1_PHYS + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; -/* - * rk2818 4 uarts device - */ -#ifdef CONFIG_UART0_RK2818 -static struct resource resources_uart0[] = { - { - .start = IRQ_NR_UART0, - .end = IRQ_NR_UART0, - .flags = IORESOURCE_IRQ, - }, - { - .start = RK2818_UART0_PHYS, - .end = RK2818_UART0_PHYS + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, -}; -#endif -#ifdef CONFIG_UART1_RK2818 -static struct resource resources_uart1[] = { - { - .start = IRQ_NR_UART1, - .end = IRQ_NR_UART1, - .flags = IORESOURCE_IRQ, - }, - { - .start = RK2818_UART1_PHYS, - .end = RK2818_UART1_PHYS + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, -}; -#endif -#ifdef CONFIG_UART2_RK2818 -static struct resource resources_uart2[] = { - { - .start = IRQ_NR_UART2, - .end = IRQ_NR_UART2, - .flags = IORESOURCE_IRQ, - }, - { - .start = RK2818_UART2_PHYS, - .end = RK2818_UART2_PHYS + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, -}; -#endif -#ifdef CONFIG_UART3_RK2818 -static struct resource resources_uart3[] = { - { - .start = IRQ_NR_UART3, - .end = IRQ_NR_UART3, - .flags = IORESOURCE_IRQ, - }, - { - .start = RK2818_UART3_PHYS, - .end = RK2818_UART3_PHYS + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, -}; -#endif -/* sdmmc */ -struct platform_device rk2818_device_sdmmc0 = { - .name = "rk2818_sdmmc", - .id = 0, - .num_resources = ARRAY_SIZE(resources_sdmmc0), - .resource = resources_sdmmc0, - .dev = { - .platform_data = &default_sdmmc0_data, - }, -}; -struct platform_device rk2818_device_sdmmc1 = { - .name = "rk2818_sdmmc", - .id = 1, - .num_resources = ARRAY_SIZE(resources_sdmmc1), - .resource = resources_sdmmc1, - .dev = { - .platform_data = &default_sdmmc1_data, - }, -}; - -struct platform_device rk2818_device_i2c0 = { - .name = "rk2818_i2c", - .id = 0, - .num_resources = ARRAY_SIZE(resources_i2c0), - .resource = resources_i2c0, - .dev = { - .platform_data = &default_i2c0_data, - }, -}; -struct platform_device rk2818_device_i2c1 = { - .name = "rk2818_i2c", - .id = 1, - .num_resources = ARRAY_SIZE(resources_i2c1), - .resource = resources_i2c1, - .dev = { - .platform_data = &default_i2c1_data, - }, -}; -#ifdef CONFIG_SPI_FPGA_I2C -struct platform_device rk2818_device_i2c2 = { - .name = "fpga_i2c", - .id = 2, - .dev = { - .platform_data = &default_i2c2_data, - }, -}; -struct platform_device rk2818_device_i2c3 = { - .name = "fpga_i2c", - .id = 3, - .dev = { - .platform_data = &default_i2c3_data, - }, -}; -#endif -#ifdef CONFIG_UART0_RK2818 -struct platform_device rk2818_device_uart0 = { - .name = "rk2818_serial", - .id = 0, - .num_resources = ARRAY_SIZE(resources_uart0), - .resource = resources_uart0, - .dev = { - .platform_data = &rk2818_serial0_platdata, - }, -}; -#endif -#ifdef CONFIG_UART1_RK2818 -struct platform_device rk2818_device_uart1 = { - .name = "rk2818_serial", - .id = 1, - .num_resources = ARRAY_SIZE(resources_uart1), - .resource = resources_uart1, -}; -#endif -#ifdef CONFIG_UART2_RK2818 -struct platform_device rk2818_device_uart2 = { - .name = "rk2818_serial", - .id = 2, - .num_resources = ARRAY_SIZE(resources_uart2), - .resource = resources_uart2, - .dev = { - .platform_data = &rk2818_serial2_platdata, - }, -}; -#endif -#ifdef CONFIG_UART3_RK2818 -struct platform_device rk2818_device_uart3 = { - .name = "rk2818_serial", - .id = 3, - .num_resources = ARRAY_SIZE(resources_uart3), - .resource = resources_uart3, -}; -#endif -/* - * rk2818 spi master device - */ -static struct resource resources_spim[] = { - { - .start = IRQ_NR_SPIM, - .end = IRQ_NR_SPIM, - .flags = IORESOURCE_IRQ, - }, - { - .start = RK2818_SPIMASTER_PHYS, - .end = RK2818_SPIMASTER_PHYS + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; -struct platform_device rk2818_device_spim = { - .name = "rk2818_spim", - .id = 0, - .num_resources = ARRAY_SIZE(resources_spim), - .resource = resources_spim, - .dev = { - .platform_data = &rk2818_spi_platdata, - }, -}; - -/* rk2818 fb resource */ -static struct resource rk2818_fb_resource[] = { - [0] = { - .start = RK2818_LCDC_PHYS, - .end = RK2818_LCDC_PHYS + RK2818_LCDC_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_NR_LCDC, - .end = IRQ_NR_LCDC, - .flags = IORESOURCE_IRQ, - }, -}; - -/*platform_device*/ -extern struct rk2818fb_info rk2818_fb_info; - -struct platform_device rk2818_device_fb = { - .name = "rk2818-fb", - .id = 4, - .num_resources = ARRAY_SIZE(rk2818_fb_resource), - .resource = rk2818_fb_resource, - .dev = { - .platform_data = &rk2818_fb_info, - } -}; - -/*********************************************************** -* backlight -* author :nzy zhongyw -* data:2010-05-18 -***************************************************************/ -struct platform_device rk2818_device_backlight = { - .name = "rk2818_backlight", - .id = -1, - .dev = { - .platform_data = &rk2818_bl_info, - } -}; - -/* RK2818 Camera : ddl@rock-chips.com */ -#ifdef CONFIG_VIDEO_RK2818 - -static struct resource rk2818_camera_resource[] = { - [0] = { - .start = RK2818_VIP_PHYS, - .end = RK2818_VIP_PHYS + RK2818_VIP_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_NR_VIP, - .end = IRQ_NR_VIP, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 rockchip_device_camera_dmamask = 0xffffffffUL; - -/*platform_device : */ -struct platform_device rk2818_device_camera = { - .name = RK28_CAM_DRV_NAME, - .id = RK28_CAM_PLATFORM_DEV_ID, /* This is used to put cameras on this interface */ - .num_resources = ARRAY_SIZE(rk2818_camera_resource), - .resource = rk2818_camera_resource, - .dev = { - .dma_mask = &rockchip_device_camera_dmamask, - .coherent_dma_mask = 0xffffffffUL, - .platform_data = &rk28_camera_platform_data, - } -}; -extern struct platform_device rk2818_soc_camera_pdrv; -#endif - -/*ADC*/ -static struct resource rk2818_adc_resource[] = { - { - .start = IRQ_NR_ADC, - .end = IRQ_NR_ADC, - .flags = IORESOURCE_IRQ, - }, - { - .start = RK2818_ADC_PHYS, - .end = RK2818_ADC_PHYS + RK2818_ADC_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - -}; - -struct platform_device rk2818_device_adc = { - .name = "rk2818-adc", - .id = -1, - .num_resources = ARRAY_SIZE(rk2818_adc_resource), - .resource = rk2818_adc_resource, -}; - - -struct platform_device rk2818_device_adckey = { - .name = "rk2818-adckey", - .id = -1, - .dev.parent = &rk2818_device_adc.dev, - .dev.platform_data = &rk2818_adckey_platdata, -}; - -/* - *rk2818 i2s - */ -static struct resource resources_i2s[] = { - { - .start = IRQ_NR_I2S, - .end = IRQ_NR_I2S, - .flags = IORESOURCE_IRQ, - }, - { - .start = RK2818_I2S_PHYS, - .end = RK2818_I2S_PHYS + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, -}; -struct platform_device rk2818_device_i2s = { - .name = "rk2818_i2s", - .id = 0, - .num_resources = ARRAY_SIZE(resources_i2s), - .resource = resources_i2s, - .dev = { - .platform_data = &rk2818_i2s_platdata, - }, -}; - -struct platform_device rk2818_device_battery = { - .name = "rk2818-battery", - .id = -1, - .dev = { - .platform_data = &rk2818_battery_platdata, - }, -}; - -/* - * rk2818 dsp device - */ - static struct resource resources_dsp[] = { - [0] = { - .start = RK2818_DSP_PHYS, - .end = RK2818_DSP_PHYS + 0x5fffff, - .flags = IORESOURCE_DMA, - }, - [1] = { - .start = IRQ_NR_PIUCMD, - .end = IRQ_NR_PIUCMD, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = IRQ_NR_DSPSWI, - .end = IRQ_NR_DSPSWI, - .flags = IORESOURCE_IRQ, - }, -}; -static u64 rk2818_device_dsp_dmamask = 0xffffffffUL; -struct platform_device rk2818_device_dsp = { - .name = "rk28-dsp", - .id = 0, - .num_resources = ARRAY_SIZE(resources_dsp), - .resource = resources_dsp, - .dev = { - .dma_mask = &rk2818_device_dsp_dmamask, - .coherent_dma_mask = 0xffffffffUL - } -}; - -#if defined(CONFIG_ANDROID_PMEM) - -static struct android_pmem_platform_data pmem_pdata = { - .name = "pmem", - .no_allocator = 1, - .cached = 0, - .start = 0x6f000000, - .size = 0x1000000, -}; - -static struct android_pmem_platform_data pmem_pdata_dsp = { - .name = "pmem-dsp", - .no_allocator = 0, - .cached = 0, - .start = 0x6db00000, - .size = 0x1500000, -}; - -struct platform_device rk2818_device_pmem = { - .name = "android_pmem", - .id = 0, - .dev = { .platform_data = &pmem_pdata }, -}; - -struct platform_device rk2818_device_pmem_dsp = { - .name = "android_pmem", - .id = 1, - .dev = { .platform_data = &pmem_pdata_dsp }, -}; - -#endif -#if defined(CONFIG_MTD_NAND_RK2818) -static struct resource nand_resources[] = { - { - .start = RK2818_NANDC_PHYS, - .end = RK2818_NANDC_PHYS+RK2818_NANDC_SIZE -1, - .flags = IORESOURCE_MEM, - } -}; - -struct platform_device rk2818_nand_device = { - .name = "rk2818-nand", - .id = -1, - .resource = nand_resources, - .num_resources= ARRAY_SIZE(nand_resources), - .dev = { - .platform_data= &rk2818_nand_data, - }, - -}; - -#endif - -#if defined(CONFIG_INPUT_JOGBALL) -struct platform_device rk2818_jogball_device = { - .name = "rk2818_jogball", - .id = -1, - .dev = { - .platform_data = &rk2818_jogball_platdata, - }, -}; -#endif - -/*DWC_OTG*/ -static struct resource dwc_otg_resource[] = { - { - .start = IRQ_NR_OTG, - .end = IRQ_NR_OTG, - .flags = IORESOURCE_IRQ, - }, - { - .start = RK2818_USBOTG_PHYS, - .end = RK2818_USBOTG_PHYS + RK2818_USBOTG_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - -}; - -struct platform_device rk2818_device_dwc_otg = { - .name = "dwc_otg", - .id = -1, - .num_resources = ARRAY_SIZE(dwc_otg_resource), - .resource = dwc_otg_resource, -}; -#ifdef CONFIG_RK2818_HOST11 -static struct resource rk2818_host11_resource[] = { - { - .start = IRQ_NR_USB_HOST, - .end = IRQ_NR_USB_HOST, - .flags = IORESOURCE_IRQ, - }, - { - .start = RK2818_USBHOST_PHYS, - .end = RK2818_USBHOST_PHYS + RK2818_USBHOST_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - -}; - -struct platform_device rk2818_device_host11 = { - .name = "rk2818_host11", - .id = -1, - .num_resources = ARRAY_SIZE(rk2818_host11_resource), - .resource = rk2818_host11_resource, -}; -#endif -static char *usb_functions_rockchip[] = { - "usb_mass_storage", -}; - -static char *usb_functions_rockchip_adb[] = { - "usb_mass_storage", - "adb", -}; - -static char *usb_functions_rndis_rockchip[] = { - "rndis", - "usb_mass_storage", -}; - -static char *usb_functions_rndis_rockchip_adb[] = { - "rndis", - "usb_mass_storage", - "adb", -}; - -#ifdef CONFIG_USB_ANDROID_DIAG -static char *usb_functions_adb_diag[] = { - "usb_mass_storage", - "adb", - "diag", -}; -#endif - -static char *usb_functions_all[] = { -#ifdef CONFIG_USB_ANDROID_RNDIS - "rndis", -#endif - "usb_mass_storage", -#ifdef CONFIG_USB_ANDROID_ADB - "adb", -#endif -#ifdef CONFIG_USB_ANDROID_ACM - "acm", -#endif -#ifdef CONFIG_USB_ANDROID_DIAG - "diag", -#endif -}; - -static struct android_usb_product usb_products[] = { - { - .product_id = 0x2810,//0x0c02,//0x4e11, - .num_functions = ARRAY_SIZE(usb_functions_rockchip), - .functions = usb_functions_rockchip, - }, - { - .product_id = 0x4e12, - .num_functions = ARRAY_SIZE(usb_functions_rockchip_adb), - .functions = usb_functions_rockchip_adb, - }, - { - .product_id = 0x4e13, - .num_functions = ARRAY_SIZE(usb_functions_rndis_rockchip), - .functions = usb_functions_rndis_rockchip, - }, - { - .product_id = 0x4e14, - .num_functions = ARRAY_SIZE(usb_functions_rndis_rockchip_adb), - .functions = usb_functions_rndis_rockchip_adb, - }, -#ifdef CONFIG_USB_ANDROID_DIAG - { - .product_id = 0x4e17, - .num_functions = ARRAY_SIZE(usb_functions_adb_diag), - .functions = usb_functions_adb_diag, - }, -#endif -}; - -static struct android_usb_platform_data android_usb_pdata = { - .vendor_id = 0x2207,//0x0bb4,//0x18d1, - .product_id = 0x2810,//0x4e11, - .version = 0x0100, - .product_name = "rk2818 sdk", - .manufacturer_name = "RockChip", - .num_products = ARRAY_SIZE(usb_products), - .products = usb_products, - .num_functions = ARRAY_SIZE(usb_functions_all), - .functions = usb_functions_all, -}; - -//static -struct platform_device android_usb_device = { - .name = "android_usb", - .id = -1, - .dev = { - .platform_data = &android_usb_pdata, - }, -}; - -//static -struct platform_device usb_mass_storage_device = { - .name = "usb_mass_storage", - .id = -1, - .dev = { - .platform_data = &mass_storage_pdata, - }, -}; - -#if CONFIG_ANDROID_TIMED_GPIO -struct platform_device rk28_device_vibrator ={ - .name = "timed-gpio", - .id = -1, - .dev = { - .platform_data = &rk28_vibrator_info, - }, - -}; -#endif - diff --git a/arch/arm/mach-rk2818/devices.h b/arch/arm/mach-rk2818/devices.h deleted file mode 100755 index ae0dc43f3847..000000000000 --- a/arch/arm/mach-rk2818/devices.h +++ /dev/null @@ -1,71 +0,0 @@ -/* linux/arch/arm/mach-rk2818/devices.h - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __ARCH_ARM_MACH_RK2818_DEVICES_H -#define __ARCH_ARM_MACH_RK2818_DEVICES_H - -extern struct platform_device rk2818_device_uart0; -extern struct platform_device rk2818_device_uart1; -extern struct platform_device rk2818_device_uart2; -extern struct platform_device rk2818_device_uart3; -extern struct rk2818_serial_platform_data rk2818_serial0_platdata; -extern struct rk2818_serial_platform_data rk2818_serial2_platdata; -extern struct platform_device rk2818_device_spim; -extern struct rk2818_spi_platform_data rk2818_spi_platdata; -extern struct platform_device rk2818_device_i2c0; -extern struct platform_device rk2818_device_i2c1; -extern struct platform_device rk2818_device_i2c2; -extern struct platform_device rk2818_device_i2c3; -extern struct rk2818_i2c_platform_data default_i2c0_data; -extern struct rk2818_i2c_platform_data default_i2c1_data; -extern struct rk2818_i2c_spi_data default_i2c2_data; -extern struct rk2818_i2c_spi_data default_i2c3_data; -extern struct rk2818_bl_info rk2818_bl_info; -extern struct rk2818_nand_platform_data rk2818_nand_data; - -extern struct soc_camera_link rk2818_iclink; /* ddl@rock-chips.com : camera support */ -extern struct rk28camera_platform_data rk28_camera_platform_data; - -extern struct platform_device rk2818_device_sdmmc0; -extern struct platform_device rk2818_device_sdmmc1; -extern struct rk2818_sdmmc_platform_data default_sdmmc0_data; -extern struct rk2818_sdmmc_platform_data default_sdmmc1_data; -extern struct platform_device rk2818_jogball_device; -extern struct platform_device rk2818_device_i2s; -extern struct rk2818_i2s_platform_data rk2818_i2s_platdata; -extern struct platform_device rk2818_device_pmem; -extern struct platform_device rk2818_device_pmem_dsp; -extern struct platform_device rk2818_device_fb; -extern struct platform_device rk2818_device_adc; -extern struct platform_device rk2818_device_adckey; -extern struct rk2818_adckey_platform_data rk2818_adckey_platdata; -extern struct rk2818_jogball_paltform_data rk2818_jogball_platdata; -extern struct platform_device rk2818_device_battery; -extern struct rk2818_battery_platform_data rk2818_battery_platdata; -extern struct platform_device rk2818_device_backlight; -extern struct platform_device rk2818_device_camera; /* ddl@rock-chips.com : camera support */ -extern struct platform_device rk2818_soc_camera_pdrv; -extern struct platform_device rk2818_device_dsp; -extern struct platform_device rk2818_device_rfkill; -extern struct platform_device rk2818_nand_device; -extern struct platform_device rk2818_device_dwc_otg; -extern struct platform_device rk2818_device_host11; -extern struct platform_device android_usb_device; -extern struct usb_mass_storage_platform_data mass_storage_pdata; -extern struct platform_device usb_mass_storage_device; -extern struct platform_device rk28_device_vibrator; -extern struct timed_gpio_platform_data rk28_vibrator_info; - -#endif diff --git a/arch/arm/mach-rk2818/dma.c b/arch/arm/mach-rk2818/dma.c deleted file mode 100644 index ca05cfc77000..000000000000 --- a/arch/arm/mach-rk2818/dma.c +++ /dev/null @@ -1,768 +0,0 @@ -/* arch/arm/mach-rk2818/dma.c - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - - -static struct rk2818_dma rk2818_dma[MAX_DMA_CHANNELS]; - -static struct tasklet_struct rk2818_dma_tasklet; - -const static char *rk28_dma_dev_id[] = { - "sd_mmc", - "uart_2", - "uart_3", - "sdio", - "i2s", - "spi_m", - "spi_s", - "uart_0", - "uart_1", -#ifdef test_dma - "mobile_sdram" -#endif -}; - -const static struct rk28_dma_dev rk28_dev_info[] = { - [RK28_DMA_SD_MMC] = { - .hd_if_r = RK28_DMA_SD_MMC0, - .hd_if_w = RK28_DMA_SD_MMC0, - .dev_addr_r = RK2818_SDMMC0_PHYS + 0x100, - .dev_addr_w = RK2818_SDMMC0_PHYS + 0x100, - .fifo_width = 32, - }, - [RK28_DMA_URAT2] = { - .hd_if_r = RK28_DMA_URAT2_RXD, - .hd_if_w = RK28_DMA_URAT2_TXD, - .dev_addr_r = RK2818_UART2_PHYS, - .dev_addr_w = RK2818_UART2_PHYS, - .fifo_width = 32, - }, - [RK28_DMA_URAT3] = { - .hd_if_r = RK28_DMA_URAT3_RXD, - .hd_if_w = RK28_DMA_URAT3_TXD, - .dev_addr_r = RK2818_UART3_PHYS, - .dev_addr_w = RK2818_UART3_PHYS, - .fifo_width = 32, - }, - [RK28_DMA_SDIO] = { - - .hd_if_r = RK28_DMA_SD_MMC1, - .hd_if_w = RK28_DMA_SD_MMC1, - .dev_addr_r = RK2818_SDMMC1_PHYS + 0x100, - .dev_addr_w = RK2818_SDMMC1_PHYS + 0x100, - .fifo_width = 32, - }, - [RK28_DMA_I2S] = { - .hd_if_r = RK28_DMA_I2S_RXD, - .hd_if_w = RK28_DMA_I2S_TXD, - .dev_addr_r = RK2818_I2S_PHYS + 0x04, - .dev_addr_w = RK2818_I2S_PHYS + 0x08, - .fifo_width = 32, - }, - [RK28_DMA_SPI_M] = { - .hd_if_r = RK28_DMA_SPI_M_RXD, - .hd_if_w = RK28_DMA_SPI_M_TXD, - .dev_addr_r = RK2818_SPIMASTER_PHYS + 0x60, - .dev_addr_w = RK2818_SPIMASTER_PHYS + 0x60, - .fifo_width = 8, - }, - [RK28_DMA_SPI_S] = { - .hd_if_r = RK28_DMA_SPI_S_RXD, - .hd_if_w = RK28_DMA_SPI_S_TXD, - .dev_addr_r = RK2818_SPISLAVE_PHYS + 0x60, - .dev_addr_w = RK2818_SPISLAVE_PHYS + 0x60, - .fifo_width = 8, - }, - [RK28_DMA_URAT0] = { - .hd_if_r = RK28_DMA_URAT0_RXD, - .hd_if_w = RK28_DMA_URAT0_TXD, - .dev_addr_r = RK2818_UART0_PHYS, - .dev_addr_w = RK2818_UART0_PHYS, - .fifo_width = 8, - }, - [RK28_DMA_URAT1] = { - .hd_if_r = RK28_DMA_URAT1_RXD, - .hd_if_w = RK28_DMA_URAT1_TXD, - .dev_addr_r = RK2818_UART1_PHYS, - .dev_addr_w = RK2818_UART1_PHYS, - .fifo_width = 8, - }, -#ifdef test_dma - [RK28_DMA_SDRAM] = { - .hd_if_r = 0, - .hd_if_w = 0, - .dev_addr_r = BUF_READ_ARRR, - .dev_addr_w = BUF_WRITE_ARRR, - .fifo_width = 32, - }, -#endif - -}; - - - - -/** - * rk28_dma_ctl_for_write - set dma control register for writing mode - * - */ -static inline unsigned int rk28_dma_ctl_for_write(unsigned int dma_ch, const struct rk28_dma_dev *dev_info, dma_t *dma_t) -{ -#ifdef test_dma - unsigned int dev_mode = B_CTLL_MEM2MEM_DMAC; - unsigned int inc_mode = B_CTLL_DINC_INC; -#else - unsigned int dev_mode = B_CTLL_MEM2PER_DMAC; - unsigned int inc_mode = B_CTLL_DINC_UNC; -#endif - unsigned int llp_mode = (dma_t->sg) ? (B_CTLL_LLP_DST_EN | B_CTLL_LLP_SRC_EN) : 0; - unsigned int int_mode = (!dma_t->sg) ? B_CTLL_INT_EN : 0; - - unsigned int ctll = B_CTLL_SRC_TR_WIDTH_32 | B_CTLL_DST_TR_WIDTH(dev_info->fifo_width >> 4) | - B_CTLL_SINC_INC | inc_mode | - B_CTLL_DMS_ARMD | B_CTLL_SMS_EXP | dev_mode | - B_CTLL_SRC_MSIZE_4 | B_CTLL_DST_MSIZE_4 | - llp_mode | int_mode; - - return ctll; -} - -/** - * rk28_dma_ctl_for_read - set dma control register for reading mode - * - */ -static inline unsigned int rk28_dma_ctl_for_read(unsigned int dma_ch, const struct rk28_dma_dev *dev_info, dma_t *dma_t) -{ -#ifdef test_dma - unsigned int dev_mode = B_CTLL_MEM2MEM_DMAC; - unsigned int inc_mode = B_CTLL_SINC_INC; -#else - unsigned int dev_mode = B_CTLL_PER2MEM_DMAC; - unsigned int inc_mode = B_CTLL_SINC_UNC; -#endif - unsigned int llp_mode = (dma_t->sg) ? (B_CTLL_LLP_DST_EN | B_CTLL_LLP_SRC_EN) : 0; - unsigned int int_mode = (!dma_t->sg) ? B_CTLL_INT_EN : 0; - - unsigned int ctll = B_CTLL_SRC_TR_WIDTH(dev_info->fifo_width>> 4) | B_CTLL_DST_TR_WIDTH_32 | - inc_mode | B_CTLL_DINC_INC | - B_CTLL_DMS_EXP | B_CTLL_SMS_ARMD | dev_mode | - B_CTLL_SRC_MSIZE_4 | B_CTLL_DST_MSIZE_4 | - llp_mode | int_mode; - - return ctll; -} - -/** - * rk28_dma_set_reg - set dma registers - * - */ -static inline void rk28_dma_set_reg(unsigned int dma_ch, struct rk28_dma_llp *reg, unsigned int dma_if) -{ - write_dma_reg(DWDMA_SAR(dma_ch), reg->sar); - write_dma_reg(DWDMA_DAR(dma_ch), reg->dar); - write_dma_reg(DWDMA_LLP(dma_ch), (unsigned int)(reg->llp)); - write_dma_reg(DWDMA_CTLL(dma_ch), reg->ctll); - write_dma_reg(DWDMA_CTLH(dma_ch), reg->size); - write_dma_reg(DWDMA_CFGL(dma_ch), B_CFGL_CH_PRIOR(7) | - B_CFGL_H_SEL_DST | B_CFGL_H_SEL_SRC | - B_CFGL_DST_HS_POL_H | B_CFGL_SRC_HS_POL_H); - write_dma_reg(DWDMA_CFGH(dma_ch), B_CFGH_SRC_PER(dma_if & 0xf) | - B_CFGH_DST_PER(dma_if & 0xf) | - B_CFGH_PROTCTL); -} - -/** - * rk28_dma_setup_reg - set linked list content - * - */ -static inline void rk28_dma_set_llp(unsigned int sar, - unsigned int dar, - struct rk28_dma_llp *curllp, - struct rk28_dma_llp *nexllp, - unsigned int ctll, - unsigned int size) -{ - curllp->sar = sar; //pa - curllp->dar = dar; //pa - curllp->ctll = ctll; - curllp->llp = nexllp; //physical next linked list pointer - curllp->size = size; -} - -/** - * rk28_dma_end_of_llp - set linked list end - * - */ -static inline void rk28_dma_end_of_llp(struct rk28_dma_llp *curllp) -{ - curllp->llp = 0; - curllp->ctll &= (~B_CTLL_LLP_DST_EN) & (~B_CTLL_LLP_SRC_EN); - curllp->ctll |= B_CTLL_INT_EN; -} - -/** - * rk28_dma_setup_sg - setup rk28 DMA channel SG list to/from device transfer - * @dma_ch: rk28 device ID which using DMA, device id list is showed in dma.h - * @dma_t: pointer to the dma struct - * - * The function sets up DMA channel state and registers to be ready for transfer - * specified by provided parameters. The scatter-gather emulation is set up - * according to the parameters. - * - * enbale dma should be called after setup sg - * - * Return value: negative if incorrect parameters - * Zero indicates success. - */ -static void rk28_dma_write_to_sg(unsigned int dma_ch, dma_t *dma_t) -{ - unsigned int i, ctll_r, dev_addr_w; - struct rk2818_dma *rk28dma; - struct rk28_dma_llp * rk28llp_vir; - struct rk28_dma_llp * rk28llp_phy; - struct rk28_dma_llp rk28dma_reg; - struct scatterlist *sg; - unsigned int wid_off, bk_count, bk_res, sgcount_tmp, bk_length; - - rk28dma = &rk2818_dma[dma_ch]; - - dev_addr_w = rk28dma->dev_info->dev_addr_w; - ctll_r = rk28_dma_ctl_for_read(dma_ch, rk28dma->dev_info, dma_t); - wid_off = rk28dma->dev_info->fifo_width >> 4; - - if (dma_t->sg) { - rk28llp_vir = rk28dma->dma_llp_vir; - rk28llp_phy = (struct rk28_dma_llp *)rk28dma->dma_llp_phy; - sg = dma_t->sg; -#if 1 - bk_length = RK28_DMA_CH0A1_MAX_LEN << wid_off; - - for (sgcount_tmp = 0; sgcount_tmp < dma_t->sgcount; sgcount_tmp++, sg++) { - bk_count = (sg->length >> wid_off) / RK28_DMA_CH0A1_MAX_LEN; - bk_res = (sg->length >> wid_off) % RK28_DMA_CH0A1_MAX_LEN; - for (i = 0; i < bk_count; i++) { - rk28_dma_set_llp(dev_addr_w, - sg->dma_address + i * bk_length, - rk28llp_vir++, - ++rk28llp_phy, - ctll_r, - RK28_DMA_CH0A1_MAX_LEN); - } - if (bk_res > 0) { - rk28_dma_set_llp(dev_addr_w, - sg->dma_address + bk_count * bk_length, - rk28llp_vir++, - ++rk28llp_phy, - ctll_r, - bk_res); - } - } -#else - for (i = 0; i < dma_t->sgcount; i++, sg++) { - rk28_dma_set_llp(dev_addr_w, sg->dma_address, rk28llp_vir++, ++rk28llp_phy, ctll_r, (sg->length >> wid_off)); - } -#endif - rk28_dma_end_of_llp(rk28llp_vir - 1); - rk28dma_reg.llp = (struct rk28_dma_llp *)rk28dma->dma_llp_phy; - } else { /*single transfer*/ - if (dma_t->buf.length > RK28_DMA_CH2_MAX_LEN) { - rk28dma->length = RK28_DMA_CH2_MAX_LEN; - rk28dma->residue = dma_t->buf.length - RK28_DMA_CH2_MAX_LEN; - } else { - rk28dma->length = dma_t->buf.length; - rk28dma->residue = 0; - } - rk28dma_reg.llp = NULL; - } - rk28dma_reg.sar = dev_addr_w; - rk28dma_reg.dar = dma_t->buf.dma_address; - rk28dma_reg.ctll = ctll_r; - rk28dma_reg.size = rk28dma->length; - rk28_dma_set_reg(dma_ch, &rk28dma_reg, rk28dma->dev_info->hd_if_r); - /* - printk(KERN_INFO "dma_write_to_sg: ch = %d, sar = 0x%x, dar = 0x%x, ctll = 0x%x, llp = 0x%x, size = %d, \n", - dma_ch, rk28dma_reg.sar, rk28dma_reg.dar, rk28dma_reg.ctll, rk28dma_reg.llp, rk28dma_reg.size); - rk28llp_vir = rk28dma->dma_llp_vir; - for (i=0; isgcount; i++, rk28llp_vir++) - printk(KERN_INFO "dma_write_to_sg: ch = %d, sar = 0x%x, dar = 0x%x, ctll = 0x%x, llp = 0x%x, size = %d, \n", - dma_ch, rk28llp_vir->sar, rk28llp_vir->dar, rk28llp_vir->ctll, rk28llp_vir->llp, rk28llp_vir->size); - */ - -} - -/** - * rk28_dma_setup_sg - setup rk28 DMA channel SG list to/from device transfer - * @dma_ch: rk28 device ID which using DMA, device id list is showed in dma.h - * @dma_t: pointer to the dma struct - * - * The function sets up DMA channel state and registers to be ready for transfer - * specified by provided parameters. The scatter-gather emulation is set up - * according to the parameters. - * - * enbale dma should be called after setup sg - * - * Return value: negative if incorrect parameters - * Zero indicates success. - */ -static void rk28_dma_read_from_sg(unsigned int dma_ch, dma_t *dma_t) -{ - unsigned int i, ctll_w, dev_addr_r; - struct rk2818_dma *rk28dma; - struct rk28_dma_llp * rk28llp_vir; - struct rk28_dma_llp * rk28llp_phy; - struct rk28_dma_llp rk28dma_reg; - struct scatterlist *sg; - unsigned int wid_off, bk_count, bk_res, sgcount_tmp, bk_length; - - rk28dma = &rk2818_dma[dma_ch]; - - /*setup linked list table end*/ - dev_addr_r = rk28dma->dev_info->dev_addr_r; - ctll_w = rk28_dma_ctl_for_write(dma_ch, rk28dma->dev_info, dma_t); - wid_off = rk28dma->dev_info->fifo_width >> 4; - - if (dma_t->sg) { - rk28llp_vir = rk28dma->dma_llp_vir; - rk28llp_phy = (struct rk28_dma_llp *)rk28dma->dma_llp_phy; - sg = dma_t->sg; -#if 1 - bk_length = RK28_DMA_CH0A1_MAX_LEN << wid_off; - - for (sgcount_tmp = 0; sgcount_tmp < dma_t->sgcount; sgcount_tmp++, sg++) { - bk_count = (sg->length >> wid_off) / RK28_DMA_CH0A1_MAX_LEN; - bk_res = (sg->length >> wid_off) % RK28_DMA_CH0A1_MAX_LEN; - for (i = 0; i < bk_count; i++) { - rk28_dma_set_llp(sg->dma_address + i * bk_length, - dev_addr_r, - rk28llp_vir++, - ++rk28llp_phy, - ctll_w, - RK28_DMA_CH0A1_MAX_LEN); - } - if (bk_res > 0) { - rk28_dma_set_llp(sg->dma_address + bk_count * bk_length, - dev_addr_r, - rk28llp_vir++, - ++rk28llp_phy, - ctll_w, - bk_res); - } - } -#else - for (i = 0; i < dma_t->sgcount; i++, sg++) { - rk28_dma_set_llp(sg->dma_address, dev_addr_r, rk28llp_vir++, ++rk28llp_phy, ctll_w, (sg->length >> wid_off)); - } -#endif - rk28_dma_end_of_llp(rk28llp_vir - 1); - rk28dma_reg.llp = (struct rk28_dma_llp *)rk28dma->dma_llp_phy; - } else { /*single transfer*/ - if (dma_t->buf.length > RK28_DMA_CH2_MAX_LEN) { - rk28dma->length = RK28_DMA_CH2_MAX_LEN; - rk28dma->residue = dma_t->buf.length - RK28_DMA_CH2_MAX_LEN; - } else { - rk28dma->length = dma_t->buf.length; - rk28dma->residue = 0; - } - rk28dma_reg.llp = NULL; - } - rk28dma_reg.sar = dma_t->buf.dma_address; - rk28dma_reg.dar = dev_addr_r; - rk28dma_reg.ctll = ctll_w; - rk28dma_reg.size = rk28dma->length; - rk28_dma_set_reg(dma_ch, &rk28dma_reg, rk28dma->dev_info->hd_if_w); - - //printk(KERN_INFO "read_from_sg: ch = %d, sar = 0x%x, dar = 0x%x, ctll = 0x%x, llp = 0x%x, size = %d, \n", - // dma_ch, rk28dma_reg.sar, rk28dma_reg.dar, rk28dma_reg.ctll, rk28dma_reg.llp, rk28dma_reg.size); -} - -/** - * rk28_dma_enable - function to start rk28 DMA channel operation - * @dma_ch: rk28 device ID which using DMA, device id list is showed in dma.h - * - * The channel has to be allocated by driver through rk28_dma_request() - * The transfer parameters has to be set to the channel registers through - * call of the rk28_dma_setup_sg() function. - - */ -static int rk28_dma_enable(unsigned int dma_ch, dma_t *dma_t) -{ - //printk(KERN_INFO "enter dwdma_enable\n"); - struct rk2818_dma *rk28dma = &rk2818_dma[dma_ch]; - - spin_lock(&rk28dma->lock); - - if (dma_t->sg) { - if (dma_ch >= RK28_DMA_CH2) { - printk(KERN_ERR "dma_enable: channel %d does not support sg transfer mode\n", dma_ch); - goto bad_enable; - } - if (dma_t->sgcount > RK28_MAX_DMA_LLPS) { - printk(KERN_ERR "dma_enable: count %d are more than supported number %d\n", dma_t->sgcount, RK28_MAX_DMA_LLPS); - goto bad_enable; - } - } else { /*single transfer*/ - if ((!dma_t->addr) || (dma_t->count == 0)) { - printk(KERN_ERR "dma_enable: channel %d does not have leagal address or count\n", dma_ch); - goto bad_enable; - } - dma_t->buf.dma_address = (dma_addr_t)dma_t->addr; - dma_t->buf.length = dma_t->count; - } - //printk(KERN_INFO "dma_enable: addr = 0x%x\n", (dma_addr_t)dma_t->addr); - - if (dma_t->dma_mode == DMA_MODE_READ) { - rk28_dma_write_to_sg(dma_ch, dma_t); - } else { - rk28_dma_read_from_sg(dma_ch, dma_t); - } - - dma_t->invalid = 0; - - ENABLE_DWDMA(dma_ch); - - spin_unlock(&rk28dma->lock); - //printk(KERN_INFO "exit dwdma_enable\n"); - - return 0; - -bad_enable: - dma_t->active = 0; - return -EINVAL; -} - -/** - * rk28_dma_disable - stop, finish rk28 DMA channel operatin - * @dma_ch: rk28 device ID which using DMA, device id list is showed in dma.h - * - * dma transfer will be force into suspend state whether dma have completed current transfer - */ -static int rk28_dma_disable(unsigned int dma_ch, dma_t *dma_t) -{ - struct rk2818_dma *rk28dma = &rk2818_dma[dma_ch]; - - spin_lock(&rk28dma->lock); - - DISABLE_DWDMA(dma_ch); - while (GET_DWDMA_STATUS(dma_ch)) - cpu_relax(); - - rk28dma->tasklet_flag = 0; - - spin_unlock(&rk28dma->lock); - - return 0; -} - -/** - * rk28_dma_request - request/allocate specified channel number - * @dma_ch: rk28 device ID which using DMA, device id list is showed in dma.h - * requesting dma channel if device need dma transfer - * but just called one time in one event, and channle should be - * free after this event - */ -static int rk28_dma_request(unsigned int dma_ch, dma_t *dma_t) -{ - int i; - struct rk2818_dma *rk28dma = &rk2818_dma[dma_ch]; - - //printk(KERN_INFO "enter dwdma request\n"); - - spin_lock(&rk28dma->lock); - - /*compare to make sure whether device that request dma is legal*/ - for (i = 0; i < RK28_DMA_DEV_NUM_MAX; i++) { - if (!strcmp(dma_t->device_id, rk28_dma_dev_id[i])) - break; - } - - if (i >= RK28_DMA_DEV_NUM_MAX) { - printk(KERN_ERR "dma_request: called for non-existed dev %s\n", dma_t->device_id); - return -ENODEV; - } - - /*channel 0 and 1 support llp, but others does not*/ - if (dma_ch < RK28_DMA_CH2) { - rk28dma->dma_llp_vir = (struct rk28_dma_llp *)dma_alloc_coherent(NULL, RK28_MAX_DMA_LLPS*sizeof(struct rk28_dma_llp), &rk28dma->dma_llp_phy, GFP_ATOMIC); - if (!rk28dma->dma_llp_vir) { - printk(KERN_ERR "dma_request: no dma space can be allocated for llp by virtual channel %d\n", dma_ch); - return -ENOMEM; - } - } else { - rk28dma->dma_llp_vir = NULL; - rk28dma->dma_llp_phy = 0; - } - - rk28dma->dev_info = &rk28_dev_info[i]; - - /* clear interrupt */ - CLR_DWDMA_INTR(dma_ch); - - UN_MASK_DWDMA_TRF_INTR(dma_ch); - - spin_unlock(&rk28dma->lock); - - //printk(KERN_INFO "exit dwdma request device %d\n", i); - - return 0; -} - -/** - * rk28_dma_free - release previously acquired channel - * @dma_ch: rk28 device ID which using DMA, device id list is showed in dma.h - * - * request dam should be prior free dma - */ -static int rk28_dma_free(unsigned int dma_ch, dma_t *dma_t) -{ - struct rk2818_dma *rk28dma = &rk2818_dma[dma_ch]; - - spin_lock(&rk28dma->lock); - - /* clear interrupt */ - CLR_DWDMA_INTR(dma_ch); - - MASK_DWDMA_TRF_INTR(dma_ch); - - if (dma_ch < RK28_DMA_CH2) { - if (!rk28dma->dma_llp_vir) { - printk(KERN_ERR "dma_free: no dma space can be free by virtual channel %d\n", dma_ch); - return -ENOMEM; - } - dma_free_coherent(NULL, RK28_MAX_DMA_LLPS*sizeof(struct rk28_dma_llp), (void *)rk28dma->dma_llp_vir, rk28dma->dma_llp_phy); - } - - rk28dma->dma_t.irqHandle = NULL; - rk28dma->dma_t.data = NULL; - rk28dma->dma_t.sg = NULL; - rk28dma->dma_t.addr = NULL; - rk28dma->dma_t.count = 0; - rk28dma->dma_llp_vir = NULL; - rk28dma->dma_llp_phy = 0; - rk28dma->residue = 0; - rk28dma->length = 0; - - spin_unlock(&rk28dma->lock); - - return 0; -} - -/** - * rk28_dma_next - set dma regiters and start of next transfer if using channel 2 - * @dma_ch: rk28 device ID which using DMA, device id list is showed in dma.h - * - * just be applied to channel 2 - */ -static int rk28_dma_next(unsigned int dma_ch) -{ - struct rk2818_dma *rk28dma = &rk2818_dma[dma_ch]; - unsigned int nextlength; - unsigned int nextaddr; - unsigned int width_off = rk28dma->dev_info->fifo_width >> 4; - unsigned int dma_if; - struct rk28_dma_llp rk28dma_reg; - - /*go on transfering if there are buffer of other blocks leave*/ - if (rk28dma->residue > 0) { - nextaddr = rk28dma->dma_t.buf.dma_address + (rk28dma->length << width_off); - if (rk28dma->residue > RK28_DMA_CH2_MAX_LEN) { - nextlength = RK28_DMA_CH2_MAX_LEN; - rk28dma->residue -= RK28_DMA_CH2_MAX_LEN; - } else { - nextlength = rk28dma->residue; - rk28dma->residue = 0; - } - rk28dma->length = nextlength; - - if (rk28dma->dma_t.dma_mode == DMA_MODE_READ) { - rk28dma_reg.sar = rk28dma->dev_info->dev_addr_r; - rk28dma_reg.dar = nextaddr; - rk28dma_reg.ctll = rk28_dma_ctl_for_read(dma_ch, rk28dma->dev_info, &rk28dma->dma_t); - dma_if = rk28dma->dev_info->hd_if_r; - } else { - rk28dma_reg.sar = nextaddr; - rk28dma_reg.dar = rk28dma->dev_info->dev_addr_w; - rk28dma_reg.ctll = rk28_dma_ctl_for_write(dma_ch, rk28dma->dev_info, &rk28dma->dma_t); - dma_if = rk28dma->dev_info->hd_if_w; - } - rk28dma_reg.llp = NULL; - rk28dma_reg.size = nextlength; - - rk28_dma_set_reg(dma_ch, &rk28dma_reg, dma_if); - - ENABLE_DWDMA(dma_ch); - - return nextlength; - } - - return 0; -} - -/** - * rk28_dma_tasklet - irq callback function - * - */ -static void rk28_dma_tasklet(unsigned long data) -{ - int i; - struct rk2818_dma *rk28dma; - - for (i = 0; i < MAX_DMA_CHANNELS; i++) { - rk28dma = &rk2818_dma[i]; - if ((rk28dma->tasklet_flag) && (rk28dma->dma_t.irq_mode == DMA_IRQ_DELAY_MODE)) { - rk28dma->dma_t.active = 0; - rk28dma->tasklet_flag = 0; - if (rk28dma->dma_t.irqHandle) - rk28dma->dma_t.irqHandle(i, rk28dma->dma_t.data); - UN_MASK_DWDMA_TRF_INTR(i); - } - } -} - -/** - * rk28_dma_irq_handler - irq callback function - * - */ -static irqreturn_t rk28_dma_irq_handler(int irq, void *dev_id) -{ - int i, raw_status; - struct rk2818_dma *rk28dma; - - raw_status = read_dma_reg(DWDMA_RawTfr); - - for (i = 0; i < MAX_DMA_CHANNELS; i++) { - if (raw_status & (1 << i)) { - CLR_DWDMA_INTR(i); - - rk28dma = &rk2818_dma[i]; - - if ((!rk28dma->dma_t.sg) && (rk28_dma_next(i))) { - //printk(KERN_WARNING "dma_irq: don't finish for channel %d\n", i); - continue; - } - - if (rk28dma->dma_t.irqHandle) { - if (rk28dma->dma_t.irq_mode != DMA_IRQ_DELAY_MODE) { - /* already have completed transfer */ - rk28dma->dma_t.active = 0; - rk28dma->dma_t.irqHandle(i, rk28dma->dma_t.data); - } else { - MASK_DWDMA_TRF_INTR(i); - rk28dma->tasklet_flag = 1; - tasklet_schedule(&rk2818_dma_tasklet); - //printk(KERN_WARNING "dma_irq: no IRQ handler for DMA channel %d\n", i); - } - } else { - /* already have completed transfer */ - rk28dma->dma_t.active = 0; - } - } - } - - //tasklet_schedule(&rk2818_dma_tasklet); - - return IRQ_HANDLED; -} - -static void rk28_dma_position(unsigned int dma_ch, dma_t *dma_t) -{ - dma_t->src_pos = read_dma_reg(DWDMA_SAR(dma_ch)); - dma_t->dst_pos = read_dma_reg(DWDMA_DAR(dma_ch)); -} - -static struct dma_ops rk2818_dma_ops = { - .request = rk28_dma_request, - .free = rk28_dma_free, - .enable = rk28_dma_enable, - .disable = rk28_dma_disable, - .position = rk28_dma_position, -}; - -/** - * rk28_dma_init - dma information initialize - * - */ -static int __init rk28_dma_init(void) -{ - int ret; - int i; - - printk(KERN_INFO "enter dwdma init\n"); - - for (i = 0; i < MAX_DMA_CHANNELS; i++) { - rk2818_dma[i].dma_t.irqHandle = NULL; - rk2818_dma[i].dma_t.data = NULL; - rk2818_dma[i].dma_t.sg = NULL; - rk2818_dma[i].dma_t.addr = NULL; - rk2818_dma[i].dma_t.count = 0; - rk2818_dma[i].dma_t.d_ops = &rk2818_dma_ops; - dma_add(i, &rk2818_dma[i].dma_t); - - rk2818_dma[i].dma_llp_vir = NULL; - rk2818_dma[i].dma_llp_phy = 0; - rk2818_dma[i].residue = 0; - rk2818_dma[i].length = 0; - rk2818_dma[i].tasklet_flag = 0; - spin_lock_init(&rk2818_dma[i].lock); - } - - /* clear all interrupts */ - write_dma_reg(DWDMA_ClearBlock, 0x3f3f); - write_dma_reg(DWDMA_ClearTfr, 0x3f3f); - write_dma_reg(DWDMA_ClearSrcTran, 0x3f3f); - write_dma_reg(DWDMA_ClearDstTran, 0x3f3f); - write_dma_reg(DWDMA_ClearErr, 0x3f3f); - - /*mask all interrupts*/ - write_dma_reg(DWDMA_MaskBlock, 0x3f00); - write_dma_reg(DWDMA_MaskSrcTran, 0x3f00); - write_dma_reg(DWDMA_MaskDstTran, 0x3f00); - write_dma_reg(DWDMA_MaskErr, 0x3f00); - - /*unmask transfer completion interrupt*/ - //UN_MASK_DWDMA_ALL_TRF_INTR; - MASK_DWDMA_ALL_TRF_INTR; - - ret = request_irq(RK28_DMA_IRQ_NUM, rk28_dma_irq_handler, 0, "DMA", NULL); - if (ret < 0) { - printk(KERN_CRIT "Can't register IRQ for DMA\n"); - return ret; - } - - tasklet_init(&rk2818_dma_tasklet, rk28_dma_tasklet, 0); - - /* enable DMA module */ - write_dma_reg(DWDMA_DmaCfgReg, 0x01); - - printk(KERN_INFO "exit dwdma init\n"); - - return 0; -} -arch_initcall(rk28_dma_init); - -MODULE_AUTHOR("nzy@rock-chips.com"); -MODULE_DESCRIPTION("Driver for rk2818 dma device"); -MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-rk2818/gpio.c b/arch/arm/mach-rk2818/gpio.c deleted file mode 100644 index 6ff84bd07906..000000000000 --- a/arch/arm/mach-rk2818/gpio.c +++ /dev/null @@ -1,1335 +0,0 @@ -/* arch/arm/mach-rk2818/gpio.c - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#define to_rk2818_gpio_chip(c) container_of(c, struct rk2818_gpio_chip, chip) - -struct rk2818_gpio_chip { - struct gpio_chip chip; /*RK2818Ïà¹ØGPIOº¯Êý²Ù×÷ºÍÂß¼­ÐÅÏ¢*/ - struct rk2818_gpio_chip *next; /* Bank sharing same clock */ - struct rk2818_gpio_bank *bank; /* Bank definition */ - unsigned char __iomem *regbase; /* Base of register bank */ -}; - -static int gpio_banks;//GPIO×éÊý -static int gpio_banksInGrp;//num of GPIOS.eg:GPIO0_X or GPIO1_X(X=A\B\C\D) -/* - * This lock class tells lockdep that GPIO irqs are in a different - * category than their parents, so it won't report false recursion. - */ -static struct lock_class_key gpio_lock_class; - -static void rk2818_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip); -static void rk2818_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val); -static int rk2818_gpiolib_get(struct gpio_chip *chip, unsigned offset); -static int rk2818_gpiolib_direction_output(struct gpio_chip *chip, - unsigned offset, int val); -static int rk2818_gpiolib_direction_input(struct gpio_chip *chip, - unsigned offset); -static int rk2818_gpiolib_PullUpDown(struct gpio_chip *chip, unsigned offset, unsigned value); -static int rk2818_gpiolib_to_irq(struct gpio_chip *chip, - unsigned offset); -/* -ÉùÃ÷Á˽ṹÌårk2818gpio_chipÊý×飬²¢×¢²áÁËGPIOÏà¹Ø²Ù×÷ -µÄ»Øµ÷º¯ÊýºÍÏà¹ØÂß¼­ÐÅÏ¢¡£ -*/ -#define RK2818_GPIO_CHIP(name, base_gpio, nr_gpio) \ - { \ - .chip = { \ - .label = name, \ - .direction_input = rk2818_gpiolib_direction_input, \ - .direction_output = rk2818_gpiolib_direction_output, \ - .get = rk2818_gpiolib_get, \ - .set = rk2818_gpiolib_set, \ - .pull_updown = rk2818_gpiolib_PullUpDown, \ - .dbg_show = rk2818_gpiolib_dbg_show, \ - .to_irq = rk2818_gpiolib_to_irq, \ - .base = base_gpio, \ - .ngpio = nr_gpio, \ - }, \ - } - -static struct rk2818_gpio_chip rk2818gpio_chip[] = { - RK2818_GPIO_CHIP("A", 0*NUM_GROUP + PIN_BASE, NUM_GROUP), - RK2818_GPIO_CHIP("B", 1*NUM_GROUP + PIN_BASE, NUM_GROUP), - RK2818_GPIO_CHIP("C", 2*NUM_GROUP + PIN_BASE, NUM_GROUP), - RK2818_GPIO_CHIP("D", 3*NUM_GROUP + PIN_BASE, NUM_GROUP), - RK2818_GPIO_CHIP("A", 4*NUM_GROUP + PIN_BASE, NUM_GROUP), - RK2818_GPIO_CHIP("B", 5*NUM_GROUP + PIN_BASE, NUM_GROUP), - RK2818_GPIO_CHIP("C", 6*NUM_GROUP + PIN_BASE, NUM_GROUP), - RK2818_GPIO_CHIP("D", 7*NUM_GROUP + PIN_BASE, NUM_GROUP), -}; -static u32 wakeups[MAX_GPIO_BANKS]; -static u32 wakeupsDepth[MAX_GPIO_BANKS]; -/*---------------------------------------------------------------------- -Name : rk2818_gpio_write -Desc : ÍùÖ¸¶¨¼Ä´æÆ÷дÈëÖ¸¶¨Öµ -Params : ÊäÈë²ÎÊý: - regbase :Ö¸¶¨¼Ä´æÆ÷µÄ»ùµØÖ· - regOff :Ö¸¶¨¼Ä´æÆ÷µÄÆ«ÒƵØÖ· - val :Ö¸¶¨Ð´ÈëµÄÊýÖµ - Êä³ö²ÎÊý: - ÎÞ -Return : - ÎÞ -----------------------------------------------------------------------*/ -static inline void rk2818_gpio_write(unsigned char __iomem *regbase, unsigned int regOff,unsigned int val) -{ - __raw_writel(val,regbase + regOff); - return ; -} - -/*---------------------------------------------------------------------- -Name : rk2818_gpio_read -Desc : ¶ÁÈ¡Ö¸¶¨¼Ä´æÆ÷µÄÊýÖµ -Params : ÊäÈë²ÎÊý: - regbase :Ö¸¶¨¼Ä´æÆ÷µÄ»ùµØÖ· - regOff :Ö¸¶¨¼Ä´æÆ÷µÄÆ«ÒƵØÖ· - Êä³ö²ÎÊý: - ÎÞ -Return : - ¶ÁÈ¡µ½µÄÊýÖµ -----------------------------------------------------------------------*/ -static inline unsigned int rk2818_gpio_read(unsigned char __iomem *regbase, unsigned int regOff) -{ - return __raw_readl(regbase + regOff); -} - -/*---------------------------------------------------------------------- -Name : rk2818_gpio_bitOp -Desc : ¶ÔÖ¸¶¨¼Ä´æÆ÷½øÐÐÂß¼­ÔËËã -Params : ÊäÈë²ÎÊý: - regbase :Ö¸¶¨¼Ä´æÆ÷µÄ»ùµØÖ· - regOff :Ö¸¶¨¼Ä´æÆ÷µÄÆ«ÒƵØÖ· - mask :ÆÁ±Îλ - opFlag :0--½øÐÐÓë0ÔËËã;1--½øÐлò1ÔËËã - Êä³ö²ÎÊý: - ÎÞ -Return : - ÎÞ -----------------------------------------------------------------------*/ -static inline void rk2818_gpio_bitOp(unsigned char __iomem *regbase, unsigned int regOff,unsigned int mask,unsigned char opFlag) -{ - unsigned int valTemp = 0; - unsigned char __iomem *regAddr = regbase + regOff; - - if(opFlag == 0)//¶Ô¼Ä´æÆ÷ÏàӦλ½øÐÐÓë0²Ù×÷ - { - valTemp = __raw_readl(regAddr); - valTemp &= (~mask); - //printk(KERN_INFO "rk2818_gpio_bitOp--0:regAddr=%x,valTemp=%x\n",regAddr,valTemp); - __raw_writel(valTemp,regAddr); - } - else if(opFlag == 1)//¶Ô¼Ä´æÆ÷ÏàӦλ½øÐлò1²Ù×÷ - { - valTemp = __raw_readl(regAddr); - valTemp |= mask; - //printk(KERN_INFO "rk2818_gpio_bitOp--1:regAddr=%x,valTemp=%x\n",regAddr,valTemp); - __raw_writel(valTemp,regAddr); - } - - return; -} - -/*---------------------------------------------------------------------- -Name : GPIOSetPinDirection -Desc : ÉèÖö˿ڷ½Ïò£¬PA¡¢PEĬÈÏΪDebounce·½Ê½ -Params : ÊäÈë²ÎÊý: - chip :rk2818µÄÊôÐÔchip£¬Èç&rk2818_gpio->chip - mask :¼Ä´æÆ÷ÆÁ±Îλ - direction :ÊäÈëÊä³ö·½Ïò 0--ÊäÈë; 1--Êä³ö - Êä³ö²ÎÊý: - ÎÞ -Return : - 0 --- ³É¹¦ - -1 --- ʧ°Ü -----------------------------------------------------------------------*/ -static int GPIOSetPinDirection(struct gpio_chip *chip, unsigned int mask,eGPIOPinDirection_t direction) -{ - struct rk2818_gpio_chip *rk2818_gpio = to_rk2818_gpio_chip(chip); - unsigned char __iomem *gpioRegBase = rk2818_gpio->regbase; - - if(!rk2818_gpio || !gpioRegBase) - { - return -1; - } - - if(strcmp(rk2818_gpio->chip.label,"A") == 0) - { - rk2818_gpio_bitOp(gpioRegBase,GPIO_SWPORTA_DDR,mask,direction); - rk2818_gpio_bitOp(gpioRegBase,GPIO_DEBOUNCE,mask,1); - } - else if(strcmp(rk2818_gpio->chip.label,"B") == 0) - { - rk2818_gpio_bitOp(gpioRegBase,GPIO_SWPORTB_DDR,mask,direction); - } - else if(strcmp(rk2818_gpio->chip.label,"C") == 0) - { - rk2818_gpio_bitOp(gpioRegBase,GPIO_SWPORTC_DDR,mask,direction); - } - else if(strcmp(rk2818_gpio->chip.label,"D") == 0) - { - rk2818_gpio_bitOp(gpioRegBase,GPIO_SWPORTD_DDR,mask,direction); - } - else - { - return -1; - } - return 0; - -} - -/*---------------------------------------------------------------------- -Name : GPIOSetPinLevel -Desc : ÉèÖö˿ڵçƽ -Params : ÊäÈë²ÎÊý: - chip :rk2818µÄÊôÐÔchip£¬Èç&rk2818_gpio->chip - mask :¼Ä´æÆ÷ÆÁ±Îλ - level :µçƽ 0:low 1:high - Êä³ö²ÎÊý: - ÎÞ -Return : - 0 --- ³É¹¦ - -1 --- ʧ°Ü -----------------------------------------------------------------------*/ -static int GPIOSetPinLevel(struct gpio_chip *chip, unsigned int mask,eGPIOPinLevel_t level) -{ - struct rk2818_gpio_chip *rk2818_gpio = to_rk2818_gpio_chip(chip); - unsigned char __iomem *gpioRegBase = rk2818_gpio->regbase; - - if(!rk2818_gpio || !gpioRegBase) - { - return -1; - } - - if(strcmp(rk2818_gpio->chip.label,"A") == 0) - { - rk2818_gpio_bitOp(gpioRegBase,GPIO_SWPORTA_DDR,mask,1); - rk2818_gpio_bitOp(gpioRegBase,GPIO_SWPORTA_DR,mask,level); - } - else if(strcmp(rk2818_gpio->chip.label,"B") == 0) - { - rk2818_gpio_bitOp(gpioRegBase,GPIO_SWPORTB_DDR,mask,1); - rk2818_gpio_bitOp(gpioRegBase,GPIO_SWPORTB_DR,mask,level); - } - else if(strcmp(rk2818_gpio->chip.label,"C") == 0) - { - rk2818_gpio_bitOp(gpioRegBase,GPIO_SWPORTC_DDR,mask,1); - rk2818_gpio_bitOp(gpioRegBase,GPIO_SWPORTC_DR,mask,level); - } - else if(strcmp(rk2818_gpio->chip.label,"D") == 0) - { - rk2818_gpio_bitOp(gpioRegBase,GPIO_SWPORTD_DDR,mask,1); - rk2818_gpio_bitOp(gpioRegBase,GPIO_SWPORTD_DR,mask,level); - } - else - { - return -1; - } - return 0; -} - -/*---------------------------------------------------------------------- -Name : GPIOGetPinLevel -Desc : »ñÈ¡¶Ë¿Úµçƽ -Params : ÊäÈë²ÎÊý: - chip :rk2818µÄÊôÐÔchip£¬Èç&rk2818_gpio->chip - mask :¼Ä´æÆ÷ÆÁ±Îλ - Êä³ö²ÎÊý: - ÎÞ -Return : - 0 --- µÍµçƽ - 1 --- ¸ßµçƽ - -1 --- ʧ°Ü -----------------------------------------------------------------------*/ -static int GPIOGetPinLevel(struct gpio_chip *chip, unsigned int mask) -{ - unsigned int valTemp; - struct rk2818_gpio_chip *rk2818_gpio = to_rk2818_gpio_chip(chip); - unsigned char __iomem *gpioRegBase = rk2818_gpio->regbase; - - if(!rk2818_gpio || !gpioRegBase) - { - return -1; - } - - if(strcmp(rk2818_gpio->chip.label,"A") == 0) - { - valTemp = rk2818_gpio_read(gpioRegBase,GPIO_EXT_PORTA); - } - else if(strcmp(rk2818_gpio->chip.label,"B") == 0) - { - valTemp = rk2818_gpio_read(gpioRegBase,GPIO_EXT_PORTB); - } - else if(strcmp(rk2818_gpio->chip.label,"C") == 0) - { - valTemp = rk2818_gpio_read(gpioRegBase,GPIO_EXT_PORTC); - } - else if(strcmp(rk2818_gpio->chip.label,"D") == 0) - { - valTemp = rk2818_gpio_read(gpioRegBase,GPIO_EXT_PORTD); - } - else - { - return -1; - } -//printk(KERN_INFO "GPIOGetPinLevel:%s,%x,%x,%x\n",rk2818_gpio->chip.label,rk2818_gpio->regbase,mask,valTemp); - return ((valTemp & mask) != 0); -} - -/*---------------------------------------------------------------------- -Name : GPIOEnableIntr -Desc : ÉèÖö˿ڵÄÖжϽţ¬Ö»ÓÐPA¡¢PE¿Ú²Å¿ÉÒÔÖÐ¶Ï -Params : ÊäÈë²ÎÊý: - chip :rk2818µÄÊôÐÔchip£¬Èç&rk2818_gpio->chip - mask :¼Ä´æÆ÷ÆÁ±Îλ - Êä³ö²ÎÊý: - ÎÞ -Return : - 0 --- ³É¹¦ - -1 --- ʧ°Ü -----------------------------------------------------------------------*/ -static int GPIOEnableIntr(struct gpio_chip *chip, unsigned int mask) -{ - struct rk2818_gpio_chip *rk2818_gpio = to_rk2818_gpio_chip(chip); - unsigned char __iomem *gpioRegBase = rk2818_gpio->regbase; - - if(!rk2818_gpio || !gpioRegBase) - { - return -1; - } - - rk2818_gpio_bitOp(gpioRegBase,GPIO_INTEN,mask,1); - return 0; -} - -/*---------------------------------------------------------------------- -Name : GPIODisableIntr -Desc : ÉèÖö˿ڲ»ÄÜÖжϣ¬Ö»ÓÐPA¡¢PE²Å¿ÉÒÔÖÐ¶Ï -Params : ÊäÈë²ÎÊý: - chip :rk2818µÄÊôÐÔchip£¬Èç&rk2818_gpio->chip - mask :¼Ä´æÆ÷ÆÁ±Îλ - Êä³ö²ÎÊý: - ÎÞ -Return : - 0 --- ³É¹¦ - -1 --- ʧ°Ü -----------------------------------------------------------------------*/ -static int GPIODisableIntr(struct gpio_chip *chip, unsigned int mask) -{ - struct rk2818_gpio_chip *rk2818_gpio = to_rk2818_gpio_chip(chip); - unsigned char __iomem *gpioRegBase = rk2818_gpio->regbase; - - if(!rk2818_gpio || !gpioRegBase) - { - return -1; - } - - rk2818_gpio_bitOp(gpioRegBase,GPIO_INTEN,mask,0); - return 0; -} -#if 0 -/*---------------------------------------------------------------------- -Name : GPIOClearIntr -Desc : Çå³ýÖжϿڱêÖ¾£¬Ö»ÓÐÔÚ±ßÑØÖжÏʱÓÐЧ£¬µçƽÖжÏÎÞЧ -Params : ÊäÈë²ÎÊý: - chip :rk2818µÄÊôÐÔchip£¬Èç&rk2818_gpio->chip - mask :¼Ä´æÆ÷ÆÁ±Îλ - Êä³ö²ÎÊý: - ÎÞ -Return : - 0 --- ³É¹¦ - -1 --- ʧ°Ü -----------------------------------------------------------------------*/ -static int GPIOClearIntr(struct gpio_chip *chip, unsigned int mask) -{ - struct rk2818_gpio_chip *rk2818_gpio = to_rk2818_gpio_chip(chip); - unsigned char __iomem *gpioRegBase = rk2818_gpio->regbase; - - if(!rk2818_gpio || !gpioRegBase) - { - return -1; - } - - rk2818_gpio_bitOp(gpioRegBase,GPIO_PORTS_EOI,mask,1); - return 0; -} -#endif -/*---------------------------------------------------------------------- -Name : GPIOInmarkIntr -Desc : ÏÈÆÁ±ÎÆäÖеÄij¸öÖжϣ¬ÔÚµçƽÖжÏÖбØÐëÒªÕâÑù×ö£¬·ñÔò»á½Ó×ÅÖÐ¶Ï -Params : ÊäÈë²ÎÊý: - chip :rk2818µÄÊôÐÔchip£¬Èç&rk2818_gpio->chip - mask :¼Ä´æÆ÷ÆÁ±Îλ - Êä³ö²ÎÊý: - ÎÞ -Return : - 0 --- ³É¹¦ - -1 --- ʧ°Ü -----------------------------------------------------------------------*/ -static int GPIOInmarkIntr(struct gpio_chip *chip, unsigned int mask) -{ - struct rk2818_gpio_chip *rk2818_gpio = to_rk2818_gpio_chip(chip); - unsigned char __iomem *gpioRegBase = rk2818_gpio->regbase; - - if(!rk2818_gpio || !gpioRegBase) - { - return -1; - } - - rk2818_gpio_bitOp(gpioRegBase,GPIO_INTMASK,mask,1); - return 0; -} - -/*---------------------------------------------------------------------- -Name : GPIOUnInmarkIntr -Desc : ²»ÆÁ±Îij¸öÖжϣ¬Õë¶ÔµÄÊǵçƽÖÐ¶Ï -Params : ÊäÈë²ÎÊý: - chip :rk2818µÄÊôÐÔchip£¬Èç&rk2818_gpio->chip - mask :¼Ä´æÆ÷ÆÁ±Îλ - Êä³ö²ÎÊý: - ÎÞ -Return : - 0 --- ³É¹¦ - -1 --- ʧ°Ü -----------------------------------------------------------------------*/ -static int GPIOUnInmarkIntr(struct gpio_chip *chip, unsigned int mask) -{ - struct rk2818_gpio_chip *rk2818_gpio = to_rk2818_gpio_chip(chip); - unsigned char __iomem *gpioRegBase = rk2818_gpio->regbase; - - if(!rk2818_gpio || !gpioRegBase) - { - return -1; - } - - rk2818_gpio_bitOp(gpioRegBase,GPIO_INTMASK,mask,0); - return 0; -} - -/*---------------------------------------------------------------------- -Name : GPIOSetIntrType -Desc : ÉèÖÃÖжÏÀàÐÍ -Params : ÊäÈë²ÎÊý: - chip :rk2818µÄÊôÐÔchip£¬Èç&rk2818_gpio->chip - mask :¼Ä´æÆ÷ÆÁ±Îλ - IntType :Öжϴ¥·¢ÀàÐÍ - Êä³ö²ÎÊý: - ÎÞ -Return : - 0 --- ³É¹¦ - -1 --- ʧ°Ü -----------------------------------------------------------------------*/ -static int GPIOSetIntrType(struct gpio_chip *chip, unsigned int mask, eGPIOIntType_t IntType) -{ - struct rk2818_gpio_chip *rk2818_gpio = to_rk2818_gpio_chip(chip); - unsigned char __iomem *gpioRegBase = rk2818_gpio->regbase; - - - if(!rk2818_gpio || !gpioRegBase) - { - return -1; - } - - switch ( IntType ) - { - case GPIOLevelLow: - rk2818_gpio_bitOp(gpioRegBase,GPIO_INT_POLARITY,mask,0); - rk2818_gpio_bitOp(gpioRegBase,GPIO_INTTYPE_LEVEL,mask,0); - break; - case GPIOLevelHigh: - rk2818_gpio_bitOp(gpioRegBase,GPIO_INTTYPE_LEVEL,mask,0); - rk2818_gpio_bitOp(gpioRegBase,GPIO_INT_POLARITY,mask,1); - break; - case GPIOEdgelFalling: - rk2818_gpio_bitOp(gpioRegBase,GPIO_INTTYPE_LEVEL,mask,1); - rk2818_gpio_bitOp(gpioRegBase,GPIO_INT_POLARITY,mask,0); - break; - case GPIOEdgelRising: - rk2818_gpio_bitOp(gpioRegBase,GPIO_INTTYPE_LEVEL,mask,1); - rk2818_gpio_bitOp(gpioRegBase,GPIO_INT_POLARITY,mask,1); - break; - default: - return(-1); - } - return(0); -} - -/*---------------------------------------------------------------------- -Name : GPIOPullUpDown -Desc : ¶ÔÆäÖеĽÅλ½øÐж˿ÚÉÏÀ­»òÏÂÀ­³õʼ»¯ -Params : ÊäÈë²ÎÊý: - chip :rk2818µÄÊôÐÔchip£¬Èç&rk2818_gpio->chip - offset :Æ«ÒÆÖµ - GPIOPullUpDown :0-- Õý³£;1--ÉÏÀ­;2--ÏÂÀ­;3--δ³õʼ»¯ - Êä³ö²ÎÊý: - ÎÞ -Return : - 0 --- ³É¹¦ - -1 --- ʧ°Ü -----------------------------------------------------------------------*/ -static int GPIOPullUpDown(struct gpio_chip *chip, unsigned int offset, eGPIOPullType_t GPIOPullUpDown) -{ - unsigned char temp=0; - struct rk2818_gpio_chip *rk2818_gpio = to_rk2818_gpio_chip(chip); - unsigned char __iomem *pAPBRegBase = (unsigned char __iomem *)RK2818_REGFILE_BASE; - unsigned int mask1 = 0,mask2 = 0; - - if(!rk2818_gpio || !pAPBRegBase) - { - return -1; - } - - if(offset >= 8) - { - return -1; - } - - if(rk2818_gpio->bank->id%2 == 1) - { - temp = 16; - } - mask1 = 0x03<<(2*offset+temp); - mask2 = GPIOPullUpDown <<(2*offset+temp); - if(rk2818_gpio->bank->id==RK2818_ID_PIOA || rk2818_gpio->bank->id==RK2818_ID_PIOB) - { - - rk2818_gpio_bitOp(pAPBRegBase,GPIO0_AB_PU_CON,mask1,0); - rk2818_gpio_bitOp(pAPBRegBase,GPIO0_AB_PU_CON,mask2,1); - } - else if(rk2818_gpio->bank->id==RK2818_ID_PIOC || rk2818_gpio->bank->id==RK2818_ID_PIOD) - { - rk2818_gpio_bitOp(pAPBRegBase,GPIO0_CD_PU_CON,mask1,0); - rk2818_gpio_bitOp(pAPBRegBase,GPIO0_CD_PU_CON,mask2,1); - } - else if(rk2818_gpio->bank->id==RK2818_ID_PIOE || rk2818_gpio->bank->id==RK2818_ID_PIOF) - { - rk2818_gpio_bitOp(pAPBRegBase,GPIO1_AB_PU_CON,mask1,0); - rk2818_gpio_bitOp(pAPBRegBase,GPIO1_AB_PU_CON,mask2,1); - } - else if(rk2818_gpio->bank->id==RK2818_ID_PIOG|| rk2818_gpio->bank->id==RK2818_ID_PIOH) - { - rk2818_gpio_bitOp(pAPBRegBase,GPIO1_CD_PU_CON,mask1,0); - rk2818_gpio_bitOp(pAPBRegBase,GPIO1_CD_PU_CON,mask2,1); - } - else - { - return -1; - } - return 0; -} - -/*---------------------------------------------------------------------- -Name : pin_to_gpioChip -Desc : ¸ù¾ÝÊäÈëµÄPINÖµËã³ö¶ÔÓ¦µÄchip½á¹¹ÌåÊ×µØÖ· -Params : ÊäÈë²ÎÊý: - pin :ÊäÈëµÄPINÖµ - Êä³ö²ÎÊý: - ÎÞ -Return : - ·µ»Ø¶ÔÓ¦µÄchip½á¹¹ÌåÊ×µØÖ·£¬Ê§°ÜÔò·µ»ØNULL -----------------------------------------------------------------------*/ -static inline struct gpio_chip *pin_to_gpioChip(unsigned pin) -{ - if(pin < PIN_BASE) - return NULL; - - pin -= PIN_BASE; - pin /= NUM_GROUP; - if (likely(pin < gpio_banks)) - return &(rk2818gpio_chip[pin].chip); - return NULL; -} - -/*---------------------------------------------------------------------- -Name : pin_to_mask -Desc : ¸ù¾ÝÊäÈëµÄPINÖµËã³ö¶ÔÓ¦µÄÆÁ±Îλ -Params : ÊäÈë²ÎÊý: - pin :ÊäÈëµÄPINÖµ - Êä³ö²ÎÊý: - ÎÞ -Return : - ·µ»Ø¶ÔÓ¦µÄÆÁ±Îλֵ£¬0±íʾʧ°Ü -----------------------------------------------------------------------*/ -static inline unsigned pin_to_mask(unsigned pin) -{ - if(pin < PIN_BASE) - return 0; - pin -= PIN_BASE; - return 1ul << (pin % NUM_GROUP); -} - -/*---------------------------------------------------------------------- -Name : offset_to_mask -Desc : ¸ù¾ÝÆ«ÒÆÁ¿Ëã³ö¶ÔÓ¦µÄÆÁ±Îλֵ -Params : ÊäÈë²ÎÊý: - offset :Æ«ÒÆÁ¿ - Êä³ö²ÎÊý: - ÎÞ -Return : - ·µ»Ø¶ÔÓ¦µÄÆÁ±Îλֵ -----------------------------------------------------------------------*/ -static inline unsigned offset_to_mask(unsigned offset) -{ - return 1ul << (offset% NUM_GROUP); -} -static int gpio_irq_set_wake(unsigned irq, unsigned state) -{ - unsigned int pin = irq_to_gpio(irq); - unsigned mask = pin_to_mask(pin); - unsigned bank = (pin - PIN_BASE) / NUM_GROUP; - - if (unlikely(bank >= MAX_GPIO_BANKS)) - return -EINVAL; - - if(rk2818gpio_chip[bank].bank->id == RK2818_ID_PIOA) - { - set_irq_wake(IRQ_NR_GPIO0, state); - } - else if(rk2818gpio_chip[bank].bank->id == RK2818_ID_PIOE) - { - set_irq_wake(IRQ_NR_GPIO1, state); - } - else - { - return 0; - } - - if (state) - wakeups[bank] |= mask; - else - wakeups[bank] &= ~mask; - - return 0; - -} - -static int rk2818_gpio_resume(struct sys_device *dev) -{ - int i; - - for (i = 0; i < gpio_banks; i+=gpio_banksInGrp) { - printk("rk2818_gpio_resume:wakeups[%d]=%d,wakeupsDepth[%d]=%d\n", - i,wakeups[i],i,wakeupsDepth[i]); - if (!wakeups[i] && wakeupsDepth[i]) - { - wakeupsDepth[i] = 0; - clk_enable(rk2818gpio_chip[i].bank->clock); - } - } - - return 0; -} - -static int rk2818_gpio_suspend(struct sys_device *dev, pm_message_t mesg) -{ - int i; - - for (i = 0; i < gpio_banks; i+=gpio_banksInGrp) { - printk("rk2818_gpio_suspend:wakeups[%d]=%d,wakeupsDepth[%d]=%d\n", - i,wakeups[i],i,wakeupsDepth[i]); - if (!wakeups[i] && !wakeupsDepth[i]) - { - wakeupsDepth[i] = 1; - clk_disable(rk2818gpio_chip[i].bank->clock); - } - else if(wakeups[i]) - rk2818_gpio_write(rk2818gpio_chip[i].regbase,GPIO_INTEN,wakeups[i]); - } - - return 0; -} - - #if 0 -int rk2818_set_gpio_input(unsigned pin, int use_pullup) -{ - struct gpio_chip *chip = pin_to_gpioChip(pin); - unsigned mask = pin_to_mask(pin); - unsigned offset = 0; - - if (!chip || !mask) - return -EINVAL; - - offset = (pin-PIN_BASE) % NUM_GROUP; - - if(GPIOSetPinDirection(chip,mask,GPIO_IN) == 0) - { - if(use_pullup) - { - return GPIOPullUpDown(chip,offset,GPIOPullUp); - } - else - { - return GPIOPullUpDown(chip,offset,GPIOPullDown); - } - } - else - { - return -1; - } -} - -/* - * mux the pin to the gpio controller (instead of "A" or "B" peripheral), - * and configure it for an output. - */ -int rk2818_set_gpio_output(unsigned pin, int value) -{ - struct gpio_chip *chip = pin_to_gpioChip(pin); - unsigned mask = pin_to_mask(pin); - - if (!chip || !mask) - return -EINVAL; - - if(GPIOSetPinDirection(chip,mask,GPIO_OUT) == 0) - { - return GPIOSetPinLevel(chip,mask,value); - } - else - { - return -1; - } -} - -/* - * assuming the pin is muxed as a gpio output, set its value. - */ -int rk2818_set_gpio_value(unsigned pin, int value) -{ - struct gpio_chip *chip = pin_to_gpioChip(pin); - unsigned mask = pin_to_mask(pin); - - if (!chip || !mask) - return -EINVAL; - - GPIOSetPinLevel(chip,mask,value); - - return 0; -} - -/* - * read the pin's value (works even if it's not muxed as a gpio). - */ -int rk2818_get_gpio_value(unsigned pin) -{ - struct gpio_chip *chip = pin_to_gpioChip(pin); - unsigned mask = pin_to_mask(pin); - - if (!chip || !mask) - return -EINVAL; - - return GPIOGetPinLevel(chip,mask); -} -#endif -/*--------------------------------------------------------------------------*/ - - - /*---------------------------------------------------------------------- -Name : gpio_irq_disable -Desc : ²»Ê¹ÄÜÖжϣ¬Ö»ÓÐPA¡¢PE²Å¿ÉÒÔÖÐ¶Ï -Params : ÊäÈë²ÎÊý: - irq :Ö¸¶¨²»Ê¹ÄܵÄIRQ - Êä³ö²ÎÊý: - ÎÞ -Return : - ÎÞ -----------------------------------------------------------------------*/ - static void gpio_irq_disable(unsigned irq) -{ - unsigned int pin = irq_to_gpio(irq); - struct gpio_chip *chip = pin_to_gpioChip(pin); - unsigned mask = pin_to_mask(pin); - - if(chip && mask) - GPIODisableIntr(chip,mask); - - return; -} - -/*---------------------------------------------------------------------- -Name : gpio_irq_enable -Desc : ʹÄÜÖжϣ¬Ö»ÓÐPA¡¢PE²Å¿ÉÒÔÖÐ¶Ï -Params : ÊäÈë²ÎÊý: - irq :Ö¸¶¨Ê¹ÄܵÄIRQ - Êä³ö²ÎÊý: - ÎÞ -Return : - ÎÞ -----------------------------------------------------------------------*/ -static void gpio_irq_enable(unsigned irq) -{ - unsigned int pin = irq_to_gpio(irq); - struct gpio_chip *chip = pin_to_gpioChip(pin); - unsigned mask = pin_to_mask(pin); - - if(chip && mask) - GPIOEnableIntr(chip,mask); - - return; -} - -/*---------------------------------------------------------------------- -Name : gpio_irq_mask -Desc : ÆÁ±ÎÖÐ¶Ï -Params : ÊäÈë²ÎÊý: - irq :Ö¸¶¨ÆÁ±ÎµÄIRQ - Êä³ö²ÎÊý: - ÎÞ -Return : - ÎÞ -----------------------------------------------------------------------*/ -static void gpio_irq_mask(unsigned irq) -{ - unsigned int pin = irq_to_gpio(irq); - struct gpio_chip *chip = pin_to_gpioChip(pin); - unsigned mask = pin_to_mask(pin); - - if(chip && mask) - GPIOInmarkIntr(chip,mask); -} - -/*---------------------------------------------------------------------- -Name : gpio_irq_unmask -Desc : ²»ÆÁ±ÎÖÐ¶Ï -Params : ÊäÈë²ÎÊý: - irq :Ö¸¶¨²»ÆÁ±ÎµÄIRQ - Êä³ö²ÎÊý: - ÎÞ -Return : - ÎÞ -----------------------------------------------------------------------*/ -static void gpio_irq_unmask(unsigned irq) -{ - unsigned int pin = irq_to_gpio(irq); - struct gpio_chip *chip = pin_to_gpioChip(pin); - unsigned mask = pin_to_mask(pin); - - if (chip && mask) - GPIOUnInmarkIntr(chip,mask); -} -/*---------------------------------------------------------------------- -Name : gpio_irq_type -Desc : ÉèÖÃÖжÏÀàÐÍ -Params : ÊäÈë²ÎÊý: - irq :Ö¸¶¨µÄIRQ - type :Ö¸¶¨µÄÖжÏÀàÐÍ - Êä³ö²ÎÊý: - ÎÞ -Return : - 0 --- ³É¹¦ - -22 --- ʧ°Ü -----------------------------------------------------------------------*/ -static int gpio_irq_type(unsigned irq, unsigned type) -{ - unsigned int pin = irq_to_gpio(irq); - struct gpio_chip *chip = pin_to_gpioChip(pin); - unsigned mask = pin_to_mask(pin); - - if(!chip || !mask) - return -EINVAL; - //ÉèÖÃΪÖжÏ֮ǰ£¬±ØÐëÏÈÉèÖÃΪÊäÈë״̬ - GPIOSetPinDirection(chip,mask,GPIO_IN); - - switch (type) { - case IRQ_TYPE_NONE: - break; - case IRQ_TYPE_EDGE_RISING: - GPIOSetIntrType(chip,mask,GPIOEdgelRising); - break; - case IRQ_TYPE_EDGE_FALLING: - GPIOSetIntrType(chip,mask,GPIOEdgelFalling); - break; - case IRQ_TYPE_EDGE_BOTH: - break; - case IRQ_TYPE_LEVEL_HIGH: - GPIOSetIntrType(chip,mask,GPIOLevelHigh); - break; - case IRQ_TYPE_LEVEL_LOW: - GPIOSetIntrType(chip,mask,GPIOLevelLow); - break; - default: - return -EINVAL; - } - return 0; -} - -static struct irq_chip rk2818gpio_irqchip = { - .name = "RK2818_GPIOIRQ", - .enable = gpio_irq_enable, - .disable = gpio_irq_disable, - .mask = gpio_irq_mask, - .unmask = gpio_irq_unmask, - .set_type = gpio_irq_type, - .set_wake = gpio_irq_set_wake, -}; - -/*---------------------------------------------------------------------- -Name : gpio_irq_handler -Desc : ÖжÏ6»òÖжÏ7µÄ´¦Àíº¯Êý -Params : ÊäÈë²ÎÊý: - irq :±»´¥·¢µÄÖжϺÅ6»òÖжϺÅ7 - desc :ÖжϽṹÌå - Êä³ö²ÎÊý: - ÎÞ -Return : - ÎÞ -----------------------------------------------------------------------*/ -static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) -{ - unsigned pin,gpioToirq=0; - struct irq_desc *gpio; - struct rk2818_gpio_chip *rk2818_gpio; - unsigned char __iomem *gpioRegBase; - u32 isr; - - rk2818_gpio = get_irq_chip_data(irq); - gpioRegBase = rk2818_gpio->regbase; - - //ÆÁ±ÎÖжÏ6»ò7 - desc->chip->mask(irq); - //¶ÁÈ¡µ±Ç°ÖжÏ״̬£¬¼´²éѯ¾ßÌåÊÇGPIOµÄÄĸöPINÒýÆðµÄÖÐ¶Ï - isr = rk2818_gpio_read(gpioRegBase,GPIO_INT_STATUS); - if (!isr) { - desc->chip->unmask(irq); - return; - } - - pin = rk2818_gpio->chip.base; - gpioToirq = gpio_to_irq(pin); - gpio = &irq_desc[gpioToirq]; - - while (isr) { - if (isr & 1) { - //if (unlikely(gpio->depth)) { - /* - * The core ARM interrupt handler lazily disables IRQs so - * another IRQ must be generated before it actually gets - * here to be disabled on the GPIO controller. - */ - // gpio_irq_mask(gpioToirq); - //} - //else - { - unsigned int gpio_Int_Level = 0; - unsigned int mask = pin_to_mask(pin); - if(!mask) - break; - gpio_Int_Level = rk2818_gpio_read(gpioRegBase,GPIO_INTTYPE_LEVEL); - if(gpio_Int_Level == 0)//±íʾ´ËÖжÏÀàÐÍÊǵçƽÖÐ¶Ï - { - rk2818_gpio_bitOp(gpioRegBase,GPIO_INTMASK,mask,1); - } - generic_handle_irq(gpioToirq); - - if(gpio_Int_Level)//±íʾ´ËÖжÏÀàÐÍÊDZßÑØÖÐ¶Ï - { - rk2818_gpio_bitOp(gpioRegBase,GPIO_PORTS_EOI,mask,1); - } - else//±íʾ´ËÖжÏÀàÐÍÊǵçƽÖÐ¶Ï - { - rk2818_gpio_bitOp(gpioRegBase,GPIO_INTMASK,mask,0); - } - } - - } - pin++; - gpio++; - isr >>= 1; - gpioToirq = gpio_to_irq(pin); - } - - desc->chip->unmask(irq); - /* now it may re-trigger */ -} - - /*---------------------------------------------------------------------- -Name : rk2818_gpio_irq_setup -Desc : enable GPIO interrupt support. -Params : ÊäÈë²ÎÊý: - ÎÞ - Êä³ö²ÎÊý: - ÎÞ -Return : - ÎÞ -----------------------------------------------------------------------*/ -void __init rk2818_gpio_irq_setup(void) -{ - unsigned int i,j, pin,irq=IRQ_NR_GPIO0; - struct rk2818_gpio_chip *this; - - this = rk2818gpio_chip; - pin = NR_AIC_IRQS; - - for(i=0;i<2;i++) - { - rk2818_gpio_write(this->regbase,GPIO_INTEN,0); - for (j = 0; j < 8; j++) - { - lockdep_set_class(&irq_desc[pin+j].lock, &gpio_lock_class); - /* - * Can use the "simple" and not "edge" handler since it's - * shorter, and the AIC handles interrupts sanely. - */ - set_irq_chip(pin+j, &rk2818gpio_irqchip); - set_irq_handler(pin+j, handle_simple_irq); - set_irq_flags(pin+j, IRQF_VALID); - } - if(this->bank->id == RK2818_ID_PIOA) - { - irq = IRQ_NR_GPIO0; - - } - else if(this->bank->id == RK2818_ID_PIOE) - { - irq = IRQ_NR_GPIO1; - } - set_irq_chip_data(irq, this); - set_irq_chained_handler(irq, gpio_irq_handler); - this += 4; - pin += 8; - } - pr_info("rk2818_gpio_irq_setup: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); - -} - -/*---------------------------------------------------------------------- -Name : rk2818_gpiolib_direction_input -Desc : ÉèÖö˿ÚΪÊäÈë -Params : ÊäÈë²ÎÊý: - chip :rk2818µÄÊôÐÔchip£¬Èç&rk2818_gpio->chip - offset :¼Ä´æÆ÷λƫÒÆÁ¿ - Êä³ö²ÎÊý: - ÎÞ -Return : - 0 --- ³É¹¦ - -1 --- ʧ°Ü -----------------------------------------------------------------------*/ -static int rk2818_gpiolib_direction_input(struct gpio_chip *chip, - unsigned offset) -{ - unsigned mask = offset_to_mask(offset); - - return GPIOSetPinDirection(chip,mask,GPIO_IN); -} -/*---------------------------------------------------------------------- -Name : rk2818_gpiolib_direction_output -Desc : ÉèÖö˿ÚΪÊä³ö£¬ÇÒÉèÖõçƽ -Params : ÊäÈë²ÎÊý: - chip :rk2818µÄÊôÐÔchip£¬Èç&rk2818_gpio->chip - offset :¼Ä´æÆ÷λƫÒÆÁ¿ - val :0--µÍµçƽ;1--¸ßµçƽ - Êä³ö²ÎÊý: - ÎÞ -Return : - 0 --- ³É¹¦ - -1 --- ʧ°Ü -----------------------------------------------------------------------*/ -static int rk2818_gpiolib_direction_output(struct gpio_chip *chip, - unsigned offset, int val) -{ - unsigned mask = offset_to_mask(offset); - - if(GPIOSetPinDirection(chip,mask,GPIO_OUT) == 0) - { - return GPIOSetPinLevel(chip,mask,val); - } - else - { - return -1; - } -} - -/*---------------------------------------------------------------------- -Name : rk2818_gpiolib_PullUpDown -Desc : ¶ÔÆäÖеĽÅλ½øÐж˿ÚÉÏÀ­»òÏÂÀ­³õʼ»¯ -Params : ÊäÈë²ÎÊý: - chip :rk2818µÄÊôÐÔchip£¬Èç&rk2818_gpio->chip - offset :¼Ä´æÆ÷λƫÒÆÖµ - GPIOPullUpDown :0-- Õý³£;1--ÉÏÀ­;2--ÏÂÀ­;3--δ³õʼ»¯ - Êä³ö²ÎÊý: - ÎÞ -Return : - 0 --- ³É¹¦ - -1 --- ʧ°Ü -----------------------------------------------------------------------*/ -static int rk2818_gpiolib_PullUpDown(struct gpio_chip *chip, unsigned offset, unsigned val) -{ - return GPIOPullUpDown(chip, offset, val); -} -/*---------------------------------------------------------------------- -Name : rk2818_gpiolib_get -Desc : »ñÈ¡¶Ë¿Úµçƽ -Params : ÊäÈë²ÎÊý: - chip :rk2818µÄÊôÐÔchip£¬Èç&rk2818_gpio->chip - offset :¼Ä´æÆ÷λƫÒÆÖµ - Êä³ö²ÎÊý: - ÎÞ -Return : - 0 --- µÍµçƽ - 1 --- ¸ßµçƽ - -1 --- ʧ°Ü -----------------------------------------------------------------------*/ -static int rk2818_gpiolib_get(struct gpio_chip *chip, unsigned offset) -{ - unsigned mask = offset_to_mask(offset); - - return GPIOGetPinLevel(chip,mask); -} - -/*---------------------------------------------------------------------- -Name : rk2818_gpiolib_set -Desc : ÉèÖö˿ڵçƽ -Params : ÊäÈë²ÎÊý: - chip :rk2818µÄÊôÐÔchip£¬Èç&rk2818_gpio->chip - offset :¼Ä´æÆ÷λƫÒÆÖµ - Êä³ö²ÎÊý: - ÎÞ -Return : - ÎÞ -----------------------------------------------------------------------*/ -static void rk2818_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val) -{ - unsigned mask = offset_to_mask(offset); - - GPIOSetPinLevel(chip,mask,val); - return; -} - -/*---------------------------------------------------------------------- -Name : rk2818_gpiolib_to_irq -Desc : °ÑGPIOתΪIRQ -Params : ÊäÈë²ÎÊý: - chip :rk2818µÄÊôÐÔchip£¬Èç&rk2818_gpio->chip - offset :PINÆ«ÒÆÖµ - level :µçƽ 0:low 1:high - Êä³ö²ÎÊý: - ÎÞ -Return : - ÆäËûÖµ --- ¶ÔÓ¦µÄIRQÖµ - -6 --- ʧ°Ü -----------------------------------------------------------------------*/ -static int rk2818_gpiolib_to_irq(struct gpio_chip *chip, - unsigned offset) -{ - struct rk2818_gpio_chip *rk2818_gpio = to_rk2818_gpio_chip(chip); - - if(!rk2818_gpio) - { - return -1; - } - if(rk2818_gpio->bank->id==RK2818_ID_PIOA) - { - return offset + NR_AIC_IRQS; - } - else if(rk2818_gpio->bank->id==RK2818_ID_PIOE) - { - return offset + NR_AIC_IRQS + NUM_GROUP; - } - else - { - return -1; - } -} - -/*---------------------------------------------------------------------- -Name : rk2818_gpiolib_dbg_show -Desc : DBG -Params : ÊäÈë²ÎÊý: - s :Îļþ - chip :rk2818µÄÊôÐÔchip£¬Èç&rk2818_gpio->chip - Êä³ö²ÎÊý: - ÎÞ -Return : - ÎÞ -----------------------------------------------------------------------*/ -static void rk2818_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip) -{ - - int i; - - for (i = 0; i < chip->ngpio; i++) { - unsigned pin = chip->base + i; - struct gpio_chip *chip = pin_to_gpioChip(pin); - unsigned mask = pin_to_mask(pin); - const char *gpio_label; - - if(!chip ||!mask) - return; - - gpio_label = gpiochip_is_requested(chip, i); - if (gpio_label) { - seq_printf(s, "[%s] GPIO%s%d: ", - gpio_label, chip->label, i); - - if (!chip || !mask) - { - seq_printf(s, "!chip || !mask\t"); - return; - } - - GPIOSetPinDirection(chip,mask,GPIO_IN); - seq_printf(s, "pin=%d,level=%d\t", pin,GPIOGetPinLevel(chip,mask)); - seq_printf(s, "\t"); - } - } - - return; -} - -static struct sysdev_class rk2818_gpio_sysclass = { - .name = "gpio", - .suspend = rk2818_gpio_suspend, - .resume = rk2818_gpio_resume, -}; - -static struct sys_device rk2818_gpio_device = { - .cls = &rk2818_gpio_sysclass, -}; - -static int __init rk2818_gpio_sysinit(void) -{ - int ret = sysdev_class_register(&rk2818_gpio_sysclass); - if (ret == 0) - ret = sysdev_register(&rk2818_gpio_device); - return ret; -} - -arch_initcall(rk2818_gpio_sysinit); - - /*---------------------------------------------------------------------- -Name : rk2818_gpio_init -Desc : enable GPIO pin support. -Params : ÊäÈë²ÎÊý: - data :rk2818_gpio_bank½á¹¹Ìå - nr_banks :GPIO×éÊý - Êä³ö²ÎÊý: - ÎÞ -Return : - ÎÞ -----------------------------------------------------------------------*/ -void __init rk2818_gpio_init(struct rk2818_gpio_bank *data, int nr_banks) -{ - unsigned i; - const char clkId[2][6] = {"gpio0","gpio1"}; - struct rk2818_gpio_chip *rk2818_gpio, *last = NULL; - - BUG_ON(nr_banks > MAX_GPIO_BANKS); - - gpio_banks = nr_banks; - gpio_banksInGrp = nr_banks/2; - - for (i = 0; i < nr_banks; i++) { - - rk2818_gpio = &rk2818gpio_chip[i]; - rk2818_gpio->bank = &data[i]; - rk2818_gpio->bank->clock = clk_get(NULL,clkId[i/gpio_banksInGrp]); - rk2818_gpio->regbase = (unsigned char __iomem *)rk2818_gpio->bank->offset; - - /* enable gpio controller's clock */ - if(i%gpio_banksInGrp == 0) - clk_enable(rk2818_gpio->bank->clock); - - if(last) - last->next = rk2818_gpio; - last = rk2818_gpio; - - gpiochip_add(&rk2818_gpio->chip); - } - pr_info("rk2818_gpio_init:nr_banks=%d\n",nr_banks); - return; -} - - -#if 0 -//#ifdef CONFIG_DEBUG_FS - -static int rk2818_gpio_show(struct seq_file *s, void *unused) -{ - int bank, j; - //printk(KERN_INFO "rk2818_gpio_show\n"); - /* print heading */ - seq_printf(s, "Pin\t"); - for (bank = 0; bank < gpio_banks; bank++) { - seq_printf(s, "PIO%c\t", 'A' + bank); - }; - seq_printf(s, "\n\n"); - - /* print pin status */ - for (j = 0; j < NUM_GROUP; j++) { - seq_printf(s, "%d:\t", j); - - for (bank = 0; bank < gpio_banks; bank++) { - unsigned pin = PIN_BASE + (NUM_GROUP * bank) + j; - struct gpio_chip *chip = pin_to_gpioChip(pin); - unsigned mask = pin_to_mask(pin); - - if (!chip ||!mask) - { - seq_printf(s, "!chip || !mask\t"); - //printk(KERN_INFO "rk2818_gpio_show:!chip || !mask\n"); - return -1; - } - - GPIOSetPinDirection(chip,mask,GPIO_IN); - seq_printf(s, "pin=%d,level=%d\t", pin,GPIOGetPinLevel(chip,mask)); - seq_printf(s, "\t"); - } - seq_printf(s, "\n"); - } - - return 0; -} - -static int rk2818_gpio_open(struct inode *inode, struct file *file) -{ - return single_open(file, rk2818_gpio_show, NULL); -} - -static const struct file_operations rk2818_gpio_operations = { - .open = rk2818_gpio_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int __init rk2818_gpio_debugfs_init(void) -{ - /* /sys/kernel/debug/rk2818_gpio */ - //printk(KERN_INFO "rk2818_gpio_debugfs_init\n"); - - (void) debugfs_create_file("rk2818_gpio", S_IFREG | S_IRUGO, NULL, NULL, &rk2818_gpio_operations); - return 0; -} -postcore_initcall(rk2818_gpio_debugfs_init); - -#endif - diff --git a/arch/arm/mach-rk2818/include/mach/adc.h b/arch/arm/mach-rk2818/include/mach/adc.h deleted file mode 100644 index 166b9742ed2b..000000000000 --- a/arch/arm/mach-rk2818/include/mach/adc.h +++ /dev/null @@ -1,57 +0,0 @@ -/* arch/arm/mach-rk28418/include/mach/adc.h - * - * Copyright (c) 2010 luowei - * - * This program is free software; yosu can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - -#ifndef __ASM_ARCH_ADC_H -#define __ASM_ARCH_ADC_H - -#define RK28_ADCREG(x) (x) -#define RK28_ADCDAT RK28_ADCREG(0x00) -#define RK28_ADCSTAS RK28_ADCREG(0x04) -#define RK28_ADCCON RK28_ADCREG(0x08) - -//ADC_DATA -#define RK28_ADC_DATA_MASK (0x3ff) - -//ADC_STAS -#define RK28_ADC_STAS_STOP (0) - -//ADC_CTRL -#define RK28_ADC_INT_END (1<<6) -#define RK28_ADC_INT_CLEAR (~(1<<6)) -#define RK28_ADC_INT_ENABLE (1<<5) -#define RK28_ADC_INT_DISABLE (~(1<<5)) -#define RK28_ADC_CONV_START (1<<4) -#define RK28_ADC_CONV_STOP (~(1<<4)) -#define RK28_ADC_POWER_UP (1<<3) -#define RK28_ADC_POWER_DOWN (~(1<<3)) -#define RK28_ADC_SEL_CH(x) ((x)&0x03) -#define RK28_ADC_MASK_CH (~(0x03)) - -struct rk28_adc_client; - -extern volatile int gAdcValue[4]; //start adc in rk2818_adckey.c -extern int rk28_adc_start(struct rk28_adc_client *client, - unsigned int channel, unsigned int nr_samples); - -extern int rk28_adc_read(struct rk28_adc_client *client, unsigned int ch); - -extern struct rk28_adc_client * - rk28_adc_register(struct platform_device *pdev, - void (*select)(struct rk28_adc_client *client, - unsigned selected), - void (*conv)(struct rk28_adc_client *client, - unsigned d0, unsigned d1, - unsigned *samples_left), - unsigned int is_ts); - -extern void rk28_adc_release(struct rk28_adc_client *client); - -#endif - diff --git a/arch/arm/mach-rk2818/include/mach/board.h b/arch/arm/mach-rk2818/include/mach/board.h deleted file mode 100755 index 9438d61963f8..000000000000 --- a/arch/arm/mach-rk2818/include/mach/board.h +++ /dev/null @@ -1,288 +0,0 @@ -/* arch/arm/mach-rk2818/include/mach/board.h - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __ASM_ARCH_RK2818_BOARD_H -#define __ASM_ARCH_RK2818_BOARD_H - -#include -#include -#include - - - -#define INVALID_GPIO -1 - - -struct rk2818_io_cfg { - int (*io_init)(void *); - int (*io_deinit)(void *); -}; - -/* platform device data structures */ -struct platform_device; -struct i2c_client; -struct rk2818_sdmmc_platform_data { - unsigned int host_caps; - unsigned int host_ocr_avail; - unsigned int use_dma:1; - unsigned int no_detect:1; - char dma_name[8]; - int (*io_init)(void); - int (*io_deinit)(void); - int (*status)(struct device *); - int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id); -}; - -struct wifi_platform_data { - int (*set_power)(int val); - int (*set_reset)(int val); - int (*set_carddetect)(int val); - void *(*mem_prealloc)(int section, unsigned long size); -}; - -struct wifi_power_gpio_control_data { - unsigned int use_gpio; /* If uses GPIO to control wifi power supply. 0 - no, 1 - yes. */ - unsigned int gpio_iomux; /* If the GPIO is iomux. 0 - no, 1 - yes. */ - char *iomux_name; /* IOMUX name */ - unsigned int iomux_value; /* IOMUX value - which function is choosen. */ - unsigned int gpio_id; /* GPIO number */ - unsigned int sensi_level; /* GPIO sensitive level. */ -}; - -struct rk2818_i2c_spi_data { - int bus_num; - unsigned int flags; - unsigned int slave_addr; - unsigned long scl_rate; -}; -struct rk2818_i2c_platform_data { - int bus_num; - unsigned int flags; - unsigned int slave_addr; - unsigned long scl_rate; -#define I2C_MODE_IRQ 0 -#define I2C_MODE_POLL 1 - unsigned int mode:1; - int (*io_init)(void); - int (*io_deinit)(void); -}; - -struct rk2818lcd_info{ - u32 lcd_id; - u32 txd_pin; - u32 clk_pin; - u32 cs_pin; - int (*io_init)(void); - int (*io_deinit)(void); -}; - -struct rk2818_fb_setting_info{ - u8 data_num; - u8 vsync_en; - u8 den_en; - u8 mcu_fmk_en; - u8 disp_on_en; - u8 standby_en; -}; - -struct rk2818fb_info{ - u32 fb_id; - u32 disp_on_pin; - u8 disp_on_value; - u32 standby_pin; - u8 standby_value; - u32 mcu_fmk_pin; - struct rk2818lcd_info *lcd_info; - int (*io_init)(struct rk2818_fb_setting_info *fb_setting); - int (*io_deinit)(void); -}; - -struct rk2818_bl_info{ - u32 pwm_id; - u32 bl_ref; - int (*io_init)(void); - int (*io_deinit)(void); - struct timer_list timer; - struct notifier_block freq_transition; -}; - -struct rk2818_gpio_expander_info { - unsigned int gpio_num;// RK2818_PIN_PI0 - unsigned int pin_type;//GPIO_IN or GPIO_OUT - unsigned int pin_value;//GPIO_HIGH or GPIO_LOW -}; - - -struct pca9554_platform_data { - /* the first extern gpio number in all of gpio groups */ - unsigned int gpio_base; - unsigned int gpio_pin_num; - /* the first gpio irq number in all of irq source */ - - unsigned int gpio_irq_start; - unsigned int irq_pin_num; //number of intterupt - unsigned int pca9954_irq_pin; //rk28 gpio - /* initial polarity inversion setting */ - uint16_t invert; - struct rk2818_gpio_expander_info *settinginfo; - int settinginfolen; - void *context; /* param to setup/teardown */ - - int (*setup)(struct i2c_client *client,unsigned gpio, unsigned ngpio,void *context); - int (*teardown)(struct i2c_client *client,unsigned gpio, unsigned ngpio,void *context); - char **names; -}; - -struct tca6424_platform_data { - /* the first extern gpio number in all of gpio groups */ - unsigned int gpio_base; - unsigned int gpio_pin_num; - /* the first gpio irq number in all of irq source */ - - unsigned int gpio_irq_start; - unsigned int irq_pin_num; //number of interrupt - unsigned int tca6424_irq_pin; //rk28 gpio - unsigned int expand_port_group; - unsigned int expand_port_pinnum; - unsigned int rk_irq_mode; - unsigned int rk_irq_gpio_pull_up_down; - - /* initial polarity inversion setting */ - uint16_t invert; - struct rk2818_gpio_expander_info *settinginfo; - int settinginfolen; - void *context; /* param to setup/teardown */ - - int (*setup)(struct i2c_client *client,unsigned gpio, unsigned ngpio,void *context); - int (*teardown)(struct i2c_client *client,unsigned gpio, unsigned ngpio,void *context); - char **names; - void (*reseti2cpin)(void); -}; - -/*battery*/ -struct rk2818_battery_platform_data { - int (*io_init)(void); - int (*io_deinit)(void); - int charge_ok_pin; - int charge_ok_level; -}; - -/*g_sensor*/ -struct rk2818_gs_platform_data { - int (*io_init)(void); - int (*io_deinit)(void); - int gsensor_irq_pin; - bool swap_xy; /* swap x and y axes add swj */ -}; - -/*serial*/ -struct rk2818_serial_platform_data { - int (*io_init)(void); - int (*io_deinit)(void); -}; - -/*i2s*/ -struct rk2818_i2s_platform_data { - int (*io_init)(void); - int (*io_deinit)(void); -}; - -/*spi*/ -struct spi_cs_gpio { - const char *name; - unsigned int cs_gpio; - char *cs_iomux_name; - unsigned int cs_iomux_mode; -}; - -struct rk2818_spi_platform_data { - int (*io_init)(struct spi_cs_gpio*, int); - int (*io_deinit)(struct spi_cs_gpio*, int); - int (*io_fix_leakage_bug)(void); - int (*io_resume_leakage_bug)(void); - struct spi_cs_gpio *chipselect_gpios; - u16 num_chipselect; -}; - -/*rtc*/ -struct rk2818_rtc_platform_data { - u8 irq_type; - int (*io_init)(void); - int (*io_deinit)(void); -}; - -//ROCKCHIP AD KEY CODE ,for demo board -// key ---> EV -#define AD2KEY1 114 ///VOLUME_DOWN -#define AD2KEY2 115 ///VOLUME_UP -#define AD2KEY3 59 ///MENU -#define AD2KEY4 102 ///HOME -#define AD2KEY5 158 ///BACK -#define AD2KEY6 61 ///CALL -#define AD2KEY7 127 ///SEARCH -#define ENDCALL 62 -#define KEYSTART 232 ///DPAD_CENTER 28 //ENTER -#define KEYMENU AD2KEY6 ///CALL -#define KEY_PLAY_SHORT_PRESS KEYSTART //code for short press the play key -#define KEY_PLAY_LONG_PRESS ENDCALL //code for long press the play key -#define KEY_HEADSETHOOK 226 - -//ADC Registers -typedef struct tagADC_keyst -{ - unsigned int adc_value; - unsigned int adc_keycode; -}ADC_keyst,*pADC_keyst; - -/*ad key*/ -struct adc_key_data{ - u32 pin_playon; - u32 playon_level; - u32 adc_empty; - u32 adc_invalid; - u32 adc_drift; - u32 adc_chn; - ADC_keyst * adc_key_table; - unsigned char *initKeyCode; - u32 adc_key_cnt; -}; - -struct rk2818_adckey_platform_data { - int (*io_init)(void); - int (*io_deinit)(void); - struct adc_key_data *adc_key; - const char *name; -}; - -struct jgball_data { - u32 pin_up; - u32 pin_down; - u32 pin_left; - u32 pin_right; -}; - -struct rk2818_jogball_paltform_data { - struct jgball_data *jogball_key; -}; - - -/* common init routines for use by arch/arm/mach-msm/board-*.c */ -void __init rk2818_add_devices(void); -void __init rk2818_map_common_io(void); -void __init rk2818_init_irq(void); -void __init rk2818_init_gpio(void); -void __init rk2818_clock_init(void); - -#endif diff --git a/arch/arm/mach-rk2818/include/mach/clkdev.h b/arch/arm/mach-rk2818/include/mach/clkdev.h deleted file mode 100755 index 730c49d1ebd8..000000000000 --- a/arch/arm/mach-rk2818/include/mach/clkdev.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef __MACH_CLKDEV_H -#define __MACH_CLKDEV_H - -static inline int __clk_get(struct clk *clk) -{ - return 1; -} - -static inline void __clk_put(struct clk *clk) -{ -} - -#endif diff --git a/arch/arm/mach-rk2818/include/mach/debug-macro.S b/arch/arm/mach-rk2818/include/mach/debug-macro.S deleted file mode 100644 index b29c353ed427..000000000000 --- a/arch/arm/mach-rk2818/include/mach/debug-macro.S +++ /dev/null @@ -1,39 +0,0 @@ -/* arch/arm/mach-rk2818/include/mach/debug-macro.S - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include - - .macro addruart,rx - @ see if the MMU is enabled and select appropriate base address - mrc p15, 0, \rx, c1, c0 - tst \rx, #1 - ldreq \rx, =RK2818_UART1_PHYS - ldrne \rx, =RK2818_UART1_BASE - .endm - - .macro senduart,rd,rx - str \rd, [\rx, #0x00] - .endm - - .macro waituart,rd,rx - @ wait for TX_READY -1: ldr \rd, [\rx, #0x7C] - tst \rd, #0x02 - beq 1b - .endm - - .macro busyuart,rd,rx - .endm diff --git a/arch/arm/mach-rk2818/include/mach/dma.h b/arch/arm/mach-rk2818/include/mach/dma.h deleted file mode 100644 index f0cdfb2666c1..000000000000 --- a/arch/arm/mach-rk2818/include/mach/dma.h +++ /dev/null @@ -1,257 +0,0 @@ -/* - * arch/arm/mach-rk2818/include/mach/dma.h - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __ASM_ARCH_RK2818_DMA_H -#define __ASM_ARCH_RK2818_DMA_H - -#include -#include - - - -/******dam registers*******/ -//cfg low word -#define B_CFGL_CH_PRIOR(P) ((P)<<5)//pri = 0~2 -#define B_CFGL_CH_SUSP (1<<8) -#define B_CFGL_FIFO_EMPTY (1<<9) -#define B_CFGL_H_SEL_DST (0<<10) -#define B_CFGL_S_SEL_DST (1<<10) -#define B_CFGL_H_SEL_SRC (0<<11) -#define B_CFGL_S_SEL_SRC (1<<11) -#define B_CFGL_LOCK_CH_L_OTF (0<<12) -#define B_CFGL_LOCK_CH_L_OBT (1<<12) -#define B_CFGL_LOCK_CH_L_OTN (2<<12) -#define B_CFGL_LOCK_B_L_OTF (0<<14) -#define B_CFGL_LOCK_B_L_OBT (1<<14) -#define B_CFGL_LOCK_B_L_OTN (2<<14) -#define B_CFGL_LOCK_CH_EN (0<<16) -#define B_CFGL_LOCK_B_EN (0<<17) -#define B_CFGL_DST_HS_POL_H (0<<18) -#define B_CFGL_DST_HS_POL_L (1<<18) -#define B_CFGL_SRC_HS_POL_H (0<<19) -#define B_CFGL_SRC_HS_POL_L (1<<19) -#define B_CFGL_RELOAD_SRC (1<<30) -#define B_CFGL_RELOAD_DST (1<<31) -//cfg high word -#define B_CFGH_FCMODE (1<<0) -#define B_CFGH_FIFO_MODE (1<<1) -#define B_CFGH_PROTCTL (1<<2) -#define B_CFGH_DS_UPD_EN (1<<5) -#define B_CFGH_SS_UPD_EN (1<<6) -#define B_CFGH_SRC_PER(HS) ((HS)<<7) -#define B_CFGH_DST_PER(HS) ((HS)<<11) - -//ctl low word -#define B_CTLL_INT_EN (1<<0) -#define B_CTLL_DST_TR_WIDTH_8 (0<<1) -#define B_CTLL_DST_TR_WIDTH_16 (1<<1) -#define B_CTLL_DST_TR_WIDTH_32 (2<<1) -#define B_CTLL_DST_TR_WIDTH(W) ((W)<<1) -#define B_CTLL_SRC_TR_WIDTH_8 (0<<4) -#define B_CTLL_SRC_TR_WIDTH_16 (1<<4) -#define B_CTLL_SRC_TR_WIDTH_32 (2<<4) -#define B_CTLL_SRC_TR_WIDTH(W) ((W)<<4) -#define B_CTLL_DINC_INC (0<<7) -#define B_CTLL_DINC_DEC (1<<7) -#define B_CTLL_DINC_UNC (2<<7) -#define B_CTLL_DINC(W) ((W)<<7) -#define B_CTLL_SINC_INC (0<<9) -#define B_CTLL_SINC_DEC (1<<9) -#define B_CTLL_SINC_UNC (2<<9) -#define B_CTLL_SINC(W) ((W)<<9) -#define B_CTLL_DST_MSIZE_1 (0<<11) -#define B_CTLL_DST_MSIZE_4 (1<<11) -#define B_CTLL_DST_MSIZE_8 (2<<11) -#define B_CTLL_DST_MSIZE_16 (3<<11) -#define B_CTLL_DST_MSIZE_32 (4<<11) -#define B_CTLL_SRC_MSIZE_1 (0<<14) -#define B_CTLL_SRC_MSIZE_4 (1<<14) -#define B_CTLL_SRC_MSIZE_8 (2<<14) -#define B_CTLL_SRC_MSIZE_16 (3<<14) -#define B_CTLL_SRC_MSIZE_32 (4<<14) -#define B_CTLL_SRC_GATHER (1<<17) -#define B_CTLL_DST_SCATTER (1<<18) -#define B_CTLL_MEM2MEM_DMAC (0<<20) -#define B_CTLL_MEM2PER_DMAC (1<<20) -#define B_CTLL_PER2MEM_DMAC (2<<20) -#define B_CTLL_PER2MEM_PER (4<<20) -#define B_CTLL_DMS_EXP (0<<23) -#define B_CTLL_DMS_ARMD (1<<23) -#define B_CTLL_SMS_EXP (0<<25) -#define B_CTLL_SMS_ARMD (1<<25) -#define B_CTLL_LLP_DST_EN (1<<27) -#define B_CTLL_LLP_SRC_EN (1<<28) - -#define DWDMA_SAR(chn) 0x00+0x58*(chn) -#define DWDMA_DAR(chn) 0x08+0x58*(chn) -#define DWDMA_LLP(chn) 0x10+0x58*(chn) -#define DWDMA_CTLL(chn) 0x18+0x58*(chn) -#define DWDMA_CTLH(chn) 0x1c+0x58*(chn) -#define DWDMA_SSTAT(chn) 0x20+0x58*(chn) -#define DWDMA_DSTAT(chn) 0x28+0x58*(chn) -#define DWDMA_SSTATAR(chn) 0x30+0x58*(chn) -#define DWDMA_DSTATAR(chn) 0x38+0x58*(chn) -#define DWDMA_CFGL(chn) 0x40+0x58*(chn) -#define DWDMA_CFGH(chn) 0x44+0x58*(chn) -#define DWDMA_SGR(chn) 0x48+0x58*(chn) -#define DWDMA_DSR(chn) 0x50+0x58*(chn) - -#define DWDMA_RawTfr 0x2c0 -#define DWDMA_RawBlock 0x2c8 -#define DWDMA_RawSrcTran 0x2d0 -#define DWDMA_RawDstTran 0x2d8 -#define DWDMA_RawErr 0x2e0 -#define DWDMA_StatusTfr 0x2e8 -#define DWDMA_StatusBlock 0x2f0 -#define DWDMA_StatusSrcTran 0x2f8 -#define DWDMA_StatusDstTran 0x300 -#define DWDMA_StatusErr 0x308 -#define DWDMA_MaskTfr 0x310 -#define DWDMA_MaskBlock 0x318 -#define DWDMA_MaskSrcTran 0x320 -#define DWDMA_MaskDstTran 0x328 -#define DWDMA_MaskErr 0x330 -#define DWDMA_ClearTfr 0x338 -#define DWDMA_ClearBlock 0x340 -#define DWDMA_ClearSrcTran 0x348 -#define DWDMA_ClearDstTran 0x350 -#define DWDMA_ClearErr 0x358 -#define DWDMA_StatusInt 0x360 -#define DWDMA_ReqSrcReg 0x368 -#define DWDMA_ReqDstReg 0x370 -#define DWDMA_SglReqSrcReg 0x378 -#define DWDMA_SglReqDstReg 0x380 -#define DWDMA_LstSrcReg 0x388 -#define DWDMA_LstDstReg 0x390 -#define DWDMA_DmaCfgReg 0x398 -#define DWDMA_ChEnReg 0x3a0 -#define DWDMA_DmaIdReg 0x3a8 -#define DWDMA_DmaTestReg 0x3b0 -/**************************/ - -#define write_dma_reg(addr, val) __raw_writel(val, addr+RK2818_DWDMA_BASE) -#define read_dma_reg(addr) __raw_readl(addr+RK2818_DWDMA_BASE) -#define mask_dma_reg(addr, msk, val) write_dma_reg(addr, (val)|((~(msk))&read_dma_reg(addr))) - - /* clear interrupt */ -#define CLR_DWDMA_INTR(dma_ch) write_dma_reg(DWDMA_ClearTfr, 0x101< -#include -#include - -#define PIN_BASE 0//¶¨ÒåRK2818ÄÚ²¿GPIOµÄµÚÒ»¸öPIN¿Ú(¼´GPIO0_A0)ÔÚgpio_descÊý×éµÄµØÖ· -#define NUM_GROUP 8// ¶¨ÒåRK2818ÄÚ²¿GPIOÿһ×é×î´óµÄPINÊýÄ¿£¬ÏÖÔÚ¶¨Îª8¸ö£¬¼´GPIOX_Y0~ GPIOX_Y7(ÆäÖÐX=0/1;Y=A/B/C/D) -#define MAX_GPIO_BANKS 8//¶¨ÒåRK2818ÄÚ²¿GPIO×ܹ²Óм¸×飬ÏÖÔÚ¶¨Îª8×飬¼´GPIO0_A~ GPIO0_D£¬GPIO1_A~ GPIO1_D¡£ -#define SPI_FPGA_EXPANDER_BASE (PIN_BASE+NUM_GROUP*MAX_GPIO_BANKS) - -#if defined (CONFIG_SPI_FPGA_GPIO) -#define GPIO_EXPANDER_BASE (PIN_BASE+NUM_GROUP*MAX_GPIO_BANKS+CONFIG_SPI_FPGA_GPIO_NUM) -#else -#define GPIO_EXPANDER_BASE (PIN_BASE+NUM_GROUP*MAX_GPIO_BANKS) -#endif - -//¶¨ÒåGPIOµÄPIN¿Ú×î´óÊýÄ¿¡£(NUM_GROUP*MAX_GPIO_BANKS)±íʾRK2818µÄÄÚ²¿GPIOµÄPIN¿Ú×î´óÊýÄ¿£»CONFIG_ARCH_EXTEND_GPIOS±íʾÀ©Õ¹IOµÄ×î´óÊýÄ¿,CONFIG_SPI_FPGA_GPIO_NUM±íʾFPGAµÄPIN½ÅÊý¡£ -#define ARCH_NR_GPIOS ((NUM_GROUP*MAX_GPIO_BANKS)+CONFIG_EXPANDED_GPIO_NUM+CONFIG_SPI_FPGA_GPIO_NUM) -typedef enum eGPIOPinLevel -{ - GPIO_LOW=0, - GPIO_HIGH -}eGPIOPinLevel_t; - -typedef enum eGPIOPinDirection -{ - GPIO_IN=0, - GPIO_OUT -}eGPIOPinDirection_t; -typedef enum GPIOPullType { - GPIONormal, - GPIOPullUp, - GPIOPullDown, - GPIONOInit -}eGPIOPullType_t; - -typedef enum GPIOIntType { - GPIOLevelLow=0, - GPIOLevelHigh, - GPIOEdgelFalling, - GPIOEdgelRising -}eGPIOIntType_t; -//GPIO Registers - -struct rk2818_gpio_bank { - unsigned short id; //GPIO¼Ä´æÆ÷×éµÄIDʶ±ðºÅ - unsigned long offset; //GPIO0»òGPIO1µÄ»ùµØÖ· - struct clk *clock; /* associated clock */ -}; -//¶¨ÒåGPIOÏà¹Ø¼Ä´æÆ÷Æ«ÒƵØÖ· -#define GPIO_SWPORTA_DR 0x00 -#define GPIO_SWPORTA_DDR 0x04 - -#define GPIO_SWPORTB_DR 0x0c -#define GPIO_SWPORTB_DDR 0x10 - -#define GPIO_SWPORTC_DR 0x18 -#define GPIO_SWPORTC_DDR 0x1c - -#define GPIO_SWPORTD_DR 0x24 -#define GPIO_SWPORTD_DDR 0x28 - -#define GPIO_INTEN 0x30 -#define GPIO_INTMASK 0x34 -#define GPIO_INTTYPE_LEVEL 0x38 -#define GPIO_INT_POLARITY 0x3c -#define GPIO_INT_STATUS 0x40 -#define GPIO_INT_RAWSTATUS 0x44 -#define GPIO_DEBOUNCE 0x48 -#define GPIO_PORTS_EOI 0x4c -#define GPIO_EXT_PORTA 0x50 -#define GPIO_EXT_PORTB 0x54 -#define GPIO_EXT_PORTC 0x58 -#define GPIO_EXT_PORTD 0x5c -#define GPIO_LS_SYNC 0x60 - -#define RK2818_ID_PIOA 0 -#define RK2818_ID_PIOB 1 -#define RK2818_ID_PIOC 2 -#define RK2818_ID_PIOD 3 -#define RK2818_ID_PIOE 4 -#define RK2818_ID_PIOF 5 -#define RK2818_ID_PIOG 6 -#define RK2818_ID_PIOH 7 -/* these pin numbers double as IRQ numbers, like RK2818xxx_ID_* values */ - -#define RK2818_PIN_PA0 (PIN_BASE + 0*NUM_GROUP + 0) -#define RK2818_PIN_PA1 (PIN_BASE + 0*NUM_GROUP + 1) -#define RK2818_PIN_PA2 (PIN_BASE + 0*NUM_GROUP + 2) -#define RK2818_PIN_PA3 (PIN_BASE + 0*NUM_GROUP + 3) -#define RK2818_PIN_PA4 (PIN_BASE + 0*NUM_GROUP + 4) -#define RK2818_PIN_PA5 (PIN_BASE + 0*NUM_GROUP + 5) -#define RK2818_PIN_PA6 (PIN_BASE + 0*NUM_GROUP + 6) -#define RK2818_PIN_PA7 (PIN_BASE + 0*NUM_GROUP + 7) - - -#define RK2818_PIN_PB0 (PIN_BASE + 1*NUM_GROUP + 0) -#define RK2818_PIN_PB1 (PIN_BASE + 1*NUM_GROUP + 1) -#define RK2818_PIN_PB2 (PIN_BASE + 1*NUM_GROUP + 2) -#define RK2818_PIN_PB3 (PIN_BASE + 1*NUM_GROUP + 3) -#define RK2818_PIN_PB4 (PIN_BASE + 1*NUM_GROUP + 4) -#define RK2818_PIN_PB5 (PIN_BASE + 1*NUM_GROUP + 5) -#define RK2818_PIN_PB6 (PIN_BASE + 1*NUM_GROUP + 6) -#define RK2818_PIN_PB7 (PIN_BASE + 1*NUM_GROUP + 7) - -#define RK2818_PIN_PC0 (PIN_BASE + 2*NUM_GROUP + 0) -#define RK2818_PIN_PC1 (PIN_BASE + 2*NUM_GROUP + 1) -#define RK2818_PIN_PC2 (PIN_BASE + 2*NUM_GROUP + 2) -#define RK2818_PIN_PC3 (PIN_BASE + 2*NUM_GROUP + 3) -#define RK2818_PIN_PC4 (PIN_BASE + 2*NUM_GROUP + 4) -#define RK2818_PIN_PC5 (PIN_BASE + 2*NUM_GROUP + 5) -#define RK2818_PIN_PC6 (PIN_BASE + 2*NUM_GROUP + 6) -#define RK2818_PIN_PC7 (PIN_BASE + 2*NUM_GROUP + 7) - -#define RK2818_PIN_PD0 (PIN_BASE + 3*NUM_GROUP + 0) -#define RK2818_PIN_PD1 (PIN_BASE + 3*NUM_GROUP + 1) -#define RK2818_PIN_PD2 (PIN_BASE + 3*NUM_GROUP + 2) -#define RK2818_PIN_PD3 (PIN_BASE + 3*NUM_GROUP + 3) -#define RK2818_PIN_PD4 (PIN_BASE + 3*NUM_GROUP + 4) -#define RK2818_PIN_PD5 (PIN_BASE + 3*NUM_GROUP + 5) -#define RK2818_PIN_PD6 (PIN_BASE + 3*NUM_GROUP + 6) -#define RK2818_PIN_PD7 (PIN_BASE + 3*NUM_GROUP + 7) - -#define RK2818_PIN_PE0 (PIN_BASE + 4*NUM_GROUP + 0) -#define RK2818_PIN_PE1 (PIN_BASE + 4*NUM_GROUP + 1) -#define RK2818_PIN_PE2 (PIN_BASE + 4*NUM_GROUP + 2) -#define RK2818_PIN_PE3 (PIN_BASE + 4*NUM_GROUP + 3) -#define RK2818_PIN_PE4 (PIN_BASE + 4*NUM_GROUP + 4) -#define RK2818_PIN_PE5 (PIN_BASE + 4*NUM_GROUP + 5) -#define RK2818_PIN_PE6 (PIN_BASE + 4*NUM_GROUP + 6) -#define RK2818_PIN_PE7 (PIN_BASE + 4*NUM_GROUP + 7) - -#define RK2818_PIN_PF0 (PIN_BASE + 5*NUM_GROUP + 0) -#define RK2818_PIN_PF1 (PIN_BASE + 5*NUM_GROUP + 1) -#define RK2818_PIN_PF2 (PIN_BASE + 5*NUM_GROUP + 2) -#define RK2818_PIN_PF3 (PIN_BASE + 5*NUM_GROUP + 3) -#define RK2818_PIN_PF4 (PIN_BASE + 5*NUM_GROUP + 4) -#define RK2818_PIN_PF5 (PIN_BASE + 5*NUM_GROUP + 5) -#define RK2818_PIN_PF6 (PIN_BASE + 5*NUM_GROUP + 6) -#define RK2818_PIN_PF7 (PIN_BASE + 5*NUM_GROUP + 7) - - -#define RK2818_PIN_PG0 (PIN_BASE + 6*NUM_GROUP + 0) -#define RK2818_PIN_PG1 (PIN_BASE + 6*NUM_GROUP + 1) -#define RK2818_PIN_PG2 (PIN_BASE + 6*NUM_GROUP + 2) -#define RK2818_PIN_PG3 (PIN_BASE + 6*NUM_GROUP + 3) -#define RK2818_PIN_PG4 (PIN_BASE + 6*NUM_GROUP + 4) -#define RK2818_PIN_PG5 (PIN_BASE + 6*NUM_GROUP + 5) -#define RK2818_PIN_PG6 (PIN_BASE + 6*NUM_GROUP + 6) -#define RK2818_PIN_PG7 (PIN_BASE + 6*NUM_GROUP + 7) - -#define RK2818_PIN_PH0 (PIN_BASE + 7*NUM_GROUP + 0) -#define RK2818_PIN_PH1 (PIN_BASE + 7*NUM_GROUP + 1) -#define RK2818_PIN_PH2 (PIN_BASE + 7*NUM_GROUP + 2) -#define RK2818_PIN_PH3 (PIN_BASE + 7*NUM_GROUP + 3) -#define RK2818_PIN_PH4 (PIN_BASE + 7*NUM_GROUP + 4) -#define RK2818_PIN_PH5 (PIN_BASE + 7*NUM_GROUP + 5) -#define RK2818_PIN_PH6 (PIN_BASE + 7*NUM_GROUP + 6) -#define RK2818_PIN_PH7 (PIN_BASE + 7*NUM_GROUP + 7) -/***********************define extern gpio pin num******************************/ - -#if defined(CONFIG_SPI_FPGA_GPIO) -#define FPGA_PIO0_00 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 0) -#define FPGA_PIO0_01 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 1) -#define FPGA_PIO0_02 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 2) -#define FPGA_PIO0_03 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 3) -#define FPGA_PIO0_04 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 4) -#define FPGA_PIO0_05 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 5) -#define FPGA_PIO0_06 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 6) -#define FPGA_PIO0_07 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 7) - -#define FPGA_PIO0_08 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 0) -#define FPGA_PIO0_09 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 1) -#define FPGA_PIO0_10 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 2) -#define FPGA_PIO0_11 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 3) -#define FPGA_PIO0_12 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 4) -#define FPGA_PIO0_13 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 5) -#define FPGA_PIO0_14 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 6) -#define FPGA_PIO0_15 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 7) - -#define FPGA_PIO1_00 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 0) -#define FPGA_PIO1_01 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 1) -#define FPGA_PIO1_02 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 2) -#define FPGA_PIO1_03 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 3) -#define FPGA_PIO1_04 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 4) -#define FPGA_PIO1_05 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 5) -#define FPGA_PIO1_06 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 6) -#define FPGA_PIO1_07 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 7) - -#define FPGA_PIO1_08 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 0) -#define FPGA_PIO1_09 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 1) -#define FPGA_PIO1_10 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 2) -#define FPGA_PIO1_11 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 3) -#define FPGA_PIO1_12 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 4) -#define FPGA_PIO1_13 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 5) -#define FPGA_PIO1_14 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 6) -#define FPGA_PIO1_15 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 7) - -#define FPGA_PIO2_00 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 0) -#define FPGA_PIO2_01 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 1) -#define FPGA_PIO2_02 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 2) -#define FPGA_PIO2_03 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 3) -#define FPGA_PIO2_04 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 4) -#define FPGA_PIO2_05 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 5) -#define FPGA_PIO2_06 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 6) -#define FPGA_PIO2_07 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 7) - -#define FPGA_PIO2_08 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 0) -#define FPGA_PIO2_09 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 1) -#define FPGA_PIO2_10 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 2) -#define FPGA_PIO2_11 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 3) -#define FPGA_PIO2_12 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 4) -#define FPGA_PIO2_13 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 5) -#define FPGA_PIO2_14 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 6) -#define FPGA_PIO2_15 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 7) - -#define FPGA_PIO3_00 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 0) -#define FPGA_PIO3_01 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 1) -#define FPGA_PIO3_02 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 2) -#define FPGA_PIO3_03 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 3) -#define FPGA_PIO3_04 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 4) -#define FPGA_PIO3_05 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 5) -#define FPGA_PIO3_06 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 6) -#define FPGA_PIO3_07 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 7) - -#define FPGA_PIO3_08 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 0) -#define FPGA_PIO3_09 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 1) -#define FPGA_PIO3_10 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 2) -#define FPGA_PIO3_11 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 3) -#define FPGA_PIO3_12 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 4) -#define FPGA_PIO3_13 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 5) -#define FPGA_PIO3_14 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 6) -#define FPGA_PIO3_15 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 7) - -#define FPGA_PIO4_00 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 0) -#define FPGA_PIO4_01 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 1) -#define FPGA_PIO4_02 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 2) -#define FPGA_PIO4_03 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 3) -#define FPGA_PIO4_04 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 4) -#define FPGA_PIO4_05 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 5) -#define FPGA_PIO4_06 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 6) -#define FPGA_PIO4_07 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 7) - -#define FPGA_PIO4_08 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 0) -#define FPGA_PIO4_09 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 1) -#define FPGA_PIO4_10 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 2) -#define FPGA_PIO4_11 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 3) -#define FPGA_PIO4_12 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 4) -#define FPGA_PIO4_13 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 5) -#define FPGA_PIO4_14 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 6) -#define FPGA_PIO4_15 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 7) - -#define FPGA_PIO5_00 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 0) -#define FPGA_PIO5_01 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 1) -#define FPGA_PIO5_02 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 2) -#define FPGA_PIO5_03 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 3) -#define FPGA_PIO5_04 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 4) -#define FPGA_PIO5_05 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 5) -#define FPGA_PIO5_06 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 6) -#define FPGA_PIO5_07 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 7) - -#define FPGA_PIO5_08 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 0) -#define FPGA_PIO5_09 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 1) -#define FPGA_PIO5_10 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 2) -#define FPGA_PIO5_11 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 3) -#define FPGA_PIO5_12 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 4) -#define FPGA_PIO5_13 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 5) -#define FPGA_PIO5_14 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 6) -#define FPGA_PIO5_15 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 7) - -#endif - -#if defined(CONFIG_IOEXTEND_TCA6424) -#define TCA6424_P00 (GPIO_EXPANDER_BASE + 0*NUM_GROUP + 0) -#define TCA6424_P01 (GPIO_EXPANDER_BASE + 0*NUM_GROUP + 1) -#define TCA6424_P02 (GPIO_EXPANDER_BASE + 0*NUM_GROUP + 2) -#define TCA6424_P03 (GPIO_EXPANDER_BASE + 0*NUM_GROUP + 3) -#define TCA6424_P04 (GPIO_EXPANDER_BASE + 0*NUM_GROUP + 4) -#define TCA6424_P05 (GPIO_EXPANDER_BASE + 0*NUM_GROUP + 5) -#define TCA6424_P06 (GPIO_EXPANDER_BASE + 0*NUM_GROUP + 6) -#define TCA6424_P07 (GPIO_EXPANDER_BASE + 0*NUM_GROUP + 7) - -#define TCA6424_P10 (GPIO_EXPANDER_BASE + 1*NUM_GROUP + 0) -#define TCA6424_P11 (GPIO_EXPANDER_BASE + 1*NUM_GROUP + 1) -#define TCA6424_P12 (GPIO_EXPANDER_BASE + 1*NUM_GROUP + 2) -#define TCA6424_P13 (GPIO_EXPANDER_BASE + 1*NUM_GROUP + 3) -#define TCA6424_P14 (GPIO_EXPANDER_BASE + 1*NUM_GROUP + 4) -#define TCA6424_P15 (GPIO_EXPANDER_BASE + 1*NUM_GROUP + 5) -#define TCA6424_P16 (GPIO_EXPANDER_BASE + 1*NUM_GROUP + 6) -#define TCA6424_P17 (GPIO_EXPANDER_BASE + 1*NUM_GROUP + 7) - -#define TCA6424_P20 (GPIO_EXPANDER_BASE + 2*NUM_GROUP + 0) -#define TCA6424_P21 (GPIO_EXPANDER_BASE + 2*NUM_GROUP + 1) -#define TCA6424_P22 (GPIO_EXPANDER_BASE + 2*NUM_GROUP + 2) -#define TCA6424_P23 (GPIO_EXPANDER_BASE + 2*NUM_GROUP + 3) -#define TCA6424_P24 (GPIO_EXPANDER_BASE + 2*NUM_GROUP + 4) -#define TCA6424_P25 (GPIO_EXPANDER_BASE + 2*NUM_GROUP + 5) -#define TCA6424_P26 (GPIO_EXPANDER_BASE + 2*NUM_GROUP + 6) -#define TCA6424_P27 (GPIO_EXPANDER_BASE + 2*NUM_GROUP + 7) - -#endif - - -#ifndef __ASSEMBLY__ -extern void __init rk2818_gpio_init(struct rk2818_gpio_bank *data, int nr_banks); -extern void __init rk2818_gpio_irq_setup(void); -/*-------------------------------------------------------------------------*/ - -/* wrappers for "new style" GPIO calls. the old RK2818-specfic ones should - * eventually be removed (along with this errno.h inclusion), and the - * gpio request/free calls should probably be implemented. - */ - -#include -#include /* cansleep wrappers */ - -#define gpio_get_value __gpio_get_value -#define gpio_set_value __gpio_set_value -#define gpio_cansleep __gpio_cansleep - -static inline int gpio_to_irq(unsigned gpio) -{ - return __gpio_to_irq(gpio); -} - -static inline int irq_to_gpio(unsigned irq) -{ - if(irq -#include - - -#define RK2818_PM_PRT_ORIGINAL_REG -#define RK2818_PM_PRT_CHANGED_REG - -#define PM_SAVE_REG_NUM 4 - -#define PM_NUM_BIT_MASK(b) ((0x1<<(b))-1) -#define PM_BIT_OFF_MASK(off,numbit) (PM_NUM_BIT_MASK(numbit)<<(off)) -#define PM_BIT_CLEAR(off,numbit) (~(PM_BIT_OFF_MASK(off,numbit))) -#define PM_BIT_SET(off,val,numbit) ((val&PM_NUM_BIT_MASK(numbit))<>off) - -#if defined (CONFIG_RK2818_SOC_PM_DBG) - -#define PM_SCU_ATTR_DBG_NUM 30 -#define PM_GENERAL_ATTR_DBG_NUM 10 -#define PM_GPIO0_ATTR_DBG_NUM 10 -#define PM_GPIO1_ATTR_DBG_NUM 10 - - -#define PM_DBG_CH_REG_INI 0 -#define PM_DBG_CH_REG_UPDATA 1 - - - -#define PM_DBG_SET_ONCE 0xEE -#define PM_DBG_SET_ALWAY 0x99 -#define PM_DBG_NOT_SET 0 - -enum PM_DBG_USER_EN{ - - PM_DBG_USER_VALUE, - PM_DBG_USER_REGOFF, - PM_DBG_USER_BITS_OFF, - PM_DBG_USER_BITS_NUM, - PM_DBG_USER_FLAG, - PM_DBG_USER_END, -}; - - -#define PM_ATTR_CTR_ONCE 0xEE -#define PM_ATTR_CTR_ALWAY 0x99 -#define PM_ATTR_NO_CTR 0x0 - -struct rk2818_pm_attr_dbg_st{ - unsigned int value; - unsigned char regoff; - unsigned char regbits_off; - unsigned char bitsnum; - unsigned char flag; -}; - -bool rk2818_socpm_attr_store(int type,const char *buf, size_t n); -ssize_t rk2818_socpm_attr_show(int type,char *buf); -#endif - -typedef void (*pm_scu_suspend)(unsigned int *tempdata,int regoff); -typedef void (*pm_general_reg_suspend)(void); -typedef void (*pm_suspend_ctr_pin)(void); -typedef void (*pm_resume_ctr_pin)(void); - -struct rk2818_pm_soc_st{ -unsigned int *reg_save; -unsigned int *reg_base_addr; -u16 reg_ctrbit; -u8 reg_num; -#ifdef RK2818_PM_PRT_CHANGED_REG -unsigned int *reg_ch; -#endif -#if defined (CONFIG_RK2818_SOC_PM_DBG) -u8 attr_num; -struct rk2818_pm_attr_dbg_st *attr_dbg; -u8 attr_flag; -#endif -}; - -struct rk2818_pm_callback_st{ -pm_scu_suspend scu_suspend; -pm_general_reg_suspend general_reg_suspend; -pm_suspend_ctr_pin set_pin; -pm_resume_ctr_pin resume_pin; -}; - - - -struct rk2818_pm_st{ -struct rk2818_pm_soc_st *scu; -unsigned int *scu_tempreg; -unsigned int scu_reg; -struct rk2818_pm_soc_st *general; -struct rk2818_pm_soc_st *gpio0; -struct rk2818_pm_soc_st *gpio1; -//struct rk2818_pm_callback_st *callback; -unsigned int *save_reg; -unsigned int *save_ch; -}; - -/***********************scu SCU_CLKSEL0 reg bit************************************/ -#define PM_RESUME_BIT 0 -#define PM_DEBUG_BIT 1 -#define PM_SET_BIT(b) (1<>b) - -/***********************scu SCU_CLKSEL0 reg bit************************************/ - -#define SCU_GATE0CLK_ALL_EN 0 -#define SCU_GATE0CLK_ALL_DIS 0XFFFFFFFF -#define DIS_TIMER_CLK (1<<25) -#define DIS_UART1_CLK (1<<19) -#define DIS_UART0_CLK (1<<18) -#define DIS_GPIO1_CLK (1<<17) -#define DIS_GPIO0_CLK (1<<16) -#define DIS_INTC_CLK (1<<9) -#define DIS_ARM_CLK (1<<0) -/***********************scu SCU_CLKSEL1_CON reg bit************************************/ - -#define SCU_GATE1CLK_ALL_EN 0 -//#define SCU_GATE1CLK_BASE_SET (0XFFFFFFFF&(~DIS_DDR_CLK)&(~DIS_DDR_HCLK)) // ×¢ÒâAXI λΪ1ʱΪenable - -#define SCU_GATE1CLK_BASE_SET (0XFFFF8001&(~EN_AXI_CLK)) // ×¢ÒâAXI λΪ1ʱΪenable -//#define SCU_GATE1CLK_BASE_SET (0XFFFFFFFF) -#define EN_AXI_CLK (1<<27) -#define DIS_DDR_CLK (1<<23) -#define DIS_DDR_HCLK (1<<22) -#define DIS_MSDRAM_CTR_HCLK (1<<17) -#define DIS_SDRAM_CTR_HCLK (1<<16) -#define DIS_MAndSDRAM_CMM_HCLK (1<<15) -/***********************scu SCU_CLKSEL2_CON reg bit************************************/ -#define SCU_GATE2CLK_ALL_EN 0 -#define SCU_GATE2CLK_ALL_DIS 0X3FF -#define SCU_GATE2CLK_BASE_SET (SCU_GATE2CLK_ALL_DIS&(~DIS_ARMIBUS_CLK)&(~DIS_ARMDBUS_CLK)&(~DIS_EXPAHBBUS_CLK)&(~DIS_APBBUS_CLK)) - -#define DIS_ITCMBUS_CLK (1<<8) -#define DIS_DTCM0BUS_CLK (1<<7) -#define DIS_DTCM1BUS_CLK (1<<6) - -#define DIS_APBBUS_CLK (1<<4) -#define DIS_EXPAHBBUS_CLK (1<<3) -#define DIS_ARMDBUS_CLK (1<<1) -#define DIS_ARMIBUS_CLK (1<<0) -/***********************scu SCU_APLL_CON reg bit************************************/ -#define ARMPLL_POERDOWN (1<<22) -#define ARMPLL_BYPASSMODE (1<<0) -/***********************scu SCU_DPLL_CON reg bit************************************/ - -#define DSPPLL_POERDOWN (1<<22) - -/***********************scu SCU_CPLL_CON reg bit************************************/ -#define CPLL_POERDOWN (1<<22) - -/***********************scu PM_SCU_MODE_CON reg bit************************************/ -#define CPU_SLOW_MODE (~(3<<2)) -#define CPU_STOP_MODE (1<<4) - - - -/***********************scu SCU_PMU_CON reg bit************************************/ - -#define LCDC_POWER_DOWN (1<<3) -#define DSP_POWER_DOWN (1<<0) - #define DDR_POWER_DOWN (1<<2) - - -/***********************scu PM_SCU_CLKSEL0_CON reg bit************************************/ -#define CLKSEL0_HCLK (0) -#define CLKSEL0_PCLK (2) - -#define CLK_ARM1_H1 (0) -#define CLK_ARM2_H1 (1) -#define CLK_ARM3_H1 (2) -#define CLK_ARM4_H1 (3) - -#define CLK_HCLK1_P1 (0) -#define CLK_HCLK2_P1 (1) -#define CLK_HCLK4_P1 (2) - -/***********************scu PM_SCU_SOFTRST_CON] reg bit************************************/ -#define RST_ALL 0xFFFFFFFF - -#define RST_DDR_BUS (1<<31) -#define RST_DDR_CORE_LOGIC (1<<30) - -#define RST_ARM (1<<23) - -enum -{ - PM_SCU_APLL_CON, - PM_SCU_DPLL_CON, - PM_SCU_CPLL_CON, - PM_SCU_MODE_CON, - PM_SCU_PMU_CON, - PM_SCU_CLKSEL0_CON, - PM_SCU_CLKSEL1_CON, - PM_SCU_CLKGATE0_CON, - PM_SCU_CLKGATE1_CON, - PM_SCU_CLKGATE2_CON, - PM_SCU_SOFTRST_CON, - PM_SCU_CHIPCFG_CON, - PM_SCU_CPUPD, - PM_CLKSEL2_CON, - PM_SCU_REG_NUM -}; - -/***********************general cpu reg bit************************************/ -#define RK2818GPIO_TOTAL (PIN_BASE+NUM_GROUP*MAX_GPIO_BANKS) - -/***********************general cpu reg IOMUX_A bit************************************/ - -#define PM_I2C0 (30) -#define PM_I2C1 (28) -#define PM_UART1_OUT (26) -#define PM_UART1_IN (24) -#define PM_SDIO1_CMD (23) -#define PM_SDIO1_DATA (22) -#define PM_UART0_OUT (14) -#define PM_UART0_IN (12) - -#define PM_SDIO0_CMD (5) -#define PM_SDIO0_DATA (4) - - - -/***********************general cpu reg IOMUX_B bit************************************/ - -#define PM_UART0_RTS (13) -#define PM_UART0_CTS (12) - - - - - - -/***********************general cpu reg PU bit************************************/ -#define PM_CLEAR_IO_PU(pin) (~((3)< - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -*/ - -#ifndef __ASM_ARCH_CAMERA_H_ -#define __ASM_ARCH_CAMERA_H_ - - -#define RK28_CAM_DRV_NAME "rk2818-camera" -#define RK28_CAM_PLATFORM_DEV_ID 33 - -#define RK28_CAM_SENSOR_NAME_OV9650 "ov9650" -#define RK28_CAM_SENSOR_NAME_OV2655 "ov2655" -#define RK28_CAM_SENSOR_NAME_OV3640 "ov3640" - -#define RK28_CAM_POWERACTIVE_BITPOS 0x00 -#define RK28_CAM_POWERACTIVE_MASK (1< - -/* defines */ - -#define SZ_22K 0x5800 - -/* Physical base address and size of peripherals. - * Ordered by the virtual base addresses they will be mapped at. - * - * RK2818_VIC_BASE must be an value that can be loaded via a "mov" - * instruction, otherwise entry-macro.S will not compile. - * - * If you add or remove entries here, you'll want to edit the - * rk2818_io_desc array in arch/arm/mach-rk2818/io.c to reflect your - * changes. - * - */ -//ÄÚ´æÎïÀíµØÖ· -#ifdef CONFIG_DRAM_BASE -#define RK2818_SDRAM_BASE 0x60000000//CONFIG_DRAM_BASE -#else -#define RK2818_SDRAM_PHYS 0x60000000 -#define RK2818_SDRAM_SIZE (0x00100000*64) -#endif - -#define RK2818_AHB_PHYS 0x10000000 //AHB ×ÜÏßÉ豸»ùÎïÀíµØÖ· -#define RK2818_AHB_SIZE 0x00100000 // size:1M - -#define RK2818_APB_BASE 0xFF100000 -#define RK2818_APB_PHYS 0x18000000 // APB×ÜÏßÉ豸»ùÎïÀíµØÖ· -#define RK2818_APB_SIZE 0x00100000 // size:1M - -#define RK2818_BOOTROM_PHYS 0x10000000 -#define RK2818_BOOTROM_SIZE SZ_8K - -#define RK2818_SRAM_PHYS 0x10002000 -#define RK2818_SRAM_SIZE SZ_8K - -#define RK2818_USBOTG_PHYS 0x10040000 -#define RK2818_USBOTG_SIZE SZ_256K - -#define RK2818_MCDMA_BASE 0xFF080000 -#define RK2818_MCDMA_PHYS 0x10080000 -#define RK2818_MCDMA_SIZE SZ_8K - -#define RK2818_SHAREMEM_PHYS 0x10090000 -#define RK2818_SHAREMEM_SIZE SZ_64K - -#define RK2818_DWDMA_BASE 0xFF0A0000 -#define RK2818_DWDMA_PHYS 0x100A0000 -#define RK2818_DWDMA_SIZE SZ_8K - -#define RK2818_HOSTIF_PHYS 0x100A2000 -#define RK2818_HOSTIF_SIZE SZ_8K - -#define RK2818_LCDC_PHYS 0x100A4000 -#define RK2818_LCDC_SIZE SZ_8K - -#define RK2818_VIP_PHYS 0x100A6000 -#define RK2818_VIP_SIZE SZ_8K - -#define RK2818_SDMMC1_PHYS 0x100A8000 -#define RK2818_SDMMC1_SIZE SZ_8K - -#define RK2818_INTC_BASE 0xFF0AA000 -#define RK2818_INTC_PHYS 0x100AA000 -#define RK2818_INTC_SIZE SZ_8K - -#define RK2818_SDMMC0_PHYS 0x100AC000 -#define RK2818_SDMMC0_SIZE SZ_8K - -#define RK2818_NANDC_BASE 0xFF0AE000 -#define RK2818_NANDC_PHYS 0x100AE000 -#define RK2818_NANDC_SIZE SZ_16K - -#define RK2818_SDRAMC_BASE 0xFF0B0000 -#define RK2818_SDRAMC_PHYS 0x100B0000 -#define RK2818_SDRAMC_SIZE SZ_8K - -#define RK2818_ARMDARBITER_BASE 0xFF0B4000 -#define RK2818_ARMDARBITER_PHYS 0x100B4000 -#define RK2818_ARMDARBITER_SIZE SZ_8K - -#define RK2818_VIDEOCOP_PHYS 0x100B8000 -#define RK2818_VIDEOCOP_SIZE SZ_8K - -#define RK2818_ESRAM_PHYS 0x100BA000 -#define RK2818_ESRAM_SIZE SZ_8K - -#define RK2818_USBHOST_PHYS 0x10100000 -#define RK2818_USBHOST_SIZE SZ_256K - -#define RK2818_UART0_BASE 0xFF100000 -#define RK2818_UART0_PHYS 0x18000000 -#define RK2818_UART0_SIZE SZ_4K - -#define RK2818_UART2_BASE 0xFF101000 -#define RK2818_UART2_PHYS 0x18001000 -#define RK2818_UART2_SIZE SZ_4K - -#define RK2818_UART1_BASE 0xFF102000 -#define RK2818_UART1_PHYS 0x18002000 -#define RK2818_UART1_SIZE SZ_4K - -#define RK2818_UART3_BASE 0xFF103000 -#define RK2818_UART3_PHYS 0x18003000 -#define RK2818_UART3_SIZE SZ_4K - -#define RK2818_TIMER_BASE 0xFF104000 -#define RK2818_TIMER_PHYS 0x18004000 -#define RK2818_TIMER_SIZE SZ_8K - -#define RK2818_eFUSE_BASE 0xFF106000 -#define RK2818_eFUSE_PHYS 0x18006000 -#define RK2818_eFUSE_SIZE SZ_8K - -#define RK2818_GPIO0_BASE 0xFF108000 -#define RK2818_GPIO0_PHYS 0x18008000 -#define RK2818_GPIO0_SIZE SZ_8K - -#define RK2818_GPIO1_BASE 0xFF109000 -#define RK2818_GPIO1_PHYS 0x18009000 -#define RK2818_GPIO1_SIZE SZ_8K - -#define RK2818_I2S_PHYS 0x1800A000 -#define RK2818_I2S_SIZE SZ_8K - -#define RK2818_I2C0_PHYS 0x1800C000 -#define RK2818_I2C0_SIZE SZ_4K - -#define RK2818_I2C1_PHYS 0x1800D000 -#define RK2818_I2C1_SIZE SZ_4K - -#define RK2818_SPIMASTER_PHYS 0x1800E000 -#define RK2818_SPIMASTER_SIZE SZ_4K - -#define RK2818_SPISLAVE_BASE 0xFF10F000 -#define RK2818_SPISLAVE_PHYS 0x1800F000 -#define RK2818_SPISLAVE_SIZE SZ_4K - -#define RK2818_WDT_BASE 0xFF110000 -#define RK2818_WDT_PHYS 0x18010000 -#define RK2818_WDT_SIZE SZ_8K - -#define RK2818_PWM_BASE 0xFF112000 -#define RK2818_PWM_PHYS 0x18012000 -#define RK2818_PWM_SIZE SZ_8K - -#define RK2818_RTC_BASE 0xFF114000 -#define RK2818_RTC_PHYS 0x18014000 -#define RK2818_RTC_SIZE SZ_8K - -#define RK2818_ADC_BASE 0xFF116000 -#define RK2818_ADC_PHYS 0x18016000 -#define RK2818_ADC_SIZE SZ_8K - -#define RK2818_SCU_BASE 0xFF118000 -#define RK2818_SCU_PHYS 0x18018000 -#define RK2818_SCU_SIZE SZ_4K - -#define RK2818_REGFILE_BASE 0xFF119000 -#define RK2818_REGFILE_PHYS 0x18019000 -#define RK2818_REGFILE_SIZE SZ_4K - -#define RK2818_DSP_PHYS 0x80000000 -#define RK2818_DSP_SIZE 0x00600000 - -#endif diff --git a/arch/arm/mach-rk2818/include/mach/rk2818_nand.h b/arch/arm/mach-rk2818/include/mach/rk2818_nand.h deleted file mode 100755 index 81d824e67a4e..000000000000 --- a/arch/arm/mach-rk2818/include/mach/rk2818_nand.h +++ /dev/null @@ -1,123 +0,0 @@ - -/* - * arch/arm/mach-rk2818/include/mach/rk2818_nand.h - * - * Copyright (C) 2010 RockChip, Inc. - * Author: - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARCH_RK2818_NAND_H -#define __ASM_ARCH_RK2818_NAND_H - - -//BCHCTL¼Ä´æÆ÷ -#define BCH_WR 0x0002 -#define BCH_RST 0x0001 -//FLCTL¼Ä´æÆ÷ -#define FL_RDY (0x1<<20) -#define FL_LBA_EN (0x1<<11) -#define FL_COR_EN (0x1<<10) -#define FL_INT_EN (0x1<<9) -#define FL_INTCLR (0x1<<8) -#define FL_STMOD (0x1<<7) -#define FL_TRCNT (0x3<<5) -#define FL_STADDR (0x1<<4) -#define FL_BYPASS (0x1<<3) -#define FL_START (0x1<<2) -#define FL_RDN (0x1<<1) -#define FL_RST (0x1<<0) -//FMCTL¼Ä´æÆ÷ -#define FMC_WP (0x1<<8) -#define FMC_FRDY (0x1<<9) -#define FMC_FRDY_INT_EN (0x1<<10) -#define FMC_FRDY_INT_CLR (0x1<<11) -//FMWAIT¼Ä´æÆ÷ -#define FMW_RWCS_OFFSET 0 -#define FMW_RWPW_OFFSET 5 -#define FMW_RDY (0x1<<11) -#define FMW_CSRW_OFFSET 12 -#define FMW_DLY_OFFSET 16 -#define FMW_DLY_DBG (0x1<<23) - -struct rk2818_nand_timing { - unsigned int tCH; /* Enable signal hold time */ - unsigned int tCS; /* Enable signal setup time */ - unsigned int tWH; /* ND_nWE high duration */ - unsigned int tWP; /* ND_nWE pulse time */ - unsigned int tRH; /* ND_nRE high duration */ - unsigned int tRP; /* ND_nRE pulse width */ - unsigned int tR; /* ND_nWE high to ND_nRE low for read */ - unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */ - unsigned int tAR; /* ND_ALE low to ND_nRE low delay */ -}; - -struct rk2818_nand_cmdset { - uint16_t read1; - uint16_t read2; - uint16_t program; - uint16_t read_status; - uint16_t read_id; - uint16_t erase; - uint16_t reset; - uint16_t lock; - uint16_t unlock; - uint16_t lock_status; -}; - -typedef volatile struct tagCHIP_IF -{ - uint32_t data; - uint32_t addr; - uint32_t cmd; - uint32_t RESERVED[0x3d]; -}CHIP_IF, *pCHIP_IF; - -//NANDC Registers -typedef volatile struct tagNANDC -{ - volatile uint32_t FMCTL; - volatile uint32_t FMWAIT; - volatile uint32_t FLCTL; - volatile uint32_t BCHCTL; - volatile uint32_t BCHST; - volatile uint32_t RESERVED1[(0x200-0x14)/4]; //FLR - volatile uint32_t spare[0x200/4]; - volatile uint32_t RESERVED2[0x400/4]; - volatile CHIP_IF chip[8]; - volatile uint32_t buf[0x800/4]; -}NANDC, *pNANDC; - -struct rk2818_nand_flash { - const struct rk2818_nand_timing *timing; /* NAND Flash timing */ - const struct rk2818_nand_cmdset *cmdset; - - uint32_t page_per_block; /* Pages per block (PG_PER_BLK) */ - uint32_t page_size; /* Page size in bytes (PAGE_SZ) */ - uint32_t flash_width; /* Width of Flash memory (DWIDTH_M) */ - uint32_t num_blocks; /* Number of physical blocks in Flash */ - uint32_t chip_id; -}; - -struct rk2818_nand_platform_data { - - int width; /* data bus width in bytes */ - int hw_ecc; /* 1:hw ecc, 0: soft ecc */ - struct mtd_partition *parts; - unsigned int nr_parts; - size_t num_flash; - int (*io_init)(void); - int (*io_deinit)(void); -}; - - -#endif /* __ASM_ARCH_RK2818_NAND_H */ - diff --git a/arch/arm/mach-rk2818/include/mach/rk2818_pm.h b/arch/arm/mach-rk2818/include/mach/rk2818_pm.h deleted file mode 100755 index 7997e3297bcf..000000000000 --- a/arch/arm/mach-rk2818/include/mach/rk2818_pm.h +++ /dev/null @@ -1,215 +0,0 @@ -/* - * rockchip-pcm.h - ALSA PCM interface for the Rockchip rk28 SoC - * - * Driver for rockchip iis audio - * Copyright (C) 2009 lhh - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _ROCKCHIP_PM_H -#define _ROCKCHIP_PM_H - -/***********************scu SCU_CLKSEL0 reg bit************************************/ -#define PM_RESUME_BIT 0 -#define PM_DEBUG_BIT 1 -#define PM_SET_BIT(b) (1<>b) - -#define PM_BIT_CLEAR(off,b) (~((1<<(b))-1)<<(off)) - - -/***********************scu SCU_CLKSEL0 reg bit************************************/ - -#define SCU_GATE0CLK_ALL_EN 0 -#define SCU_GATE0CLK_ALL_DIS 0XFFFFFFFF -#define DIS_RTC_PCLK (1<<27) -#define DIS_WDT_PCLK (1<<26) -#define DIS_TIMER_CLK (1<<25) -#define DIS_PWM_CLK (1<<24) -#define DIS_SPI1_CLK (1<<23) -#define DIS_SPI0_CLK (1<<22) -#define DIS_I2C1_CLK (1<<21) -#define DIS_I2C0_CLK (1<<20) -#define DIS_UART1_CLK (1<<19) -#define DIS_UART0_CLK (1<<18) -#define DIS_GPIO1_CLK (1<<17) -#define DIS_GPIO0_CLK (1<<16) -#define DIS_EMBEDED_ROM_CLK (1<<15) -#define DIS_LCDC_CLK (1<<11) -#define DIS_DEBLOCK_HCLK (1<<10) -#define DIS_INTC_CLK (1<<9) -#define DIS_NANDC_HCLK (1<<8) -#define DIS_DMA_CLK (1<<2) -#define DIS_DSP_CLK (1<<1) -#define DIS_ARM_CLK (1<<0) -/***********************scu SCU_CLKSEL1_CON reg bit************************************/ - -#define SCU_GATE1CLK_ALL_EN 0 -//#define SCU_GATE1CLK_BASE_SET (0XFFFFFFFF&(~DIS_DDR_CLK)&(~DIS_DDR_HCLK)) // ×¢ÒâAXI λΪ1ʱΪenable - -#define SCU_GATE1CLK_BASE_SET (0XFFFF8001&(~EN_AXI_CLK)) // ×¢ÒâAXI λΪ1ʱΪenable -//#define SCU_GATE1CLK_BASE_SET (0XFFFFFFFF) -#define EN_AXI_CLK (1<<27) -#define DIS_DDR_CLK (1<<23) -#define DIS_DDR_HCLK (1<<22) -#define DIS_LCDC_HCLK (1<<19) -#define DIS_LCDC_SHARE_MEM_CLK (1<<18) -#define DIS_MSDRAM_CTR_HCLK (1<<17) -#define DIS_SDRAM_CTR_HCLK (1<<16) -#define DIS_MAndSDRAM_CMM_HCLK (1<<15) -/***********************scu SCU_CLKSEL2_CON reg bit************************************/ -#define SCU_GATE2CLK_ALL_EN 0 -#define SCU_GATE2CLK_ALL_DIS 0X3FF -#define SCU_GATE2CLK_BASE_SET (SCU_GATE2CLK_ALL_DIS&(~DIS_ARMIBUS_CLK)&(~DIS_ARMDBUS_CLK)&(~DIS_EXPAHBBUS_CLK)&(~DIS_APBBUS_CLK)) - -#define DIS_ITCMBUS_CLK (1<<8) -#define DIS_DTCM0BUS_CLK (1<<7) -#define DIS_DTCM1BUS_CLK (1<<6) - -#define DIS_APBBUS_CLK (1<<4) -#define DIS_EXPAHBBUS_CLK (1<<3) -#define DIS_ARMDBUS_CLK (1<<1) -#define DIS_ARMIBUS_CLK (1<<0) -/***********************scu SCU_APLL_CON reg bit************************************/ -#define ARMPLL_POERDOWN (1<<22) -#define ARMPLL_BYPASSMODE (1<<0) -/***********************scu SCU_DPLL_CON reg bit************************************/ - -#define DSPPLL_POERDOWN (1<<22) - -/***********************scu SCU_CPLL_CON reg bit************************************/ -#define CPLL_POERDOWN (1<<22) - -/***********************scu PM_SCU_MODE_CON reg bit************************************/ -#define CPU_SLOW_MODE (~(3<<2)) - - -/***********************scu SCU_PMU_CON reg bit************************************/ - -#define LCDC_POWER_DOWN (1<<3) -#define DSP_POWER_DOWN (1<<0) - #define DDR_POWER_DOWN (1<<2) - - -/***********************scu PM_SCU_CLKSEL0_CON reg bit************************************/ -#define CLKSEL0_HCLK (0) -#define CLKSEL0_PCLK (2) - -#define CLKSEL0_HCLK21 (0x01 - -#define DDR_SAVE_SP do { save_sp = ddr_save_sp((DTCM_END&(~7))); } while (0) -#define DDR_RESTORE_SP do { ddr_save_sp(save_sp); } while (0) -unsigned long ddr_save_sp( unsigned long new_sp ); -extern unsigned long save_sp; -extern int __tcmdata ddr_disabled; - -/* - * delay at itcm. one loops == 6 arm instruction - * at 600M,about 6,000,0 for 1ms delay. - */ -extern void __tcmfunc ddr_pll_delay( int loops ) ; - -/** - * tcm_udelay - delay usecs microseconds in tcm - * @usecs: in microseconds - * @arm_freq_mhz: arm frequency in MHz - * - * for example when arm run at slow mode, call tcm_udelay(usecs, 24) - */ -extern void __tcmfunc tcm_udelay(unsigned long usecs, unsigned long arm_freq_mhz); -void scu_set_clk_for_reboot( void ); -void ddr_change_mode( int performance ); -void change_ddr_freq(int freq_MHZ); -extern void kernel_restart(char *cmd); -#endif diff --git a/arch/arm/mach-rk2818/include/mach/spi_fpga.h b/arch/arm/mach-rk2818/include/mach/spi_fpga.h deleted file mode 100755 index 1c9a4f9faba2..000000000000 --- a/arch/arm/mach-rk2818/include/mach/spi_fpga.h +++ /dev/null @@ -1,570 +0,0 @@ -/* -defines of FPGA chip ICE65L08's register -*/ - -#ifndef SPI_UART_H -#define SPI_UART_H - -#include -#include - -#define SPI_FPGA_INT_PIN RK2818_PIN_PA4 -#define SPI_DPRAM_INT_PIN RK2818_PIN_PA2 -#define SPI_FPGA_STANDBY_PIN RK2818_PIN_PH7 -#define SPI_FPGA_RST_PIN RK2818_PIN_PF4 - -#define SPI_FPGA_POLL_WAIT 0 -#define SPI_FPGA_TRANS_WORK 1 -#define SPI_FPGA_TEST_DEBUG 0 -#if SPI_FPGA_TEST_DEBUG -#define SPI_FPGA_TEST_DEBUG_PIN RK2818_PIN_PE0 -extern int spi_test_wrong_handle(void); -#endif - -#define TRUE 1 -#define FALSE 0 - -struct uart_icount { - __u32 cts; - __u32 dsr; - __u32 rng; - __u32 dcd; - __u32 rx; - __u32 tx; - __u32 frame; - __u32 overrun; - __u32 parity; - __u32 brk; -}; - -struct spi_uart -{ - struct workqueue_struct *spi_uart_workqueue; - struct work_struct spi_uart_work; - struct timer_list uart_timer; - struct tty_struct *tty; - struct kref kref; - struct mutex open_lock; - struct task_struct *in_spi_uart_irq; - struct circ_buf xmit; - struct uart_icount icount; - spinlock_t write_lock; - spinlock_t irq_lock; - unsigned int index; - unsigned int opened; - unsigned int regs_offset; - unsigned int uartclk; - unsigned int mctrl; - unsigned int read_status_mask; - unsigned int ignore_status_mask; - unsigned char x_char; - unsigned char ier; - unsigned char lcr; - -}; - -struct spi_gpio -{ - struct workqueue_struct *spi_gpio_workqueue; - struct work_struct spi_gpio_work; - struct workqueue_struct *spi_gpio_irq_workqueue; - struct work_struct spi_gpio_irq_work; - struct timer_list gpio_timer; - struct list_head msg_queue; - -}; -struct spi_i2c_data -{ - struct i2c_adapter adapter; - struct i2c_client *client; - struct spi_fpga_port *port; - unsigned int speed; - unsigned int mode; - unsigned int msg_idx; - unsigned int msg_num; -}; -struct spi_i2c -{ - struct workqueue_struct *spi_i2c_workqueue; - struct work_struct spi_i2c_work; - struct timer_list i2c_timer; - struct i2c_adapter *adapter; - struct i2c_client *client; - spinlock_t i2c_lock ; - unsigned char interrupt; - unsigned char i2c_data_width[2]; - unsigned int speed[2]; - wait_queue_head_t wait_w,wait_r; -}; - -struct spi_dpram -{ - struct workqueue_struct *spi_dpram_workqueue; - struct work_struct spi_dpram_work; - struct workqueue_struct *spi_dpram_irq_workqueue; - struct work_struct spi_dpram_irq_work; - struct timer_list dpram_timer; - unsigned char *prx; - unsigned char *ptx; - unsigned int rec_len; - unsigned int send_len; - unsigned int max_rec_len; - unsigned int max_send_len; - volatile int apwrite_en; - unsigned short int dpram_addr; - struct semaphore rec_sem; - struct semaphore send_sem; - struct mutex rec_lock,send_lock; - spinlock_t spin_rec_lock,spin_send_lock; - wait_queue_head_t recq, sendq; - struct miscdevice miscdev; - - int (*write_dpram)(struct spi_dpram *, unsigned short int addr, unsigned char *buf, unsigned int len); - int (*read_dpram)(struct spi_dpram *, unsigned short int addr, unsigned char *buf, unsigned int len); - int (*write_ptr)(struct spi_dpram *, unsigned short int addr, unsigned int size); - int (*read_ptr)(struct spi_dpram *, unsigned short int addr); - int (*write_irq)(struct spi_dpram *, unsigned int mailbox); - int (*read_irq)(struct spi_dpram *); - int (*write_ack)(struct spi_dpram *, unsigned int mailbox); - int (*read_ack)(struct spi_dpram *); - -}; - -struct spi_fpga_port { - const char *name; - struct spi_device *spi; - spinlock_t work_lock; - struct mutex spi_lock; - struct workqueue_struct *fpga_irq_workqueue; - struct work_struct fpga_irq_work; - struct timer_list fpga_timer; -#if SPI_FPGA_TRANS_WORK - struct workqueue_struct *fpga_trans_workqueue; - struct work_struct fpga_trans_work; - int write_en; - int read_en; - wait_queue_head_t wait_wq, wait_rq; - struct list_head trans_queue; -#endif - -#if SPI_FPGA_POLL_WAIT - wait_queue_head_t spi_wait_q; -#endif - - /*spi2uart*/ -#ifdef CONFIG_SPI_FPGA_UART - struct spi_uart uart; -#endif - /*spi2gpio*/ -#ifdef CONFIG_SPI_FPGA_GPIO - struct spi_gpio gpio; -#endif - /*spi2i2c*/ -#ifdef CONFIG_SPI_FPGA_I2C - struct spi_i2c i2c; -#endif - /*spi2dpram*/ -#ifdef CONFIG_SPI_FPGA_DPRAM - struct spi_dpram dpram; -#endif - -}; - - -#define ICE_CC72 0 -#define ICE_CC196 1 -#define FPGA_TYPE ICE_CC196 -#define SEL_UART 0 -#define SEL_GPIO 1 -#define SEL_I2C 2 -#define SEL_DPRAM 3 -#define READ_TOP_INT 4 - -/* CMD */ -#define ICE_SEL_UART (SEL_UART<<6) -#define ICE_SEL_GPIO (SEL_GPIO<<6) -#define ICE_SEL_I2C (SEL_I2C<<6) -#define ICE_SEL_DPRAM (SEL_DPRAM<<6) - -#define ICE_SEL_WRITE (~(1<<5)) -#define ICE_SEL_READ (1<<5) - -#define ICE_SEL_UART_CH(ch) ((ch&0x03)<<3) -#define ICE_SEL_READ_INT_TYPE (3<<3) - -/*read int type*/ -#define ICE_INT_TYPE_UART0 (~(1<<0)) -#define ICE_INT_TYPE_UART1 (~(1<<1)) -#define ICE_INT_TYPE_UART2 (~(1<<2)) -#define ICE_INT_TYPE_I2C2 (~(1<<3)) -#define ICE_INT_TYPE_I2C3 (~(1<<4)) -#define ICE_INT_TYPE_GPIO (~(1<<5)) -#define ICE_INT_TYPE_DPRAM (~(1<<6)) -#define ICE_INT_TYPE_SLEEP (~(1<<7)) - -#define ICE_INT_I2C_ACK (~(1<<0)) -#define ICE_INT_I2C_READ (~(1<<1)) -#define ICE_INT_I2C_WRITE (~(1<<2)) - -/*spi to uart*/ -#define ICE_RXFIFO_FULL (1<<8) -#define ICE_RXFIFO_NOT_FULL (~(1<<8)) -#define ICE_RXFIFO_EMPTY (1<<9) -#define ICE_RXFIFO_NOT_EMPTY (~(1<<9)) -#define ICE_TXFIFO_FULL (1<<10) -#define ICE_TXFIFO_NOT_FULL (~(1<<10)) -#define ICE_TXFIFO_EMPTY (1<<11) -#define ICE_TXFIFO_NOT_EMPTY (~(1<<11)) - - -/*spi to gpio*/ -#define ICE_SEL_GPIO0 (0X00<<3) //INT/GPIO0 -#define ICE_SEL_GPIO1 (0X02<<2) //GPIO1 -#define ICE_SEL_GPIO2 (0X03<<2) -#define ICE_SEL_GPIO3 (0X04<<2) -#define ICE_SEL_GPIO4 (0X05<<2) -#define ICE_SEL_GPIO5 (0X06<<2) - -#define ICE_SEL_GPIO0_TYPE (0X00) -#define ICE_SEL_GPIO0_DIR (0X01) -#define ICE_SEL_GPIO0_DATA (0X02) -#define ICE_SEL_GPIO0_INT_EN (0X03) -#define ICE_SEL_GPIO0_INT_TRI (0X04) //0:falling edge 1:rising edge -#define ICE_SEL_GPIO0_INT_STATE (0X05) -#define ICE_SEL_GPIO0_INT_TYPE (0X06) //0:edge 1:level,if 1 then support falling and rising trigger -#define ICE_SEL_GPIO0_INT_WAKE (0X07) - -#define ICE_SEL_GPIO_DIR (0X01) -#define ICE_SEL_GPIO_DATA (0X02) - -#define ICE_STATUS_SLEEP 1 -#define ICE_STATUS_WAKE 0 - -/*spi to i2c*/ - -typedef enum I2C_ch -{ - I2C_CH0, - I2C_CH1, - I2C_CH2, - I2C_CH3 -}eI2C_ch_t; -typedef enum eI2CReadMode -{ - I2C_NORMAL, - I2C_NO_REG, - I2C_NO_STOP -}eI2ReadMode_t; - -#define ICE_SEL_I2C_START (0<<0) -#define ICE_SEL_I2C_STOP (1<<0) -#define ICE_SEL_I2C_RESTART (2<<0) -#define ICE_SEL_I2C_TRANS (3<<0) -#define ICE_SEL_I2C_SMASK (~(3<<0)) -#define ICE_SEL_I2C_CH2 (0<<2) -#define ICE_SEL_I2C_CH3 (1<<2) -#define ICE_SEL_I2C_DEFMODE (0<<3) -#define ICE_SEL_I2C_FIFO (1<<3) -#define ICE_SEL_I2C_SPEED (2<<3) -#define ICE_SEL_I2C_INT (3<<3) -#define ICE_SEL_I2C_MMASK (~(3<<3)) - -#define ICE_I2C_SLAVE_WRITE (0<<0) -#define ICE_I2C_SLAVE_READ (1<<0) - - - -#define ICE_SEL_I2C_W8BIT (0<<2) -#define ICE_SEL_I2C_W16BIT (1<<2) -#define ICE_SEL_I2C_DWIDTH (2<<2) - -#define ICE_I2C_AD_ACK (~(1<<0)) -#define ICE_I2C_WRITE_ACK (~(1<<1)) -#define ICE_I2C_READ_ACK (~(1<<2)) - -#define ICE_SEL_I2C_CH2_8BIT (0<<2) -#define ICE_SEL_I2C_CH2_16BIT (1<<2) -#define ICE_SEL_I2C_CH2_MIX (2<<2) - -#define ICE_SEL_I2C_CH3_8BIT (4<<2) -#define ICE_SEL_I2C_CH3_16BIT (5<<2) -#define ICE_SEL_I2C_CH3_MIX (6<<2) -#define ICE_SEL_I2C_RD_A (7<<2) -#define ICE_SEL_I2C_MASK (7<<2) -#define ICE_SEL_I2C_ACK3 (1<<1) -#define ICE_SEL_I2C_ACK2 (0<<1) - -#define INT_I2C_WRITE_ACK (2) -#define INT_I2C_WRITE_NACK (3) -#define INT_I2C_READ_ACK (4) -#define INT_I2C_READ_NACK (5) -#define INT_I2C_WRITE_MASK (~(1<<1)) -#define INT_I2C_READ_MASK (~(1<<2)) - -#define ICE_SET_10K_I2C_SPEED (0x01) -#define ICE_SET_100K_I2C_SPEED (0x02) -#define ICE_SET_200K_I2C_SPEED (0x04) -#define ICE_SET_300K_I2C_SPEED (0x08) -#define ICE_SET_400K_I2C_SPEED (0x10) - - -/*spi to dpram*/ -#define ICE_SEL_DPRAM_NOMAL (~(1<<5)) -#define ICE_SEL_DPRAM_SEM (1<<5) -#define ICE_SEL_DPRAM_READ (~(1<<4)) -#define ICE_SEL_DPRAM_WRITE (1<<4) -#define ICE_SEL_DPRAM_BL1 (0) -#define ICE_SEL_DPRAM_BL32 (1) -#define ICE_SEL_DPRAM_BL64 (2) -#define ICE_SEL_DPRAM_BL128 (3) -#define ICE_SEL_DPRAM_FULL (4) - -#define ICE_SEL_SEM_WRITE (0x7F) -#define ICE_SEL_SEM_READ (0xBF) -#define ICE_SEL_SEM_WRRD (0x3F) - -typedef void (*pSpiFunc)(void); //¶¨Ò庯ÊýÖ¸Õë, ÓÃÓÚµ÷Óþø¶ÔµØÖ· -typedef void (*pSpiFuncIntr)(int,void *); -typedef struct -{ - pSpiFuncIntr gpio_vector; - void *gpio_devid; -}SPI_GPIO_PDATA; - - -typedef enum eSpiGpioTypeSel -{ - SPI_GPIO0_IS_GPIO = 0, - SPI_GPIO0_IS_INT, -}eSpiGpioTypeSel_t; - - - -typedef enum eSpiGpioPinInt -{ - SPI_GPIO_INT_DISABLE = 0, - SPI_GPIO_INT_ENABLE, -}eSpiGpioPinInt_t; - - -typedef enum eSpiGpioIntTri -{ - SPI_GPIO_EDGE_FALLING = 0, - SPI_GPIO_EDGE_RISING, -}eSpiGpioIntTri_t; - - -typedef enum eSpiGpioIntType -{ - SPI_GPIO_EDGE = 0, - SPI_GPIO_LEVEL, -}eSpiGpioIntType_t; - -typedef enum eSpiGpioPinDirection -{ - SPI_GPIO_IN = 0, - SPI_GPIO_OUT, - SPI_GPIO_DIR_ERR, -}eSpiGpioPinDirection_t; - - -typedef enum eSpiGpioPinLevel -{ - SPI_GPIO_LOW = 0, - SPI_GPIO_HIGH, - SPI_GPIO_LEVEL_ERR, -}eSpiGpioPinLevel_t; - -#if (FPGA_TYPE == ICE_CC72) -typedef enum eSpiGpioPinNum -{ - SPI_GPIO_P0_00 = 0, //GPIO0[0] - SPI_GPIO_P0_01, - SPI_GPIO_P0_02, - SPI_GPIO_P0_03, - SPI_GPIO_P0_04, - SPI_GPIO_P0_05, - - SPI_GPIO_P2_00, - SPI_GPIO_P2_01, - SPI_GPIO_P2_02, - SPI_GPIO_P2_03, - SPI_GPIO_P2_04, - SPI_GPIO_P2_05, - SPI_GPIO_P2_06, - SPI_GPIO_P2_07, - SPI_GPIO_P2_08, - SPI_GPIO_P2_09 = 15, //GPIO0[15],the last interrupt/gpio pin - - SPI_GPIO_P3_00 = 16, //GPIO1[0] - SPI_GPIO_P3_01, - SPI_GPIO_P3_02, - SPI_GPIO_P3_03, - SPI_GPIO_P3_04, - SPI_GPIO_P3_05, - SPI_GPIO_P3_06, - SPI_GPIO_P3_07, - SPI_GPIO_P3_08, - SPI_GPIO_P3_09, - SPI_GPIO_P0_06 = 26, - SPI_GPIO_I2C3_SCL, - SPI_GPIO_I2C3_SDA, - SPI_GPIO_I2C4_SCL, - SPI_GPIO_I2C4_SDA, - -}eSpiGpioPinNum_t; - -#elif (FPGA_TYPE == ICE_CC196) - -typedef enum eSpiGpioPinNum -{ - //GPIO0/INT - SPI_GPIO_P6_00 = 0, //HS_DET input - SPI_GPIO_P6_01, - SPI_GPIO_P6_02, - SPI_GPIO_P6_03, - SPI_GPIO_P6_04, //CM3605_POUT_L_INT input - SPI_GPIO_P6_05, - SPI_GPIO_P6_06, //CHG_OK input - SPI_GPIO_P6_07, //HP_HOOK input - SPI_GPIO_P6_08, - SPI_GPIO_P6_09, - SPI_GPIO_P6_10, //DEFSEL input - SPI_GPIO_P6_11, //FLASH_WP_INT input - SPI_GPIO_P6_12, //LOW_BATT_INT input - SPI_GPIO_P6_13, //DC_DET input - SPI_GPIO_P3_08, - SPI_GPIO_P3_09 = 15, - - //GPIO1 - SPI_GPIO_P1_00 = 16, //LCD_ON output - SPI_GPIO_P1_01, //LCD_PWR_CTRL output - SPI_GPIO_P1_02, //SD_POW_ON output - SPI_GPIO_P1_03, //WL_RST_N/WIFI_EN output - SPI_GPIO_P1_04, //HARDO,input - SPI_GPIO_P1_05, //SENSOR_PWDN output - SPI_GPIO_P1_06, //BT_PWR_EN output - SPI_GPIO_P1_07, //BT_RST output - SPI_GPIO_P1_08, //BT_WAKE_B output - SPI_GPIO_P1_09, //LCD_DISP_ON output - SPI_GPIO_P1_10, //WM_PWR_EN output - SPI_GPIO_P1_11, //HARD1,input - SPI_GPIO_P1_12, //VIB_MOTO output - SPI_GPIO_P1_13, //KEYLED_EN output - SPI_GPIO_P1_14, //CAM_RST output - SPI_GPIO_P1_15 = 31, //WL_WAKE_B output - - //GPIO2 - SPI_GPIO_P2_00 = 32, //Y+YD input - SPI_GPIO_P2_01, //Y-YU input - SPI_GPIO_P2_02, //AP_TD_UNDIFED input - SPI_GPIO_P2_03, //AP_PW_EN_TD output - SPI_GPIO_P2_04, //AP_RESET_TD output - SPI_GPIO_P2_05, //AP_SHUTDOWN_TD_PMU output - SPI_GPIO_P2_06, //AP_RESET_CMMB output - SPI_GPIO_P2_07, //AP_CHECK_TD_STATUS input - SPI_GPIO_P2_08, //CHARGE_CURRENT_SEL output - SPI_GPIO_P2_09, //AP_PWD_CMMB output - SPI_GPIO_P2_10, //X-XL input - SPI_GPIO_P2_11, //X+XR input - SPI_GPIO_P2_12, //LCD_RESET output - SPI_GPIO_P2_13, //USB_PWR_EN output - SPI_GPIO_P2_14, //WL_HOST_WAKE_B output - SPI_GPIO_P2_15 = 47, //TOUCH_SCREEN_RST output - - //GPIO3 - SPI_GPIO_P0_00 = 48, // - SPI_GPIO_P0_01, - SPI_GPIO_P0_02, - SPI_GPIO_P0_03, - SPI_GPIO_P0_04, - SPI_GPIO_P0_05, - SPI_GPIO_P0_06, - SPI_GPIO_P0_07, - SPI_GPIO_P0_08, - SPI_GPIO_P0_09, //FPGAС°å¸ÃÒý½ÅδÒý³ö C5 - SPI_GPIO_P0_10, - SPI_GPIO_P0_11, - SPI_GPIO_P0_12, - SPI_GPIO_P0_13, - SPI_GPIO_P0_14, - SPI_GPIO_P0_15 = 63, - - //GPIO4 - SPI_GPIO_P4_00 = 64, - SPI_GPIO_P4_01, - SPI_GPIO_P4_02, - SPI_GPIO_P4_03, - SPI_GPIO_P4_04, - SPI_GPIO_P4_05, - SPI_GPIO_P4_06, //CHARGER_INT_END input - SPI_GPIO_P4_07, //CM3605_PWD output - SPI_GPIO_P3_00, - SPI_GPIO_P3_01, - SPI_GPIO_P3_02, - SPI_GPIO_P3_03, - SPI_GPIO_P3_04, - SPI_GPIO_P3_05, - SPI_GPIO_P3_06, - SPI_GPIO_P3_07 = 79, - - //GPIO5 - SPI_GPIO_P4_08 = 80, //CM3605_PS_SHUTDOWN - SPI_GPIO_P0_TXD2, //temp - -}eSpiGpioPinNum_t; - -#endif - - -typedef enum eSpiGpioPinIntIsr -{ - SPI_GPIO_IS_INT = 0, - SPI_GPIO_NO_INT, -}eSpiGpioPinIntIsr_t; - -extern struct spi_fpga_port *pFpgaPort; -#if SPI_FPGA_TRANS_WORK -extern int spi_write_work(struct spi_device *spi, u8 *buf, size_t len); -#endif -extern unsigned int spi_in(struct spi_fpga_port *port, int reg, int type); -extern void spi_out(struct spi_fpga_port *port, int reg, int value, int type); - -#if defined(CONFIG_SPI_FPGA_UART) -extern void spi_uart_handle_irq(struct spi_device *spi); -extern int spi_uart_register(struct spi_fpga_port *port); -extern int spi_uart_unregister(struct spi_fpga_port *port); -#endif -#if defined(CONFIG_SPI_FPGA_GPIO) -extern int spi_gpio_int_sel(eSpiGpioPinNum_t PinNum,eSpiGpioTypeSel_t type); -extern int spi_gpio_set_pindirection(eSpiGpioPinNum_t PinNum,eSpiGpioPinDirection_t direction); -extern int spi_gpio_set_pinlevel(eSpiGpioPinNum_t PinNum, eSpiGpioPinLevel_t PinLevel); -extern eSpiGpioPinLevel_t spi_gpio_get_pinlevel(eSpiGpioPinNum_t PinNum); -extern int spi_gpio_enable_int(eSpiGpioPinNum_t PinNum); -extern int spi_gpio_disable_int(eSpiGpioPinNum_t PinNum); -extern int spi_gpio_set_int_trigger(eSpiGpioPinNum_t PinNum,eSpiGpioIntTri_t IntTri); -extern int spi_gpio_read_iir(void); -extern int spi_request_gpio_irq(eSpiGpioPinNum_t PinNum, pSpiFunc Routine, eSpiGpioIntTri_t IntType,void *dev_id); -extern int spi_free_gpio_irq(eSpiGpioPinNum_t PinNum); -extern int spi_gpio_handle_irq(struct spi_device *spi); -extern int spi_gpio_init(void); -extern void spi_gpio_irq_setup(void); -extern int spi_gpio_register(struct spi_fpga_port *port); -extern int spi_gpio_unregister(struct spi_fpga_port *port); -#endif -#if defined(CONFIG_SPI_FPGA_I2C) -extern int spi_i2c_handle_irq(struct spi_fpga_port *port,unsigned char channel); -extern int spi_i2c_register(struct spi_fpga_port *port,int num); -extern int spi_i2c_unregister(struct spi_fpga_port *port); -#endif -#if defined(CONFIG_SPI_FPGA_DPRAM) -extern int spi_dpram_handle_ack(struct spi_device *spi); -extern int spi_dpram_register(struct spi_fpga_port *port); -extern int spi_dpram_unregister(struct spi_fpga_port *port); -#endif - -#if defined(CONFIG_SPI_FPGA_FW) -extern int __init fpga_dl_fw(void); -#endif - -#endif diff --git a/arch/arm/mach-rk2818/include/mach/system.h b/arch/arm/mach-rk2818/include/mach/system.h deleted file mode 100644 index d96755306066..000000000000 --- a/arch/arm/mach-rk2818/include/mach/system.h +++ /dev/null @@ -1,57 +0,0 @@ -/* arch/arm/mach-rk2818/include/mach/system.h - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - - /*************** -* DEBUG -****************/ -#define RESTART_DEBUG -#ifdef RESTART_DEBUG -#define restart_dbg(format, arg...) \ - printk("RESTART_DEBUG : " format "\n" , ## arg) -#else -#define restart_dbg(format, arg...) do {} while (0) -#endif - -#ifdef CONFIG_RK2818_POWER -extern int rk2818_restart( int mode, const char *cmd) ; - -static inline void arch_reset(int mode, const char *cmd) -{ - - /* - * debug trace - */ - restart_dbg("%s->%s->%d->mode=%d cmd=%s",__FILE__,__FUNCTION__,__LINE__,mode,cmd); - rk2818_restart( mode, cmd) ; -} - -#else - -static inline void arch_reset(int mode, const char *cmd) -{ - - /* - * debug trace - */ - restart_dbg("%s->%s->%d->mode=%c cmd=%s",__FILE__,__FUNCTION__,__LINE__,mode,cmd); - printk("Can't reboot. Please open rk2818 power manage!!\n"); - for(;;); -} -#endif - -static inline void arch_idle(void) -{ - cpu_do_idle(); -} diff --git a/arch/arm/mach-rk2818/include/mach/timex.h b/arch/arm/mach-rk2818/include/mach/timex.h deleted file mode 100644 index b6027f0682de..000000000000 --- a/arch/arm/mach-rk2818/include/mach/timex.h +++ /dev/null @@ -1,21 +0,0 @@ -/* arch/arm/mach-rk2818/include/mach/timex.h - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __ASM_ARCH_RK2818_TIMEX_H -#define __ASM_ARCH_RK2818_TIMEX_H - -#define CLOCK_TICK_RATE 1000000 - -#endif diff --git a/arch/arm/mach-rk2818/include/mach/uncompress.h b/arch/arm/mach-rk2818/include/mach/uncompress.h deleted file mode 100644 index c6f711b6fbf1..000000000000 --- a/arch/arm/mach-rk2818/include/mach/uncompress.h +++ /dev/null @@ -1,36 +0,0 @@ -/* arch/arm/mach-rk2818/include/mach/uncompress.h - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __ASM_ARCH_RK2818_UNCOMPRESS_H - -#include "hardware.h" - -static void putc(int c) -{ -} - -static inline void flush(void) -{ -} - -static inline void arch_decomp_setup(void) -{ -} - -static inline void arch_decomp_wdog(void) -{ -} - -#endif diff --git a/arch/arm/mach-rk2818/include/mach/vmalloc.h b/arch/arm/mach-rk2818/include/mach/vmalloc.h deleted file mode 100644 index dc22dadfe03b..000000000000 --- a/arch/arm/mach-rk2818/include/mach/vmalloc.h +++ /dev/null @@ -1,22 +0,0 @@ -/* arch/arm/mach-rk2818/include/mach/vmalloc.h - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __ASM_ARCH_RK2818_VMALLOC_H -#define __ASM_ARCH_RK2818_VMALLOC_H - -#define VMALLOC_END (PAGE_OFFSET + 0x18000000) - -#endif - diff --git a/arch/arm/mach-rk2818/include/mach/vreg.h b/arch/arm/mach-rk2818/include/mach/vreg.h deleted file mode 100644 index 85aca9c10366..000000000000 --- a/arch/arm/mach-rk2818/include/mach/vreg.h +++ /dev/null @@ -1,28 +0,0 @@ -/* linux/include/asm-arm/arch-rk2818/vreg.h - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __ARCH_ARM_MACH_RK2818_VREG_H -#define __ARCH_ARM_MACH_RK2818_VREG_H - -struct vreg; - -struct vreg *vreg_get(struct device *dev, const char *id); -void vreg_put(struct vreg *vreg); - -int vreg_enable(struct vreg *vreg); -void vreg_disable(struct vreg *vreg); -int vreg_set_level(struct vreg *vreg, unsigned mv); - -#endif diff --git a/arch/arm/mach-rk2818/iomux.c b/arch/arm/mach-rk2818/iomux.c deleted file mode 100755 index 1b8db69ff0cf..000000000000 --- a/arch/arm/mach-rk2818/iomux.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * arch/arm/mach-rk2818/iomux.c - * - *Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include -#include -#include -#include -#include - -#include -#include - - -#define RK2818_IOMUX_A_CON (RK2818_REGFILE_BASE + IOMUX_A_CON) -#define RK2818_IOMUX_B_CON (RK2818_REGFILE_BASE + IOMUX_B_CON) - -static struct mux_config rk2818_muxs[] = { -/* - * description mux mode mux mux - * reg offset inter mode - */ -MUX_CFG(GPIOE_I2C0_SEL_NAME, A, 30, 2, 0, DEFAULT) /* 0: i2c0_sda/scl gpioe_u1ir_i2c1 */ -MUX_CFG(GPIOE_U1IR_I2C1_NAME, A, 28, 2, 0, DEFAULT) /* 00 : gpio_e6/e7 01 gpiof1_uart1_cpwm1_out_n 10 : i2c1_sda/scl */ -MUX_CFG(GPIOF1_UART1_CPWM1_NAME, A, 26, 2, 1, DEFAULT) /* 00 : gpio_f1 01 : uart1_sout 10 : cx_timer1_pwm */ -MUX_CFG(GPIOF0_UART1_CPWM0_NAME, A, 24, 2, 1, DEFAULT) /* 00 : gpio_f0 01 : uart1_sin 10 : cx_timer0_pwm */ -MUX_CFG(GPIOG_MMC1_SEL_NAME, A, 23, 1, 0, DEFAULT) /* 0 : gpio_g2/g3/g7 1: sdmmc1_cmd/data0/clkout */ -MUX_CFG(GPIOG_MMC1D_SEL_NAME, A, 22, 1, 0, DEFAULT) /* 0 : gpio_g4/g5/g6 1 : sdmmc1_data1/data2/data3 */ -MUX_CFG(GPIOE_SPI1_FLASH_SEL_NAME, A, 20, 2, 0, DEFAULT) /* 00 : gpio_e1/e2/e3/f7 01 : spi1_clkin/spi1_ss_in_n/spi1_rxd/spi1_txd 10 :flash_cs6 / flash_cs7*/ -MUX_CFG(GPIOE_SPI1_FLASH_SEL1_NAME, A, 18, 2, 0, DEFAULT) /*00 : gpio1_a1/a2 01 : spi1_clkin/spi1_ss_in_n 10 : flash_cs4 / flash_cs5 */ -MUX_CFG(GPIOB0_SPI0CSN1_MMC1PCA_NAME, A, 16, 2, 0, DEFAULT) /* 00 : gpio_b0 01 : spi0_csn1 10 : sdmmc1_pwr_en */ -MUX_CFG(GPIOG1_UART0_MMC1WPT_NAME, A, 14, 2, 0, DEFAULT) /* 00 : gpio_g1 01 : uart0_sout 10 : sdmmc1_write_prt */ -MUX_CFG(GPIOG0_UART0_MMC1DET_NAME, A, 12, 2, 0, DEFAULT) /* 00 : gpio_g0 01 : uart0_sin 10 : sdmmc1_detect_n */ -MUX_CFG(GPIOF4_APWM2_MMC0WPT_NAME, A, 10, 2, 0, DEFAULT) /* 00 : gpio_f4 01 : pwm2 10 : sdmmc0_write_prt */ -MUX_CFG(GPIOF3_APWM1_MMC0DETN_NAME, A, 8, 2, 0, DEFAULT) /* 00 : gpio_f3 01 : pwm1 10 : sdmmc0_detect_n */ -MUX_CFG(GPIOB1_SMCS1_MMC0PCA_NAME, A, 6, 2, 0, DEFAULT) /* 00 : gpio_b1 01 : sm_cs1_n 10 : sdmmc0_pwr_en */ -MUX_CFG(GPIOH_MMC0D_SEL_NAME, A, 5, 1, 0, DEFAULT) /* 0 : gpio_h2/h3/h4 1 : sdmm0_data1/data2/data3 */ -MUX_CFG(GPIOH_MMC0_SEL_NAME, A, 4, 1, 0, DEFAULT) /* 0 : gpio_h0/h1/h5 1 : sdmmc0_cmd/data0/clkout */ -MUX_CFG(GPIOB_SPI0_MMC0_NAME, A, 2, 2, 0, DEFAULT) /* 00 : gpio_b5/b6/b7 01 : spi0_clkout/spi0_txd/spi0_rxd 10 : sdmmc0_data5/data6/data7 */ -MUX_CFG(GPIOB4_SPI0CS0_MMC0D4_NAME, A, 0, 2, 0, DEFAULT) /* 00 : gpio_b4 01 : spi0_csn0 10 : sdmmc0_data4 */ - -MUX_CFG(GPIOF34_UART3_SEL_NAME, B, 31, 1, 0, DEFAULT) /*0 : gpio1_b3 / gpio1_b4 function is decided by gpio1b3_apwm1_mmc0detn(IOMUX_A_CON[9:8]) and gpio1b4_apwm2_mmc0wpt(IOMUX_A_CON[11:10] separately 1 : uart3_sin / uart3_sout*/ -MUX_CFG(GPIOF01_UART2_SEL_NAME, B, 30, 1, 0, DEFAULT) /*0 : gpio0_b0 / gpio0_b1 function is decided by gpio0b0_spi0csn1_mmc1pca(IOMUX_A_CON [17:16]) and gpio0b1_smcs1_mmc0pca(IOMUX_A_CON [7:6] separately 1 : uart2_sin / uart2_sout */ -MUX_CFG(GPIOA23_UART2_SEL_NAME, B, 29, 1, 0, DEFAULT) /*0 : gpio0_a2/gpio0_a3 1 : uart2_cts_n / uart2_rts_n */ -MUX_CFG(CXGPIO_HSADC_NORFLASH_SEL_NAME, B, 27, 2, 0, DEFAULT) /*00 : gpio2_22 ~ gpio2_23 01 : hsadc_data_q[9:8] 10 : sm_we_n/sm_oe_n */ -MUX_CFG(CXGPIO_HSADC_HIF_SEL_NAME, B, 25, 2, 0, DEFAULT) /*00 : gpio2_14 ~ gpio2_21 01 : hsadc_data_q[7:0] 10 : host_data[15:8]*/ -MUX_CFG(GPIOA1_HOSTDATA17_SEL_NAME, B, 24, 1, 0, DEFAULT) /*0 : gpio0_a1 1: host data 17 */ -MUX_CFG(GPIOA0_HOSTDATA16_SEL_NAME, B, 23, 1, 0, DEFAULT) /*0 : gpio0_a0 1: host data 16 */ -MUX_CFG(GPIOE0_VIPDATA0_SEL_NAME, B, 22, 1, 0, DEFAULT) /*0: gpio1_a0 1: vip_data0 */ -MUX_CFG(CXGPIO_GPSCLK_HSADCCLKOUT_NAME, B, 20, 2, 0, DEFAULT) /* 00 : gpio2_24 01 : gps clk 10 : hsadc_clkout */ -MUX_CFG(HSADCDATA_TSCON_SEL_NAME, B, 19, 1, 0, DEFAULT) /* 0: hsadc_data_i[9:8] 1: ts_fail / ts_valid */ -MUX_CFG(GPIOA7_FLASHCS3_SEL_NAME, B, 18, 1, 0, DEFAULT) /* 0 : gpio_a7 1 : flash_cs3 */ -MUX_CFG(GPIOA6_FLASHCS2_SEL_NAME, B, 17, 1, 0, DEFAULT) /* 0 : gpio_a6 1 : flash_cs2 */ -MUX_CFG(GPIOA5_FLASHCS1_SEL_NAME, B, 16, 1, 0, DEFAULT) /* 0 : gpio_a5 1 : flash_cs1 */ -MUX_CFG(GPIOF5_APWM3_DPWM3_NAME, B, 14, 2, 0, DEFAULT) /* 00 : gpio_f5 01 : pwm3 10 : demod pwm out */ -MUX_CFG(GPIOB3_U0RTSN_SEL_NAME, B, 13, 1, 0, DEFAULT) /* 0 : gpio_b3 1 : uart0_rts_n */ -MUX_CFG(GPIOB2_U0CTSN_SEL_NAME, B, 12, 1, 0, DEFAULT) /* 0 : gpio_b2 1 : uart0_cts_n */ -MUX_CFG(GPIOF2_APWM0_SEL_NAME, B, 11, 1, 0, INITIAL) /* 0 : gpio_f2 1 : pwm0 */ -MUX_CFG(GPIOC_LCDC16BIT_SEL_NAME, B, 10, 1, 1, INITIAL) /* 0 : gpio_d0 ~ gpio_d7 1 : lcdc_data8 ~ lcdc_data15 */ -#if defined(CONFIG_MACH_RAHO)||defined(CONFIG_MACH_RAHOSDK) -MUX_CFG(GPIOC_LCDC24BIT_SEL_NAME, B, 9, 1, 0, INITIAL) /* 0 : gpio_c2 ~ gpio_c7 1 : lcdc_data18 ~ lcdc_data23 */ -#else -MUX_CFG(GPIOC_LCDC24BIT_SEL_NAME, B, 9, 1, 1, INITIAL) /* 0 : gpio_c2 ~ gpio_c7 1 : lcdc_data18 ~ lcdc_data23 */ -#endif -MUX_CFG(GPIOC_LCDC18BIT_SEL_NAME, B, 8, 1, 1, INITIAL) /* 0 : gpio_c0/c1 1 : lcdc_data16 ~ lcdc_data17 */ -MUX_CFG(CXGPIO_LCDDEN_SEL_NAME, B, 7, 1, 1, INITIAL) /* 0 : gpio2_26 1 : lcdc_denable */ -MUX_CFG(CXGPIO_LCDVSYNC_SEL_NAME, B, 6, 1, 1, INITIAL) /* 0 : gpio2_25 1 : lcdc_vsync */ -MUX_CFG(CXGPIO_HSADC_SEL_NAME, B, 5, 1, 0, DEFAULT) /* 0 : gpio2_14 ~ gpio2_23 1 : hsadc_data_q[9:0] */ -MUX_CFG(CXGPIO_HOST_SEL_NAME, B, 4, 1, 0, DEFAULT) /* 0 : gpio2_0 ~ gpio2_13 1 : host interface */ -MUX_CFG(GPIOH7_HSADCCLK_SEL_NAME, B, 3, 1, 0, DEFAULT) /* 0 : gpio_h7 1 : hsadc_clkin */ -MUX_CFG(GPIOH6_IQ_SEL_NAME, B, 2, 1, 0, DEFAULT) /* 0 : gpio_h6 1 : ext_iq_index */ -MUX_CFG(CXGPIO_I2S_SEL_NAME, B, 1, 1, 0, DEFAULT) /* 0 : i2s interface 1 : gpio2_27 ~ gpio2_31 */ -MUX_CFG(GPIOF6_VIPCLK_SEL_NAME, B, 0, 1, 0, DEFAULT) /* 0 : gpio_f6 1 : vip clkout */ -}; - -void rk2818_mux_set(struct mux_config *cfg) -{ - int regValue; - int mask; - - mask = ((1<<(cfg->interleave))-1)<offset; - regValue = readl(cfg->mux_reg); - regValue &=~mask; - regValue |=(cfg->mode<offset); - #ifdef DEBUG_LHH - printk("%s::regValue is %x,mask is %x\n",__FUNCTION__,regValue,mask); - #endif - writel(regValue,cfg->mux_reg); - - return; -} - -int rk2818_iomux_init(void) -{ - int i; - for(i=0;i -#include -#include -#include - -//#include -//#include -#include -//#include - -//#include -//#include -#include -#include - -//#include "include/mach/irqs.h" -//#include "include/mach/rk2818_iomap.h" - -//#include -#include -//#include -//#include - -#include - - -#define which_irq_l(irq) (0x01u << (irq)) -#define which_irq_h(irq) (0x01u << ((irq) & 0x1f)) - -#define write_irq_reg(addr, val) __raw_writel(val, addr+(RK2818_INTC_BASE)) -#define read_irq_reg(addr) __raw_readl(addr+(RK2818_INTC_BASE)) -#define set_irq_reg(addr, val) write_irq_reg(addr, ((val) | read_irq_reg(addr))) -#define clear_irq_reg(addr, val) write_irq_reg(addr, (~(val) & read_irq_reg(addr))) - - - -u32 int_priority[NR_AIC_IRQS]={ - /* priority name number */ - 0, //IRQ_DWDMA, 0 -- low - 0, //IRQ_UHI, 1 -- USB Host Interface - 0, //IRQ_NANDC, 2 - 0, //IRQ_LCDC, 3 - 0, //IRQ_SDMMC0, 4 - 0, //IRQ_VIP, 5 - 0, //IRQ_GPIO0, 6 - 0, //IRQ_GPIO1, 7 - 0, //IRQ_OTG, 8 -- USB OTG - 0, //IRQ_ABTARMD, 9 -- Arbiter in ARMD BUS - 0, //IRQ_ABTEXP, 10 -- Arbiter in EXP BUS - 0, //IRQ_I2C0, 11 - 0, //IRQ_I2C1, 12 - 0, //IRQ_I2S, 13 - 0, //IRQ_SPIM, 14 -- SPI Master - 0, //IRQ_SPIS, 15 -- SPI Slave - 0, //IRQ_TIMER1, 16 - 0, //IRQ_TIMER2, 17 - 0, //IRQ_TIMER3, 18 - 0, //IRQ_UART0, 19 - 0, //IRQ_UART1, 20 - 0, //IRQ_WDT, 21 - 0, //IRQ_PWM0, 22 - 0, //IRQ_PWM1, 23 - 0, //IRQ_PWM2, 24 - 0, //IRQ_PWM3, 25 - 0, //IRQ_ADC, 26 - 0, //IRQ_RTC, 27 - 0, //IRQ_PIUSEM0, 28 -- PIU Semphore 0 - 0, //IRQ_PIUSEM1, 29 - 0, //IRQ_PIUSEM3, 30 - 0, //IRQ_PIUCMD, 31 -- PIU command/reply - 0, //IRQ_XDMA, 32 - 0, //IRQ_SDMMC1, 33 - 0, //IRQ_DSPSEI, 34 -- DSP slave interface error interrupt - 0, //IRQ_DSPSWI, 35 -- DSP interrupt by software set - 0, //IRQ_SCU, 36 - 0, //IRQ_SWI, 37 -- Software Interrupt - 0, //IRQ_DSPMEI, 38 -- DSP master interface error interrupt - 0, //IRQ_DSPSAEI, 39 -- DSP system access error interrupt - 0 //IRQ_MAXNUM 40 -- interrupt -}; - -static void rk2818_irq_ack(u32 irq) -{ -//rk28 no irq ack -} - -static void rk2818_irq_mask(u32 irq) -{ - if (irq >= 32) - { - set_irq_reg(IRQ_REG_INTMASK_H, which_irq_h(irq)); - } - else - { - set_irq_reg(IRQ_REG_INTMASK_L, which_irq_l(irq)); - } - -} - -static void rk2818_irq_unmask(u32 irq) -{ - if (irq >= 32) - { - clear_irq_reg(IRQ_REG_INTMASK_H, which_irq_h(irq)); - } - else - { - clear_irq_reg(IRQ_REG_INTMASK_L, which_irq_l(irq)); - } -} - -static s32 rk2818_irq_wake(u32 irq, u32 value) -{ -//rk28 no irq wake - return 0; -} - - -static struct irq_chip rk2818_irq_chip = { - .name = "rk2818_irq", - .ack = rk2818_irq_ack, - .mask = rk2818_irq_mask, - .unmask = rk2818_irq_unmask, - .set_wake = rk2818_irq_wake, -}; - - -/* - * Initialize the AIC interrupt controller. - */ -void __init rk2818_init_irq(u32 priority[NR_AIC_IRQS]) -{ - u32 i; - - write_irq_reg(IRQ_REG_INTEN_L, 0xffffffff);//enable irq interrupt - write_irq_reg(IRQ_REG_INTEN_H, 0xffffffff); - write_irq_reg(IRQ_REG_INTMASK_L, 0xffffffff); //mask all irq interrupt - write_irq_reg(IRQ_REG_INTMASK_H, 0xffffffff); - write_irq_reg(IRQ_REG_INTFORCE_L, 0); - write_irq_reg(IRQ_REG_INTFORCE_H, 0); - write_irq_reg(FIQ_REG_INTEN, 0x03); //enable fiq interrupt - write_irq_reg(FIQ_REG_INTMASK, 0x03); //mask fiq interrupt - write_irq_reg(IRQ_REG_PLEVEL, 0); - - for (i = 0; i < NR_AIC_IRQS; i++) { - set_irq_chip(i, &rk2818_irq_chip); - set_irq_handler(i, handle_level_irq); - set_irq_flags(i, IRQF_VALID);//no probe and auto enable - } -} diff --git a/arch/arm/mach-rk2818/pm.c b/arch/arm/mach-rk2818/pm.c deleted file mode 100755 index ea7be85587ff..000000000000 --- a/arch/arm/mach-rk2818/pm.c +++ /dev/null @@ -1,335 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern void rockchip_timer_clocksource_suspend_resume(int suspend); -extern int rockchip_timer_clocksource_irq_checkandclear(void); - -#ifdef CONFIG_DWC_OTG_HOST_ONLY -static int rk28_usb_suspend(int exitsuspend) { return 0; } -static int rk28_usb_check_vbus_change(void) { return 0; } -#else -extern int rk28_usb_suspend(int exitsuspend); -extern int rk28_usb_check_vbus_change(void); -#endif -#ifdef CONFIG_DWC_OTG_BOTH_HOST_SLAVE -extern int rk28_usb_check_connectid_change(void); -#else -static int rk28_usb_check_connectid_change(void) { return 0; } -#endif - -#define regfile_readl(offset) readl(RK2818_REGFILE_BASE + offset) - -#define scu_readl(offset) readl(RK2818_SCU_BASE + offset) -#define scu_writel(v, offset) writel(v, RK2818_SCU_BASE + offset) - -#define msdr_readl(offset) readl(RK2818_SDRAMC_BASE + offset) -#define msdr_writel(v, offset) writel(v, RK2818_SDRAMC_BASE + offset) - -#define ddr_readl(offset) readl(RK2818_SDRAMC_BASE + offset) -#define ddr_writel(v, offset) writel(v, RK2818_SDRAMC_BASE + offset) - -#define irq_readl(offset) readl(RK2818_INTC_BASE + offset) -#define gpio0_readl(offset) readl(RK2818_GPIO0_BASE + offset) -#define gpio1_readl(offset) readl(RK2818_GPIO1_BASE + offset) - -#define PLL_PD (0x01u<<22) - -/* CPU_APB_REG0 */ -#define MEMTYPESHIFT 11 -#define MEMTYPEMASK (0x3 << MEMTYPESHIFT) - -#define SDRAM 0 -#define MOBILE_SDRAM 1 -#define DDRII 2 -#define MOBILE_DDR 3 - -static inline u32 sdram_get_mem_type(void) -{ - return (regfile_readl(CPU_APB_REG0) & MEMTYPEMASK) >> MEMTYPESHIFT; -} - -#define ASM_LOOP_INSTRUCTION_NUM 4 - -#define CLK_GATE_SDRAM_MASK ((1 << (CLK_GATE_SDRAM_COMMON & 31)) | (1 << (CLK_GATE_SDRAM_CONTROLLER & 31))) -#define CLK_GATE_MOBILESDRAM_MASK ((1 << (CLK_GATE_SDRAM_COMMON & 31)) | (1 << (CLK_GATE_MOBILE_SDRAM_CONTROLLER & 31))) - -/* SDRAM Control Regitster */ -#define SR_MODE (1 << 11) -#define ENTER_SELF_REFRESH (1 << 1) -#define MSDR_SCTLR 0x0C // SDRAM control register - -/* CTR_REG_62 */ -#define MODE5_MASK (0xFFFF << 16) -#define MODE5_CNT(n) (((n) & 0xFFFF) << 16) -#define CTRL_REG_62 0xf8 // LOWPOWER_INTERNAL_CNT/LOWPOWER_EXTERNAL_CNT. - -/****************************************************************/ -//函数匿sdram_enter_self_refresh -//描述: SDRAM进入自刷新模帿 -//参数说明: -//返回伿对于DDR就是CTRL_REG_62的值，供sdram_exit_self_refresh使用 -//相关全局变量: -//注意:(1)系统完全idle后才能进入自刷新模式，进入自刷新后不能再访问SDRAM -// (2)要进入自刷新模式，必须保证运行时这个函数所调用到的所有代码不在SDRAM -/****************************************************************/ -u32 __tcmfunc sdram_enter_self_refresh(void) -{ - u32 r; - u32 mem_type = sdram_get_mem_type(); - - switch (mem_type) { - case SDRAM: - case MOBILE_SDRAM: - msdr_writel(msdr_readl(MSDR_SCTLR) | ENTER_SELF_REFRESH, MSDR_SCTLR); - - while (!(msdr_readl(MSDR_SCTLR) & SR_MODE)); //确定已经进入self-refresh - - /* Disable Mobile SDRAM/SDRAM Common/Controller hclk clock */ - r = scu_readl(SCU_CLKGATE1_CON); - if (SDRAM == mem_type) { - r |= CLK_GATE_SDRAM_MASK; - } else { - r |= CLK_GATE_MOBILESDRAM_MASK; - } - scu_writel(r, SCU_CLKGATE1_CON); - break; - - case DDRII: - case MOBILE_DDR: - r = ddr_readl(CTRL_REG_62); - ddr_writel((r & ~MODE5_MASK) | MODE5_CNT(1), CTRL_REG_62); - // tcm_printascii("3x DDRII\n"); - - break; - } - - return r; -} - -/****************************************************************/ -//函数匿sdram_exit_self_refresh -//描述: SDRAM退出自刷新模式 -//参数说明: -//返回伿 -//相关全局变量: -//注意:(1)SDRAM在自刷新模式后不能被访问，必须先退出自刷新模式 -// (2)必须保证运行时这个函数的代码不在SDRAM -/****************************************************************/ -void __tcmfunc sdram_exit_self_refresh(u32 ctrl_reg_62) -{ - u32 r; - u32 mem_type = sdram_get_mem_type(); - - switch (mem_type) { - case SDRAM: - case MOBILE_SDRAM: - /* Enable Mobile SDRAM/SDRAM Common/Controller hclk clock */ - r = scu_readl(SCU_CLKGATE1_CON); - if (SDRAM == mem_type) { - r &= ~CLK_GATE_SDRAM_MASK; - } else { - r &= ~CLK_GATE_MOBILESDRAM_MASK; - } - scu_writel(r, SCU_CLKGATE1_CON); - tcm_udelay(1, 24); // DRVDelayUs(1); - - msdr_writel(msdr_readl(MSDR_SCTLR) & ~ENTER_SELF_REFRESH, MSDR_SCTLR); - - while (msdr_readl(MSDR_SCTLR) & SR_MODE); //确定退出进入self-refresh - break; - - case DDRII: - case MOBILE_DDR: - ddr_writel(ctrl_reg_62, CTRL_REG_62); - break; - } - - tcm_udelay(100, 24); //DRVDelayUs(100); 延时一下比较安全，保证退出后稳定 -} - -#if 0 -static void __tcmlocalfunc noinline tcm_printch(char byte) -{ - unsigned int timeout; - - timeout = 0xffffffff; - while (!(readl(RK2818_UART1_BASE + 0x7c) & (1<<1))) { - if (!timeout--) - return; - } - writel(byte, RK2818_UART1_BASE); - if (byte == '\n') - tcm_printch('\r'); -} -static void __tcmlocalfunc noinline tcm_printascii(const char *s) -{ - while (*s) { - tcm_printch(*s); - s++; - } -} - -static void __tcmlocalfunc noinline tcm_printhex(unsigned int hex) -{ - int i = 8; - tcm_printch('0'); - tcm_printch('x'); - while (i--) { - unsigned char c = (hex & 0xF0000000) >> 28; - tcm_printch(c < 0xa ? c + '0' : c - 0xa + 'a'); - hex <<= 4; - } -} -#endif - -static int __tcmfunc rk2818_tcm_idle(void) -{ - volatile u32 unit; - u32 ctrl_reg_62; - - u32 scu_mode = scu_readl(SCU_MODE_CON); - u32 scu_apll = scu_readl(SCU_APLL_CON); - u32 scu_clksel0 = scu_readl(SCU_CLKSEL0_CON); - - asm("b 1f; .align 5; 1:"); - asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */ - - scu_writel(scu_mode & ~(3 << 2), SCU_MODE_CON); // slow - scu_writel(scu_apll | PLL_PD, SCU_APLL_CON); // powerdown - - //rk28_ddr_enter_self_refresh(); - tcm_udelay(5, 24); //DRVDelayUs(100); - ctrl_reg_62=sdram_enter_self_refresh(); - tcm_udelay(200, 24); //DRVDelayUs(100); - - rk2818_socpm_suspend_first(); - rk2818_socpm_suspend(); - tcm_udelay(1, 24); //DRVDelayUs(100); - - asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */ - - tcm_udelay(1, 24); //DRVDelayUs(100); - rk2818_socpm_resume(); - rk2818_socpm_resume_last(); - tcm_udelay(1, 24); //DRVDelayUs(100); - sdram_exit_self_refresh(ctrl_reg_62); - - tcm_udelay(10, 24); - scu_writel(scu_apll, SCU_APLL_CON); // powerup - scu_writel(scu_clksel0 & (~3), SCU_CLKSEL0_CON); - tcm_udelay(20, 24); - - unit = 7200; /* 24m,0.3ms , 24*300*/ - while (unit-- > 0) { - if (regfile_readl(CPU_APB_REG0) & 0x80) - break; - } - - tcm_udelay(5 << 8, 24); - scu_writel(scu_clksel0, SCU_CLKSEL0_CON); - tcm_udelay(5, 24); - - scu_writel(scu_mode, SCU_MODE_CON); // normal - return unit; -} - -static void rk2818_idle(void) -{ - unsigned long old_sp; - unsigned long tcm_sp = ITCM_END & ~7; - - asm volatile ("mov %0, sp" : "=r" (old_sp)); - asm volatile ("mov sp, %0" :: "r" (tcm_sp)); - rk2818_tcm_idle(); - asm volatile ("mov sp, %0" :: "r" (old_sp)); -} - -#if 1 -static void dump_register(void) -{ -#ifdef CONFIG_PM_DEBUG - printk(KERN_DEBUG "SCU_APLL_CON : 0x%08x\n", scu_readl(SCU_APLL_CON)); - printk(KERN_DEBUG "SCU_DPLL_CON : 0x%08x\n", scu_readl(SCU_DPLL_CON)); - printk(KERN_DEBUG "SCU_CPLL_CON : 0x%08x\n", scu_readl(SCU_CPLL_CON)); - printk(KERN_DEBUG "SCU_MODE_CON : 0x%08x\n", scu_readl(SCU_MODE_CON)); - printk(KERN_DEBUG "SCU_PMU_CON : 0x%08x\n", scu_readl(SCU_PMU_CON)); - printk(KERN_DEBUG "SCU_CLKSEL_CON : 0x%08x 0x%08x 0x%08x\n", scu_readl(SCU_CLKSEL0_CON), scu_readl(SCU_CLKSEL1_CON), scu_readl(SCU_CLKSEL2_CON)); - printk(KERN_DEBUG "SCU_CLKGATE_CON : 0x%08x 0x%08x 0x%08x\n", scu_readl(SCU_CLKGATE0_CON), scu_readl(SCU_CLKGATE1_CON), scu_readl(SCU_CLKGATE2_CON)); - printk(KERN_DEBUG "IRQ_INTEN : 0x%08x 0x%02x\n", irq_readl(IRQ_REG_INTEN_L), irq_readl(IRQ_REG_INTEN_H)); - printk(KERN_DEBUG "IRQ_INTMASK : 0x%08x 0x%02x\n", irq_readl(IRQ_REG_INTMASK_L), irq_readl(IRQ_REG_INTMASK_H)); - printk(KERN_DEBUG "IRQ_INTFORCE : 0x%08x 0x%02x\n", irq_readl(IRQ_REG_INTFORCE_L), irq_readl(IRQ_REG_INTFORCE_H)); - printk(KERN_DEBUG "IRQ_RAWSTATUS : 0x%08x 0x%02x\n", irq_readl(IRQ_REG_RAWSTATUS_L), irq_readl(IRQ_REG_RAWSTATUS_H)); - printk(KERN_DEBUG "IRQ_STATUS : 0x%08x 0x%02x\n", irq_readl(IRQ_REG_STATUS_L), irq_readl(IRQ_REG_STATUS_H)); - printk(KERN_DEBUG "IRQ_MASKSTATUS : 0x%08x 0x%02x\n", irq_readl(IRQ_REG_MASKSTATUS_L), irq_readl(IRQ_REG_MASKSTATUS_H)); - printk(KERN_DEBUG "IRQ_FINALSTATUS : 0x%08x 0x%02x\n", irq_readl(IRQ_REG_FINALSTATUS_L), irq_readl(IRQ_REG_FINALSTATUS_H)); - printk(KERN_DEBUG "GPIO_INTEN : 0x%08x 0x%08x\n", gpio0_readl(GPIO_INTEN), gpio1_readl(GPIO_INTEN)); - printk(KERN_DEBUG "GPIO_INTMASK : 0x%08x 0x%08x\n", gpio0_readl(GPIO_INTMASK), gpio1_readl(GPIO_INTMASK)); - printk(KERN_DEBUG "GPIO_INTTYPE_LEVEL : 0x%08x 0x%08x\n", gpio0_readl(GPIO_INTTYPE_LEVEL), gpio1_readl(GPIO_INTTYPE_LEVEL)); - printk(KERN_DEBUG "GPIO_INT_POLARITY : 0x%08x 0x%08x\n", gpio0_readl(GPIO_INT_POLARITY), gpio1_readl(GPIO_INT_POLARITY)); - printk(KERN_DEBUG "GPIO_INT_STATUS : 0x%08x 0x%08x\n", gpio0_readl(GPIO_INT_STATUS), gpio1_readl(GPIO_INT_STATUS)); - printk(KERN_DEBUG "GPIO_INT_RAWSTATUS : 0x%08x 0x%08x\n", gpio0_readl(GPIO_INT_RAWSTATUS), gpio1_readl(GPIO_INT_RAWSTATUS)); -#endif -} - -static int rk2818_pm_enter(suspend_state_t state) -{ - int irq_val = 0; - struct clk *arm_clk = clk_get(NULL, "arm"); - unsigned long arm_rate = clk_get_rate(arm_clk); - - clk_set_rate(arm_clk, 24000000); - dump_register(); - -#ifdef CONFIG_RK28_USB_WAKE - rockchip_timer_clocksource_suspend_resume(1); - - while (!irq_val) { - rk28_usb_suspend(0); -#endif - - rk2818_idle(); - -#ifdef CONFIG_RK28_USB_WAKE - rk28_usb_suspend(1); - udelay(400); - - irq_val = rockchip_timer_clocksource_irq_checkandclear(); - irq_val |= rk28_usb_check_vbus_change(); - irq_val |= rk28_usb_check_connectid_change(); - } - - rockchip_timer_clocksource_suspend_resume(0); -#endif - dump_register(); - clk_set_rate(arm_clk, arm_rate); - //rk2818_socpm_print(); - printk(KERN_DEBUG "quit arm halt,irq_val=0x%x\n", irq_val); - return 0; -} -#endif - -static struct platform_suspend_ops rk2818_pm_ops = { - .enter = rk2818_pm_enter, - .valid = suspend_valid_only_mem, -}; - -static int __init rk2818_pm_init(void) -{ - suspend_set_ops(&rk2818_pm_ops); - return 0; -} -__initcall(rk2818_pm_init); diff --git a/arch/arm/mach-rk2818/rk2818-socpm.c b/arch/arm/mach-rk2818/rk2818-socpm.c deleted file mode 100755 index fe4829269e01..000000000000 --- a/arch/arm/mach-rk2818/rk2818-socpm.c +++ /dev/null @@ -1,890 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if defined (CONFIG_RK2818_SOC_PM_DBG) - -static struct rk2818_pm_attr_dbg_st __tcmdata pm_scu_attr_dbg[PM_SCU_ATTR_DBG_NUM]; -static struct rk2818_pm_attr_dbg_st __tcmdata pm_general_attr_dbg[PM_GENERAL_ATTR_DBG_NUM]; -static struct rk2818_pm_attr_dbg_st __tcmdata pm_gpio0_attr_dbg[PM_GPIO0_ATTR_DBG_NUM]; -static struct rk2818_pm_attr_dbg_st __tcmdata pm_gpio1_attr_dbg[PM_GPIO1_ATTR_DBG_NUM]; -//static void rk2818_socpm_attr_int(void); -//static void setreg_form_socpm_attr(unsigned int *reg,int regoff,struct rk2818_pm_soc_st *soc); -#else - -#define setreg_form_socpm_attr(a,b,c) -#endif - - -#ifdef RK2818_PM_PRT_CHANGED_REG -static unsigned int __tcmdata pm_scu_reg_ch[PM_SCU_REG_NUM]; -static unsigned int __tcmdata pm_general_reg_ch[PM_GENERAL_CPU_REG]; -static unsigned int __tcmdata pm_gpio0_reg_ch[PM_SCU_GPIO_SWPORTC_NUM]; -static unsigned int __tcmdata pm_gpio1_reg_ch[PM_SCU_GPIO_SWPORTC_NUM]; -#endif -static unsigned int __tcmdata pm_scu_reg_save[PM_SCU_REG_NUM]; -static unsigned int __tcmdata pm_scu_temp_reg[PM_SCU_REG_NUM]; - -static struct rk2818_pm_soc_st __tcmdata pm_scu_ctr={ -.reg_save=&pm_scu_reg_save[0], -.reg_base_addr=(unsigned int *)RK2818_SCU_BASE, -.reg_ctrbit=0, -.reg_num=PM_SCU_REG_NUM, - -#ifdef RK2818_PM_PRT_CHANGED_REG -.reg_ch=&pm_scu_reg_ch[0], -#endif -#if defined (CONFIG_RK2818_SOC_PM_DBG) -.attr_num=PM_SCU_ATTR_DBG_NUM, -.attr_dbg=&pm_scu_attr_dbg[0], -.attr_flag=0, -#endif -}; - - -static unsigned int __tcmdata pm_general_reg_save[PM_GENERAL_CPU_REG]; - -static struct rk2818_pm_soc_st __tcmdata pm_general_ctr={ -.reg_save=&pm_general_reg_save[0], -.reg_base_addr=(unsigned int *)RK2818_REGFILE_BASE, -.reg_ctrbit=0, -.reg_num=PM_GENERAL_CPU_REG, - -#ifdef RK2818_PM_PRT_CHANGED_REG -.reg_ch=&pm_general_reg_ch[0], -#endif -#if defined (CONFIG_RK2818_SOC_PM_DBG) -.attr_num=PM_GENERAL_ATTR_DBG_NUM, -.attr_dbg=&pm_general_attr_dbg[0], -.attr_flag=0, -#endif -}; - - -static unsigned int __tcmdata pm_gpio0_reg_save[PM_SCU_GPIO_SWPORTC_NUM]; - -static struct rk2818_pm_soc_st __tcmdata pm_gpio0_ctr={ -.reg_save=&pm_gpio0_reg_save[0], -.reg_base_addr=(unsigned int *)RK2818_GPIO0_BASE, -.reg_ctrbit=0, -.reg_num=PM_SCU_GPIO_SWPORTC_NUM, - -#ifdef RK2818_PM_PRT_CHANGED_REG -.reg_ch=&pm_gpio0_reg_ch[0], -#endif -#if defined (CONFIG_RK2818_SOC_PM_DBG) -.attr_num=PM_GPIO0_ATTR_DBG_NUM, -.attr_dbg=&pm_gpio0_attr_dbg[0], -.attr_flag=0, -#endif -}; -static unsigned int __tcmdata pm_gpio1_reg_save[PM_SCU_GPIO_SWPORTC_NUM]; - -static struct rk2818_pm_soc_st __tcmdata pm_gpio1_ctr={ -.reg_save=&pm_gpio1_reg_save[0], -.reg_base_addr=(unsigned int *)RK2818_GPIO1_BASE, -.reg_ctrbit=0, -.reg_num=PM_SCU_GPIO_SWPORTC_NUM, - -#ifdef RK2818_PM_PRT_CHANGED_REG -.reg_ch=&pm_gpio1_reg_ch[0], -#endif -#if defined (CONFIG_RK2818_SOC_PM_DBG) -.attr_num=PM_GPIO1_ATTR_DBG_NUM, -.attr_dbg=&pm_gpio1_attr_dbg[0], -.attr_flag=0, -#endif -}; - -static unsigned int __tcmdata pm_savereg[PM_SAVE_REG_NUM]; -static unsigned int __tcmdata savereg_ch[PM_SAVE_REG_NUM]; - -struct rk2818_pm_st __tcmdata rk2818_soc_pm={ -.scu=(struct rk2818_pm_soc_st *)&pm_scu_ctr.reg_save, -.scu_tempreg=&pm_scu_temp_reg[0], -.general=(struct rk2818_pm_soc_st *)&pm_general_ctr.reg_save, -.gpio0=(struct rk2818_pm_soc_st *)&pm_gpio0_ctr.reg_save, -.gpio1=(struct rk2818_pm_soc_st *)&pm_gpio1_ctr.reg_save, -.save_reg=&pm_savereg[0], -.save_ch=&savereg_ch[0], -}; - -static struct rk2818_pm_callback_st __tcmdata *pm_ctr_callback=NULL; - -int __tcmfunc rk2818_socpm_set_gpio(unsigned int gpio,unsigned int output,unsigned int level) -{ - unsigned int *rk2818_gpio_reg; - struct rk2818_pm_soc_st *gpioctr; - unsigned int regoff; - - if(gpio>=RK2818GPIO_TOTAL) - return -1; - - if(gpio<32) - { - gpioctr=rk2818_soc_pm.gpio0; - } - else - { - gpioctr=rk2818_soc_pm.gpio1; - gpio-=32; - } - rk2818_gpio_reg=gpioctr->reg_base_addr; - switch(gpio/8) - { - case 0: - gpioctr->reg_ctrbit|=(0x1<reg_ctrbit|=(0x1<reg_ctrbit|=(0x1<reg_ctrbit|=(0x1<=RK2818GPIO_TOTAL) - return -1; - general_reg=rk2818_soc_pm.general->reg_base_addr; - regoff=PM_GPIO0_AB_PU_CON+gpio/16; - rk2818_soc_pm.general->reg_ctrbit|=((0x1<scu_suspend&&flag) - { - pm_ctr_callback->scu_suspend(tempdata,regoff); - } - rk2818_soc_pm.scu->reg_base_addr[regoff]=*tempdata; - rk2818_soc_pm.scu->reg_ctrbit|=(0x1<reg_base_addr; - rk2818_scu_reg[PM_SCU_MODE_CON]|=CPU_STOP_MODE; - rk2818_scu_reg[PM_SCU_CPUPD]=0xdeedbabe; - -} -#endif - -static void __tcmfunc rk2818_soc_scu_suspend(void) -{ - unsigned int *rk2818_scu_reg=rk2818_soc_pm.scu->reg_base_addr; - unsigned int *tempdata=&rk2818_soc_pm.scu_reg; - - - *tempdata= SCU_GATE0CLK_ALL_DIS&(~DIS_ARM_CLK)&(~DIS_TIMER_CLK) - &(~DIS_GPIO0_CLK)&(~DIS_GPIO1_CLK)&(~DIS_INTC_CLK)/*&(~DIS_UART0_CLK)&(~DIS_UART1_CLK)*/; - rk2818_soc_updata_scureg(tempdata,PM_SCU_CLKGATE0_CON,1); - tcm_udelay(1, 24); - - *tempdata=SCU_GATE1CLK_BASE_SET/*|EN_AXI_CLK&(~DIS_DDR_CLK)&(~DIS_DDR_HCLK)*/; - rk2818_soc_updata_scureg(tempdata,PM_SCU_CLKGATE1_CON,1); - tcm_udelay(1, 24); - - *tempdata=SCU_GATE2CLK_BASE_SET&(~DIS_ITCMBUS_CLK)&(~DIS_DTCM0BUS_CLK)&(~DIS_DTCM1BUS_CLK); - rk2818_soc_updata_scureg(tempdata,PM_SCU_CLKGATE2_CON,1); - tcm_udelay(1, 24); - - *tempdata=rk2818_scu_reg[PM_SCU_DPLL_CON] |DSPPLL_POERDOWN; //dsp pll power down - rk2818_soc_updata_scureg(tempdata,PM_SCU_DPLL_CON,1); - tcm_udelay(1, 24); - - *tempdata=rk2818_scu_reg[PM_SCU_CPLL_CON] |CPLL_POERDOWN; //dsp pll power down - rk2818_soc_updata_scureg(tempdata,PM_SCU_CPLL_CON,1); - tcm_udelay(1, 24); - - rk2818_scu_reg[PM_SCU_PMU_CON] |=LCDC_POWER_DOWN; - *tempdata=rk2818_scu_reg[PM_SCU_PMU_CON] |DSP_POWER_DOWN; - rk2818_soc_updata_scureg(tempdata,PM_SCU_PMU_CON,1); - - *tempdata=rk2818_scu_reg[PM_SCU_MODE_CON] &CPU_SLOW_MODE; //general slow mode - rk2818_soc_updata_scureg(tempdata,PM_SCU_MODE_CON,1); - - *tempdata=rk2818_scu_reg[PM_SCU_APLL_CON] |ARMPLL_BYPASSMODE;//enable arm pll bypass - *tempdata=rk2818_scu_reg[PM_SCU_APLL_CON] | ARMPLL_POERDOWN; //arm pll power down - rk2818_soc_updata_scureg(tempdata,PM_SCU_APLL_CON,1); - tcm_udelay(2, 24); - - *tempdata=(rk2818_scu_reg[PM_SCU_CLKSEL0_CON]&PM_BIT_CLEAR(CLKSEL0_HCLK,2)&PM_BIT_CLEAR(CLKSEL0_PCLK,2)) - |PM_BIT_SET(CLKSEL0_HCLK,CLK_ARM1_H1,2)|PM_BIT_SET(CLKSEL0_PCLK,CLK_HCLK1_P1,2); - rk2818_soc_updata_scureg(tempdata,PM_SCU_CLKSEL0_CON,1); - tcm_udelay(2, 24); - - *tempdata=(rk2818_scu_reg[PM_CLKSEL2_CON]&(~0xf))|0xF; - rk2818_soc_updata_scureg(tempdata,PM_CLKSEL2_CON,1); - - tcm_udelay(2, 24); - - //*tempdata=rk2818_scu_reg[PM_SCU_PMU_CON] |DDR_POWER_DOWN; - //rk2818_soc_updata_scureg(tempdata,PM_SCU_PMU_CON,0); - - //*tempdata=rk2818_scu_reg[PM_SCU_SOFTRST_CON]|(1<reg_ch; - unsigned int *rk2818_gpio0_reg=gpio0->reg_ch; - unsigned int *rk2818_gpio1_reg=gpio1->reg_ch; - - int i; - - #if 1 - general->reg_ctrbit|=(0x1<reg_ctrbit|=(0x1<reg_ctrbit|=(0x1<reg_ctrbit|=(0x1<reg_ctrbit|=(0x1<reg_ctrbit|=(0x1<reg_ch); - } - - rk2818_pm_save_reg(general->reg_base_addr,general->reg_ch,general->reg_num); - - rk2818_pm_save_reg(gpio0->reg_base_addr,gpio0->reg_ch,gpio0->reg_num); - rk2818_pm_save_reg(gpio1->reg_base_addr,gpio1->reg_ch,gpio1->reg_num); - -} -#endif -static void rk2818_pm_reg_print(unsigned int *pm_save_reg,unsigned int *pm_ch_reg,int num,char *name) -{ - - int i; - -#ifdef RK2818_PM_PRT_ORIGINAL_REG - printk("***the follow inf is %s original reg***\n",name); - for(i=0;i>i)&0x0001) - base_add[i]=pm_save_reg[i]; - } -} -void __tcmfunc rk2818_socpm_suspend(void) -{ - tcm_udelay(1, 24); //DRVDelayUs(100); - rk2818_soc_scu_suspend(); - tcm_udelay(1, 24); //DRVDelayUs(100); - - if(pm_ctr_callback&&pm_ctr_callback->general_reg_suspend) - { - pm_ctr_callback->general_reg_suspend(); - } -#ifdef RK2818_PM_PRT_CHANGED_REG - - rk2818_pm_save_reg(rk2818_soc_pm.scu->reg_ch,rk2818_soc_pm.scu->reg_base_addr, - rk2818_soc_pm.scu->reg_num); - - rk2818_pm_save_reg(rk2818_soc_pm.general->reg_ch,rk2818_soc_pm.general->reg_base_addr, - rk2818_soc_pm.general->reg_num); - - rk2818_pm_save_reg(rk2818_soc_pm.gpio0->reg_ch,rk2818_soc_pm.gpio0->reg_base_addr, - rk2818_soc_pm.gpio0->reg_num); - - rk2818_pm_save_reg(rk2818_soc_pm.gpio1->reg_ch,rk2818_soc_pm.gpio1->reg_base_addr, - rk2818_soc_pm.gpio1->reg_num); -#endif - //rk2818_soc_arm_stop(); - -} -void __tcmfunc rk2818_socpm_resume(void) -{ - tcm_udelay(1, 24); //DRVDelayUs(100); - rk2818_soc_resume(rk2818_soc_pm.scu->reg_save,rk2818_soc_pm.scu->reg_base_addr, - rk2818_soc_pm.scu->reg_ctrbit,rk2818_soc_pm.scu->reg_num); - tcm_udelay(2, 24); - if(pm_ctr_callback->general_reg_suspend) - { - - rk2818_soc_resume(rk2818_soc_pm.general->reg_save,rk2818_soc_pm.general->reg_base_addr, - rk2818_soc_pm.general->reg_ctrbit,rk2818_soc_pm.general->reg_num); - - rk2818_soc_resume(rk2818_soc_pm.gpio0->reg_save,rk2818_soc_pm.gpio0->reg_base_addr, - rk2818_soc_pm.gpio0->reg_ctrbit,rk2818_soc_pm.gpio0->reg_num); - - rk2818_soc_resume(rk2818_soc_pm.gpio1->reg_save,rk2818_soc_pm.gpio1->reg_base_addr, - rk2818_soc_pm.gpio1->reg_ctrbit,rk2818_soc_pm.gpio1->reg_num); - } - - } - -void __tcmfunc rk2818_socpm_suspend_first(void) -{ - tcm_udelay(1, 24); - rk2818_pm_save_reg(rk2818_soc_pm.scu->reg_save,rk2818_soc_pm.scu->reg_base_addr,rk2818_soc_pm.scu->reg_num); - //rk2818_pm_save_reg(rk2818_soc_pm.scu_tempreg,rk2818_soc_pm.scu->reg_base_addr,rk2818_soc_pm.scu->reg_num); - - rk2818_pm_save_reg(rk2818_soc_pm.general->reg_save,rk2818_soc_pm.general->reg_base_addr,rk2818_soc_pm.general->reg_num); - rk2818_pm_save_reg(rk2818_soc_pm.gpio0->reg_save,rk2818_soc_pm.gpio0->reg_base_addr,rk2818_soc_pm.gpio0->reg_num); - rk2818_pm_save_reg(rk2818_soc_pm.gpio1->reg_save,rk2818_soc_pm.gpio1->reg_base_addr,rk2818_soc_pm.gpio1->reg_num); - rk2818_soc_pm.scu->reg_ctrbit=0; - rk2818_soc_pm.general->reg_ctrbit=0; - rk2818_soc_pm.gpio0->reg_ctrbit=0x6db; - rk2818_soc_pm.gpio1->reg_ctrbit=0x6db; - - //rk2818_soc_pm.save_reg[0]=rk2818_ddr_reg[82]; - //rk2818_ddr_reg[82]=rk2818_ddr_reg[82]&(~(0xffff))&(~(0xf<<20)); - - if(pm_ctr_callback&&pm_ctr_callback->set_pin) - pm_ctr_callback->set_pin(); - - -} - -void __tcmfunc rk2818_socpm_resume_last(void) -{ - //unsigned int *rk2818_ddr_reg=(unsigned int *)RK2818_SDRAMC_BASE; - - if(pm_ctr_callback&&pm_ctr_callback->resume_pin) - pm_ctr_callback->resume_pin(); - -} - -void rk2818_socpm_print(void) -{ - rk2818_pm_reg_print(rk2818_soc_pm.scu->reg_save,rk2818_soc_pm.scu->reg_ch, - rk2818_soc_pm.scu->reg_num,"scu"); - rk2818_pm_reg_print(rk2818_soc_pm.general->reg_save,rk2818_soc_pm.general->reg_ch, - rk2818_soc_pm.general->reg_num,"general_general"); - rk2818_pm_reg_print(rk2818_soc_pm.gpio0->reg_save,rk2818_soc_pm.gpio0->reg_ch, - rk2818_soc_pm.gpio0->reg_num,"gpio0"); - rk2818_pm_reg_print(rk2818_soc_pm.gpio1->reg_save,rk2818_soc_pm.gpio1->reg_ch, - rk2818_soc_pm.gpio1->reg_num,"gpio1"); -} - - -int rk2818_socpm_init(struct rk2818_pm_callback_st *call_back) -{ - if(call_back==NULL) - return -1; - pm_ctr_callback = call_back; - return 0; - -} - - -#if defined (CONFIG_RK2818_SOC_PM_DBG) - -static bool check_attr_dbg_value(struct rk2818_pm_attr_dbg_st *attr) -{ - if((attr->flag!=PM_DBG_SET_ONCE)&&(attr->flag!=PM_DBG_SET_ALWAY)) - return false; - if(attr->bitsnum==0||attr->bitsnum>32) - return false; - - if(attr->regbits_off>31) - return false; - if((attr->regbits_off+attr->bitsnum)>32) - return false; - - return true; -} - - -#if 0 -static void setreg_form_socpm_attr(unsigned int *reg,int regoff,struct rk2818_pm_soc_st *soc) -{ - struct rk2818_pm_attr_dbg_st *attr=soc->attr_dbg; - int i; - for(i=0;iattr_num;i++) - { - - if(check_attr_dbg_value(attr)) - { - if(attr->regoff==regoff) - { - - *reg=(*reg)&PM_BIT_CLEAR(attr->regbits_off,attr->bitsnum)|PM_BIT_SET(attr->regbits_off,attr->value,attr->bitsnum); - - } - } - } - -} - -static void rk2818_socpm_attr_int(void) -{ - struct rk2818_pm_soc_st *scu=rk2818_soc_pm.scu; - struct rk2818_pm_soc_st *general=rk2818_soc_pm.general; - struct rk2818_pm_soc_st *gpio0=rk2818_soc_pm.gpio0; - struct rk2818_pm_soc_st *gpio1=rk2818_soc_pm.gpio1; - - - - memset(scu->attr_dbg,0,sizeof(struct rk2818_pm_attr_dbg_st)*scu->attr_num); - memset(general->attr_dbg,0,sizeof(struct rk2818_pm_attr_dbg_st)*general->attr_num); - memset(gpio0->attr_dbg,0,sizeof(struct rk2818_pm_attr_dbg_st)*gpio0->attr_num); - memset(gpio1->attr_dbg,0,sizeof(struct rk2818_pm_attr_dbg_st)*gpio1->attr_num); -} - -#endif -static u32 rk2818_socpm_attr_atoh(const unsigned char *in, unsigned int len) -{ - u32 sum = 0; - unsigned int mult = 1; - unsigned char c; - - while (len) { - c = in[len - 1]; - if ((c >= '0') && (c <= '9')) - sum += mult * (c - '0'); - else if ((c >= 'A') && (c <= 'F')) - sum += mult * (c - ('A' - 10)); - else if ((c >= 'a') && (c <= 'f')) - sum += mult * (c - ('a' - 10)); - mult *= 16; - --len; - } - return sum; -} - - -static bool rk2818_socpm_attr_is_number(char *p) -{ - if((*p>='0'&&*p<='9')||(*p>='a'&&*p<='f')||(*p>='A'&&*p<='F')) - return true; - else - return false; - -} - -#if 0 -static bool rk2818_socpm_attr_check_value(unsigned int *info) -{ - if((info[PM_DBG_USER_FLAG]!=PM_DBG_SET_ONCE)&&(info[PM_DBG_USER_FLAG]!=PM_DBG_SET_ALWAY)) - return false; - if(info[PM_DBG_USER_BITS_NUM]==0||info[PM_DBG_USER_BITS_NUM]>32) - return false; - if((info[PM_DBG_USER_BITS_NUM]+info[PM_DBG_USER_BITS_OFF])>31) - return false; - - return true; -} -#endif - -static bool rk2818_socpm_attr_reset_samesituation(struct rk2818_pm_attr_dbg_st *dbg,int num,unsigned int *info) -{ - - int i; - for (i=0;i=(buf+n)) - return true; - p++; - } - for(i=0;i=(buf+n)) - return true; - info[i]=rk2818_socpm_attr_atoh(p,e-p); - i++; - p=e; - if(i==(PM_DBG_USER_END-1)) - { - if(rk2818_socpm_attr_set_value(socpm->attr_dbg,socpm->attr_num,&info[0])==true) - return true; - - printk("value is%x, regoff is%x bitsoff is%x bitsnum is%x ctr is%x\n", - info[PM_DBG_USER_VALUE],info[PM_DBG_USER_REGOFF],info[PM_DBG_USER_BITS_OFF], - info[PM_DBG_USER_BITS_NUM], info[PM_DBG_USER_FLAG]); - - memset(&info[0],0,sizeof(int)*PM_DBG_USER_END); - } - } - else - { - if((*p==' ')) - { - while(*p==' ') - { - if(p>=(buf+n)) - return false; - p++; - } - continue; - } - else - { - break; - } - } - - } - } - - } - -return true; -} - - -#if 0 -static char * rk2818_socpm_attr_show_userinfo(struct rk2818_pm_soc_st *socpm,unsigned char regoff,char *buf) -{ - int i; - struct rk2818_pm_attr_dbg_st *attr_dbg; - for(i=0;iattr_num;i++) - { - if((attr_dbg[i].regoff==regoff)&&(attr_dbg[i].flag!=PM_ATTR_NO_CTR)&&attr_dbg[i].bitsnum) - buf += sprintf(buf, "value is%x, regoff is%x bitsoff is%x bitsnum is%x ctr is%x\n", - attr_dbg[i].value,attr_dbg[i].regoff,attr_dbg[i].regbits_off, attr_dbg[i].bitsnum, attr_dbg[i].flag); - } - - return buf; - - -} - -static ssize_t rk2818_socpm_attr_show_info(struct rk2818_pm_soc_st *socpm,char *name,char *buf) -{ - - char *s = buf; - int i; - s += sprintf(s, "this is the %s reg value,when system enter suspend lately\n",name); - for(i=0;ireg_num;i++) - { - s += sprintf(s, "reg[%d] is %x,user seting is in follow\n", i,socpm->reg_ch[i]); - s=rk2818_socpm_attr_show_userinfo(socpm,s,i); - - } - - if (s != buf) - /* convert the last space to a newline */ - *(s-1) = '\n'; - return (s - buf); - - -} - - -ssize_t rk2818_socpm_attr_show(int type,char *buf) -{ - struct rk2818_pm_soc_st *socpm; - char name[4][8]={"scu","general","gpio0","gpio1"}; - - switch(type) - { - case 0: - socpm=rk2818_soc_pm.scu; - break; - case 1: - socpm=rk2818_soc_pm.general; - break; - case 2: - socpm=rk2818_soc_pm.gpio0; - break; - case 3: - socpm=rk2818_soc_pm.gpio1; - break; - default: - return false; - - - - } - return rk2818_socpm_attr_show_info(socpm,name[type],buf); - -} -#endif - - - -bool rk2818_socpm_attr_store(int type,const char *buf, size_t n) -{ - struct rk2818_pm_soc_st *socpm; - - switch(type) - { - case 0: - socpm=rk2818_soc_pm.scu; - break; - case 1: - socpm=rk2818_soc_pm.general; - break; - case 2: - socpm=rk2818_soc_pm.gpio0; - break; - case 3: - socpm=rk2818_soc_pm.gpio1; - break; - default: - return false; - - - - } - return rk2818_socpm_attr_parse_settinginf(socpm,buf,n); - -} -#endif - -#if 0 -void rk2818_pm_updata_scu_reg(int regoff) -{ - if(0)//(rk2818_soc_pm.scu_suspend) - { - rk2818_soc_pm.scu_suspend(rk2818_soc_pm.scu_tempreg[regoff],regoff); - } - rk2818_soc_pm.scu->reg_base_addr[regoff]=rk2818_soc_pm.scu_tempreg[regoff]; - rk2818_soc_pm.scu->reg_ctrbit|=(0x1<reg_base_addr; - unsigned int *rk2818_scu_reg=rk2818_soc_pm.scu_tempreg; - - - - rk2818_scu_reg[PM_SCU_CLKGATE0_CON] = SCU_GATE0CLK_ALL_DIS&(~DIS_ARM_CLK)&(~DIS_TIMER_CLK) - &(~DIS_GPIO0_CLK)&(~DIS_GPIO1_CLK)&(~DIS_INTC_CLK)/*&(~DIS_UART0_CLK)&(~DIS_UART1_CLK)*/; - rk2818_pm_updata_scu_reg(PM_SCU_CLKGATE0_CON); - - rk2818_scu_reg[PM_SCU_CLKGATE1_CON] =SCU_GATE1CLK_BASE_SET/*|EN_AXI_CLK&(~DIS_DDR_CLK)&(~DIS_DDR_HCLK)*/; - rk2818_pm_updata_scu_reg(PM_SCU_CLKGATE1_CON); - - - rk2818_scu_reg[PM_SCU_CLKGATE2_CON] =SCU_GATE2CLK_BASE_SET&(~DIS_ITCMBUS_CLK)&(~DIS_DTCM0BUS_CLK)&(~DIS_DTCM1BUS_CLK); - rk2818_pm_updata_scu_reg(PM_SCU_CLKGATE2_CON); - - - - rk2818_scu_reg[PM_SCU_CLKSEL0_CON]&=PM_BIT_CLEAR(CLKSEL0_HCLK,2)&PM_BIT_CLEAR(CLKSEL0_PCLK,2) - |PM_BIT_SET(CLKSEL0_HCLK,CLK_ARM1_H1,2)|PM_BIT_SET(CLKSEL0_PCLK,CLK_HCLK1_P1,2); - rk2818_pm_updata_scu_reg(PM_SCU_CLKSEL0_CON); - - rk2818_scu_reg[PM_SCU_DPLL_CON] |= DSPPLL_POERDOWN; //dsp pll power down - rk2818_pm_updata_scu_reg(PM_SCU_DPLL_CON); - - rk2818_scu_reg[PM_SCU_CPLL_CON] |= CPLL_POERDOWN; //dsp pll power down - rk2818_pm_updata_scu_reg(PM_SCU_CPLL_CON); - - rk2818_scu_reg[PM_SCU_PMU_CON] |=LCDC_POWER_DOWN; - rk2818_scu_reg[PM_SCU_PMU_CON] |=DSP_POWER_DOWN; - - - rk2818_scu_reg[PM_SCU_MODE_CON] &= CPU_SLOW_MODE; //general slow mode - rk2818_pm_updata_scu_reg(PM_SCU_MODE_CON); - - rk2818_scu_reg[PM_SCU_APLL_CON] |= ARMPLL_BYPASSMODE;//enable arm pll bypass - rk2818_scu_reg[PM_SCU_APLL_CON] |= ARMPLL_POERDOWN; //arm pll power down - rk2818_pm_updata_scu_reg(PM_SCU_APLL_CON); - - rk2818_scu_reg[PM_CLKSEL2_CON] =(rk2818_scu_reg[PM_CLKSEL2_CON]&(~0xf))|0xF; - rk2818_pm_updata_scu_reg(PM_CLKSEL2_CON); - - - - - - rk2818_pm_updata_scu_reg(PM_SCU_PMU_CON); - //rk2818_scu_reg[PM_SCU_PMU_CON] |=DDR_POWER_DOWN; - //rk2818_pm_updata_scu_reg(PM_SCU_PMU_CON); - - //scu->reg_ctrbit|=(0x1< -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#define TIMER_LOAD_COUNT 0x0000 -#define TIMER_CUR_VALUE 0x0004 -#define TIMER_CONTROL_REG 0x0008 -#define TIMER_EOI 0x000C -#define TIMER_INT_STATUS 0x0010 - -#define TIMER_DISABLE 4 -#define TIMER_ENABLE 3 -#define TIMER_ENABLE_FREE_RUNNING 1 - -#define CHECK_VBUS_MS 1000 /* ms */ - -#define RK_TIMER_ENABLE(n) writel(TIMER_ENABLE, RK2818_TIMER_BASE + 0x14 * (n - 1) + TIMER_CONTROL_REG) -#define RK_TIMER_ENABLE_FREE_RUNNING(n) writel(TIMER_ENABLE_FREE_RUNNING, RK2818_TIMER_BASE + 0x14 * (n - 1) + TIMER_CONTROL_REG) -#define RK_TIMER_DISABLE(n) writel(TIMER_DISABLE, RK2818_TIMER_BASE + 0x14 * (n - 1) + TIMER_CONTROL_REG) - -#define RK_TIMER_SETCOUNT(n, count) writel(count, RK2818_TIMER_BASE + 0x14 * (n - 1) + TIMER_LOAD_COUNT) -#define RK_TIMER_GETCOUNT(n) readl(RK2818_TIMER_BASE + 0x14 * (n - 1) + TIMER_LOAD_COUNT) - -#define RK_TIMER_READVALUE(n) readl(RK2818_TIMER_BASE + 0x14 * (n - 1) + TIMER_CUR_VALUE) -#define RK_TIMER_INT_CLEAR(n) readl(RK2818_TIMER_BASE + 0x14 * (n - 1) + TIMER_EOI) - -#define TIMER_CLKEVT 2 /* timer2 */ -#define IRQ_NR_TIMER_CLKEVT IRQ_NR_TIMER2 -#define TIMER_CLKEVT_NAME "timer2" - -#define TIMER_CLKSRC 3 /* timer3 */ -#define IRQ_NR_TIMER_CLKSRC IRQ_NR_TIMER3 -#define TIMER_CLKSRC_NAME "timer3" - -static struct clk *timer_clk; -static volatile unsigned long timer_mult; /* timer count = cycle * timer_mult */ - -void rk2818_timer_update_mult(void) -{ - if (timer_clk) - timer_mult = clk_get_rate(timer_clk) / 1000000; -} - -static int rk2818_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) -{ - RK_TIMER_DISABLE(TIMER_CLKEVT); - RK_TIMER_SETCOUNT(TIMER_CLKEVT, cycles * timer_mult); - RK_TIMER_ENABLE(TIMER_CLKEVT); - - return 0; -} - -static void rk2818_timer_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) -{ - switch (mode) { - case CLOCK_EVT_MODE_RESUME: - case CLOCK_EVT_MODE_PERIODIC: - case CLOCK_EVT_MODE_ONESHOT: - break; - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - RK_TIMER_DISABLE(TIMER_CLKEVT); - break; - } -} - -static struct clock_event_device rk2818_timer_clockevent = { - .name = TIMER_CLKEVT_NAME, - .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, - .rating = 200, - .set_next_event = rk2818_timer_set_next_event, - .set_mode = rk2818_timer_set_mode, -}; - -static irqreturn_t rk2818_timer_clockevent_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = dev_id; - - RK_TIMER_INT_CLEAR(TIMER_CLKEVT); - RK_TIMER_DISABLE(TIMER_CLKEVT); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct irqaction rk2818_timer_clockevent_irq = { - .name = TIMER_CLKEVT_NAME, - .flags = IRQF_DISABLED | IRQF_TIMER, - .handler = rk2818_timer_clockevent_interrupt, - .irq = IRQ_NR_TIMER_CLKEVT, - .dev_id = &rk2818_timer_clockevent, -}; - -static int rk2818_timer_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data) -{ - if (val == CPUFREQ_POSTCHANGE) { - rk2818_timer_update_mult(); - } - - return 0; -} - -static struct notifier_block rk2818_timer_cpufreq_notifier_block = { - .notifier_call = rk2818_timer_cpufreq_notifier, - .priority = 0x7ffffff, -}; - -static __init int rk2818_timer_init_cpufreq(void) -{ - cpufreq_register_notifier(&rk2818_timer_cpufreq_notifier_block, CPUFREQ_TRANSITION_NOTIFIER); - return 0; -} - -arch_initcall_sync(rk2818_timer_init_cpufreq); - -static __init int rk2818_timer_init_clockevent(void) -{ - struct clock_event_device *ce = &rk2818_timer_clockevent; - - timer_clk = clk_get(NULL, "timer"); - rk2818_timer_update_mult(); - - RK_TIMER_DISABLE(TIMER_CLKEVT); - - setup_irq(rk2818_timer_clockevent_irq.irq, &rk2818_timer_clockevent_irq); - - ce->mult = div_sc(1000000, NSEC_PER_SEC, ce->shift); - ce->max_delta_ns = clockevent_delta2ns(0xFFFFFFFFUL / 256, ce); // max pclk < 256MHz - ce->min_delta_ns = clockevent_delta2ns(1, ce) + 1; - - ce->cpumask = cpumask_of(0); - - clockevents_register_device(ce); - - return 0; -} - -static cycle_t rk2818_timer_read(struct clocksource *cs) -{ - return ~RK_TIMER_READVALUE(TIMER_CLKSRC); -} - -static struct clocksource rk2818_timer_clocksource = { - .name = TIMER_CLKSRC_NAME, - .rating = 200, - .read = rk2818_timer_read, - .mask = CLOCKSOURCE_MASK(32), - .shift = 26, - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -#ifdef CONFIG_RK28_USB_WAKE -static irqreturn_t rk2818_timer_clocksource_interrupt(int irq, void *dev_id) -{ - RK_TIMER_INT_CLEAR(TIMER_CLKSRC); - return IRQ_HANDLED; -} - -static struct irqaction rk2818_timer_clocksource_irq = { - .name = TIMER_CLKSRC_NAME, - .handler = rk2818_timer_clocksource_interrupt, - .irq = IRQ_NR_TIMER_CLKSRC, -}; -#endif - -static void __init rk2818_timer_init_clocksource(void) -{ - static char err[] __initdata = KERN_ERR "%s: can't register clocksource!\n"; - struct clocksource *cs = &rk2818_timer_clocksource; - - RK_TIMER_DISABLE(TIMER_CLKSRC); - RK_TIMER_SETCOUNT(TIMER_CLKSRC, 0xFFFFFFFF); - RK_TIMER_ENABLE_FREE_RUNNING(TIMER_CLKSRC); - - cs->mult = clocksource_hz2mult(24000000, cs->shift); - if (clocksource_register(cs)) - printk(err, cs->name); - -#ifdef CONFIG_RK28_USB_WAKE - setup_irq(rk2818_timer_clocksource_irq.irq, &rk2818_timer_clocksource_irq); -#endif -} - -static void __init rk2818_timer_init(void) -{ - rk2818_timer_init_clocksource(); - rk2818_timer_init_clockevent(); -} - -struct sys_timer rk2818_timer = { - .init = rk2818_timer_init -}; - -#ifdef CONFIG_RK28_USB_WAKE -void rockchip_timer_clocksource_suspend_resume(int suspend) -{ - RK_TIMER_DISABLE(TIMER_CLKSRC); - if (suspend) { - RK_TIMER_SETCOUNT(TIMER_CLKSRC, 24000 * CHECK_VBUS_MS); - RK_TIMER_ENABLE(TIMER_CLKSRC); - } else { - RK_TIMER_SETCOUNT(TIMER_CLKSRC, 0xFFFFFFFF); - RK_TIMER_ENABLE_FREE_RUNNING(TIMER_CLKSRC); - } -} - -int rockchip_timer_clocksource_irq_checkandclear(void) -{ - u32 l, h; - - l = readl(RK2818_INTC_BASE + IRQ_REG_MASKSTATUS_L); - h = readl(RK2818_INTC_BASE + IRQ_REG_MASKSTATUS_H); - - /* clock source irq */ - if (l & (1 << IRQ_NR_TIMER_CLKSRC)) { - RK_TIMER_INT_CLEAR(TIMER_CLKSRC); - l &= ~(1 << IRQ_NR_TIMER_CLKSRC); - } - - /* 20091103,HSL@RK,all irq must be handle !*/ - l |= (h & 0xffff); - - return l; -} -#endif - diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 2caffbbf4108..26ec582519b1 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -1608,7 +1608,6 @@ kb9263 MACH_KB9263 KB9263 1612 mt7108 MACH_MT7108 MT7108 1613 smtr2440 MACH_SMTR2440 SMTR2440 1614 manao MACH_MANAO MANAO 1615 -rk2818 MACH_RK2818 RK2818 1616 gulfstream_kp MACH_GULFSTREAM_KP GULFSTREAM_KP 1617 lanreadyfn522 MACH_LANREADYFN522 LANREADYFN522 1618 arma37 MACH_ARMA37 ARMA37 1619 @@ -2536,4 +2535,4 @@ c3ax03 MACH_C3AX03 C3AX03 2549 mxt_td60 MACH_MXT_TD60 MXT_TD60 2550 esyx MACH_ESYX ESYX 2551 bulldog MACH_BULLDOG BULLDOG 2553 -rk29 MACH_RK29 RK29 2929 \ No newline at end of file +rk29 MACH_RK29 RK29 2929 diff --git a/drivers/Kconfig b/drivers/Kconfig index a499ce714db4..96753d32fe3f 100755 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -54,8 +54,6 @@ source "drivers/spi/Kconfig" source "drivers/adc/Kconfig" -source "drivers/fpga/Kconfig" - source "drivers/headset_observe/Kconfig" source "drivers/pps/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 8221447aef81..91a927688ae6 100755 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -46,7 +46,6 @@ obj-$(CONFIG_SCSI) += scsi/ obj-$(CONFIG_ATA) += ata/ obj-$(CONFIG_MTD) += mtd/ obj-$(CONFIG_SPI) += spi/ -obj-$(CONFIG_SPI_FPGA) += fpga/ obj-y += headset_observe/ obj-y += net/ obj-$(CONFIG_ATM) += atm/ diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig deleted file mode 100755 index e40d463f3efc..000000000000 --- a/drivers/fpga/Kconfig +++ /dev/null @@ -1,94 +0,0 @@ -# -# FPGA driver configuration -# -# NOTE: This FPGA(ice65l08xx) support spi2uart,spi2gpio,spi2i2c and spi2dpram. -# - -menuconfig SPI_FPGA - bool "SPI FPGA(ice65l08xx) support" - #depends on SPI && SPIM_RK2818 - help - This fpga(ice65l08xx) is used for spi2uart,spi2gpio,spi2i2c,spi2dpram. - -if SPI_FPGA - -config SPI_FPGA_INIT - tristate "spi fpga init support" - depends on SPI && SPIM_RK2818 - help - fpga driver for spi init. - -if SPI_FPGA_INIT - config SPI_FPGA_INIT_DEBUG - boolean "Debug support for spi fpga init drivers" - depends on DEBUG_KERNEL - help - Say "yes" to enable debug messaging in spi fpga init drivers. -endif - -if SPI_FPGA_INIT -config SPI_FPGA_UART - tristate "spi to uart support" - depends on SPI && SPIM_RK2818 - help - fpga driver for spi to uart. - -if SPI_FPGA_UART - config SPI_UART_DEBUG - boolean "Debug support for spi to uart drivers" - depends on DEBUG_KERNEL - help - Say "yes" to enable debug messaging in spi to uart drivers. -endif - -config SPI_FPGA_GPIO - tristate "spi to gpio support" - depends on SPI && SPIM_RK2818 - help - fpga driver for spi to gpio. - -if SPI_FPGA_GPIO - config SPI_GPIO_DEBUG - boolean "Debug support for spi to gpio drivers" - depends on DEBUG_KERNEL - help - Say "yes" to enable debug messaging in spi to gpio drivers. -endif - -config SPI_FPGA_I2C - tristate "spi to i2c support" - depends on SPI && SPIM_RK2818 - help - fpga driver for spi to i2c. - -if SPI_FPGA_I2C - config SPI_I2C_DEBUG - boolean "Debug support for spi to i2c drivers" - depends on DEBUG_KERNEL - help - Say "yes" to enable debug messaging in spi to i2c drivers. -endif - -config SPI_FPGA_DPRAM - tristate "spi to dpram support" - depends on SPI && SPIM_RK2818 - help - fpga driver for spi to dpram. - -if SPI_FPGA_DPRAM - config SPI_DPRAM_DEBUG - boolean "Debug support for spi to dpram drivers" - depends on DEBUG_KERNEL - help - Say "yes" to enable debug messaging in spi to dpram drivers. -endif - -config SPI_FPGA_FW - tristate "spi fpga firmware online" - depends on SPI && SPIM_RK2818 - help - load fpga firmware online. -endif - -endif - diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile deleted file mode 100755 index 187b0d467e6d..000000000000 --- a/drivers/fpga/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# Makefile for fpga(ice65l08xx) drivers. -# - -# fpga drivers -obj-$(CONFIG_SPI_FPGA_INIT) += spi_fpga_init.o -obj-$(CONFIG_SPI_FPGA_UART) += spi_uart.o -obj-$(CONFIG_SPI_FPGA_GPIO) += spi_gpio.o -obj-$(CONFIG_SPI_FPGA_I2C) += spi_i2c.o -obj-$(CONFIG_SPI_FPGA_DPRAM) += spi_dpram.o -obj-$(CONFIG_SPI_FPGA_FW) += spi_fpga_fw.o diff --git a/drivers/fpga/spi_dpram.c b/drivers/fpga/spi_dpram.c deleted file mode 100755 index 542f47c1ca9e..000000000000 --- a/drivers/fpga/spi_dpram.c +++ /dev/null @@ -1,844 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#if defined(CONFIG_SPI_DPRAM_DEBUG) -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -#define SPI_DPRAM_TEST 0 - -/*****RAM0 for bp write and ap read*****/ -#define SPI_DPRAM_BPWRITE_START 0 -#define SPI_DPRAM_BPWRITE_END 0x0fff -#define SPI_DPRAM_BPWRITE_SIZE 0x1000 // 4K*16bits -/*****RAM1 for ap write and bp read*****/ -#define SPI_DPRAM_APWRITE_START 0x1000 -#define SPI_DPRAM_APWRITE_END 0x17ff -#define SPI_DPRAM_APWRITE_SIZE 0x0800 // 2K*16bits -/*****RAM2 for log of bp write and ap read*****/ -#define SPI_DPRAM_LOG_BPWRITE_START 0x2000 -#define SPI_DPRAM_LOG_BPWRITE_END 0x23ff -#define SPI_DPRAM_LOG_BPWRITE_SIZE 0x0400 // 1K*16bits -/*****RAM3 for log of ap write and bp read*****/ -#define SPI_DPRAM_LOG_APWRITE_START 0x3000 -#define SPI_DPRAM_LOG_APWRITE_END 0x33ff -#define SPI_DPRAM_LOG_APWRITE_SIZE 0x0400 // 1K*16bits - - -#define SPI_DPRAM_PTR0_BPWRITE_APREAD 0X3fee -#define SPI_DPRAM_PTR0_APWRITE_BPREAD 0X3ff0 - -#define SPI_DPRAM_PTR1_BPWRITE_APREAD 0x3ff2 -#define SPI_DPRAM_PTR1_APWRITE_BPREAD 0x3ff4 - -#define SPI_DPRAM_PTR2_BPWRITE_APREAD 0x3ff6 -#define SPI_DPRAM_PTR2_APWRITE_BPREAD 0x3ff8 - -#define SPI_DPRAM_PTR3_BPWRITE_APREAD 0x3ffa -#define SPI_DPRAM_PTR3_APWRITE_BPREAD 0x3ffc - -#define SPI_DPRAM_MAILBOX_BPIRQ 0x3ffe -#define SPI_DPRAM_MAILBOX_APIRQ 0x3fff -#define SPI_DPRAM_MAILBOX_BPACK 0x3ffb -#define SPI_DPRAM_MAILBOX_APACK 0x3ffd - -/*mailbox comminication's definition*/ -#define MAILBOX_BPSEND_IRQ (0<<15) -#define MAILBOX_BPSEND_ACK (1<<15) -#define MAILBOX_APSEND_IRQ (0<<15) -#define MAILBOX_APSEND_ACK (1<<15) -#define MAILBOX_RAM0 (0<<13) -#define MAILBOX_RAM1 (1<<13) -#define MAILBOX_RAM2 (2<<13) -#define MAILBOX_RAM3 (3<<13) - -#define PIN_BPSEND_ACK RK2818_PIN_PE0 -#define PIN_APSEND_ACK RK2818_PIN_PF7 - -#define MAX_SPI_LEN 512 //the bytes of spi write or read one time - - -static int spi_dpram_write_buf(struct spi_dpram *dpram, unsigned short int addr, unsigned char *buf, unsigned int len) -{ - struct spi_fpga_port *port = container_of(dpram, struct spi_fpga_port, dpram); - unsigned char opt = ((ICE_SEL_DPRAM & ICE_SEL_DPRAM_NOMAL) | ICE_SEL_DPRAM_WRITE); - unsigned char tx_buf[MAX_SPI_LEN+3]; - int i,ret,mod,num,count; - -#if 0 - unsigned char *p = buf; - for(i=0;i>1)) << 1) >> 8) & 0xff; - tx_buf[2] = (((addr + i*(MAX_SPI_LEN>>1)) << 1) & 0xff); - ret = spi_write(port->spi, tx_buf, count+3); - if(ret) - { - DBG("%s:spi_write err! i=%d\n",__FUNCTION__,i); - return ret; - } - } - - return 0; -} - -static int spi_dpram_read_buf(struct spi_dpram *dpram, unsigned short int addr, unsigned char *buf, unsigned int len) -{ - struct spi_fpga_port *port = container_of(dpram, struct spi_fpga_port, dpram); - unsigned char opt = ((ICE_SEL_DPRAM & ICE_SEL_DPRAM_NOMAL & ICE_SEL_DPRAM_READ)); - unsigned char tx_buf[4]; - unsigned char stat; - int i,mod,num,count; - - mod = len%MAX_SPI_LEN; - if(!mod) - num = len/MAX_SPI_LEN; - else - num = len/MAX_SPI_LEN + 1; - - for(i=0;i>1)) << 1) >> 8) & 0xff; - tx_buf[2] = (((addr + i*(MAX_SPI_LEN>>1)) << 1) & 0xff); - tx_buf[3] = 0;//give fpga 8 clks for reading data - - stat = spi_write_then_read(port->spi, tx_buf, sizeof(tx_buf), buf + i*MAX_SPI_LEN, count); - if(stat) - { - DBG("%s:spi_write_then_read is error!,err=%d\n\n",__FUNCTION__,stat); - return -1; - } - - } - - return 0; - -} - - -int spi_dpram_write_word(struct spi_dpram *dpram, unsigned short int addr, unsigned int size) -{ - int ret; - //int i; - struct spi_fpga_port *port = container_of(dpram, struct spi_fpga_port, dpram); - unsigned char opt = ((ICE_SEL_DPRAM & ICE_SEL_DPRAM_NOMAL) | ICE_SEL_DPRAM_WRITE); - unsigned char tx_buf[5]; - - tx_buf[0] = opt; - tx_buf[1] = ((addr << 1) >> 8) & 0xff; - tx_buf[2] = ((addr << 1) & 0xff); - tx_buf[3] = (size>>8); - tx_buf[4] = (size&0xff); - - //for(i=0;i<5;i++) - //{ - // printk("%s:tx_buf[%d]=0x%x\n",__FUNCTION__,i,tx_buf[i]); - //} - - ret = spi_write(port->spi, tx_buf, sizeof(tx_buf)); - if(ret) - { - DBG("%s:spi_write err!\n",__FUNCTION__); - return -1; - } - - return 0; - -} - - -int spi_dpram_read_word(struct spi_dpram *dpram, unsigned short int addr) -{ - int ret; - struct spi_fpga_port *port = container_of(dpram, struct spi_fpga_port, dpram); - unsigned char opt = ((ICE_SEL_DPRAM & ICE_SEL_DPRAM_NOMAL & ICE_SEL_DPRAM_READ)); - unsigned char tx_buf[4],rx_buf[2]; - - tx_buf[0] = opt; - tx_buf[1] = ((addr << 1) >> 8) & 0xff; - tx_buf[2] = ((addr << 1) & 0xff); - tx_buf[3] = 0;//give fpga 8 clks for reading data - - ret = spi_write_then_read(port->spi, tx_buf, sizeof(tx_buf), rx_buf, sizeof(rx_buf)); - if(ret) - { - DBG("%s:spi_write_then_read err!\n",__FUNCTION__); - return -1; - } - - ret = (rx_buf[0] << 8) | rx_buf[1]; - - return (ret&0xffff); - -} - -int spi_dpram_write_ptr(struct spi_dpram *dpram, unsigned short int addr, unsigned int size) -{ - return spi_dpram_write_word(dpram, addr, size); -} - - -int spi_dpram_read_ptr(struct spi_dpram *dpram, unsigned short int addr) -{ - return spi_dpram_read_word(dpram, addr); -} - - -int spi_dpram_write_irq(struct spi_dpram *dpram, unsigned int mailbox) -{ - return spi_dpram_write_word(dpram, SPI_DPRAM_MAILBOX_APIRQ,mailbox); -} - - -int spi_dpram_read_irq(struct spi_dpram *dpram) -{ - return spi_dpram_read_word(dpram, SPI_DPRAM_MAILBOX_BPIRQ); -} - -int spi_dpram_write_ack(struct spi_dpram *dpram, unsigned int mailbox) -{ - return spi_dpram_write_word(dpram, SPI_DPRAM_MAILBOX_APACK,mailbox); -} - - -int spi_dpram_read_ack(struct spi_dpram *dpram) -{ - return spi_dpram_read_word(dpram, SPI_DPRAM_MAILBOX_BPACK); -} - -int gNumSendInt=0,gLastNumSendInt = 0; -int gNumSendAck=0,gLastNumSendAck = 0; -int gNumRecInt=0,gNumLastRecInt = 0; -int gNumCount = 0; -unsigned char buf_dpram[SPI_DPRAM_BPWRITE_SIZE<<1]; - -int gRecCount = 0; - -//really is spi_dpram_irq_work_handler after dpram's pin is exchanged -static void spi_dpram_irq_work_handler(struct work_struct *work) -{ - struct spi_fpga_port *port = - container_of(work, struct spi_fpga_port, dpram.spi_dpram_irq_work); - - unsigned short int mbox = port->dpram.read_irq(&port->dpram); - unsigned int ptr,len; - int i; - char temp,*p; - DBG("Enter::%s,mbox=%d\n",__FUNCTION__,mbox); - //gNumRecInt = mbox & 0x1fff; - //if(gNumRecInt - gNumLastRecInt !=1) - //if(++gNumLastRecInt > (1<<12)) - //gNumLastRecInt = 0; - //printk("gNumRecInt=%d,gLastNumInt=%d\n",gNumRecInt,gNumLastRecInt); - - if((mbox&MAILBOX_RAM3) == MAILBOX_RAM0) - { - //RAM0 - ptr = port->dpram.read_ptr(&port->dpram,SPI_DPRAM_PTR0_BPWRITE_APREAD); - if(ptr%2) - len = ptr+1; - else - len = ptr; - port->dpram.read_dpram(&port->dpram, SPI_DPRAM_BPWRITE_START, port->dpram.prx, len); - port->dpram.rec_len += ptr; - gRecCount = port->dpram.rec_len; - DBG("%s:ram0:ptr=%d,len=%d\n",__FUNCTION__,ptr,len); - //send ack - //if(++gNumSendAck > (1<<12)) - //gNumSendAck = 0; - //port->dpram.write_ack(&port->dpram, (MAILBOX_APSEND_ACK | MAILBOX_RAM0 | gNumSendAck)); - - p = port->dpram.prx; - for(i=0;i<(len>>1);i++) - { - temp = *(p+(i<<1)); - *(p+(i<<1))= *(p+(i<<1)+1); - *(p+(i<<1)+1) = temp; - } - - p = port->dpram.prx; - for(i=0;idpram.recq); - - mutex_lock(&port->dpram.rec_lock); - - //allow bp write ram0 again - port->dpram.write_ack(&port->dpram, (MAILBOX_APSEND_ACK | MAILBOX_RAM0)); - - //DBG("%s:r_irq=0x%x,s_ack=0x%x\n",__FUNCTION__,mbox, (MAILBOX_APSEND_ACK | MAILBOX_RAM0 | gNumSendAck)); - } - else if((mbox&MAILBOX_RAM3) == MAILBOX_RAM2) - { - //RAM2 - ptr = port->dpram.read_ptr(&port->dpram,SPI_DPRAM_PTR2_BPWRITE_APREAD); - if(ptr%2) - len = ptr+1; - else - len = ptr; - port->dpram.read_dpram(&port->dpram, SPI_DPRAM_LOG_BPWRITE_START, port->dpram.prx, len); - port->dpram.rec_len += ptr; - DBG("%s:ram2:ptr=%d,len=%d\n",__FUNCTION__,ptr,len); - //if(++gNumSendAck > (1<<12)) - //gNumSendAck = 0; - //port->dpram.write_ack(&port->dpram, (MAILBOX_APSEND_ACK | MAILBOX_RAM2 | gNumSendAck)); - - p = port->dpram.prx; - for(i=0;i<(len>>1);i++) - { - temp = *(p+(i<<1)); - *(p+(i<<1))= *(p+(i<<1)+1); - *(p+(i<<1)+1) = temp; - } - - //wake up ap to read data - wake_up_interruptible(&port->dpram.recq); - - mutex_lock(&port->dpram.rec_lock); - - //allow bp write ram0 again - port->dpram.write_ack(&port->dpram, (MAILBOX_APSEND_ACK | MAILBOX_RAM2)); - - //DBG("%s:r_irq=0x%x,s_ack=0x%x\n",__FUNCTION__, mbox, (MAILBOX_APSEND_ACK | MAILBOX_RAM2 | gNumSendAck)); - } - -} - -static irqreturn_t spi_dpram_irq(int irq, void *dev_id) -{ - struct spi_fpga_port *port = dev_id; - - DBG("Enter::%s,LINE=%d\n",__FUNCTION__,__LINE__); - /* - * Can't do anything in interrupt context because we need to - * block (spi_sync() is blocking) so fire of the interrupt - * handling workqueue. - * Remember that we access ICE65LXX registers through SPI bus - * via spi_sync() call. - */ - - queue_work(port->dpram.spi_dpram_irq_workqueue, &port->dpram.spi_dpram_irq_work); - - return IRQ_HANDLED; -} - - -#if SPI_DPRAM_TEST -#define SEL_RAM0 0 -#define SEL_RAM1 1 -#define SEL_RAM2 2 -#define SEL_RAM3 3 -#define SEL_REG 4 -#define SEL_RAM SEL_REG - -void spi_dpram_work_handler(struct work_struct *work) -{ - int i; - struct spi_fpga_port *port = - container_of(work, struct spi_fpga_port, dpram.spi_dpram_work); - DBG("*************test spi_dpram now***************\n"); - - for(i=0;i>8; - buf_dpram[2*i+1] = (0xa000+i)&0xff; - } - -#if(SEL_RAM == SEL_RAM0) - //RAM0 - port->dpram.read_dpram(&port->dpram, SPI_DPRAM_BPWRITE_START, port->dpram.prx, SPI_DPRAM_BPWRITE_SIZE<<1); - for(i=0;idpram.prx+2*i)<<8) | (*(port->dpram.prx+2*i+1)); - if(ret != 0xa000+i) - DBG("prx[%d]=0x%x ram[%d]=0x%x\n",i,ret&0xffff,i,0xa000+i); - } - -#elif(SEL_RAM == SEL_RAM1) - //RAM1 - port->dpram.write_dpram(&port->dpram, SPI_DPRAM_APWRITE_START, buf_dpram, SPI_DPRAM_APWRITE_SIZE<<1); - port->dpram.write_ptr(&port->dpram, SPI_DPRAM_PTR1_APWRITE_BPREAD, SPI_DPRAM_APWRITE_START); - port->dpram.write_irq(&port->dpram, MAILBOX_APSEND_IRQ); //send irq to bp after ap write data to dpram - -#elif(SEL_RAM == SEL_RAM2) - //RAM2 - port->dpram.read_dpram(&port->dpram, SPI_DPRAM_LOG_BPWRITE_START, port->dpram.prx, SPI_DPRAM_LOG_BPWRITE_SIZE<<1); - for(i=0;idpram.prx+2*i)<<8) | (*(port->dpram.prx+2*i+1)); - if(ret != 0xc000+i) - DBG("prx[%d]=0x%x ram[%d]=0x%x\n",i,ret&0xffff,i,0xc000+i); - } - -#elif(SEL_RAM == SEL_RAM3) - //RAM3 - port->dpram.write_dpram(&port->dpram, SPI_DPRAM_LOG_APWRITE_START, buf_dpram, SPI_DPRAM_LOG_APWRITE_SIZE<<1); - port->dpram.write_ptr(&port->dpram, SPI_DPRAM_PTR3_APWRITE_BPREAD, SPI_DPRAM_LOG_APWRITE_START); - port->dpram.write_irq(&port->dpram, MAILBOX_APSEND_IRQ); //send irq to bp after ap write data to dpram - -#elif(SEL_RAM == SEL_REG) -#if 1 - if(gNumCount++ == 0) - { - if(++gNumSendAck > (1<<12)) - gNumSendAck = 0; - port->dpram.write_ack(&port->dpram, MAILBOX_APSEND_ACK | MAILBOX_RAM0 | gNumSendAck); - printk("%s:line=%d,s_ack=0x%x\n",__FUNCTION__,__LINE__,MAILBOX_APSEND_ACK | MAILBOX_RAM0 | gNumSendAck); - - while(port->dpram.apwrite_en != TRUE); - port->dpram.apwrite_en = FALSE; - if(++gNumSendInt > (1<<12)) - gNumSendInt = 0; - port->dpram.write_dpram(&port->dpram, SPI_DPRAM_APWRITE_START, buf_dpram, SPI_DPRAM_APWRITE_SIZE<<1); - port->dpram.write_ptr(&port->dpram, SPI_DPRAM_PTR1_APWRITE_BPREAD, SPI_DPRAM_APWRITE_SIZE<<1); - port->dpram.write_irq(&port->dpram, MAILBOX_APSEND_IRQ | MAILBOX_RAM1 | gNumSendInt); - printk("%s:line=%d,s_irq=0x%x\n",__FUNCTION__,__LINE__,MAILBOX_APSEND_IRQ | MAILBOX_RAM1 | gNumSendInt); - - if(gNumCount > (1<<15)) - gNumCount = 2; - } -#endif - -#if 0 - while(port->dpram.apwrite_en != TRUE); - port->dpram.apwrite_en == FALSE; - if(++gNumSendInt > (1<<12)) - gNumSendInt = 0; - port->dpram.write_dpram(&port->dpram, SPI_DPRAM_LOG_APWRITE_START, buf_dpram, SPI_DPRAM_LOG_APWRITE_SIZE<<1); - port->dpram.write_ptr(&port->dpram, SPI_DPRAM_PTR3_APWRITE_BPREAD, SPI_DPRAM_LOG_APWRITE_SIZE<<1); - port->dpram.write_irq(&port->dpram, MAILBOX_APSEND_IRQ | MAILBOX_RAM3 | gNumSendInt); -#endif -#endif - -} - -static void spi_testdpram_timer(unsigned long data) -{ - struct spi_fpga_port *port = (struct spi_fpga_port *)data; - port->dpram.dpram_timer.expires = jiffies + msecs_to_jiffies(500); - add_timer(&port->dpram.dpram_timer); - //schedule_work(&port->gpio.spi_gpio_work); - queue_work(port->dpram.spi_dpram_workqueue, &port->dpram.spi_dpram_work); -} - -#endif - -//really is spi_dpram_handle_ack after dpram's pin is exchanged -int spi_dpram_handle_ack(struct spi_device *spi) -{ - struct spi_fpga_port *port = spi_get_drvdata(spi); - printk("Enter::%s,LINE=%d\n",__FUNCTION__,__LINE__); - //clear ack interrupt - port->dpram.read_ack(&port->dpram); - - //allow ap to write and wake ap to write data - port->dpram.apwrite_en = TRUE; - wake_up_interruptible(&port->dpram.sendq); -#if 0 - //while(port->dpram.apwrite_en != TRUE); - port->dpram.apwrite_en = FALSE; - if(++gNumSendInt > (1<<12)) - gNumSendInt = 0; - port->dpram.write_dpram(&port->dpram, SPI_DPRAM_APWRITE_START, buf_dpram, SPI_DPRAM_APWRITE_SIZE<<1); - port->dpram.write_ptr(&port->dpram, SPI_DPRAM_PTR1_APWRITE_BPREAD, SPI_DPRAM_APWRITE_SIZE<<1); - port->dpram.write_irq(&port->dpram, MAILBOX_APSEND_IRQ | MAILBOX_RAM1 | gNumSendInt); - printk("%s:r_ack=0x%x,s_irq=0x%x\n",__FUNCTION__,ack, MAILBOX_APSEND_IRQ | MAILBOX_RAM1 | gNumSendInt); -#endif - return 0; -} - -static int dpr_open(struct inode *inode, struct file *filp) -{ - struct spi_fpga_port *port = pFpgaPort; - - DBG("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port); - filp->private_data = port; - port->dpram.rec_len = 0; - port->dpram.send_len = 0; - port->dpram.apwrite_en = TRUE; - - return nonseekable_open(inode, filp); -} - - -static int dpr_close(struct inode *inode, struct file *filp) -{ - //struct spi_fpga_port *port = pFpgaPort; - DBG("%s:line=%d\n",__FUNCTION__,__LINE__); - filp->private_data = NULL; - return 0; -} - -static ssize_t dpr_read (struct file *filp, char __user *buffer, size_t count, loff_t *ppos) -{ - int ret; - struct spi_fpga_port *port = filp->private_data; - - ret = down_interruptible(&port->dpram.rec_sem); - //DBG("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port); - DBG("%s, port=0x%x , count=%d, port->dpram.rec_len=%d \n",__FUNCTION__, (int)port, count, port->dpram.rec_len); - - //printk("%s:CURRENT_TASK=0x%x\n",__FUNCTION__,current); - while(port->dpram.rec_len == 0) - { - if( filp->f_flags&O_NONBLOCK ) - return -EAGAIN; - - if(wait_event_interruptible(port->dpram.recq, (port->dpram.rec_len != 0))) - { - DBG("%s:NO data in dpram!\n",__FUNCTION__); - return -ERESTARTSYS; - } - - //gRecCount = port->dpram.rec_len; - } - - /*read data from buffer*/ - if(copy_to_user((char*)buffer, (char *)(port->dpram.prx + gRecCount - port->dpram.rec_len), count)) - { - DBG("%s:copy_to_user err!\n",__FUNCTION__); - return -EFAULT; - } - - #if 1 - int i,len; - char *p = buffer; - len = port->dpram.rec_len; - //for(i=0;idpram.prx + gRecCount - port->dpram.rec_len))); - }else{ - printk("count = %d, $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$\n", count); - } - #endif - - port->dpram.rec_len -= count; - if(port->dpram.rec_len == 0) - mutex_unlock(&port->dpram.rec_lock); - - up(&port->dpram.rec_sem); - - return count; -} - - -static ssize_t dpr_write (struct file *filp, const char __user *buffer, size_t count, loff_t *ppos) -{ - struct spi_fpga_port *port = filp->private_data; - int mod,num; - char i,*p,temp; - printk("%s:line=%d,port=0x%x, count=%d \n",__FUNCTION__,__LINE__,(int)port, count); - - while(port->dpram.apwrite_en == FALSE) - { - - //if(filp->f_flags & O_NONBLOCK) - // return -EAGAIN; - if(wait_event_interruptible(port->dpram.sendq, (port->dpram.apwrite_en == TRUE))){ - printk("port->dpram.apwrite_en == FALSE"); - return -ERESTARTSYS; - } - printk("%s, wake up \n", __FUNCTION__); - } - - if(count > port->dpram.max_send_len) - { - count = port->dpram.max_send_len; - printk("%s:count is large than max_send_len(%d),and only %d's bytes is valid!\n",__FUNCTION__,count,count); - } - - if(copy_from_user((char *)port->dpram.ptx,buffer,count)) - { - printk("%s:copy_from_user err!\n",__FUNCTION__); - return -EFAULT; - } - mod = count % 2; - num = count; - if(mod) - { - *((char *)port->dpram.ptx + count) = 0; - num = count + 1; - } - - p=port->dpram.ptx; - - /*swap data to suitable bp:p[0]<->p[1]*/ - for(i=0;i<(num>>1);i++) - { - temp = *(p+(i<<1)); - *(p+(i<<1))= *(p+(i<<1)+1); - *(p+(i<<1)+1) = temp; - } - -#if 1 - p=port->dpram.ptx; - for(i=0;idpram.write_dpram(&port->dpram, SPI_DPRAM_APWRITE_START, port->dpram.ptx, num); - port->dpram.apwrite_en = FALSE; //clear apwrite_en after wirte data to dpram - port->dpram.write_ptr(&port->dpram, SPI_DPRAM_PTR1_APWRITE_BPREAD, count); - if(++gNumSendInt > (1<<12)) - gNumSendInt = 0; - - if(gpio_get_value(PIN_BPSEND_ACK)==0){ - printk("BP_READY is LOW, wake up BP \n"); - gpio_direction_output(PIN_APSEND_ACK,GPIO_LOW); - msleep(50); - gpio_direction_output(PIN_APSEND_ACK,GPIO_HIGH); - msleep(50); - } - - while(gpio_get_value(PIN_BPSEND_ACK)==0){ - printk("BP_READY is LOW, wait 100ms !!!!!!!!!!!!\n"); - msleep(100); - } - - //send irq to bp after ap write data to dpram - port->dpram.write_irq(&port->dpram, MAILBOX_APSEND_IRQ | MAILBOX_RAM1 | gNumSendInt); - - return count; - -} - - -unsigned int dpr_poll(struct file *filp, struct poll_table_struct * wait) -{ - unsigned int mask = 0; - struct spi_fpga_port *port; - port = filp->private_data; - DBG("%s:line=%d\n",__FUNCTION__,__LINE__); - -#if 1 - poll_wait(filp, &port->dpram.recq, wait); - poll_wait(filp, &port->dpram.sendq, wait); - - if(port->dpram.rec_len >0) - { - mask |= POLLIN|POLLRDNORM; - DBG("%s:exsram_poll_____1\n",__FUNCTION__); - } - - if(port->dpram.apwrite_en == TRUE) - { - mask |= POLLOUT|POLLWRNORM; - DBG("%s:exsram_poll_____2\n",__FUNCTION__); - } -#endif - - return mask; -} - - -static struct file_operations dpr_fops={ - .owner= THIS_MODULE, - .open= dpr_open, - .release= dpr_close, - .read= dpr_read, - .write= dpr_write, - .poll = dpr_poll, -}; - -int spi_dpram_register(struct spi_fpga_port *port) -{ - char b[28]; - int ret; - DBG("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port); - port->dpram.prx = (char *)kzalloc(sizeof(char)*((SPI_DPRAM_BPWRITE_SIZE<<1)+6), GFP_KERNEL); - if(port->dpram.prx == NULL) - { - DBG("port->dpram.prx kzalloc err!!!\n"); - return -ENOMEM; - } - - port->dpram.ptx = (char *)kzalloc(sizeof(char)*((SPI_DPRAM_APWRITE_SIZE<<1)+6), GFP_KERNEL); - if(port->dpram.ptx == NULL) - { - DBG("port->dpram.ptx kzalloc err!!!\n"); - return -ENOMEM; - } - DBG("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port); - sprintf(b, "spi_dpram_irq_workqueue"); - port->dpram.spi_dpram_irq_workqueue = create_freezeable_workqueue(b); - if (!port->dpram.spi_dpram_irq_workqueue) { - DBG("cannot create workqueue\n"); - return -EBUSY; - } - INIT_WORK(&port->dpram.spi_dpram_irq_work, spi_dpram_irq_work_handler); - -#if SPI_DPRAM_TEST - sprintf(b, "spi_dpram_workqueue"); - port->dpram.spi_dpram_workqueue = create_freezeable_workqueue(b); - if (!port->dpram.spi_dpram_workqueue) { - DBG("cannot create workqueue\n"); - return -EBUSY; - } - INIT_WORK(&port->dpram.spi_dpram_work, spi_dpram_work_handler); - - setup_timer(&port->dpram.dpram_timer, spi_testdpram_timer, (unsigned long)port); - port->dpram.dpram_timer.expires = jiffies+2000;//>1000ms - add_timer(&port->dpram.dpram_timer); -#endif - - DBG("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port); - - //init the struct spi_dpram - init_waitqueue_head(&port->dpram.recq); - init_waitqueue_head(&port->dpram.sendq); - mutex_init(&port->dpram.rec_lock); - mutex_init(&port->dpram.send_lock); - init_MUTEX(&port->dpram.rec_sem); - init_MUTEX(&port->dpram.send_sem); - spin_lock_init(&port->dpram.spin_rec_lock); - spin_lock_init(&port->dpram.spin_send_lock); - port->dpram.rec_len = 0; - port->dpram.send_len = 0; - port->dpram.apwrite_en = TRUE; - port->dpram.max_rec_len = SPI_DPRAM_BPWRITE_SIZE; - port->dpram.max_send_len = SPI_DPRAM_APWRITE_SIZE; - port->dpram.miscdev.minor = MISC_DYNAMIC_MINOR; - port->dpram.miscdev.name = "spi_dpram";//spi_fpga - port->dpram.miscdev.fops = &dpr_fops; - - ret = misc_register(&port->dpram.miscdev); - if(ret) - { - DBG("%s:misc_register err!!!\n",__FUNCTION__); - goto err0; - } - - port->dpram.write_dpram = spi_dpram_write_buf; - port->dpram.read_dpram = spi_dpram_read_buf; - port->dpram.write_ptr = spi_dpram_write_ptr; - port->dpram.read_ptr = spi_dpram_read_ptr; - port->dpram.write_irq = spi_dpram_write_irq; - port->dpram.read_irq = spi_dpram_read_irq; - port->dpram.write_ack = spi_dpram_write_ack; - port->dpram.read_ack = spi_dpram_read_ack; - - DBG("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port); - - ret = gpio_request(SPI_DPRAM_INT_PIN, NULL); - if (ret) { - DBG("%s:failed to request dpram irq gpio\n",__FUNCTION__); - goto err1; - } - - rk2818_mux_api_set(GPIOA23_UART2_SEL_NAME,0); - gpio_pull_updown(SPI_DPRAM_INT_PIN,GPIOPullUp); - ret = request_irq(gpio_to_irq(SPI_DPRAM_INT_PIN),spi_dpram_irq,IRQF_TRIGGER_FALLING,NULL,port); - if(ret) - { - DBG("%s:unable to request dpram irq_gpio irq\n",__FUNCTION__); - goto err2; - } - DBG("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port); - - - /*disable speaker */ - gpio_request(RK2818_PIN_PF7, "DPRAM"); - rk2818_mux_api_set(GPIOE_SPI1_FLASH_SEL_NAME, IOMUXA_GPIO1_A3B7); - gpio_direction_output(RK2818_PIN_PF7,GPIO_LOW); - msleep(100); - gpio_direction_output(RK2818_PIN_PF7,GPIO_HIGH); - msleep(100); - - return 0; - -err2: - free_irq(gpio_to_irq(SPI_DPRAM_INT_PIN),NULL); -err1: - gpio_free(SPI_DPRAM_INT_PIN); -err0: - kfree(port->dpram.prx); - kfree(port->dpram.ptx); - - return ret; - -} - -int spi_dpram_unregister(struct spi_fpga_port *port) -{ - - return 0; -} - - diff --git a/drivers/fpga/spi_fpga_fw.c b/drivers/fpga/spi_fpga_fw.c deleted file mode 100755 index 0e571e52444c..000000000000 --- a/drivers/fpga/spi_fpga_fw.c +++ /dev/null @@ -1,252 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "spi_fpga_fw.h" - -#define FPGA_GPIO_TYPE 0 - -#define FPGA_PIN_CRESET_B RK2818_PIN_PC4 -#define SPI_PIN_TX RK2818_PIN_PB6 -#define SPI_PIN_CLK RK2818_PIN_PB5 -#define SPI_PIN_CS RK2818_PIN_PB0 - -#if (FPGA_GPIO_TYPE == 0) -#define FPGA_CRESER_OUTPUT() __raw_writel(__raw_readl(RK2818_GPIO0_BASE+GPIO_SWPORTC_DDR)|(0x1<<4), (RK2818_GPIO0_BASE+GPIO_SWPORTC_DDR)) -#define FPGA_CRESET_HIGH() __raw_writel(__raw_readl(RK2818_GPIO0_BASE+GPIO_SWPORTC_DR)|(0x1<<4), (RK2818_GPIO0_BASE+GPIO_SWPORTC_DR)) -#define FPGA_CRESET_LOW() __raw_writel(__raw_readl(RK2818_GPIO0_BASE+GPIO_SWPORTC_DR)&(~(0x1<<4)), (RK2818_GPIO0_BASE+GPIO_SWPORTC_DR)) - -#define FPGA_TX_OUTPUT() __raw_writel(__raw_readl(RK2818_GPIO0_BASE+GPIO_SWPORTB_DDR)|(0x1<<6), (RK2818_GPIO0_BASE+GPIO_SWPORTB_DDR)) -#define FPGA_TX_HIGH() __raw_writel(__raw_readl(RK2818_GPIO0_BASE+GPIO_SWPORTB_DR)|(0x1<<6), (RK2818_GPIO0_BASE+GPIO_SWPORTB_DR)) -#define FPGA_TX_LOW() __raw_writel(__raw_readl(RK2818_GPIO0_BASE+GPIO_SWPORTB_DR)&(~(0x1<<6)), (RK2818_GPIO0_BASE+GPIO_SWPORTB_DR)) - -#define FPGA_CLK_OUTPUT() __raw_writel(__raw_readl(RK2818_GPIO0_BASE+GPIO_SWPORTB_DDR)|(0x1<<5), (RK2818_GPIO0_BASE+GPIO_SWPORTB_DDR)) -#define FPGA_CLK_HIGH() __raw_writel(__raw_readl(RK2818_GPIO0_BASE+GPIO_SWPORTB_DR)|(0x1<<5), (RK2818_GPIO0_BASE+GPIO_SWPORTB_DR)) -#define FPGA_CLK_LOW() __raw_writel(__raw_readl(RK2818_GPIO0_BASE+GPIO_SWPORTB_DR)&(~(0x1<<5)), (RK2818_GPIO0_BASE+GPIO_SWPORTB_DR)) - -#define FPGA_CS_OUTPUT() __raw_writel(__raw_readl(RK2818_GPIO0_BASE+GPIO_SWPORTB_DDR)|(0x1<<0), (RK2818_GPIO0_BASE+GPIO_SWPORTB_DDR)) -#define FPGA_CS_HIGH() __raw_writel(__raw_readl(RK2818_GPIO0_BASE+GPIO_SWPORTB_DR)|(0x1<<0), (RK2818_GPIO0_BASE+GPIO_SWPORTB_DR)) -#define FPGA_CS_LOW() __raw_writel(__raw_readl(RK2818_GPIO0_BASE+GPIO_SWPORTB_DR)&(~(0x1<<0)), (RK2818_GPIO0_BASE+GPIO_SWPORTB_DR)) -#else -#define FPGA_CRESER_OUTPUT() gpio_direction_output(FPGA_PIN_CRESET_B,GPIO_HIGH) -#define FPGA_CRESET_HIGH() gpio_set_value(FPGA_PIN_CRESET_B,GPIO_HIGH) -#define FPGA_CRESET_LOW() gpio_set_value(FPGA_PIN_CRESET_B,GPIO_LOW) - -#define FPGA_TX_OUTPUT() gpio_direction_output(SPI_PIN_TX,GPIO_HIGH) -#define FPGA_TX_HIGH() gpio_set_value(SPI_PIN_TX,GPIO_HIGH) -#define FPGA_TX_LOW() gpio_set_value(SPI_PIN_TX,GPIO_LOW) - -#define FPGA_CLK_OUTPUT() gpio_direction_output(SPI_PIN_CLK,GPIO_HIGH) -#define FPGA_CLK_HIGH() gpio_set_value(SPI_PIN_CLK,GPIO_HIGH) -#define FPGA_CLK_LOW() gpio_set_value(SPI_PIN_CLK,GPIO_LOW) - -#define FPGA_CS_OUTPUT() gpio_direction_output(SPI_PIN_CS,GPIO_HIGH) -#define FPGA_CS_HIGH() gpio_set_value(SPI_PIN_CS,GPIO_HIGH) -#define FPGA_CS_LOW() gpio_set_value(SPI_PIN_CS,GPIO_LOW) -#endif - -static void __init spi_fpga_send_bytes(unsigned char * bytes, unsigned int len) -{ - unsigned int i,j; - unsigned char spibit; - unsigned char * fw = bytes; - - i=0; - while (i < len) - { - j=0; - spibit = *fw++; - while (j < 8) - { - FPGA_CLK_LOW(); - if(spibit & 0x80) - { - FPGA_TX_HIGH(); - } - else - { - FPGA_TX_LOW(); - } - FPGA_CLK_HIGH(); - spibit = spibit<<1; - j++; - } - i++; - } -} - -static void __init spi_fpga_wait(unsigned int num) -{ - unsigned int i = 0; - - while(i<(num<<1)) - { - FPGA_CLK_LOW(); - i++; - FPGA_CLK_HIGH(); - i++; - } -} - -static DEFINE_SPINLOCK(lock_fw); -static void __init spi_fpga_dlfw(unsigned char * fpga_fw, unsigned int fpga_fw_len) -{ - //int ret; - unsigned long flags; - unsigned char command1[6] = {0x7e, 0xaa, 0x99, 0x7e, 0x01, 0x0e}; - unsigned char command2[5] = {0x83, 0x00, 0x00, 0x26, 0x11}; - unsigned char command3[5] = {0x83, 0x00, 0x00, 0x27, 0x21}; - unsigned char command4[1] = {0x81}; - - //local_irq_save(flags); - spin_lock_irqsave(&lock_fw, flags); - rk2818_mux_api_set(GPIOC_LCDC24BIT_SEL_NAME, IOMUXB_GPIO0_C2_7); - //ret = gpio_request(FPGA_PIN_CRESET_B, NULL); - //if (ret) { - // printk("%s:failed to request fpga download pin\n",__FUNCTION__); - //} - - rk2818_mux_api_set(GPIOB_SPI0_MMC0_NAME,IOMUXA_GPIO0_B567); - //ret = gpio_request(SPI_PIN_CLK, NULL); - //if (ret) { - // printk("%s:failed to request fpga clk pin\n",__FUNCTION__); - //} - - //ret = gpio_request(SPI_PIN_TX, NULL); - //if (ret) { - // printk("%s:failed to request fpga tx pin\n",__FUNCTION__); - //} - - rk2818_mux_api_set(GPIOB0_SPI0CSN1_MMC1PCA_NAME, IOMUXA_GPIO0_B0); - //ret = gpio_request(SPI_PIN_CS, NULL); - //if (ret) { - // printk("%s:failed to request fpga cs pin\n",__FUNCTION__); - //} - - FPGA_CS_LOW(); - FPGA_CS_OUTPUT(); - FPGA_CRESET_LOW(); - FPGA_CRESER_OUTPUT(); - FPGA_TX_LOW(); - FPGA_TX_OUTPUT(); - FPGA_CLK_LOW(); - FPGA_CLK_OUTPUT(); - - //step 1 - FPGA_CS_LOW(); - FPGA_CRESET_LOW(); - udelay(10);//delay >= 200ns - - //step 2 - FPGA_CRESET_HIGH(); - mdelay(2); //delay >= 300us for clear internal memory - - //step 3 - //spi_fpga_wait(8); //need ??? - - //step 4 - FPGA_CS_HIGH(); - spi_fpga_wait(8); - - //step 5 - FPGA_CS_LOW(); - spi_fpga_send_bytes(command1, 6); - - - //step 6 - FPGA_CS_HIGH(); - spi_fpga_wait(13000); - - //step 7 - FPGA_CS_LOW(); - spi_fpga_send_bytes(command2, 5); - - - //step 8 - FPGA_CS_HIGH(); - spi_fpga_wait(8); - - //step 9 - FPGA_CS_LOW(); - spi_fpga_send_bytes(command3, 5); - - - //step 10 - FPGA_CS_HIGH(); - spi_fpga_wait(8); - - //step 11 - FPGA_CS_LOW(); - spi_fpga_send_bytes(command4, 1); - - - //step 12 - FPGA_CS_HIGH(); - spi_fpga_wait(8); - - //step 13 - FPGA_CS_HIGH(); - spi_fpga_send_bytes(fpga_fw, fpga_fw_len); - - //step 14 - spi_fpga_wait(100); - - //step 15 - //local_irq_restore(flags); - spin_unlock_irqrestore(&lock_fw, flags); - - //free gpio and set to spi - //gpio_free(FPGA_PIN_CRESET_B); - //gpio_free(SPI_PIN_TX); - //gpio_free(SPI_PIN_CLK); - //gpio_free(SPI_PIN_CS); - rk2818_mux_api_mode_resume(GPIOB_SPI0_MMC0_NAME); - rk2818_mux_api_mode_resume(GPIOB0_SPI0CSN1_MMC1PCA_NAME); - rk2818_mux_api_mode_resume(GPIOC_LCDC24BIT_SEL_NAME); -} - -int __init fpga_dl_fw(void) -{ - printk("%s:start to load FPGA HEX.........\n",__FUNCTION__); - - //rk2818_mux_api_set(GPIOE0_VIPDATA0_SEL_NAME,0); - //gpio_request(RK2818_PIN_PE0, NULL); - //gpio_direction_output(RK2818_PIN_PE0,1); - //udelay(2); - //gpio_direction_output(RK2818_PIN_PE0,0); - - spi_fpga_dlfw(spibyte, CONFIGURATION_SIZE); - - //gpio_direction_output(RK2818_PIN_PE0,1); - //udelay(2); - //gpio_direction_output(RK2818_PIN_PE0,0); - - return 0; -} - diff --git a/drivers/fpga/spi_fpga_fw.h b/drivers/fpga/spi_fpga_fw.h deleted file mode 100755 index f483f09f8868..000000000000 --- a/drivers/fpga/spi_fpga_fw.h +++ /dev/null @@ -1,16898 +0,0 @@ -#define CONFIGURATION_SIZE 135096 -#if 1 -unsigned char spibyte[CONFIGURATION_SIZE] __initdata = { - 0x7E, 0xAA, 0x99, 0x7E, 0x51, 0x00, 0x01, 0x05, 0x92, 0x00, 0x20, 0x62, 0x03, 0x67, 0x72, 0x01, - 0x10, 0x82, 0x00, 0x00, 0x11, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 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* linux/drivers/fpga/spi_fpga_init.c - spi fpga init driver - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or (at - * your option) any later version. - */ - -/* - * Note: fpga ice65l08xx is used for spi2uart,spi2gpio,spi2i2c and spi2dpram. - * this driver is the entry of all modules's drivers,should be run at first. - * the struct for fpga is build in the driver,and it is important. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_SPI_FPGA_INIT_DEBUG) -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -struct spi_fpga_port *pFpgaPort; - -#if SPI_FPGA_TRANS_WORK -#define ID_SPI_FPGA_WRITE 1 -#define ID_SPI_FPGA_READ 2 -struct spi_fpga_transfer -{ - u8 *txbuf; - unsigned n_tx; - u8 *rxbuf; - unsigned n_rx; - int id; - struct list_head queue; -}; - -static void spi_fpga_trans_work_handler(struct work_struct *work) -{ - struct spi_fpga_port *port = - container_of(work, struct spi_fpga_port, fpga_trans_work); - - while (1) { - unsigned long flags; - struct spi_fpga_transfer *t = NULL; - - spin_lock_irqsave(&port->work_lock, flags); - if (!list_empty(&port->trans_queue)) { - t = list_first_entry(&port->trans_queue, struct spi_fpga_transfer, queue); - list_del(&t->queue); - } - spin_unlock_irqrestore(&port->work_lock, flags); - - if (!t) // trans_queue empty - break; - - DBG("%s:id=%d,txbuf=0x%x\n",__FUNCTION__,t->id,(int)t->txbuf); - switch (t->id) { - case ID_SPI_FPGA_WRITE: - spi_write(port->spi, t->txbuf, t->n_tx); - break; - default: - break; - } - kfree(t->txbuf); - kfree(t); - } -} - -int spi_write_work(struct spi_device *spi, u8 *buf, size_t len) -{ - struct spi_fpga_port *port = spi_get_drvdata(spi); - struct spi_fpga_transfer *t; - unsigned long flags; - - t = kzalloc(sizeof(struct spi_fpga_transfer), GFP_KERNEL); - if (!t) - { - printk("err:%s:ENOMEM\n",__FUNCTION__); - return -ENOMEM; - } - - t->txbuf = (char *)kmalloc(32, GFP_KERNEL); - if(t->txbuf == NULL) - { - printk("%s:t->txbuf kzalloc err!!!\n",__FUNCTION__); - return -ENOMEM; - } - - memcpy(t->txbuf, buf, len); - t->n_tx = len; - t->id = ID_SPI_FPGA_WRITE; - - spin_lock_irqsave(&port->work_lock, flags); - list_add_tail(&t->queue, &port->trans_queue); - spin_unlock_irqrestore(&port->work_lock, flags); - queue_work(port->fpga_trans_workqueue, &port->fpga_trans_work); - - return 0; - -} - -#endif - - -#if SPI_FPGA_POLL_WAIT - -#define SPI_BUFSIZE 1028 -static void spi_fpga_complete(void *arg) -{ - struct spi_fpga_port *port = pFpgaPort; - msleep(5); - wake_up_interruptible(&port->spi_wait_q); - printk("%s:line=%d\n",__FUNCTION__,__LINE__); -} - -int spi_fpga_write(struct spi_device *spi, const u8 *buf, size_t len) -{ - struct spi_transfer t = { - .tx_buf = buf, - .len = len, - }; - struct spi_message m; - printk("%s:line=%d\n",__FUNCTION__,__LINE__); - spi_message_init(&m); - spi_message_add_tail(&t, &m); - printk("%s:line=%d\n",__FUNCTION__,__LINE__); - return spi_async(spi, &m); -} - -struct poll_table_struct wait; -struct file filp; -int spi_fpga_write_then_read(struct spi_device *spi, - const u8 *txbuf, unsigned n_tx, - u8 *rxbuf, unsigned n_rx) -{ - struct spi_fpga_port *port = spi_get_drvdata(spi); - int status; - struct spi_message message; - struct spi_transfer x[2]; - u8 *local_buf; - printk("%s:line=%d,n_tx+n_rx=%d\n",__FUNCTION__,__LINE__,(n_tx + n_rx)); - /* Use preallocated DMA-safe buffer. We can't avoid copying here, - * (as a pure convenience thing), but we can keep heap costs - * out of the hot path ... - */ - printk("%s:line=%d\n",__FUNCTION__,__LINE__); - - if ((n_tx + n_rx) > SPI_BUFSIZE) - return -EINVAL; - printk("%s:line=%d\n",__FUNCTION__,__LINE__); - - spi_message_init(&message); - memset(x, 0, sizeof x); - printk("%s:line=%d\n",__FUNCTION__,__LINE__); - if (n_tx) { - x[0].len = n_tx; - spi_message_add_tail(&x[0], &message); - } - printk("%s:line=%d\n",__FUNCTION__,__LINE__); - - if (n_rx) { - x[1].len = n_rx; - spi_message_add_tail(&x[1], &message); - } - printk("%s:line=%d\n",__FUNCTION__,__LINE__); - /* ... unless someone else is using the pre-allocated buffer */ - - local_buf = kmalloc(SPI_BUFSIZE, GFP_KERNEL); - if (!local_buf) - return -ENOMEM; - - memcpy(local_buf, txbuf, n_tx); - x[0].tx_buf = local_buf; - x[1].rx_buf = local_buf + n_tx; - printk("%s:line=%d\n",__FUNCTION__,__LINE__); - message.complete = spi_fpga_complete; - - /* do the i/o */ - status = spi_async(spi, &message); -#if 1 - //poll_wait(&filp, &port->spi_wait_q, &wait); - - //if (status == 0) - memcpy(rxbuf, x[1].rx_buf, n_rx); - printk("%s:line=%d\n",__FUNCTION__,__LINE__); - kfree(local_buf); - printk("%s:line=%d\n",__FUNCTION__,__LINE__); -#endif - return status; -} - -#define spi_write spi_fpga_write -#define spi_write_then_read spi_fpga_write_then_read - -#endif - -/*------------------------spi¶ÁдµÄ»ù±¾º¯Êý-----------------------*/ -unsigned int spi_in(struct spi_fpga_port *port, int reg, int type) -{ - unsigned char index = 0; - unsigned char tx_buf[2], rx_buf[2], n_rx=2, stat=0; - unsigned int result=0; - //printk("index1=%d\n",index); - - switch(type) - { -#if defined(CONFIG_SPI_FPGA_UART) - case SEL_UART: - index = port->uart.index; - reg = (((reg) | ICE_SEL_UART) | ICE_SEL_READ | ICE_SEL_UART_CH(index)); - tx_buf[0] = reg & 0xff; - tx_buf[1] = 1;//give fpga 8 clks for reading data - rx_buf[0] = 0; - rx_buf[1] = 0; - stat = spi_write_then_read(port->spi, (const u8 *)&tx_buf, sizeof(tx_buf), rx_buf, n_rx); - result = (rx_buf[0] << 8) | rx_buf[1]; - DBG("%s,SEL_UART reg=0x%x,result=0x%x\n",__FUNCTION__,reg&0xff,result&0xff); - break; -#endif - -#if defined(CONFIG_SPI_FPGA_GPIO) - case SEL_GPIO: - reg = (((reg) | ICE_SEL_GPIO) | ICE_SEL_READ ); - tx_buf[0] = reg & 0xff; - tx_buf[1] = 0;//give fpga 8 clks for reading data - rx_buf[0] = 0; - rx_buf[1] = 0; - stat = spi_write_then_read(port->spi, (const u8 *)&tx_buf, sizeof(tx_buf), rx_buf, n_rx); - result = (rx_buf[0] << 8) | rx_buf[1]; - DBG("%s,SEL_GPIO reg=0x%x,result=0x%x\n",__FUNCTION__,reg&0xff,result&0xffff); - break; -#endif - -#if defined(CONFIG_SPI_FPGA_I2C) - case SEL_I2C: - reg = (((reg) | ICE_SEL_I2C) | ICE_SEL_READ ); - tx_buf[0] = reg & 0xff; - tx_buf[1] = 0; - rx_buf[0] = 0; - rx_buf[1] = 0; - stat = spi_write_then_read(port->spi, (const u8 *)&tx_buf, sizeof(tx_buf)-1, rx_buf, n_rx); - result = rx_buf[1]; - DBG("%s,SEL_I2C reg=0x%x,result=0x%x \n",__FUNCTION__,reg&0xff,result&0xffff); - break; -#endif - -#if defined(CONFIG_SPI_FPGA_DPRAM) - case SEL_DPRAM: - reg = (((reg) | ICE_SEL_DPRAM) & ICE_SEL_DPRAM_READ ); - tx_buf[0] = reg & 0xff; - tx_buf[1] = 0;//give fpga 8 clks for reading data - rx_buf[0] = 0; - rx_buf[1] = 0; - stat = spi_write_then_read(port->spi, (const u8 *)&tx_buf, sizeof(tx_buf), rx_buf, n_rx); - result = (rx_buf[0] << 8) | rx_buf[1]; - DBG("%s,SEL_GPIO reg=0x%x,result=0x%x\n",__FUNCTION__,reg&0xff,result&0xffff); - break; -#endif - case READ_TOP_INT: - reg = (((reg) | ICE_SEL_UART) | ICE_SEL_READ); - tx_buf[0] = reg & 0xff; - tx_buf[1] = 0; - rx_buf[0] = 0; - rx_buf[1] = 0; - stat = spi_write_then_read(port->spi, (const u8 *)&tx_buf, sizeof(tx_buf)-1, rx_buf, n_rx); - result = (rx_buf[0] << 8) | rx_buf[1]; - DBG("%s,SEL_INT reg=0x%x,result=0x%x\n",__FUNCTION__,reg&0xff,result&0xff); - break; - default: - printk("%s err: Can not support this type!\n",__FUNCTION__); - break; - } - - return result; -} - -void spi_out(struct spi_fpga_port *port, int reg, int value, int type) -{ - unsigned char index = 0; - unsigned char tx_buf[3]; - int reg_temp = reg; - switch(type) - { -#if defined(CONFIG_SPI_FPGA_UART) - case SEL_UART: - index = port->uart.index; - reg = ((((reg) | ICE_SEL_UART) & ICE_SEL_WRITE) | ICE_SEL_UART_CH(index)); - tx_buf[0] = reg & 0xff; - tx_buf[1] = (value>>8) & 0xff; - tx_buf[2] = value & 0xff; - if(reg_temp == UART_IER) - spi_write_work(port->spi, tx_buf, sizeof(tx_buf)); - else - spi_write(port->spi, (const u8 *)&tx_buf, sizeof(tx_buf)); - DBG("%s,SEL_UART reg=0x%x,value=0x%x\n",__FUNCTION__,reg&0xff,value&0xffff); - break; -#endif - -#if defined(CONFIG_SPI_FPGA_GPIO) - case SEL_GPIO: - reg = (((reg) | ICE_SEL_GPIO) & ICE_SEL_WRITE ); - tx_buf[0] = reg & 0xff; - tx_buf[1] = (value>>8) & 0xff; - tx_buf[2] = value & 0xff; - spi_write(port->spi, (const u8 *)&tx_buf, sizeof(tx_buf)); - DBG("%s,SEL_GPIO reg=0x%x,value=0x%x\n",__FUNCTION__,reg&0xff,value&0xffff); - break; -#endif - -#if defined(CONFIG_SPI_FPGA_I2C) - case SEL_I2C: - reg = (((reg) | ICE_SEL_I2C) & ICE_SEL_WRITE); - tx_buf[0] = reg & 0xff; - tx_buf[1] = (value>>8) & 0xff; - tx_buf[2] = value & 0xff; - spi_write(port->spi, (const u8 *)&tx_buf, sizeof(tx_buf)); - DBG("%s,SEL_I2C reg=0x%x,value=0x%x\n",__FUNCTION__,reg&0xff,value&0xffff); - break; -#endif - -#if defined(CONFIG_SPI_FPGA_DPRAM) - case SEL_DPRAM: - reg = (((reg) | ICE_SEL_DPRAM) | ICE_SEL_DPRAM_WRITE ); - tx_buf[0] = reg & 0xff; - tx_buf[1] = (value>>8) & 0xff; - tx_buf[2] = value & 0xff; - spi_write(port->spi, (const u8 *)&tx_buf, sizeof(tx_buf)); - DBG("%s,SEL_DPRAM reg=0x%x,value=0x%x\n",__FUNCTION__,reg&0xff,value&0xffff); - break; -#endif - - default: - printk("%s err: Can not support this type!\n",__FUNCTION__); - break; - } - -} - -#if SPI_FPGA_TEST_DEBUG -int spi_test_wrong_handle(void) -{ - gpio_direction_output(SPI_FPGA_TEST_DEBUG_PIN,0); - udelay(2); - gpio_direction_output(SPI_FPGA_TEST_DEBUG_PIN,1); - printk("%s:give one trailing edge!\n",__FUNCTION__); - return 0; -} - -static int spi_test_request_gpio(int set) -{ - int ret; - rk2818_mux_api_set(GPIOE0_VIPDATA0_SEL_NAME,0); - ret = gpio_request(SPI_FPGA_TEST_DEBUG_PIN, NULL); - if (ret) { - printk("%s:failed to request SPI_FPGA_TEST_DEBUG_PIN pin\n",__FUNCTION__); - return ret; - } - gpio_direction_output(SPI_FPGA_TEST_DEBUG_PIN,set); - - return 0; -} - -#endif - -static void spi_fpga_irq_work_handler(struct work_struct *work) -{ - struct spi_fpga_port *port = - container_of(work, struct spi_fpga_port, fpga_irq_work); - struct spi_device *spi = port->spi; - int ret,uart_ch=0; - - DBG("Enter::%s,LINE=%d\n",__FUNCTION__,__LINE__); - - ret = spi_in(port, ICE_SEL_READ_INT_TYPE, READ_TOP_INT) & 0xff; - if((ret | ICE_INT_TYPE_UART0) == ICE_INT_TYPE_UART0) - { -#if defined(CONFIG_SPI_FPGA_UART) - DBG("%s:ICE_INT_TYPE_UART0 ret=0x%x\n",__FUNCTION__,ret); - port->uart.index = uart_ch; - spi_uart_handle_irq(spi); -#endif - } - else if((ret | ICE_INT_TYPE_GPIO) == ICE_INT_TYPE_GPIO) - { -#if defined(CONFIG_SPI_FPGA_GPIO) - DBG("%s:ICE_INT_TYPE_GPIO ret=0x%x\n",__FUNCTION__,ret); - spi_gpio_handle_irq(spi); -#endif - } - else if((ret | ICE_INT_TYPE_I2C2) == ICE_INT_TYPE_I2C2) - { -#if defined(CONFIG_SPI_FPGA_I2C) - DBG("%s:ICE_INT_TYPE_I2C2 ret=0x%x\n",__FUNCTION__,ret); - spi_i2c_handle_irq(port,I2C_CH2); -#endif - } - else if((ret | ICE_INT_TYPE_I2C3) == ICE_INT_TYPE_I2C3) - { -#if defined(CONFIG_SPI_FPGA_I2C) - DBG("%s:ICE_INT_TYPE_I2C3 ret=0x%x\n",__FUNCTION__,ret); - spi_i2c_handle_irq(port,I2C_CH3); -#endif - } - else if((ret | ICE_INT_TYPE_DPRAM) == ICE_INT_TYPE_DPRAM) - { -#if defined(CONFIG_SPI_FPGA_DPRAM) - DBG("%s:ICE_INT_TYPE_DPRAM ret=0x%x\n",__FUNCTION__,ret); - spi_dpram_handle_ack(spi); -#endif - } - else if((ret | ICE_INT_TYPE_SLEEP) == ICE_INT_TYPE_SLEEP) - { - DBG("%s:ICE_INT_TYPE_SLEEP ret=0x%x\n",__FUNCTION__,ret); - printk("FPGA wake up system now ...\n"); - } - else - { - printk("warning:ret=0x%x\n",ret); - } - - DBG("Enter::%s,LINE=%d\n",__FUNCTION__,__LINE__); -} - - -static irqreturn_t spi_fpga_irq(int irq, void *dev_id) -{ - struct spi_fpga_port *port = dev_id; - DBG("Enter::%s,LINE=%d\n",__FUNCTION__,__LINE__); - /* - * Can't do anything in interrupt context because we need to - * block (spi_sync() is blocking) so fire of the interrupt - * handling workqueue. - * Remember that we access ICE65LXX registers through SPI bus - * via spi_sync() call. - */ - - //schedule_work(&port->fpga_irq_work); - queue_work(port->fpga_irq_workqueue, &port->fpga_irq_work); - - return IRQ_HANDLED; -} - - -static int spi_fpga_set_sysclk(int set) -{ - rk2818_mux_api_set(GPIOH7_HSADCCLK_SEL_NAME,IOMUXB_GPIO1_D7); - gpio_direction_output(SPI_FPGA_STANDBY_PIN,set); - - return 0; -} - -static int spi_fpga_set_status(struct spi_fpga_port *port, int stat) -{ - if(stat == ICE_STATUS_SLEEP) - { - spi_out(port, (ICE_SEL_GPIO0 | ICE_SEL_GPIO0_INT_WAKE), ICE_STATUS_SLEEP, SEL_GPIO); - } - else - { - spi_out(port, (ICE_SEL_GPIO0 | ICE_SEL_GPIO0_INT_WAKE), ICE_STATUS_WAKE, SEL_GPIO); - } - - return 0; -} - -static int spi_fpga_rst(void) -{ - int ret; - ret = gpio_request(SPI_FPGA_RST_PIN, NULL); - if (ret) { - printk("%s:failed to request fpga rst pin\n",__FUNCTION__); - return ret; - } - rk2818_mux_api_set(GPIOH6_IQ_SEL_NAME,0); - gpio_direction_output(SPI_FPGA_RST_PIN,GPIO_HIGH); - gpio_direction_output(SPI_FPGA_RST_PIN,GPIO_LOW); - mdelay(1); - gpio_direction_output(SPI_FPGA_RST_PIN,GPIO_HIGH); - - gpio_direction_input(SPI_FPGA_RST_PIN); - - return 0; -} - -static int __devinit spi_fpga_probe(struct spi_device * spi) -{ - struct spi_fpga_port *port; - int ret; - char b[24]; - int num; - DBG("Enter::%s,LINE=%d************************\n",__FUNCTION__,__LINE__); - /* - * bits_per_word cannot be configured in platform data - */ - spi->bits_per_word = 8; - - ret = spi_setup(spi); - if (ret < 0) - return ret; - - port = kzalloc(sizeof(struct spi_fpga_port), GFP_KERNEL); - if (!port) - return -ENOMEM; - DBG("port=0x%x\n",(int)port); - - mutex_init(&port->spi_lock); - spin_lock_init(&port->work_lock); - ret = gpio_request(SPI_FPGA_STANDBY_PIN, NULL); - if (ret) { - printk("%s:failed to request standby pin\n",__FUNCTION__); - return ret; - } - spi_fpga_set_sysclk(GPIO_HIGH); - -#if SPI_FPGA_TRANS_WORK - init_waitqueue_head(&port->wait_wq); - init_waitqueue_head(&port->wait_rq); - port->write_en = TRUE; - port->read_en = TRUE; - sprintf(b, "fpga_trans_workqueue"); - port->fpga_trans_workqueue = create_rt_workqueue(b); - if (!port->fpga_trans_workqueue) { - printk("cannot create workqueue\n"); - return -EBUSY; - } - INIT_WORK(&port->fpga_trans_work, spi_fpga_trans_work_handler); - INIT_LIST_HEAD(&port->trans_queue); -#endif - - spi_fpga_rst(); //reset fpga - - sprintf(b, "fpga_irq_workqueue"); - port->fpga_irq_workqueue = create_rt_workqueue(b); - if (!port->fpga_irq_workqueue) { - printk("cannot create workqueue\n"); - return -EBUSY; - } - INIT_WORK(&port->fpga_irq_work, spi_fpga_irq_work_handler); - -#if defined(CONFIG_SPI_FPGA_UART) - ret = spi_uart_register(port); - if(ret) - { - spi_uart_unregister(port); - printk("%s:ret=%d,fail to spi_uart_register\n",__FUNCTION__,ret); - return ret; - } -#endif -#if defined(CONFIG_SPI_FPGA_GPIO) - ret = spi_gpio_register(port); - if(ret) - { - spi_gpio_unregister(port); - printk("%s:ret=%d,fail to spi_gpio_register\n",__FUNCTION__,ret); - return ret; - } -#endif -#if defined(CONFIG_SPI_FPGA_I2C) - - DBG("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port); - spin_lock_init(&port->i2c.i2c_lock); - for (num= 2;num<4;num++) - { - ret = spi_i2c_register(port,num); - if(ret) - { - spi_i2c_unregister(port); - printk("%s:ret=%d,fail to spi_i2c_register\n",__FUNCTION__,ret); - return ret; - } - DBG("spi_i2c spi_i2c.%d: i2c-%d: spi_i2c I2C adapter\n",num,num); - } -#endif - -#if defined(CONFIG_SPI_FPGA_DPRAM) - ret = spi_dpram_register(port); - if(ret) - { - spi_dpram_unregister(port); - printk("%s:ret=%d,fail to spi_dpram_register\n",__FUNCTION__,ret); - return ret; - } -#endif - port->spi = spi; - spi_set_drvdata(spi, port); - - ret = gpio_request(SPI_FPGA_INT_PIN, NULL); - if (ret) { - printk("%s:failed to request fpga intterupt gpio\n",__FUNCTION__); - goto err1; - } - - rk2818_mux_api_set(CXGPIO_HSADC_SEL_NAME,IOMUXB_GPIO2_14_23); - gpio_pull_updown(SPI_FPGA_INT_PIN,GPIOPullUp); - ret = request_irq(gpio_to_irq(SPI_FPGA_INT_PIN),spi_fpga_irq,IRQF_TRIGGER_FALLING,NULL,port); - if(ret) - { - printk("unable to request spi_uart irq\n"); - goto err2; - } - DBG("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port); - pFpgaPort = port; - - -#if defined(CONFIG_SPI_FPGA_GPIO) - spi_fpga_set_status(port, ICE_STATUS_WAKE); - spi_gpio_init(); -#endif - -#if SPI_FPGA_TEST_DEBUG - spi_test_request_gpio(GPIO_HIGH); -#endif - - return 0; - -err2: - free_irq(gpio_to_irq(SPI_FPGA_INT_PIN),NULL); -err1: - gpio_free(SPI_FPGA_INT_PIN); - - return ret; - - -} - -static int __devexit spi_fpga_remove(struct spi_device *spi) -{ - //struct spi_fpga_port *port = dev_get_drvdata(&spi->dev); - - - return 0; -} - -#ifdef CONFIG_PM - -static int spi_fpga_wait_suspend(struct spi_fpga_port *port) -{ - int i,n_tx,n_rx; - for(i=0;i<1000;i++) - { - n_tx = spi_in(port, UART_LSR, READ_TOP_INT); //CONFIG_SPI_FPGA_UART = 1 - n_rx = spi_in(port, UART_LSR, SEL_UART); - if((((n_tx >> 8) & 0x3f) == 0) && (((n_rx >> 8) & 0x3f) == 0)) //no data in tx_buf and rx_buf - { - printk("%s,i=%d\n",__FUNCTION__,i); - return 0; - } - } - - return -1; -} - -static void fpga_close_power_support(void) -{ - //modem - #if 0 - gpio_request(FPGA_PIO2_03, NULL); - gpio_direction_output(FPGA_PIO2_03,GPIO_LOW); - gpio_free(FPGA_PIO2_03); - gpio_request(FPGA_PIO2_05, NULL); - gpio_direction_output(FPGA_PIO2_05,GPIO_HIGH); - gpio_free(FPGA_PIO2_05); - #endif - - //cmmb power down - gpio_request(FPGA_PIO4_03, NULL); - gpio_direction_output(FPGA_PIO4_03,GPIO_LOW); - gpio_free(FPGA_PIO4_03); - gpio_request(FPGA_PIO2_09, NULL); - gpio_direction_output(FPGA_PIO2_09,GPIO_LOW); - gpio_free(FPGA_PIO2_09); - gpio_request(FPGA_PIO2_06, NULL); - gpio_direction_output(FPGA_PIO2_06,GPIO_LOW); - gpio_free(FPGA_PIO2_06); - - //KEY LED control - gpio_request(FPGA_PIO1_13, NULL); - gpio_direction_output(FPGA_PIO1_13,GPIO_LOW); - gpio_free(FPGA_PIO1_13); -} - -static void fpga_open_power_support(void) -{ - //modem - #if 0 - gpio_request(FPGA_PIO2_03, NULL); - gpio_direction_output(FPGA_PIO2_03,GPIO_HIGH); - gpio_free(FPGA_PIO2_03); - gpio_request(FPGA_PIO2_05, NULL); - gpio_direction_output(FPGA_PIO2_05,GPIO_LOW); - gpio_free(FPGA_PIO2_05); - #endif - - //cmmb do not control here - - //KEY LED resume - gpio_request(FPGA_PIO1_13, NULL); - gpio_direction_output(FPGA_PIO1_13,GPIO_HIGH); - gpio_free(FPGA_PIO1_13); -} - - -static int spi_fpga_suspend(struct spi_device *spi, pm_message_t state) -{ - - struct spi_fpga_port *port = dev_get_drvdata(&spi->dev); - int ret; - fpga_close_power_support( ); - ret = spi_fpga_wait_suspend(port); - if(!ret) - { - spi_fpga_set_status(port, ICE_STATUS_SLEEP); //CONFIG_SPI_FPGA_GPIO = 1 - udelay(1); - spi_fpga_set_sysclk(GPIO_LOW); - } - else - { - printk("fail to suspend fpga because it is sending or recieve data!\n"); - return -1; - } - - printk("%s\n",__FUNCTION__); - - return 0; -} - -static int spi_fpga_resume(struct spi_device *spi) -{ - - struct spi_fpga_port *port = dev_get_drvdata(&spi->dev); - spi_fpga_set_sysclk(GPIO_HIGH); - udelay(1); - spi_fpga_set_status(port, ICE_STATUS_WAKE); - fpga_open_power_support( ); - printk("%s\n",__FUNCTION__); - - return 0; -} - -#else -#define spi_fpga_suspend NULL -#define spi_fpga_resume NULL -#endif - -static struct spi_driver spi_fpga_driver = { - .driver = { - .name = "spi_fpga", - .bus = &spi_bus_type, - .owner = THIS_MODULE, - }, - - .probe = spi_fpga_probe, - .remove = __devexit_p(spi_fpga_remove), - .suspend = spi_fpga_suspend, - .resume = spi_fpga_resume, -}; - -static int __init spi_fpga_init(void) -{ - return spi_register_driver(&spi_fpga_driver); -} - -static void __exit spi_fpga_exit(void) -{ - spi_unregister_driver(&spi_fpga_driver); -} - -subsys_initcall(spi_fpga_init); -module_exit(spi_fpga_exit); - -MODULE_DESCRIPTION("Driver for spi2uart,spi2gpio,spi2i2c."); -MODULE_AUTHOR("luowei "); -MODULE_LICENSE("GPL"); diff --git a/drivers/fpga/spi_gpio.c b/drivers/fpga/spi_gpio.c deleted file mode 100755 index 06620ca56fa5..000000000000 --- a/drivers/fpga/spi_gpio.c +++ /dev/null @@ -1,1229 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_SPI_GPIO_DEBUG) -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -#define SPI_GPIO_TEST 0 -#define HIGH_SPI_TEST 1 - -static DEFINE_SPINLOCK(gpio_state_lock); -//static DEFINE_SPINLOCK(gpio_irq_lock); -static unsigned short int gGpio0State = 0; -#define SPI_GPIO_IRQ_NUM 16 -static SPI_GPIO_PDATA g_spiGpioVectorTable[SPI_GPIO_IRQ_NUM] = \ -{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}; - -/************FPGA ²Ù×÷GPIOµÄº¯ÊýʵÏÖ************************/ - -static void spi_gpio_write_reg(int reg, int PinNum, int set) -{ - unsigned int old_set; - unsigned int new_set; - struct spi_fpga_port *port = pFpgaPort; - PinNum = PinNum % 16; - - old_set= spi_in(port, reg, SEL_GPIO); - - if(1 == set) - new_set = old_set | (1 << PinNum ); - else - new_set = old_set & (~(1 << PinNum )); - spi_out(port, reg, new_set, SEL_GPIO); -} - -static int spi_gpio_read_reg(int reg) -{ - int ret = 0; - struct spi_fpga_port *port = pFpgaPort; - - ret = spi_in(port, reg, SEL_GPIO); - - return ret; -} - - -static int get_gpio_addr(eSpiGpioPinNum_t PinNum) -{ - int gpio = PinNum / 16; - int reg = -1; - switch(gpio) - { - case 0: - reg = ICE_SEL_GPIO0; - break; - case 1: - reg = ICE_SEL_GPIO1; - break; - case 2: - reg = ICE_SEL_GPIO2; - break; - case 3: - reg = ICE_SEL_GPIO3; - break; - case 4: - reg = ICE_SEL_GPIO4; - break; - case 5: - reg = ICE_SEL_GPIO5; - break; - default: - break; - - } - - return reg; - -} - - -int spi_gpio_int_sel(eSpiGpioPinNum_t PinNum,eSpiGpioTypeSel_t type) -{ - int reg = get_gpio_addr(PinNum); - //struct spi_fpga_port *port = pFpgaPort; - DBG("%s:PinNum=%d,type=%d\n",__FUNCTION__,PinNum,type); - if(ICE_SEL_GPIO0 == reg) - { - reg |= ICE_SEL_GPIO0_TYPE; - spin_lock(&gpio_state_lock); - if(SPI_GPIO0_IS_INT == type) - gGpio0State |= (1 << PinNum ); - else - gGpio0State &= (~(1 << PinNum )); - spin_unlock(&gpio_state_lock); - DBG("%s,PinNum=%d,GPIO[%d]:type=%d\n",__FUNCTION__,PinNum,PinNum/16,type); - - spi_gpio_write_reg(reg, PinNum, type); - return 0; - } - else - { - printk("%s:error\n",__FUNCTION__); - return -1; - } - -} - - -int spi_gpio_set_pindirection(eSpiGpioPinNum_t PinNum,eSpiGpioPinDirection_t direction) -{ - int reg = get_gpio_addr(PinNum); - //struct spi_fpga_port *port = pFpgaPort; - int state; - spin_lock(&gpio_state_lock); - state = gGpio0State; - spin_unlock(&gpio_state_lock); - - if(reg == -1) - { - printk("%s:error\n",__FUNCTION__); - return -1; - } - - if(ICE_SEL_GPIO0 == reg) - { - reg |= ICE_SEL_GPIO0_DIR; - if((state & (1 << PinNum )) != 0) - { - printk("Fail to set direction because it is int pin!\n"); - return -1; - } - DBG("%s,PinNum=%d,direction=%d,GPIO[%d]:PinNum/16=%d\n",__FUNCTION__,PinNum,direction,PinNum/16,PinNum%16); - spi_gpio_write_reg(reg, PinNum, direction); - } - else - { - reg |= ICE_SEL_GPIO_DIR; - DBG("%s,PinNum=%d,direction=%d,GPIO[%d]:PinNum/16=%d\n",__FUNCTION__,PinNum,direction,PinNum/16,PinNum%16); - spi_gpio_write_reg(reg, PinNum, direction); - } - return 0; -} - -eSpiGpioPinDirection_t spi_gpio_get_pindirection(eSpiGpioPinNum_t PinNum) -{ - int ret = 0; - int reg = get_gpio_addr(PinNum); - int dir = 0; - //struct spi_fpga_port *port = pFpgaPort; - int state; - spin_lock(&gpio_state_lock); - state = gGpio0State; - spin_unlock(&gpio_state_lock); - - if(reg == -1) - { - printk("%s:error\n",__FUNCTION__); - return SPI_GPIO_DIR_ERR; - } - - if(ICE_SEL_GPIO0 == reg) - { - reg |= ICE_SEL_GPIO0_DIR; - if((state & (1 << PinNum )) != 0) - { - printk("Fail to get pindirection because it is int pin!\n"); - return SPI_GPIO_DIR_ERR; - } - ret = spi_gpio_read_reg(reg); - } - else - { - reg |= ICE_SEL_GPIO_DIR; - ret = spi_gpio_read_reg(reg); - } - - if((ret & (1 << (PinNum%16) )) == 0) - dir = SPI_GPIO_IN; - else - dir = SPI_GPIO_OUT; - - DBG("%s,PinNum=%d,ret=0x%x,GPIO[%d]:PinNum/16=%d,pindirection=%d\n\n",__FUNCTION__,PinNum,ret,PinNum/16,PinNum%16,dir); - - return dir; - -} - - -int spi_gpio_set_pinlevel(eSpiGpioPinNum_t PinNum, eSpiGpioPinLevel_t PinLevel) -{ - int reg = get_gpio_addr(PinNum); - //struct spi_fpga_port *port = pFpgaPort; - int state; - spin_lock(&gpio_state_lock); - state = gGpio0State; - spin_unlock(&gpio_state_lock); - - if(reg == -1) - { - printk("%s:error\n",__FUNCTION__); - return -1; - } - - if(ICE_SEL_GPIO0 == reg) - { - reg |= ICE_SEL_GPIO0_DATA; - if((state & (1 << PinNum )) != 0) - { - printk("Fail to set PinLevel because PinNum=%d is int pin!\n",PinNum); - return -1; - } - DBG("%s,PinNum=%d,GPIO[%d]:PinNum/16=%d,PinLevel=%d\n",__FUNCTION__,PinNum,PinNum/16,PinNum%16,PinLevel); - spi_gpio_write_reg(reg, PinNum, PinLevel); - - } - else - { - reg |= ICE_SEL_GPIO_DATA; - DBG("%s,PinNum=%d,GPIO[%d]:PinNum/16=%d,PinLevel=%d\n",__FUNCTION__,PinNum,PinNum/16,PinNum%16,PinLevel); - spi_gpio_write_reg(reg, PinNum, PinLevel); - } - - return 0; - -} - - -eSpiGpioPinLevel_t spi_gpio_get_pinlevel(eSpiGpioPinNum_t PinNum) -{ - int ret = 0; - int reg = get_gpio_addr(PinNum); - int level = 0; - //struct spi_fpga_port *port = pFpgaPort; - int state; - spin_lock(&gpio_state_lock); - state = gGpio0State; - spin_unlock(&gpio_state_lock); - - if(reg == -1) - { - printk("%s:error\n",__FUNCTION__); - return SPI_GPIO_LEVEL_ERR; - } - - if(ICE_SEL_GPIO0 == reg) - { - reg |= ICE_SEL_GPIO0_DATA; - //if((state & (1 << PinNum )) != 0) - //{ - // printk("Fail to get PinLevel because it is int pin!\n"); - // return SPI_GPIO_LEVEL_ERR; - //} - ret = spi_gpio_read_reg(reg); - } - else - { - reg |= ICE_SEL_GPIO_DATA; - ret = spi_gpio_read_reg(reg); - } - - if((ret & (1 << (PinNum%16) )) == 0) - level = SPI_GPIO_LOW; - else - level = SPI_GPIO_HIGH; - - DBG("%s,PinNum=%d,ret=0x%x,GPIO[%d]:PinNum/16=%d,PinLevel=%d\n\n",__FUNCTION__,PinNum,ret,PinNum/16,PinNum%16,level); - - return level; - -} - - -int spi_gpio_enable_int(eSpiGpioPinNum_t PinNum) -{ - int reg = get_gpio_addr(PinNum); - //struct spi_fpga_port *port = pFpgaPort; - int state; - spin_lock(&gpio_state_lock); - state = gGpio0State; - spin_unlock(&gpio_state_lock); - - if(ICE_SEL_GPIO0 == reg) - { - reg |= ICE_SEL_GPIO0_INT_EN; - if((state & (1 << PinNum )) == 0) - { - printk("%s:Fail to enable int because it is gpio pin!\n",__FUNCTION__); - return -1; - } - DBG("%s,PinNum=%d,IntEn=%d\n",__FUNCTION__,PinNum,SPI_GPIO_INT_ENABLE); - spi_gpio_write_reg(reg, PinNum, SPI_GPIO_INT_ENABLE); - } - else - { - printk("%s:error\n",__FUNCTION__); - return -1; - } - - return 0; -} - - -int spi_gpio_disable_int(eSpiGpioPinNum_t PinNum) -{ - int reg = get_gpio_addr(PinNum); - //struct spi_fpga_port *port = pFpgaPort; - int state; - spin_lock(&gpio_state_lock); - state = gGpio0State; - spin_unlock(&gpio_state_lock); - - if(ICE_SEL_GPIO0 == reg) - { - reg |= ICE_SEL_GPIO0_INT_EN; - - if((state & (1 << PinNum )) == 0) - { - printk("%s:Fail to enable int because it is gpio pin!\n",__FUNCTION__); - return -1; - } - - DBG("%s,PinNum=%d,IntEn=%d\n",__FUNCTION__,PinNum,SPI_GPIO_INT_DISABLE); - spi_gpio_write_reg(reg, PinNum, SPI_GPIO_INT_DISABLE); - } - else - { - printk("%s:error\n",__FUNCTION__); - return -1; - } - - return 0; -} - - -int spi_gpio_set_int_trigger(eSpiGpioPinNum_t PinNum,eSpiGpioIntTri_t IntTri) -{ - int reg = get_gpio_addr(PinNum); - //struct spi_fpga_port *port = pFpgaPort; - int state; - spin_lock(&gpio_state_lock); - state = gGpio0State; - spin_unlock(&gpio_state_lock); - - if(ICE_SEL_GPIO0 == reg) - { - reg |= ICE_SEL_GPIO0_INT_TRI; - - if((state & (1 << PinNum )) == 0) - { - printk("%s:Fail to enable int because it is gpio pin!\n",__FUNCTION__); - return -1; - } - - DBG("%s,PinNum=%d,IntTri=%d\n",__FUNCTION__,PinNum,IntTri); - - spi_gpio_write_reg(reg, PinNum, IntTri); - - } - else - { - printk("%s:error\n",__FUNCTION__); - return -1; - } - - return 0; -} - - -int spi_gpio_set_int_type(eSpiGpioPinNum_t PinNum,eSpiGpioIntType_t IntType) -{ - int reg = get_gpio_addr(PinNum); - //struct spi_fpga_port *port = pFpgaPort; - int state; - spin_lock(&gpio_state_lock); - state = gGpio0State; - spin_unlock(&gpio_state_lock); - - if(ICE_SEL_GPIO0 == reg) - { - reg |= ICE_SEL_GPIO0_INT_TYPE; - - if((state & (1 << PinNum )) == 0) - { - printk("%s:Fail to enable int because it is gpio pin!\n",__FUNCTION__); - return -1; - } - - DBG("%s,PinNum=%d,IntType=%d\n",__FUNCTION__,PinNum,IntType); - - spi_gpio_write_reg(reg, PinNum, IntType); - - } - else - { - printk("%s:error\n",__FUNCTION__); - return -1; - } - - return 0; -} - - -int spi_gpio_read_iir(void) -{ - int reg = ICE_SEL_GPIO0 | ICE_SEL_GPIO0_INT_STATE; - int ret = 0; - - ret = spi_gpio_read_reg(reg); - DBG("%s,IntState=%d\n",__FUNCTION__,ret); - return ret; -} - -int spi_request_gpio_irq(eSpiGpioPinNum_t PinNum, pSpiFunc Routine, eSpiGpioIntTri_t IntType,void *dev_id) -{ -#if 0 - if(PinNum >= SPI_GPIO_IRQ_NUM) - return -1; - DBG("Enter::%s,LINE=%d,PinNum=%d\n",__FUNCTION__,__LINE__,PinNum); - if(spi_gpio_int_sel(PinNum,SPI_GPIO0_IS_INT)) - { - printk("%s err:fail to enable select intterupt when PinNum=%d\n",__FUNCTION__,PinNum); - return -1; - } - if(spi_gpio_set_int_trigger(PinNum,IntType)) - { - printk("%s err:fail to enable set intterrupt trigger when PinNum=%d\n",__FUNCTION__,PinNum); - return -1; - } - - if(g_spiGpioVectorTable[PinNum].gpio_vector) - { - printk("%s err:fail to enable g_spiGpioVectorTable[%d] have been used\n",__FUNCTION__,PinNum); - return -1; - } - spin_lock(&gpio_irq_lock); - g_spiGpioVectorTable[PinNum].gpio_vector = (pSpiFuncIntr)Routine; - g_spiGpioVectorTable[PinNum].gpio_devid= dev_id; - spin_unlock(&gpio_irq_lock); - if(spi_gpio_enable_int(PinNum)) - { - printk("%s err:fail to enable gpio intterupt when PinNum=%d\n",__FUNCTION__,PinNum); - return -1; - } -#endif - return 0; -} - -int spi_free_gpio_irq(eSpiGpioPinNum_t PinNum) -{ - spi_gpio_disable_int(PinNum); -// spin_lock(&gpio_irq_lock); - g_spiGpioVectorTable[PinNum].gpio_vector = NULL; - g_spiGpioVectorTable[PinNum].gpio_devid= NULL; -// spin_unlock(&gpio_irq_lock); - - return 0; -} - - -int spi_gpio_handle_irq(struct spi_device *spi) -{ - int gpio_iir, i; - int state; - int irq; - struct irq_desc *desc; - spin_lock(&gpio_state_lock); - state = gGpio0State; - spin_unlock(&gpio_state_lock); - - gpio_iir = spi_gpio_read_iir() & 0xffff; - if(gpio_iir == 0xffff) - return -1; - - printk("%s:gpio_iir=%d\n",__FUNCTION__,gpio_iir); - for(i=0; iaction->handler) - desc->action->handler(irq,desc->action->dev_id); - printk("%s:pin=%d,irq=%d\n",__FUNCTION__,i,irq); - } - } - - return 0; - -} - - -#if SPI_GPIO_TEST -static irqreturn_t spi_gpio_int_test_0(int irq, void *dev) -{ - printk("%s:LINE=%d,dev=0x%x\n",__FUNCTION__,__LINE__,(int)dev); - return 0; -} - -static irqreturn_t spi_gpio_int_test_1(int irq, void *dev) -{ - printk("%s:LINE=%d,dev=0x%x\n",__FUNCTION__,__LINE__,(int)dev); - return 0; -} - -static irqreturn_t spi_gpio_int_test_2(int irq, void *dev) -{ - printk("%s:LINE=%d,dev=0x%x\n",__FUNCTION__,__LINE__,(int)dev); - return 0; -} - -static irqreturn_t spi_gpio_int_test_3(int irq, void *dev) -{ - printk("%s:LINE=%d,dev=0x%x\n",__FUNCTION__,__LINE__,(int)dev); - return 0; -} - - -static volatile int TestGpioPinLevel = 0; -void spi_gpio_work_handler(struct work_struct *work) -{ - //struct spi_fpga_port *port = - //container_of(work, struct spi_fpga_port, gpio.spi_gpio_work); - int i,ret; - printk("*************test spi_gpio now***************\n"); - - if(TestGpioPinLevel == 0) - TestGpioPinLevel = 1; - else - TestGpioPinLevel = 0; - -#if (FPGA_TYPE == ICE_CC72) - for(i=0;i<32;i++) - { - spi_gpio_set_pinlevel(i, TestGpioPinLevel); - ret = spi_gpio_get_pinlevel(i); - if(ret != TestGpioPinLevel) - DBG("PinNum=%d,set_pinlevel=%d,get_pinlevel=%d\n",i,TestGpioPinLevel,ret); - //spi_gpio_set_pindirection(i, SPI_GPIO_OUT); - } - -#elif (FPGA_TYPE == ICE_CC196) - gpio_direction_output(RK2818_PIN_PE0,0); - udelay(2); - gpio_direction_output(RK2818_PIN_PE0,1); - for(i=4;i<81;i++) - { - gpio_direction_output(SPI_FPGA_EXPANDER_BASE+i,TestGpioPinLevel); - //ret = gpio_direction_input(GPIOS_EXPANDER_BASE+i); - //if (ret) { - // printk("%s:failed to set GPIO[%d] input\n",__FUNCTION__,GPIOS_EXPANDER_BASE+i); - //} - udelay(1); - ret = gpio_get_value (SPI_FPGA_EXPANDER_BASE+i); - if(ret != TestGpioPinLevel) - { - #if SPI_FPGA_TEST_DEBUG - spi_test_wrong_handle(); - #endif - printk("err:%s:PinNum=%d,set_pinlevel=%d but get_pinlevel=%d\n",__FUNCTION__,i,TestGpioPinLevel,ret); - } - } - - DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__); -#endif - -} - -static void spi_testgpio_timer(unsigned long data) -{ - struct spi_fpga_port *port = (struct spi_fpga_port *)data; - port->gpio.gpio_timer.expires = jiffies + msecs_to_jiffies(3000); - add_timer(&port->gpio.gpio_timer); - queue_work(port->gpio.spi_gpio_workqueue, &port->gpio.spi_gpio_work); -} - -#endif - -int spi_gpio_init_first(void) -{ - int i,ret; - struct spi_fpga_port *port = pFpgaPort; -#if HIGH_SPI_TEST - printk("*************test spi communication now***************\n"); - printk("%s:LINE=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port); - for(i=0;i<0xff;i++) - { - spi_out(port, (ICE_SEL_GPIO1 | ICE_SEL_GPIO_DIR), i, SEL_GPIO);//all gpio is input - ret = spi_in(port, (ICE_SEL_GPIO1 | ICE_SEL_GPIO_DIR), SEL_GPIO) & 0xffff; - if(i != ret) - printk("err:i=0x%x but ret=0x%x\n",i,ret); - } - -#endif - -#if (FPGA_TYPE == ICE_CC72) - for(i=0; i<16; i++) - { - DBG("i=%d\n\n",i); - spi_gpio_int_sel(i,SPI_GPIO0_IS_GPIO); - spi_gpio_set_pinlevel(i, SPI_GPIO_LOW); - spi_gpio_set_pindirection(i, SPI_GPIO_OUT); - } - - for(i=16; i<32; i++) - { - spi_gpio_set_pinlevel(i, SPI_GPIO_LOW); - spi_gpio_set_pindirection(i, SPI_GPIO_OUT); - } - -#elif (FPGA_TYPE == ICE_CC196) - - spi_gpio_set_pinlevel(SPI_GPIO_P1_00, SPI_GPIO_HIGH); //LCD_ON output// - spi_gpio_set_pindirection(SPI_GPIO_P1_00, SPI_GPIO_OUT); - spi_gpio_set_pinlevel(SPI_GPIO_P1_01, SPI_GPIO_HIGH); //LCD_PWR_CTRL output - spi_gpio_set_pindirection(SPI_GPIO_P1_01, SPI_GPIO_OUT); - spi_gpio_set_pinlevel(SPI_GPIO_P1_02, SPI_GPIO_HIGH); //SD_POW_ON output - spi_gpio_set_pindirection(SPI_GPIO_P1_02, SPI_GPIO_OUT); - spi_gpio_set_pinlevel(SPI_GPIO_P1_03, SPI_GPIO_LOW); //WL_RST_N/WIFI_EN output - spi_gpio_set_pindirection(SPI_GPIO_P1_03, SPI_GPIO_OUT); - - spi_gpio_set_pindirection(SPI_GPIO_P1_04, SPI_GPIO_IN); //HARDO,input - spi_gpio_set_pinlevel(SPI_GPIO_P1_05, SPI_GPIO_HIGH); //SENSOR_PWDN output - spi_gpio_set_pindirection(SPI_GPIO_P1_05, SPI_GPIO_OUT); - spi_gpio_set_pinlevel(SPI_GPIO_P1_06, SPI_GPIO_LOW); //BT_PWR_EN output - spi_gpio_set_pindirection(SPI_GPIO_P1_06, SPI_GPIO_OUT); - spi_gpio_set_pinlevel(SPI_GPIO_P1_07, SPI_GPIO_LOW); //BT_RST output - spi_gpio_set_pindirection(SPI_GPIO_P1_07, SPI_GPIO_OUT); - - spi_gpio_set_pinlevel(SPI_GPIO_P1_08, SPI_GPIO_LOW); //BT_WAKE_B output - spi_gpio_set_pindirection(SPI_GPIO_P1_08, SPI_GPIO_OUT); - spi_gpio_set_pinlevel(SPI_GPIO_P1_09, SPI_GPIO_LOW); //LCD_DISP_ON output - spi_gpio_set_pindirection(SPI_GPIO_P1_09, SPI_GPIO_OUT); - spi_gpio_set_pinlevel(SPI_GPIO_P1_10, SPI_GPIO_HIGH); //WM_PWR_EN output - spi_gpio_set_pindirection(SPI_GPIO_P1_10, SPI_GPIO_OUT); - spi_gpio_set_pindirection(SPI_GPIO_P1_11, SPI_GPIO_IN); //HARD1,input - - spi_gpio_set_pinlevel(SPI_GPIO_P1_12, SPI_GPIO_LOW); //VIB_MOTO output - spi_gpio_set_pindirection(SPI_GPIO_P1_12, SPI_GPIO_OUT); - spi_gpio_set_pinlevel(SPI_GPIO_P1_13, SPI_GPIO_HIGH); //KEYLED_EN output - spi_gpio_set_pindirection(SPI_GPIO_P1_13, SPI_GPIO_OUT); - spi_gpio_set_pinlevel(SPI_GPIO_P1_14, SPI_GPIO_LOW); //CAM_RST output - spi_gpio_set_pindirection(SPI_GPIO_P1_14, SPI_GPIO_OUT); - spi_gpio_set_pinlevel(SPI_GPIO_P1_15, SPI_GPIO_LOW); //WL_WAKE_B output - spi_gpio_set_pindirection(SPI_GPIO_P1_15, SPI_GPIO_OUT); - - spi_gpio_set_pindirection(SPI_GPIO_P2_00, SPI_GPIO_IN); //Y+YD input - spi_gpio_set_pindirection(SPI_GPIO_P2_01, SPI_GPIO_IN); //Y-YU input - spi_gpio_set_pindirection(SPI_GPIO_P2_02, SPI_GPIO_IN); //AP_TD_UNDIFED input - spi_gpio_set_pinlevel(SPI_GPIO_P2_03, SPI_GPIO_HIGH); //AP_PW_EN_TD output - spi_gpio_set_pindirection(SPI_GPIO_P2_03, SPI_GPIO_OUT); - - spi_gpio_set_pinlevel(SPI_GPIO_P2_04, SPI_GPIO_HIGH); //AP_RESET_TD output - spi_gpio_set_pindirection(SPI_GPIO_P2_04, SPI_GPIO_OUT); - spi_gpio_set_pinlevel(SPI_GPIO_P2_05, SPI_GPIO_HIGH); //AP_SHUTDOWN_TD_PMU output - spi_gpio_set_pindirection(SPI_GPIO_P2_05, SPI_GPIO_OUT); - spi_gpio_set_pinlevel(SPI_GPIO_P2_06, SPI_GPIO_LOW); //AP_RESET_CMMB output - spi_gpio_set_pindirection(SPI_GPIO_P2_06, SPI_GPIO_OUT); - spi_gpio_set_pindirection(SPI_GPIO_P2_07, SPI_GPIO_IN); //AP_CHECK_TD_STATUS input - - spi_gpio_set_pinlevel(SPI_GPIO_P2_08, SPI_GPIO_LOW); //CHARGE_CURRENT_SEL output - spi_gpio_set_pindirection(SPI_GPIO_P2_08, SPI_GPIO_OUT); - spi_gpio_set_pinlevel(SPI_GPIO_P2_09, SPI_GPIO_LOW); //AP_PWD_CMMB output - spi_gpio_set_pindirection(SPI_GPIO_P2_09, SPI_GPIO_OUT); - spi_gpio_set_pindirection(SPI_GPIO_P2_10, SPI_GPIO_IN); //X-XL input - spi_gpio_set_pindirection(SPI_GPIO_P2_11, SPI_GPIO_IN); //X+XR input - - spi_gpio_set_pinlevel(SPI_GPIO_P2_12, SPI_GPIO_LOW); //LCD_RESET output// - spi_gpio_set_pindirection(SPI_GPIO_P2_12, SPI_GPIO_OUT); - spi_gpio_set_pinlevel(SPI_GPIO_P2_12, SPI_GPIO_HIGH); - spi_gpio_set_pinlevel(SPI_GPIO_P2_13, SPI_GPIO_HIGH); //USB_PWR_EN output - spi_gpio_set_pindirection(SPI_GPIO_P2_13, SPI_GPIO_OUT); - spi_gpio_set_pinlevel(SPI_GPIO_P2_14, SPI_GPIO_LOW); //WL_HOST_WAKE_B output - spi_gpio_set_pindirection(SPI_GPIO_P2_14, SPI_GPIO_OUT); - spi_gpio_set_pinlevel(SPI_GPIO_P2_15, SPI_GPIO_HIGH); //TOUCH_SCREEN_RST output// - spi_gpio_set_pindirection(SPI_GPIO_P2_15, SPI_GPIO_OUT); - - //spi_gpio_set_pindirection(SPI_GPIO_P4_06, SPI_GPIO_IN); //CHARGER_INT_END input - spi_gpio_set_pinlevel(SPI_GPIO_P4_06, SPI_GPIO_LOW); //CM3605_PWD low - spi_gpio_set_pindirection(SPI_GPIO_P4_06, SPI_GPIO_OUT); //CHARGER_INT_END output - - - spi_gpio_set_pinlevel(SPI_GPIO_P4_07, SPI_GPIO_LOW); //CM3605_PWD output - spi_gpio_set_pindirection(SPI_GPIO_P4_07, SPI_GPIO_OUT); - spi_gpio_set_pinlevel(SPI_GPIO_P4_08, SPI_GPIO_LOW); //CM3605_PS_SHUTDOWN - spi_gpio_set_pindirection(SPI_GPIO_P4_08, SPI_GPIO_OUT); - -#endif - - return 0; - -} - -static void spi_gpio_irq_work_handler(struct work_struct *work); - -int spi_gpio_register(struct spi_fpga_port *port) -{ -#if SPI_GPIO_TEST - char b[20]; - sprintf(b, "spi_gpio_workqueue"); - port->gpio.spi_gpio_workqueue = create_freezeable_workqueue(b); - if (!port->gpio.spi_gpio_workqueue) { - printk("cannot create spi_gpio workqueue\n"); - return -EBUSY; - } - INIT_WORK(&port->gpio.spi_gpio_work, spi_gpio_work_handler); - setup_timer(&port->gpio.gpio_timer, spi_testgpio_timer, (unsigned long)port); - port->gpio.gpio_timer.expires = jiffies+2000;//>1000ms - add_timer(&port->gpio.gpio_timer); - -#endif - - INIT_LIST_HEAD(&port->gpio.msg_queue); - port->gpio.spi_gpio_irq_workqueue = create_freezeable_workqueue("spi_gpio_irq_workqueue"); - if (!port->gpio.spi_gpio_irq_workqueue) { - printk("cannot create spi_gpio_irq workqueue\n"); - return -EBUSY; - } - INIT_WORK(&port->gpio.spi_gpio_irq_work, spi_gpio_irq_work_handler); - - DBG("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port); - return 0; -} - -int spi_gpio_unregister(struct spi_fpga_port *port) -{ - return 0; -} - -#if 1 - -/************³éÏóGPIO½Ó¿Úº¯ÊýʵÏÖ²¿·Ö************************/ -static int spi_gpiolib_direction_input(struct gpio_chip *chip, unsigned offset) -{ - int pinnum = offset + chip->base -SPI_FPGA_EXPANDER_BASE; - DBG("%s:pinnum=%d\n",__FUNCTION__,pinnum); - if(pinnum < 16) - spi_gpio_int_sel(pinnum,SPI_GPIO0_IS_GPIO); - return spi_gpio_set_pindirection(pinnum, SPI_GPIO_IN); -} - -static int spi_gpiolib_direction_output(struct gpio_chip *chip, unsigned offset, int val) -{ - int pinnum = offset + chip->base -SPI_FPGA_EXPANDER_BASE; - if(pinnum < 16) - spi_gpio_int_sel(pinnum,SPI_GPIO0_IS_GPIO); - DBG("%s:pinnum=%d\n",__FUNCTION__,pinnum); - if(GPIO_HIGH == val) - spi_gpio_set_pinlevel(pinnum,SPI_GPIO_HIGH); - else - spi_gpio_set_pinlevel(pinnum,SPI_GPIO_LOW); - return spi_gpio_set_pindirection(pinnum, SPI_GPIO_OUT); -} - -static int spi_gpiolib_get_pinlevel(struct gpio_chip *chip, unsigned int offset) -{ - int pinnum = offset + chip->base -SPI_FPGA_EXPANDER_BASE; - DBG("%s:pinnum=%d\n",__FUNCTION__,pinnum); - return spi_gpio_get_pinlevel(pinnum); -} - -static void spi_gpiolib_set_pinlevel(struct gpio_chip *chip, unsigned int offset, int val) -{ - int pinnum = offset + chip->base -SPI_FPGA_EXPANDER_BASE; - DBG("%s:pinnum=%d\n",__FUNCTION__,pinnum); - if(GPIO_HIGH == val) - spi_gpio_set_pinlevel(pinnum,SPI_GPIO_HIGH); - else - spi_gpio_set_pinlevel(pinnum,SPI_GPIO_LOW); -} - -static int spi_gpiolib_pull_updown(struct gpio_chip *chip, unsigned offset, unsigned val) -{ - return 0; //FPGA do not support pull up or down -} - -static void spi_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip) -{ - //to do -} - -static int spi_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset) -{ - if(offset < CONFIG_EXPANDED_GPIO_IRQ_NUM) - return offset + NR_AIC_IRQS + CONFIG_RK28_GPIO_IRQ; - else - return -EINVAL; -} - -struct fpga_gpio_bank { - unsigned short id; //GPIO¼Ä´æÆ÷×éµÄIDʶ±ðºÅ - unsigned long offset; //GPIO0»òGPIO1µÄ»ùµØÖ· - struct clk *clock; /* associated clock */ -}; - -struct fpga_gpio_chip { - struct gpio_chip chip; - struct fpga_gpio_chip *next; /* Bank sharing same clock */ - struct fpga_gpio_bank *bank; /* Bank definition */ - void __iomem *regbase; /* Base of register bank */ -}; - -#define SPI_GPIO_CHIP_DEF(name, base_gpio, nr_gpio) \ - { \ - .chip = { \ - .label = name, \ - .direction_input = spi_gpiolib_direction_input, \ - .direction_output = spi_gpiolib_direction_output, \ - .get = spi_gpiolib_get_pinlevel, \ - .set = spi_gpiolib_set_pinlevel, \ - .pull_updown = spi_gpiolib_pull_updown, \ - .dbg_show = spi_gpiolib_dbg_show, \ - .to_irq = spi_gpiolib_to_irq, \ - .base = base_gpio, \ - .ngpio = nr_gpio, \ - }, \ - } - -static struct fpga_gpio_chip spi_gpio_chip[] = { - SPI_GPIO_CHIP_DEF("PIO0", SPI_FPGA_EXPANDER_BASE+0*NUM_GROUP*2, NUM_GROUP<<1), - SPI_GPIO_CHIP_DEF("PIO1", SPI_FPGA_EXPANDER_BASE+1*NUM_GROUP*2, NUM_GROUP<<1), - SPI_GPIO_CHIP_DEF("PIO2", SPI_FPGA_EXPANDER_BASE+2*NUM_GROUP*2, NUM_GROUP<<1), - SPI_GPIO_CHIP_DEF("PIO3", SPI_FPGA_EXPANDER_BASE+3*NUM_GROUP*2, NUM_GROUP<<1), - SPI_GPIO_CHIP_DEF("PIO4", SPI_FPGA_EXPANDER_BASE+4*NUM_GROUP*2, NUM_GROUP<<1), - SPI_GPIO_CHIP_DEF("PIO5", SPI_FPGA_EXPANDER_BASE+5*NUM_GROUP*2, NUM_GROUP<<1), -}; - - -#define ID_SPI_GPIO_IRQ_ENABLE 1 -#define ID_SPI_GPIO_IRQ_DISABLE 2 -#define ID_SPI_GPIO_IRQ_SET_TYPE 3 -#define ID_SPI_GPIO_IRQ_SET_WAKE 4 - -struct spi_gpio_irq_transfer -{ - unsigned int irq; - unsigned int type; - unsigned int state; - unsigned int id; - struct list_head queue; -}; - -static void _spi_gpio_irq_enable(unsigned irq) -{ - int gpio = irq_to_gpio(irq) - SPI_FPGA_EXPANDER_BASE; - DBG("%s:line=%d,irq=%d,gpio=%d\n",__FUNCTION__,__LINE__,irq,gpio); - if(gpio < 16) - spi_gpio_int_sel(gpio,SPI_GPIO0_IS_INT); - else - { - printk("err:%s:pin %d don't support gpio irq!\n",__FUNCTION__,gpio); - return; - } - spi_gpio_enable_int(gpio); -} - -static void _spi_gpio_irq_disable(unsigned irq) -{ - int gpio = irq_to_gpio(irq) - SPI_FPGA_EXPANDER_BASE; - DBG("%s:line=%d,irq=%d,gpio=%d\n",__FUNCTION__,__LINE__,irq,gpio); - if(gpio < 16) - spi_gpio_int_sel(gpio,SPI_GPIO0_IS_INT); - else - { - printk("err:%s:pin %d don't support gpio irq!\n",__FUNCTION__,gpio); - return; - } - spi_gpio_disable_int(gpio); - -} - -static int _spi_gpio_irq_set_type(unsigned int irq, unsigned int type) -{ - int gpio = irq_to_gpio(irq) - SPI_FPGA_EXPANDER_BASE; - int int_tri = 0, int_type = 0; - DBG("%s:line=%d,irq=%d,type=%d,gpio=%d\n",__FUNCTION__,__LINE__,irq,type,gpio); - if(gpio < 16) - spi_gpio_int_sel(gpio,SPI_GPIO0_IS_INT); - else - { - printk("err:%s:pin %d don't support gpio irq!\n",__FUNCTION__,gpio); - return -1; - } - switch(type) - { - case IRQF_TRIGGER_FALLING: - int_type = SPI_GPIO_EDGE; - int_tri = SPI_GPIO_EDGE_FALLING; - break; - case IRQF_TRIGGER_RISING: - int_type = SPI_GPIO_EDGE; - int_tri = SPI_GPIO_EDGE_RISING; - break; - case (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING): - int_type = SPI_GPIO_LEVEL; - int_tri = SPI_GPIO_EDGE_FALLING; - break; - default: - printk("err:%s:FPGA don't support this intterupt type!\n",__FUNCTION__); - break; - } - spi_gpio_set_int_type(gpio, int_type); - spi_gpio_set_int_trigger(gpio, int_tri); - return 0; -} - -static int _spi_gpio_irq_set_wake(unsigned irq, unsigned state) -{ - //unsigned int pin = irq_to_gpio(irq); - set_irq_wake(irq, state); - return 0; -} - -static void spi_gpio_irq_work_handler(struct work_struct *work) -{ - struct spi_fpga_port *port = - container_of(work, struct spi_fpga_port, gpio.spi_gpio_irq_work); - - while (1) { - struct spi_gpio_irq_transfer *t = NULL; - unsigned long flags; - unsigned int irq; - unsigned int type; - unsigned int state; - unsigned int id; - - spin_lock_irqsave(&port->work_lock, flags); - if (!list_empty(&port->gpio.msg_queue)) { - t = list_first_entry(&port->gpio.msg_queue, struct spi_gpio_irq_transfer, queue); - list_del(&t->queue); - } - spin_unlock_irqrestore(&port->work_lock, flags); - - if (!t) // msg_queue empty - break; - - irq = t->irq; - type = t->type; - state = t->state; - id = t->id; - kfree(t); - - if ((irq == 0) || (id == 0)) - continue; - printk("%s:irq=%d,type=%d,state=%d,id=%d\n",__FUNCTION__,irq,type,state,id); - switch (id) { - case ID_SPI_GPIO_IRQ_ENABLE: - _spi_gpio_irq_enable(irq); - break; - case ID_SPI_GPIO_IRQ_DISABLE: - _spi_gpio_irq_disable(irq); - break; - case ID_SPI_GPIO_IRQ_SET_TYPE: - _spi_gpio_irq_set_type(irq, type); - break; - case ID_SPI_GPIO_IRQ_SET_WAKE: - _spi_gpio_irq_set_wake(irq, state); - break; - default: - break; - } - } -} - - -static void spi_gpio_irq_enable(unsigned irq) -{ - struct spi_fpga_port *port = pFpgaPort; - struct spi_gpio_irq_transfer *t; - unsigned long flags; - t = kzalloc(sizeof(struct spi_gpio_irq_transfer), GFP_ATOMIC); - if (!t) - { - printk("err:%s:ENOMEM\n",__FUNCTION__); - return ; - } - t->irq = irq; - t->id = ID_SPI_GPIO_IRQ_ENABLE; - - spin_lock_irqsave(&port->work_lock, flags); - list_add_tail(&t->queue, &port->gpio.msg_queue); - spin_unlock_irqrestore(&port->work_lock, flags); - - queue_work(port->gpio.spi_gpio_irq_workqueue, &port->gpio.spi_gpio_irq_work); -} - -static void spi_gpio_irq_disable(unsigned irq) -{ - struct spi_fpga_port *port = pFpgaPort; - struct spi_gpio_irq_transfer *t; - unsigned long flags; - t = kzalloc(sizeof(struct spi_gpio_irq_transfer), GFP_ATOMIC); - if (!t) - { - printk("err:%s:ENOMEM\n",__FUNCTION__); - return ; - } - t->irq = irq; - t->id = ID_SPI_GPIO_IRQ_DISABLE; - - spin_lock_irqsave(&port->work_lock, flags); - list_add_tail(&t->queue, &port->gpio.msg_queue); - spin_unlock_irqrestore(&port->work_lock, flags); - - queue_work(port->gpio.spi_gpio_irq_workqueue, &port->gpio.spi_gpio_irq_work); -} - -static void spi_gpio_irq_mask(unsigned int irq) -{ - //FPGA do not support irq mask -} - -static void spi_gpio_irq_unmask(unsigned int irq) -{ - //FPGA do not support irq unmask -} - -static int spi_gpio_irq_set_type(unsigned int irq, unsigned int type) -{ - struct spi_fpga_port *port = pFpgaPort; - struct spi_gpio_irq_transfer *t; - unsigned long flags; - t = kzalloc(sizeof(struct spi_gpio_irq_transfer), GFP_ATOMIC); - if (!t) - { - printk("err:%s:ENOMEM\n",__FUNCTION__); - return -ENOMEM; - } - t->irq = irq; - t->id = ID_SPI_GPIO_IRQ_SET_TYPE; - t->type = type; - - spin_lock_irqsave(&port->work_lock, flags); - list_add_tail(&t->queue, &port->gpio.msg_queue); - spin_unlock_irqrestore(&port->work_lock, flags); - - queue_work(port->gpio.spi_gpio_irq_workqueue, &port->gpio.spi_gpio_irq_work); - - return 0; -} - -static int spi_gpio_irq_set_wake(unsigned irq, unsigned state) -{ - struct spi_fpga_port *port = pFpgaPort; - struct spi_gpio_irq_transfer *t; - unsigned long flags; - t = kzalloc(sizeof(struct spi_gpio_irq_transfer), GFP_KERNEL); - if (!t) - { - printk("err:%s:ENOMEM\n",__FUNCTION__); - return -ENOMEM; - } - t->irq = irq; - t->id = ID_SPI_GPIO_IRQ_SET_WAKE; - t->state = state; - - spin_lock_irqsave(&port->work_lock, flags); - list_add_tail(&t->queue, &port->gpio.msg_queue); - spin_unlock_irqrestore(&port->work_lock, flags); - - queue_work(port->gpio.spi_gpio_irq_workqueue, &port->gpio.spi_gpio_irq_work); - - return 0; -} - - -static struct irq_chip spi_gpio_irq_chip = { - .name = "SPI_GPIO_IRQ", - .enable = spi_gpio_irq_enable, - .disable = spi_gpio_irq_disable, - .mask = spi_gpio_irq_mask, - .unmask = spi_gpio_irq_unmask, - .set_type = spi_gpio_irq_set_type, - .set_wake = spi_gpio_irq_set_wake, -}; - -void spi_gpio_test_gpio_irq_init(void) -{ -#if SPI_GPIO_TEST - struct spi_fpga_port *port = pFpgaPort; - int i,gpio,ret,irq; - - for(i=0;i<81;i++) - { - gpio = SPI_FPGA_EXPANDER_BASE+i; - ret = gpio_request(gpio, NULL); - if (ret) { - printk("%s:failed to request GPIO[%d]\n",__FUNCTION__,gpio); - } - } - - for(i=0;i<4;i++) - { - gpio = SPI_FPGA_EXPANDER_BASE+i; - irq = gpio_to_irq(gpio); - printk("%s:line=%d,irq=%d,gpio=%d\n",__FUNCTION__,__LINE__,irq,gpio); - switch(i) - { - case 0: - ret = request_irq(irq ,spi_gpio_int_test_0,IRQF_TRIGGER_FALLING,NULL,port); - if(ret) - { - printk("%s:unable to request GPIO[%d] irq\n",__FUNCTION__,gpio); - gpio_free(gpio); - } - break; - - case 1: - ret = request_irq(irq ,spi_gpio_int_test_1,IRQF_TRIGGER_FALLING,NULL,port); - if(ret) - { - printk("%s:unable to request GPIO[%d] irq\n",__FUNCTION__,gpio); - gpio_free(gpio); - } - break; - - case 2: - ret = request_irq(irq ,spi_gpio_int_test_2,IRQF_TRIGGER_FALLING,NULL,port); - if(ret) - { - printk("%s:unable to request GPIO[%d] irq\n",__FUNCTION__,gpio); - gpio_free(gpio); - } - break; - - case 3: - ret = request_irq(irq ,spi_gpio_int_test_3,(IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING),NULL,port); - if(ret) - { - printk("%s:unable to request GPIO[%d] irq\n",__FUNCTION__,gpio); - gpio_free(gpio); - } - break; - - default: - break; - } - - } - -#endif - -} - -static int spi_gpio_banks; -static struct lock_class_key gpio_lock_class; - -/* - * Called from the processor-specific init to enable GPIO interrupt support. - */ -void spi_gpio_irq_setup(void) -{ - unsigned int j, pin; - struct fpga_gpio_chip *this; - - this = spi_gpio_chip; - pin = NR_AIC_IRQS + CONFIG_RK28_GPIO_IRQ; - - for (j = 0; j < 16; j++) - { - lockdep_set_class(&irq_desc[pin+j].lock, &gpio_lock_class); - /* - * Can use the "simple" and not "edge" handler since it's - * shorter, and the AIC handles interrupts sanely. - */ - set_irq_chip(pin+j, &spi_gpio_irq_chip); - //set_irq_handler(pin+j, handle_simple_irq); - set_irq_flags(pin+j, IRQF_VALID); - } - - printk("%s: %d gpio irqs in %d banks\n", __FUNCTION__, pin+j-SPI_FPGA_EXPANDER_BASE, spi_gpio_banks); - - spi_gpio_test_gpio_irq_init(); - -} - - -int spi_gpio_init(void) -{ - unsigned i; - struct fpga_gpio_chip *fpga_gpio_chip; - spi_gpio_banks = 6; - spi_gpio_init_first(); - for (i = 0; i < 6; i++) - { - fpga_gpio_chip = &spi_gpio_chip[i]; - gpiochip_add(&fpga_gpio_chip->chip); - } - - spi_gpio_irq_setup(); - - return 0; -} - -#endif - -MODULE_DESCRIPTION("Driver for spi2gpio."); -MODULE_AUTHOR("luowei "); -MODULE_LICENSE("GPL"); diff --git a/drivers/fpga/spi_i2c.c b/drivers/fpga/spi_i2c.c deleted file mode 100755 index dca43e1233d9..000000000000 --- a/drivers/fpga/spi_i2c.c +++ /dev/null @@ -1,529 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#if defined(CONFIG_SPI_I2C_DEBUG) -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -#define MAXMSGLEN 8 -#define I2C_COUNT 20 -#define DRV_NAME "spi_i2c" -#define SPI_I2C_TEST 0 - -#if SPI_I2C_TEST -struct i2c_adapter *adap; -#endif -int spi_i2c_handle_irq(struct spi_fpga_port *port,unsigned char channel) -{ - int reg; - int ret; - - if(channel == I2C_CH2) - reg = ICE_SEL_I2C_INT|ICE_SEL_I2C_CH2; - else - reg = ICE_SEL_I2C_INT|ICE_SEL_I2C_CH3; - - port->i2c.interrupt = 0; - ret = spi_in(port,reg,SEL_I2C); - DBG("Enter::%s,LINE=%d ret = [%d]\n",__FUNCTION__,__LINE__,ret); - if(INT_I2C_READ_ACK == (ret & 0x07)) - { - port->i2c.interrupt = INT_I2C_READ_ACK; - wake_up(&port->i2c.wait_r); - } - else if(INT_I2C_READ_NACK ==(ret & 0x07)) - { - port->i2c.interrupt = INT_I2C_READ_NACK; - wake_up(&port->i2c.wait_r); - printk("err:read no ack!ch=%d\n",channel); - } - else if(INT_I2C_WRITE_ACK == (ret & 0x07)) - { - port->i2c.interrupt = INT_I2C_WRITE_ACK; - wake_up(&port->i2c.wait_w); - } - else if(INT_I2C_WRITE_NACK == (ret & 0x07)) - { - port->i2c.interrupt = INT_I2C_WRITE_NACK; - wake_up(&port->i2c.wait_w); - printk("err:write no ack!ch=%d\n",channel); - } - else - printk("err:fpga's ack value error!\n"); - return port->i2c.interrupt; -} - -int spi_i2c_select_speed(int speed) -{ - int result = 0; - switch(speed) - { - case 10*1000: - result = ICE_SET_10K_I2C_SPEED; - break; - case 100*1000: - result = ICE_SET_100K_I2C_SPEED; - break; - case 200*1000: - result = ICE_SET_200K_I2C_SPEED; - break; - case 300*1000: - result = ICE_SET_300K_I2C_SPEED; - break; - case 400*1000: - result = ICE_SET_400K_I2C_SPEED; - break; - default: - result = ICE_SET_100K_I2C_SPEED; /* ddl@rock-chips.com : default set 100KHz */ - break; - } - return result; -} - -int spi_i2c_readbuf(struct spi_fpga_port *port ,struct i2c_msg *pmsg,int ch) -{ - - unsigned int reg ; - unsigned int len,i,j; - unsigned int slaveaddr; - unsigned int speed; - unsigned int channel = 0 ; - unsigned int result; - int ret = 0; - - slaveaddr = pmsg->addr<<1; - len = pmsg->len; - speed = spi_i2c_select_speed(pmsg->scl_rate); - - if(ch == I2C_CH2) - channel = ICE_SEL_I2C_CH2; - else if(ch == I2C_CH3) - channel = ICE_SEL_I2C_CH3; - else - { - printk("Error:try to read form error i2c channel\n"); - return 0; - } - - DBG("len = %d chan = %d read=%d\n",pmsg->len,ch,pmsg->read_type); - - - slaveaddr = slaveaddr|ICE_I2C_SLAVE_READ; - if(pmsg->read_type == I2C_NORMAL || pmsg->read_type == I2C_NO_STOP) - reg = channel |ICE_SEL_I2C_RESTART; - else if(pmsg->read_type == I2C_NO_REG ) - reg = channel |ICE_SEL_I2C_START; - spi_out(port,reg,slaveaddr,SEL_I2C); - //speed; - reg = channel |ICE_SEL_I2C_SPEED|ICE_SEL_I2C_TRANS; - spi_out(port,reg,speed,SEL_I2C); - //len; - reg = channel |ICE_SEL_I2C_FIFO |ICE_SEL_I2C_STOP; - spi_out(port,reg,len,SEL_I2C); - - ret = wait_event_timeout(port->i2c.wait_r, ((port->i2c.interrupt == INT_I2C_READ_ACK) || (port->i2c.interrupt == INT_I2C_READ_NACK)), msecs_to_jiffies(60)); - if(ret == 0) - { - printk("%s:60ms time out!\n",__FUNCTION__); - return -1; - } - for(i = 0;ibuf[i] = 0; - pmsg->buf[i] = result & 0xff ; - DBG("r_buf[%d]=0x%x\n",i,pmsg->buf[i]); - } - spin_lock(&port->i2c.i2c_lock); - port->i2c.interrupt &= INT_I2C_READ_MASK; - spin_unlock(&port->i2c.i2c_lock); - ret = pmsg->len; - //for(i = 0;ibuf[%d] = 0x%x \n",i,pmsg->buf[i]); - return ret>0 ? ret:-1; - -} - -int spi_i2c_writebuf(struct spi_fpga_port *port ,struct i2c_msg *pmsg,int ch) -{ - - unsigned int reg ; - unsigned int len,i,j; - unsigned int slaveaddr; - unsigned int speed; - unsigned int channel = 0; - int ret = 0; - - slaveaddr = pmsg->addr; - len = pmsg->len; - speed = spi_i2c_select_speed(pmsg->scl_rate); - - if(ch == I2C_CH2) - channel = ICE_SEL_I2C_CH2; - else if(ch == I2C_CH3) - channel = ICE_SEL_I2C_CH3; - else - { - printk("Error: try to write the error i2c channel\n"); - return 0; - } - DBG("len = %d chan = %d read=%d\n",pmsg->len,ch,pmsg->read_type); - - //slaveaddr ; - slaveaddr = slaveaddr<<1; - reg = channel |ICE_SEL_I2C_START; - spi_out(port,reg,slaveaddr,SEL_I2C); - //speed; - reg = channel |ICE_SEL_I2C_SPEED|ICE_SEL_I2C_TRANS; - spi_out(port,reg,speed,SEL_I2C); - //len; - reg = channel |ICE_SEL_I2C_FIFO |ICE_SEL_I2C_TRANS; - spi_out(port,reg,len,SEL_I2C); - reg = channel |ICE_SEL_I2C_TRANS; - //data; - for(i = 0 ;i < len;i++) - { - DBG("w_buf[%d]=0x%x\n",i,pmsg->buf[i]); - if(i==len-1 && pmsg->read_type == I2C_NORMAL) - { - reg = channel|ICE_SEL_I2C_STOP; - spi_out(port,reg,pmsg->buf[i],SEL_I2C); - ret = wait_event_timeout(port->i2c.wait_w, ((port->i2c.interrupt == INT_I2C_WRITE_ACK) || (port->i2c.interrupt == INT_I2C_WRITE_NACK)), msecs_to_jiffies(60)); - if(ret == 0) - { - printk("%s:60ms time out!\n",__FUNCTION__); - continue; - } - spin_lock(&port->i2c.i2c_lock); - port->i2c.interrupt &= INT_I2C_WRITE_MASK; - spin_unlock(&port->i2c.i2c_lock); - ret = pmsg->len; - } - else if(i==len-1 && pmsg->read_type == I2C_NO_STOP) - { - spi_out(port,reg,pmsg->buf[i],SEL_I2C); - ret = pmsg->len; - } - else - { - spi_out(port,reg,pmsg->buf[i],SEL_I2C); - } - } - - - return ret>0? ret:-1; - - -} - -static int spi_xfer_msg(struct i2c_adapter *adapter, - struct i2c_msg *msg,int stop) -{ - int ret; - struct spi_i2c_data *i2c = (struct spi_i2c_data *)adapter->algo_data; - struct spi_fpga_port *port = (struct spi_fpga_port *) i2c->port; - //printk("%s:line=%d,channel = %d port= 0x%x\n",__FUNCTION__,__LINE__,adapter->nr,port); - - if(msg->len >MAXMSGLEN) - return EFBIG; - if(msg->flags & I2C_M_RD) - ret = spi_i2c_readbuf(port,msg,adapter->nr); - - else - ret = spi_i2c_writebuf(port,msg,adapter->nr); - return ret; -} - -int spi_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) -{ - - int i; - int ret; - struct spi_i2c_data *i2c = (struct spi_i2c_data *)adapter->algo_data; - - if(adapter->nr != I2C_CH2 && adapter->nr != I2C_CH3) - return -EPERM; - - //i2c->msg_num = num; - - for(i = 0;imsg_idx = i; - ret = spi_xfer_msg(adapter,&msgs[i],(i == (num - 1))); - if(ret <= 0) - { - num = ret; - printk("spi_xfer_msg error .ret = %d\n",ret); - break; - } - } - return num; -} - - -static unsigned int spi_i2c_func(struct i2c_adapter *adapter) -{ - return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL); -} - -static const struct i2c_algorithm spi_i2c_algorithm = { - .master_xfer = spi_i2c_xfer, - .functionality = spi_i2c_func, -}; - -#if SPI_I2C_TEST -unsigned short rda5400[][2] = -{ -{0x3f,0x0000},//page 0 -{0x0B,0x3200},// pll_cal_eachtime -{0x0E,0x5200},// rxfilter_op_cal_bit_dr rxfilter_sys_cal_bit_dr -{0x13,0x016D},// fts_cap=01, for high nak rate at high temperature¡£ -{0x16,0x9C23},// Load8.5pf crystal,2.2pf cap -{0x17,0xBB12},// xtal_cpuclk_en,* -{0x19,0xEE18},// rxfilter_bp_mode rxfilter_tuning_cap_for die -{0x1A,0x59EE},// rmx_lo_reg=1011, tmx_iqswap -{0x1C,0x008F},// -{0x30,0x002B},// -{0x3B,0x33EA},// rxfilter_imgrej_lo -{0x3E,0x0040},// tmx_lo_reg set to1 -{0x3f,0x0001},//page 1 -{0x02,0x0001},// rxfilter_sys_cal_polarity -{0x04,0xE41E},// ldo_ictrl<5bit> set to 1 -{0x05,0xBC00},// ldo_ictrl<5bit> set to 1 -{0x06,0x262D},// -{0x0B,0x001F},// vco_bit=111 -{0x10,0x0100},// thermo power setting -{0x13,0x001C},// pre_sca=1100 -{0x19,0x001C},// lo_buff=1100, improve RF per formance at high temp -{0x1a,0x1404}, -{0x1E,0x2A48},// resetn_ex_selfgen_enable=0, for 32K is no need when poweron -{0x27,0x0070},// power table setting, maxpower -{0x26,0x3254},// power table setting -{0x25,0x2180},// power table settings -{0x24,0x0000},// power table setting -{0x23,0x0000},// power table setting -{0x22,0x0000},// power table setting -{0x21,0x0000},// power table setting -{0x20,0x0000},// power table setting -{0x37,0x0600},// padrv_cal_bypass -{0x3A,0x06E0},// dcdc setting -{0x3f,0x0000},//page 0 -}; - -int spi_i2c_16bit_test(struct spi_fpga_port *port) -{ - u8 i2c_buf[8]; - int len = 2; - int i ; - struct i2c_adapter *adapter = adap; - struct i2c_msg msg[1] = - { - {0x16,0,len+2,i2c_buf,200*1000,0,0} - }; - - for(i = 0;i < (sizeof(rda5400)/sizeof(rda5400[0]));i++) - { - i2c_buf[0] = 0x22; - i2c_buf[1] = rda5400[i][0]; - i2c_buf[2] = rda5400[i][1]>>8; - i2c_buf[3] = rda5400[i][1]&0xFF; - printk("i = %d\n",i); - spi_i2c_writebuf(port, msg,3); - msg[0].len = 2; - - spi_i2c_readbuf(port, msg,3); - if(msg->buf[0] != i2c_buf[2] ||msg->buf[1] != i2c_buf[3] ) - printk("i=%d,msg[0]=%d,msg[1]=%d\n",i,msg->buf[0],msg->buf[1]); - } - return 0; - -} - -int spi_i2c_8bit_test(struct spi_fpga_port *port) -{ - u8 i2c_buf[8]; - int len = 2; - int i ; - struct i2c_adapter *adapter = adap; - struct i2c_msg msg[1] = - { - {0x16,0,len+1,i2c_buf,200*1000,0,0} - }; - struct i2c_msg msgs[2] = - { - {0x16,0,1,i2c_buf,200*1000,2,0}, - {0x16,1,2,i2c_buf,200*1000,2,0}, - }; - for(i = 0;i < (sizeof(rda5400)/sizeof(rda5400[0]));i++) - { - printk("i=%d\n",i); - msg[0].len = 3; - i2c_buf[0] = rda5400[i][0]; - i2c_buf[1] = rda5400[i][1]>>8; - i2c_buf[2] = rda5400[i][1]&0xFF; - //spi_i2c_writebuf(port, msg,3); - spi_i2c_xfer(adapter,msg,1); - - - i2c_buf[1] = 0; - i2c_buf[2] = 0; - spi_i2c_xfer(adapter,msgs,2); - //spi_i2c_readbuf(port, msg,3); - if(msg->buf[0] != (rda5400[i][1]>>8) ||msg->buf[1] != (rda5400[i][1]&0xff) ) - printk("i=%d,msg[0]=0x%x,msg[1]=0x%x\n",i,msg->buf[0],msg->buf[1]); - } - return 0; - -} - -int spi_i2c_test(void) -{ - struct spi_fpga_port *port = pFpgaPort; - spi_i2c_8bit_test(port); - return 0; -} -void spi_i2c_work_handler(struct work_struct *work) -{ - struct spi_fpga_port *port = - container_of(work, struct spi_fpga_port, i2c.spi_i2c_work); - - printk("*************test spi_i2c now***************\n"); - spi_i2c_8bit_test(port); - -} - -static void spi_testi2c_timer(unsigned long data) -{ - struct spi_fpga_port *port = (struct spi_fpga_port *)data; - port->i2c.i2c_timer.expires = jiffies + msecs_to_jiffies(2000); - add_timer(&port->i2c.i2c_timer); - queue_work(port->i2c.spi_i2c_workqueue, &port->i2c.spi_i2c_work); -} -#define BT_RST_PIN SPI_GPIO_P1_07 -#define BT_PWR_PIN SPI_GPIO_P1_06 -int spi_i2c_set_bt_power(void) -{ -#if 0 - - spi_gpio_set_pinlevel(BT_RST_PIN, SPI_GPIO_HIGH); - spi_gpio_set_pindirection(BT_RST_PIN, SPI_GPIO_OUT); - spi_gpio_set_pinlevel(BT_PWR_PIN, SPI_GPIO_HIGH); - spi_gpio_set_pindirection(BT_PWR_PIN, SPI_GPIO_OUT); - -#else - spi_gpio_set_pinlevel(BT_PWR_PIN, SPI_GPIO_LOW); - spi_gpio_set_pindirection(BT_PWR_PIN, SPI_GPIO_OUT); - mdelay(2); - spi_gpio_set_pinlevel(BT_PWR_PIN, SPI_GPIO_HIGH); - spi_gpio_set_pindirection(BT_PWR_PIN, SPI_GPIO_OUT); - - mdelay(2); - spi_gpio_set_pinlevel(BT_RST_PIN, SPI_GPIO_LOW); - spi_gpio_set_pindirection(BT_RST_PIN, SPI_GPIO_OUT); - mdelay(20); - /*µÈ´ý10msÒÔÉÏ£¬µÈ´ý26M XTALÎȶ¨£¬È»ºóÀ­¸ßRESETN*/ - spi_gpio_set_pinlevel(BT_RST_PIN, SPI_GPIO_HIGH); -#endif - return 0; -} -#endif - - -int spi_i2c_register(struct spi_fpga_port *port,int num) -{ - int ret; - struct spi_i2c_data *i2c; - //struct i2c_adapter *adapter; - DBG("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port); - i2c = kzalloc(sizeof(struct spi_i2c_data),GFP_KERNEL); - if(i2c == NULL) - { - printk("%s:no memory for state \n",__FUNCTION__); - return -ENOMEM; - } - i2c->port = port; - strlcpy(i2c->adapter.name,DRV_NAME,sizeof(i2c->adapter.name)); - i2c->adapter.owner = THIS_MODULE; - i2c->adapter.algo = &spi_i2c_algorithm; - i2c->adapter.class = I2C_CLASS_HWMON; - //lock - i2c->adapter.nr = num; - i2c->adapter.algo_data = i2c; - ret = i2c_add_numbered_adapter(&i2c->adapter); - if(ret) - { - printk(KERN_INFO "SPI2I2C: Failed to add bus\n"); - kfree(i2c); - - return ret; - } - -#if SPI_I2C_TEST - char b[20]; - if(num != 3) - return 0; - sprintf(b, "spi_i2c_workqueue"); - DBG("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port); - adap = &i2c->adapter; - port->i2c.spi_i2c_workqueue = create_freezeable_workqueue(b); - if (!port->i2c.spi_i2c_workqueue) { - printk("cannot create workqueue\n"); - return -EBUSY; - } - - INIT_WORK(&port->i2c.spi_i2c_work, spi_i2c_work_handler); - - setup_timer(&port->i2c.i2c_timer, spi_testi2c_timer, (unsigned long)port); - port->i2c.i2c_timer.expires = jiffies+2000;//>1000ms - add_timer(&port->i2c.i2c_timer); - printk("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port); - -#endif - - init_waitqueue_head(&port->i2c.wait_w); - init_waitqueue_head(&port->i2c.wait_r); - - return 0; - -} - -int spi_i2c_unregister(struct spi_fpga_port *port) -{ - return 0; -} - -MODULE_DESCRIPTION("Driver for spi2i2c."); -MODULE_AUTHOR("swj "); -MODULE_LICENSE("GPL"); - - diff --git a/drivers/fpga/spi_uart.c b/drivers/fpga/spi_uart.c deleted file mode 100755 index 38b0dd05682d..000000000000 --- a/drivers/fpga/spi_uart.c +++ /dev/null @@ -1,1316 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#if defined(CONFIG_SPI_UART_DEBUG) -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -#define SPI_UART_TEST 0 -int gBaud = 0; -#define SPI_UART_FIFO_LEN 32 -#define SPI_UART_TXRX_BUF 1 //send or recieve several bytes one time - -static struct tty_driver *spi_uart_tty_driver; -/*------------------------ÒÔÏÂÊÇspi2uart±äÁ¿-----------------------*/ - -#define UART_NR 1 /* Number of UARTs this driver can handle */ - -#define UART_XMIT_SIZE PAGE_SIZE -#define WAKEUP_CHARS 1024 - -#define circ_empty(circ) ((circ)->head == (circ)->tail) -#define circ_clear(circ) ((circ)->head = (circ)->tail = 0) - -#define circ_chars_pending(circ) \ - (CIRC_CNT((circ)->head, (circ)->tail, UART_XMIT_SIZE)) - -#define circ_chars_free(circ) \ - (CIRC_SPACE((circ)->head, (circ)->tail, UART_XMIT_SIZE)) - - - - -static struct spi_uart *spi_uart_table[UART_NR]; -static DEFINE_SPINLOCK(spi_uart_table_lock); - -#if SPI_UART_TXRX_BUF -static int spi_uart_write_buf(struct spi_uart *uart, unsigned char *buf, int len) -{ - struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart); - int index = port->uart.index; - int reg = 0, stat = 0; - int i; - unsigned char tx_buf[SPI_UART_FIFO_LEN+2]; - - memcpy(tx_buf + 2, buf, len); - reg = ((((reg) | ICE_SEL_UART) & ICE_SEL_WRITE) | ICE_SEL_UART_CH(index)); - tx_buf[0] = reg & 0xff; - tx_buf[1] = 0; - - stat = spi_write(port->spi, tx_buf, len+2); - if(stat) - printk("%s:spi_write err!!!\n\n\n",__FUNCTION__); - DBG("%s:reg=0x%x,buf=0x%x,len=0x%x\n",__FUNCTION__,reg&0xff,(int)tx_buf,len); - return 0; -} - - -static int spi_uart_read_buf(struct spi_uart *uart, unsigned char *buf, int len) -{ - struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart); - int index = port->uart.index; - int reg = 0,stat = 0; - unsigned char tx_buf[2],rx_buf[SPI_UART_FIFO_LEN+1]; - - reg = (((reg) | ICE_SEL_UART) | ICE_SEL_READ | ICE_SEL_UART_CH(index)); - tx_buf[0] = reg & 0xff; - tx_buf[1] = len; - //give fpga 8 clks for reading data - stat = spi_write_then_read(port->spi, tx_buf, sizeof(tx_buf), rx_buf, len+1); - if(stat) - { - printk("%s:spi_write_then_read is error!,err=%d\n\n",__FUNCTION__,stat); - return -1; - } - - memcpy(buf, rx_buf+1, len); - DBG("%s:reg=0x%x,buf=0x%x,len=0x%x\n",__FUNCTION__,reg&0xff,(int)buf,len); - return stat; -} - -#endif - -static int spi_uart_add_port(struct spi_uart *uart) -{ - int index, ret = -EBUSY; - - kref_init(&uart->kref); - mutex_init(&uart->open_lock); - spin_lock_init(&uart->write_lock); - spin_lock_init(&uart->irq_lock); - - spin_lock(&spi_uart_table_lock); - for (index = 0; index < UART_NR; index++) - { - if (!spi_uart_table[index]) { - uart->index = index; - //printk("index=%d\n\n",index); - spi_uart_table[index] = uart; - ret = 0; - break; - } - } - spin_unlock(&spi_uart_table_lock); - - return ret; -} - -static struct spi_uart *spi_uart_port_get(unsigned index) -{ - struct spi_uart *uart; - - if (index >= UART_NR) - return NULL; - - spin_lock(&spi_uart_table_lock); - uart = spi_uart_table[index]; - uart->index = index; - printk("uart->index=%d\n",uart->index); - if (uart) - kref_get(&uart->kref); - spin_unlock(&spi_uart_table_lock); - - return uart; -} - -static void spi_uart_port_destroy(struct kref *kref) -{ - struct spi_uart *uart = - container_of(kref, struct spi_uart, kref); - kfree(uart); -} - -static void spi_uart_port_put(struct spi_uart *uart) -{ - kref_put(&uart->kref, spi_uart_port_destroy); -} - -static void spi_uart_port_remove(struct spi_uart *uart) -{ - struct spi_device *spi; - struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart); - - BUG_ON(spi_uart_table[uart->index] != uart); - - spin_lock(&spi_uart_table_lock); - spi_uart_table[uart->index] = NULL; - spin_unlock(&spi_uart_table_lock); - - /* - * We're killing a port that potentially still is in use by - * the tty layer. Be careful to arrange for the tty layer to - * give up on that port ASAP. - * Beware: the lock ordering is critical. - */ - mutex_lock(&uart->open_lock); - mutex_lock(&port->spi_lock); - spi = port->spi; - - port->spi = NULL; - mutex_unlock(&port->spi_lock); - if (uart->opened) - tty_hangup(uart->tty); - mutex_unlock(&uart->open_lock); - - spi_uart_port_put(uart); -} - -static unsigned int spi_uart_get_mctrl(struct spi_uart *uart) -{ - unsigned char status; - unsigned int ret; - struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart); - - status = spi_in(port, UART_MSR, SEL_UART);// - ret = 0; -#if 0 - if (status & UART_MSR_DCD) - ret |= TIOCM_CAR; - if (status & UART_MSR_RI) - ret |= TIOCM_RNG; - if (status & UART_MSR_DSR) - ret |= TIOCM_DSR; - if (status & UART_MSR_CTS) - ret |= TIOCM_CTS; -#endif - if (status & UART_MSR_CTS) - ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; - DBG("%s:LINE=%d,ret=0x%x\n",__FUNCTION__,__LINE__,ret); - return ret; -} - -static void spi_uart_write_mctrl(struct spi_uart *uart, unsigned int mctrl) -{ - unsigned char mcr = 0; - struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart); -#if 1 - if (mctrl & TIOCM_RTS) - { - mcr |= UART_MCR_RTS; - mcr |= UART_MCR_AFE; - } - //if (mctrl & TIOCM_DTR) - // mcr |= UART_MCR_DTR; - //if (mctrl & TIOCM_OUT1) - // mcr |= UART_MCR_OUT1; - //if (mctrl & TIOCM_OUT2) - // mcr |= UART_MCR_OUT2; - //if (mctrl & TIOCM_LOOP) - // mcr |= UART_MCR_LOOP; - -#endif - - DBG("%s:LINE=%d,mcr=0x%x\n",__FUNCTION__,__LINE__,mcr); - spi_out(port, UART_MCR, mcr, SEL_UART); -} - -static inline void spi_uart_update_mctrl(struct spi_uart *uart, - unsigned int set, unsigned int clear) -{ - unsigned int old; - DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__); - old = uart->mctrl; - uart->mctrl = (old & ~clear) | set; - if (old != uart->mctrl) - spi_uart_write_mctrl(uart, uart->mctrl); -} - -#define spi_uart_set_mctrl(uart, x) spi_uart_update_mctrl(uart, x, 0) -#define spi_uart_clear_mctrl(uart, x) spi_uart_update_mctrl(uart, 0, x) - -static void spi_uart_change_speed(struct spi_uart *uart, - struct ktermios *termios, - struct ktermios *old) -{ - unsigned char cval, fcr = 0; - unsigned int baud, quot; - struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart); - - switch (termios->c_cflag & CSIZE) { - case CS5: - cval = UART_LCR_WLEN5; - break; - case CS6: - cval = UART_LCR_WLEN6; - break; - case CS7: - cval = UART_LCR_WLEN7; - break; - default: - case CS8: - cval = UART_LCR_WLEN8; - break; - } - - if (termios->c_cflag & CSTOPB) - cval |= UART_LCR_STOP; - if (termios->c_cflag & PARENB) - cval |= UART_LCR_PARITY; - if (!(termios->c_cflag & PARODD)) - cval |= UART_LCR_EPAR; - - for (;;) { - baud = tty_termios_baud_rate(termios); - if (baud == 0) - baud = 115200; /* Special case: B0 rate. */ - if (baud <= uart->uartclk) - break; - /* - * Oops, the quotient was zero. Try again with the old - * baud rate if possible, otherwise default to 115200. - */ - termios->c_cflag &= ~CBAUD; - if (old) { - termios->c_cflag |= old->c_cflag & CBAUD; - old = NULL; - } else - termios->c_cflag |= B115200; - } - //quot = (2 * uart->uartclk + baud) / (2 * baud); - quot = (uart->uartclk / baud); - //gBaud = baud; - printk("baud=%d,quot=0x%x\n",baud,quot); - if (baud < 2400) - fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1; - else - fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10; - - uart->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; - if (termios->c_iflag & INPCK) - uart->read_status_mask |= UART_LSR_FE | UART_LSR_PE; - if (termios->c_iflag & (BRKINT | PARMRK)) - uart->read_status_mask |= UART_LSR_BI; - - /* - * Characters to ignore - */ - uart->ignore_status_mask = 0; - if (termios->c_iflag & IGNPAR) - uart->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; - if (termios->c_iflag & IGNBRK) { - uart->ignore_status_mask |= UART_LSR_BI; - /* - * If we're ignoring parity and break indicators, - * ignore overruns too (for real raw support). - */ - if (termios->c_iflag & IGNPAR) - uart->ignore_status_mask |= UART_LSR_OE; - } - - /* - * ignore all characters if CREAD is not set - */ - if ((termios->c_cflag & CREAD) == 0) - uart->ignore_status_mask |= UART_LSR_DR; - - /* - * CTS flow control flag and modem status interrupts - */ - uart->ier &= ~UART_IER_MSI; - if ((termios->c_cflag & CRTSCTS) || !(termios->c_cflag & CLOCAL)) - uart->ier |= UART_IER_MSI; - - uart->lcr = cval; - - spi_out(port, UART_LCR, cval | UART_LCR_DLAB, SEL_UART); - spi_out(port, UART_DLL, quot & 0xff, SEL_UART); - spi_out(port, UART_DLM, quot >> 8, SEL_UART); - spi_out(port, UART_LCR, cval, SEL_UART); - spi_out(port, UART_FCR, fcr, SEL_UART); - spi_out(port, UART_IER, uart->ier, SEL_UART);//slow - - DBG("%s:LINE=%d,baud=%d,uart->ier=0x%x,cval=0x%x,fcr=0x%x,quot=0x%x\n", - __FUNCTION__,__LINE__,baud,uart->ier,cval,fcr,quot); - spi_uart_write_mctrl(uart, uart->mctrl); -} - -static void spi_uart_start_tx(struct spi_uart *uart) -{ - struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart); - if (!(uart->ier & UART_IER_THRI)) { - uart->ier |= UART_IER_THRI; - spi_out(port, UART_IER, uart->ier, SEL_UART); - DBG("t,"); - } - - DBG("%s:UART_IER=0x%x\n",__FUNCTION__,uart->ier); - -} - -static void spi_uart_stop_tx(struct spi_uart *uart) -{ - struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart); - if (uart->ier & UART_IER_THRI) { - uart->ier &= ~UART_IER_THRI; - spi_out(port, UART_IER, uart->ier, SEL_UART); - } - DBG("%s:UART_IER=0x%x\n",__FUNCTION__,uart->ier); -} - -static void spi_uart_stop_rx(struct spi_uart *uart) -{ - struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart); - uart->ier &= ~UART_IER_RLSI; - uart->read_status_mask &= ~UART_LSR_DR; - spi_out(port, UART_IER, uart->ier, SEL_UART); -} - -static void spi_uart_receive_chars(struct spi_uart *uart, unsigned int *status) -{ - struct tty_struct *tty = uart->tty; - struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart); - unsigned char ch, flag; - int max_count = 1024; - DBG("rx:"); -#if SPI_UART_TXRX_BUF - int ret,count,stat = *status; - int i = 0; - unsigned char buf[SPI_UART_FIFO_LEN]; - while (stat & UART_LSR_DR) - { - ret = spi_in(port, UART_RX, SEL_UART); - count = (ret >> 8) & 0x3f; - DBG("%s:count=%d\n",__FUNCTION__,count); - if(count == 0) - break; - buf[0] = ret & 0xff; - if(count > 1) - { - stat = spi_uart_read_buf(uart,buf+1,count-1); - if(stat) - printk("err:%s:stat=%d,fail to read uart data because of spi bus error!\n",__FUNCTION__,stat); - } - max_count -= count; - flag = TTY_NORMAL; - uart->icount.rx += count; - for(i=0;i0 ) - { - ch = spi_in(port, UART_RX, SEL_UART);// - DBG("0x%x,",ch&0xff); - flag = TTY_NORMAL; - uart->icount.rx++; - //--max_count; - if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | - UART_LSR_FE | UART_LSR_OE))) { - /* - * For statistics only - */ - if (*status & UART_LSR_BI) { - *status &= ~(UART_LSR_FE | UART_LSR_PE); - uart->icount.brk++; - } else if (*status & UART_LSR_PE) - uart->icount.parity++; - else if (*status & UART_LSR_FE) - uart->icount.frame++; - if (*status & UART_LSR_OE) - uart->icount.overrun++; - - /* - * Mask off conditions which should be ignored. - */ - *status &= uart->read_status_mask; - if (*status & UART_LSR_BI) { - flag = TTY_BREAK; - } else if (*status & UART_LSR_PE) - flag = TTY_PARITY; - else if (*status & UART_LSR_FE) - flag = TTY_FRAME; - } - - if ((*status & uart->ignore_status_mask & ~UART_LSR_OE) == 0) - tty_insert_flip_char(tty, ch, flag); - - /* - * Overrun is special. Since it's reported immediately, - * it doesn't affect the current character. - */ - if (*status & ~uart->ignore_status_mask & UART_LSR_OE) - tty_insert_flip_char(tty, 0, TTY_OVERRUN); - *status = spi_in(port, UART_LSR, SEL_UART); - if(!(*status & UART_LSR_DR)) - break; - } - DBG("\n"); - DBG("%s:LINE=%d,rx_count=%d\n",__FUNCTION__,__LINE__,(1024-max_count)); - tty_flip_buffer_push(tty); - -#endif - DBG("r%d\n",1024-max_count); - -} - -static void spi_uart_transmit_chars(struct spi_uart *uart) -{ - struct circ_buf *xmit = &uart->xmit; - int count; -#if SPI_UART_TXRX_BUF - unsigned char buf[SPI_UART_FIFO_LEN]; -#endif - struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart); - - if (uart->x_char) { - spi_out(port, UART_TX, uart->x_char, SEL_UART); - uart->icount.tx++; - uart->x_char = 0; - printk("%s:LINE=%d\n",__FUNCTION__,__LINE__); - return; - } - if (circ_empty(xmit) || uart->tty->stopped || uart->tty->hw_stopped) { - spi_uart_stop_tx(uart); - DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__); - //printk("circ_empty()\n"); - return; - } - DBG("tx:"); - -#if SPI_UART_TXRX_BUF - //send several bytes one time - count = SPI_UART_FIFO_LEN; - while(count > 0) - { - if (circ_empty(xmit)) - break; - buf[SPI_UART_FIFO_LEN - count] = xmit->buf[xmit->tail]; - DBG("0x%x,",buf[SPI_UART_FIFO_LEN - count]&0xff); - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); - uart->icount.tx++; - --count; - - } - DBG("\n"); - if(SPI_UART_FIFO_LEN - count > 0) - spi_uart_write_buf(uart,buf,SPI_UART_FIFO_LEN - count); -#else - //send one byte one time - count = SPI_UART_FIFO_LEN; - while(count > 0) - { - spi_out(port, UART_TX, xmit->buf[xmit->tail], SEL_UART); - DBG("0x%x,",xmit->buf[xmit->tail]); - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); - uart->icount.tx++; - --count; - if (circ_empty(xmit)) - break; - } -#endif - DBG("\n"); - DBG("%s:LINE=%d,tx_count=%d\n",__FUNCTION__,__LINE__,(SPI_UART_FIFO_LEN-count)); - if (circ_chars_pending(xmit) < WAKEUP_CHARS) - { - tty_wakeup(uart->tty); - DBG("k,"); - } - DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__); - if (circ_empty(xmit)) - { - DBG("circ_empty(xmit)\n"); - spi_uart_stop_tx(uart); - DBG("e,"); - } - - DBG("t%d\n",SPI_UART_FIFO_LEN-count); - - DBG("uart->tty->hw_stopped = %d\n",uart->tty->hw_stopped); -} - -#if 1 -static void spi_uart_check_modem_status(struct spi_uart *uart) -{ - int status; - struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart); - - status = spi_in(port, UART_MSR, SEL_UART);// - DBG("%s:LINE=%d,status=0x%x*******\n",__FUNCTION__,__LINE__,status); - if ((status & UART_MSR_ANY_DELTA) == 0) - return; - - if (status & UART_MSR_TERI) - uart->icount.rng++; - if (status & UART_MSR_DDSR) - uart->icount.dsr++; - if (status & UART_MSR_DDCD) - uart->icount.dcd++; - if (status & UART_MSR_DCTS) { - uart->icount.cts++; - if (uart->tty->termios->c_cflag & CRTSCTS) { - int cts = (status & UART_MSR_CTS); - if (uart->tty->hw_stopped) { - if (cts) { - uart->tty->hw_stopped = 0; - spi_uart_start_tx(uart); - DBG("%s:UART_IER=0x%x\n",__FUNCTION__,uart->ier); - tty_wakeup(uart->tty); - } - } else { - if (!cts) { - uart->tty->hw_stopped = 1; - DBG("%s:UART_IER=0x%x\n",__FUNCTION__,uart->ier); - spi_uart_stop_tx(uart); - } - } - } - } - DBG("%s:LINE=%d,status=0x%x*******\n",__FUNCTION__,__LINE__,status); -} -#endif - - -#if SPI_UART_TEST -#define UART_TEST_LEN 32 //8bit -unsigned char buf_test_uart[UART_TEST_LEN+2]; - -void spi_uart_test_init(struct spi_fpga_port *port) -{ - unsigned char cval, fcr = 0; - unsigned int baud, quot; - unsigned char mcr = 0; - int ret; - - DBG("%s:LINE=%d,mcr=0x%x\n",__FUNCTION__,__LINE__,mcr); - spi_out(port, UART_MCR, mcr, SEL_UART); - baud = 1500000; - cval = UART_LCR_WLEN8; - fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10; - quot = 6000000 / baud; - mcr |= UART_MCR_RTS; - mcr |= UART_MCR_AFE; - - spi_out(port, UART_FCR, UART_FCR_ENABLE_FIFO, SEL_UART); - spi_out(port, UART_FCR, UART_FCR_ENABLE_FIFO | - UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, SEL_UART); - spi_out(port, UART_FCR, 0, SEL_UART); - spi_out(port, UART_LCR, UART_LCR_WLEN8, SEL_UART); - spi_out(port, UART_LCR, cval | UART_LCR_DLAB, SEL_UART); - spi_out(port, UART_DLL, quot & 0xff, SEL_UART); - ret = spi_in(port, UART_DLL, SEL_UART)&0xff; - if(ret != quot) - { - #if SPI_FPGA_TEST_DEBUG - spi_test_wrong_handle(); - #endif - printk("%s:quot=0x%x,UART_DLL=0x%x\n",__FUNCTION__,quot,ret); - } - spi_out(port, UART_DLM, quot >> 8, SEL_UART); - spi_out(port, UART_LCR, cval, SEL_UART); - spi_out(port, UART_FCR, fcr, SEL_UART); - spi_out(port, UART_MCR, mcr, SEL_UART); - - -} - -void spi_uart_work_handler(struct work_struct *work) -{ - int i; - int count; - struct spi_fpga_port *port = - container_of(work, struct spi_fpga_port, uart.spi_uart_work); - printk("*************test spi_uart now***************\n"); - spi_uart_test_init(port); - for(i=0;iuart, buf_test_uart, count); - mdelay(5); - spi_uart_read_buf(&port->uart, buf_test_uart, count); - for(i=0;i 0) - { - spi_out(port, UART_TX, buf_test_uart[UART_TEST_LEN-count], SEL_UART); - --count; - } - printk("%s,line=%d\n",__FUNCTION__,__LINE__); -#endif - -} - -static void spi_testuart_timer(unsigned long data) -{ - struct spi_fpga_port *port = (struct spi_fpga_port *)data; - port->uart.uart_timer.expires = jiffies + msecs_to_jiffies(300); - add_timer(&port->uart.uart_timer); - //schedule_work(&port->gpio.spi_gpio_work); - queue_work(port->uart.spi_uart_workqueue, &port->uart.spi_uart_work); -} - -#endif - -/* - * This handles the interrupt from one port. - */ -void spi_uart_handle_irq(struct spi_device *spi) -{ - struct spi_fpga_port *port = spi_get_drvdata(spi); - struct spi_uart *uart = &port->uart; - unsigned int uart_iir, lsr; - - if (unlikely(uart->in_spi_uart_irq == current)) - return; - DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__); - - /* - * In a few places spi_uart_handle_irq() is called directly instead of - * waiting for the actual interrupt to be raised and the SPI IRQ - * thread scheduled in order to reduce latency. However, some - * interaction with the tty core may end up calling us back - * (serial echo, flow control, etc.) through those same places - * causing undesirable effects. Let's stop the recursion here. - */ - - uart_iir = spi_in(port, UART_IIR, SEL_UART);// - DBG("%s:iir=0x%x\n",__FUNCTION__,uart_iir); - if (uart_iir & UART_IIR_NO_INT) - return; - - uart->in_spi_uart_irq = current; - lsr = spi_in(port, UART_LSR, SEL_UART);// - DBG("%s:lsr=0x%x\n",__FUNCTION__,lsr); - - if (lsr & UART_LSR_DR) - //if (((uart_iir & UART_IIR_RDI) | (uart_iir & UART_IIR_RLSI)) && (lsr & UART_LSR_DR)) - { - DBG("%s:LINE=%d,start recieve data!\n",__FUNCTION__,__LINE__); - spi_uart_receive_chars(uart, &lsr); - } - - spi_uart_check_modem_status(uart); - - - if (lsr & UART_LSR_THRE) - //if ((uart_iir & UART_IIR_THRI)&&(lsr & UART_LSR_THRE)) - { - DBG("%s:LINE=%d,start send data!\n",__FUNCTION__,__LINE__); - spi_uart_transmit_chars(uart); - } - - uart->in_spi_uart_irq = NULL; - - -} - -static int spi_uart_startup(struct spi_uart *uart) -{ - unsigned long page; - struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart); - - DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__); - /* - * Set the TTY IO error marker - we will only clear this - * once we have successfully opened the port. - */ - set_bit(TTY_IO_ERROR, &uart->tty->flags); - - /* Initialise and allocate the transmit buffer. */ - page = __get_free_page(GFP_KERNEL); - if (!page) - return -ENOMEM; - - uart->xmit.buf = (unsigned char *)page; - circ_clear(&uart->xmit); - - mutex_lock(&port->spi_lock); - - /* - * Clear the FIFO buffers and disable them. - * (they will be reenabled in spi_change_speed()) - */ - spi_out(port, UART_FCR, UART_FCR_ENABLE_FIFO, SEL_UART); - spi_out(port, UART_FCR, UART_FCR_ENABLE_FIFO | - UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, SEL_UART); - spi_out(port, UART_FCR, 0, SEL_UART); - - /* - * Clear the interrupt registers. - */ - (void) spi_in(port, UART_LSR, SEL_UART);// - (void) spi_in(port, UART_RX, SEL_UART);// - (void) spi_in(port, UART_IIR, SEL_UART);// - (void) spi_in(port, UART_MSR, SEL_UART);// - - /* - * Now, initialize the UART - */ - spi_out(port, UART_LCR, UART_LCR_WLEN8, SEL_UART); - - uart->ier = UART_IER_RLSI | UART_IER_RDI; - //uart->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE; - uart->mctrl = TIOCM_OUT2; - - spi_uart_change_speed(uart, uart->tty->termios, NULL); - - if (uart->tty->termios->c_cflag & CBAUD) - spi_uart_set_mctrl(uart, TIOCM_RTS | TIOCM_DTR); - - if (uart->tty->termios->c_cflag & CRTSCTS) - if (!(spi_uart_get_mctrl(uart) & TIOCM_CTS)) - uart->tty->hw_stopped = 1; - - clear_bit(TTY_IO_ERROR, &uart->tty->flags); - DBG("%s:LINE=%d,uart->ier=0x%x\n",__FUNCTION__,__LINE__,uart->ier); - /* Kick the IRQ handler once while we're still holding the host lock */ - //spi_uart_handle_irq(port->spi); - mutex_unlock(&port->spi_lock); - return 0; - -//err1: - //free_page((unsigned long)uart->xmit.buf); - //return ret; -} - -static void spi_uart_shutdown(struct spi_uart *uart) -{ - struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart); - DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__); - - mutex_lock(&port->spi_lock); -#if 1 - spi_uart_stop_rx(uart); - - /* TODO: wait here for TX FIFO to drain */ - - /* Turn off DTR and RTS early. */ - if (uart->tty->termios->c_cflag & HUPCL) - spi_uart_clear_mctrl(uart, TIOCM_DTR | TIOCM_RTS); - - /* Disable interrupts from this port */ - - uart->ier = 0; - spi_out(port, UART_IER, 0, SEL_UART); - - spi_uart_clear_mctrl(uart, TIOCM_OUT2); - - /* Disable break condition and FIFOs. */ - uart->lcr &= ~UART_LCR_SBC; - spi_out(port, UART_LCR, uart->lcr, SEL_UART); - spi_out(port, UART_FCR, UART_FCR_ENABLE_FIFO | - UART_FCR_CLEAR_RCVR | - UART_FCR_CLEAR_XMIT, SEL_UART); - spi_out(port, UART_FCR, 0, SEL_UART); -#endif - mutex_unlock(&port->spi_lock); - -//skip: - /* Free the transmit buffer page. */ - free_page((unsigned long)uart->xmit.buf); -} - -static int spi_uart_open (struct tty_struct *tty, struct file * filp) -{ - struct spi_uart *uart; - int ret; - - uart = spi_uart_port_get(tty->index); - if (!uart) - { - DBG("%s:LINE=%d,!port\n",__FUNCTION__,__LINE__); - return -ENODEV; - } - DBG("%s:LINE=%d,tty->index=%d\n",__FUNCTION__,__LINE__,tty->index); - mutex_lock(&uart->open_lock); - - /* - * Make sure not to mess up with a dead port - * which has not been closed yet. - */ - if (tty->driver_data && tty->driver_data != uart) { - mutex_unlock(&uart->open_lock); - spi_uart_port_put(uart); - DBG("%s:LINE=%d,!= uart\n",__FUNCTION__,__LINE__); - return -EBUSY; - } - - if (!uart->opened) { - tty->driver_data = uart; - uart->tty = tty; - ret = spi_uart_startup(uart); - if (ret) { - tty->driver_data = NULL; - uart->tty = NULL; - mutex_unlock(&uart->open_lock); - spi_uart_port_put(uart); - DBG("%s:LINE=%d,ret=%d\n",__FUNCTION__,__LINE__,ret); - return ret; - } - } - uart->opened++; - DBG("%s:uart->opened++=%d\n",__FUNCTION__,uart->opened); - mutex_unlock(&uart->open_lock); - return 0; -} - -static void spi_uart_close(struct tty_struct *tty, struct file * filp) -{ - struct spi_uart *uart = tty->driver_data; - DBG("%s:LINE=%d,tty->hw_stopped=%d\n",__FUNCTION__,__LINE__,tty->hw_stopped); - if (!uart) - return; - - mutex_lock(&uart->open_lock); - BUG_ON(!uart->opened); - - /* - * This is messy. The tty layer calls us even when open() - * returned an error. Ignore this close request if tty->count - * is larger than uart->count. - */ - if (tty->count > uart->opened) { - mutex_unlock(&uart->open_lock); - return; - } - - if (--uart->opened == 0) { - DBG("%s:opened=%d\n",__FUNCTION__,uart->opened); - tty->closing = 1; - spi_uart_shutdown(uart); - tty_ldisc_flush(tty); - uart->tty = NULL; - tty->driver_data = NULL; - tty->closing = 0; - } - spi_uart_port_put(uart); - mutex_unlock(&uart->open_lock); - -} - -static int spi_uart_write(struct tty_struct * tty, const unsigned char *buf, - int count) -{ - struct spi_uart *uart = tty->driver_data; - struct circ_buf *circ = &uart->xmit; - struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart); - int c, ret = 0; - - if (!port->spi) - { - printk("spi error!!!!\n"); - return -ENODEV; - } - - - DBG("spi_uart_write 1 circ->head=%d,circ->tail=%d\n",circ->head,circ->tail); - - spin_lock(&uart->write_lock); - while (1) { - c = CIRC_SPACE_TO_END(circ->head, circ->tail, UART_XMIT_SIZE); - if (count < c) - c = count; - if (c <= 0) - break; - memcpy(circ->buf + circ->head, buf, c); - circ->head = (circ->head + c) & (UART_XMIT_SIZE - 1); - buf += c; - count -= c; - ret += c; - } - spin_unlock(&uart->write_lock); - -#if 1 - if ( !(uart->ier & UART_IER_THRI)) { - mutex_lock(&port->spi_lock); - DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__); - /*Note:ICE65L08 output a 'Transmitter holding register interrupt' after 1us*/ - DBG("s,"); - spi_uart_start_tx(uart); - //spi_uart_handle_irq(port->spi); - mutex_unlock(&port->spi_lock); - } -#endif - - //printk("w%d\n",ret); - return ret; -} - -static int spi_uart_write_room(struct tty_struct *tty) -{ - struct spi_uart *uart = tty->driver_data; - DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__); - return uart ? circ_chars_free(&uart->xmit) : 0; -} - -static int spi_uart_chars_in_buffer(struct tty_struct *tty) -{ - struct spi_uart *uart = tty->driver_data; - DBG("%s:LINE=%d,circ=%ld\n",__FUNCTION__,__LINE__,circ_chars_pending(&uart->xmit)); - return uart ? circ_chars_pending(&uart->xmit) : 0; -} - -static void spi_uart_send_xchar(struct tty_struct *tty, char ch) -{ - struct spi_uart *uart = tty->driver_data; - struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart); - DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__); - uart->x_char = ch; - if (ch && !(uart->ier & UART_IER_THRI)) { - mutex_lock(&port->spi_lock); - spi_uart_start_tx(uart); - printk("%s:UART_IER=0x%x\n",__FUNCTION__,uart->ier); - spi_uart_handle_irq(port->spi); - mutex_unlock(&port->spi_lock); - } -} - -static void spi_uart_throttle(struct tty_struct *tty) -{ - struct spi_uart *uart = tty->driver_data; - struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart); - printk("%s:LINE=%d\n",__FUNCTION__,__LINE__); - if (!I_IXOFF(tty) && !(tty->termios->c_cflag & CRTSCTS)) - return; - printk("%s:LINE=%d\n",__FUNCTION__,__LINE__); - mutex_lock(&port->spi_lock); - if (I_IXOFF(tty)) { - uart->x_char = STOP_CHAR(tty); - spi_uart_start_tx(uart); - DBG("%s:UART_IER=0x%x\n",__FUNCTION__,uart->ier); - } - - if (tty->termios->c_cflag & CRTSCTS) - spi_uart_clear_mctrl(uart, TIOCM_RTS); - - spi_uart_handle_irq(port->spi); - mutex_unlock(&port->spi_lock); -} - -static void spi_uart_unthrottle(struct tty_struct *tty) -{ - struct spi_uart *uart = tty->driver_data; - struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart); - printk("%s:LINE=%d\n",__FUNCTION__,__LINE__); - if (!I_IXOFF(tty) && !(tty->termios->c_cflag & CRTSCTS)) - return; - mutex_lock(&port->spi_lock); - if (I_IXOFF(tty)) { - if (uart->x_char) { - uart->x_char = 0; - } else { - uart->x_char = START_CHAR(tty); - spi_uart_start_tx(uart); - DBG("%s:UART_IER=0x%x\n",__FUNCTION__,uart->ier); - } - } - - if (tty->termios->c_cflag & CRTSCTS) - spi_uart_set_mctrl(uart, TIOCM_RTS); - - spi_uart_handle_irq(port->spi); - mutex_unlock(&port->spi_lock); -} - -static void spi_uart_set_termios(struct tty_struct *tty, struct ktermios *old_termios) -{ - struct spi_uart *uart = tty->driver_data; - struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart); - unsigned int cflag = tty->termios->c_cflag; - unsigned int mask = TIOCM_DTR; - DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__); - -#define RELEVANT_IFLAG(iflag) ((iflag) & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK)) - - if ((cflag ^ old_termios->c_cflag) == 0 && - RELEVANT_IFLAG(tty->termios->c_iflag ^ old_termios->c_iflag) == 0) - return; - - mutex_lock(&port->spi_lock); - spi_uart_change_speed(uart, tty->termios, old_termios); - - /* Handle transition to B0 status */ - if ((old_termios->c_cflag & CBAUD) && !(cflag & CBAUD)){ - DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__); - spi_uart_clear_mctrl(uart, TIOCM_RTS | TIOCM_DTR); - //spi_uart_clear_mctrl(uart, TIOCM_RTS); - } - - /* Handle transition away from B0 status */ - if (!(old_termios->c_cflag & CBAUD) && (cflag & CBAUD)) { - DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__); - if (!(cflag & CRTSCTS) || !test_bit(TTY_THROTTLED, &tty->flags)) - mask |= TIOCM_RTS; - spi_uart_set_mctrl(uart, mask); - } - - /* Handle turning off CRTSCTS */ - if ((old_termios->c_cflag & CRTSCTS) && !(cflag & CRTSCTS)) { - tty->hw_stopped = 0; - spi_uart_start_tx(uart); - DBG("%s:UART_IER=0x%x\n",__FUNCTION__,uart->ier); - } - - /* Handle turning on CRTSCTS */ - if (!(old_termios->c_cflag & CRTSCTS) && (cflag & CRTSCTS)) { - //spi_uart_set_mctrl(uart, TIOCM_RTS); - if (!(spi_uart_get_mctrl(uart) & TIOCM_CTS)) { - DBG("%s:LINE=%d,tty->hw_stopped = 1\n",__FUNCTION__,__LINE__); - tty->hw_stopped = 1; - spi_uart_stop_tx(uart); - } - } - mutex_unlock(&port->spi_lock); - -} - -static int spi_uart_break_ctl(struct tty_struct *tty, int break_state) -{ - struct spi_uart *uart = tty->driver_data; - struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart); - DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__); - mutex_lock(&port->spi_lock); - if (break_state == -1) - uart->lcr |= UART_LCR_SBC; - else - uart->lcr &= ~UART_LCR_SBC; - spi_out(port, UART_LCR, uart->lcr, SEL_UART); - mutex_unlock(&port->spi_lock); - return 0; -} - -static int spi_uart_tiocmget(struct tty_struct *tty, struct file *file) -{ - struct spi_uart *uart = tty->driver_data; - struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart); - int result; - DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__); - mutex_lock(&port->spi_lock); - result = uart->mctrl | spi_uart_get_mctrl(uart); - mutex_unlock(&port->spi_lock); - return result; -} - -static int spi_uart_tiocmset(struct tty_struct *tty, struct file *file, - unsigned int set, unsigned int clear) -{ - struct spi_uart *uart = tty->driver_data; - struct spi_fpga_port *port = container_of(uart, struct spi_fpga_port, uart); - DBG("%s:LINE=%d\n",__FUNCTION__,__LINE__); - mutex_lock(&port->spi_lock); - spi_uart_update_mctrl(uart, set, clear); - mutex_unlock(&port->spi_lock); - - return 0; -} - -static int spi_uart_proc_show(struct seq_file *m, void *v) -{ - int i; - - seq_printf(m, "serinfo:1.0 driver%s%s revision:%s\n", - "", "", ""); - for (i = 0; i < UART_NR; i++) { - struct spi_uart *port = spi_uart_port_get(i); - if (port) { - seq_printf(m, "%d: uart:SPI", i); - if(capable(CAP_SYS_ADMIN)) { - seq_printf(m, " tx:%d rx:%d", - port->icount.tx, port->icount.rx); - if (port->icount.frame) - seq_printf(m, " fe:%d", - port->icount.frame); - if (port->icount.parity) - seq_printf(m, " pe:%d", - port->icount.parity); - if (port->icount.brk) - seq_printf(m, " brk:%d", - port->icount.brk); - if (port->icount.overrun) - seq_printf(m, " oe:%d", - port->icount.overrun); - if (port->icount.cts) - seq_printf(m, " cts:%d", - port->icount.cts); - if (port->icount.dsr) - seq_printf(m, " dsr:%d", - port->icount.dsr); - if (port->icount.rng) - seq_printf(m, " rng:%d", - port->icount.rng); - if (port->icount.dcd) - seq_printf(m, " dcd:%d", - port->icount.dcd); - } - spi_uart_port_put(port); - seq_putc(m, '\n'); - } - } - return 0; -} - -static int spi_uart_proc_open(struct inode *inode, struct file *file) -{ - return single_open(file, spi_uart_proc_show, NULL); -} - -static const struct file_operations spi_uart_proc_fops = { - .owner = THIS_MODULE, - .open = spi_uart_proc_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static const struct tty_operations spi_uart_ops = { - .open = spi_uart_open, - .close = spi_uart_close, - .write = spi_uart_write, - .write_room = spi_uart_write_room, - .chars_in_buffer = spi_uart_chars_in_buffer, - .send_xchar = spi_uart_send_xchar, - .throttle = spi_uart_throttle, - .unthrottle = spi_uart_unthrottle, - .set_termios = spi_uart_set_termios, - .break_ctl = spi_uart_break_ctl, - .tiocmget = spi_uart_tiocmget, - .tiocmset = spi_uart_tiocmset, - .proc_fops = &spi_uart_proc_fops, -}; - - -static struct tty_driver *spi_uart_tty_driver; - -int spi_uart_register(struct spi_fpga_port *port) -{ - int i,ret; - struct tty_driver *tty_drv; - spi_uart_tty_driver = tty_drv = alloc_tty_driver(UART_NR); - if (!tty_drv) - return -ENOMEM; - tty_drv->owner = THIS_MODULE; - tty_drv->driver_name = "spi_uart"; - tty_drv->name = "ttySPI"; - tty_drv->major = 0; /* dynamically allocated */ - tty_drv->minor_start = 0; - //tty_drv->num = UART_NR; - tty_drv->type = TTY_DRIVER_TYPE_SERIAL; - tty_drv->subtype = SERIAL_TYPE_NORMAL; - tty_drv->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV; - tty_drv->init_termios = tty_std_termios; - tty_drv->init_termios.c_cflag = B115200 | CS8 | CREAD | HUPCL | CLOCAL; - tty_drv->init_termios.c_ispeed = 115200; - tty_drv->init_termios.c_ospeed = 115200; - tty_set_operations(tty_drv, &spi_uart_ops); - - ret = tty_register_driver(tty_drv); - if (ret) - goto err1; - - //port->uart.uartclk = 64*115200; //MCLK/4 - port->uart.uartclk = 60*100000; //MCLK/4 - - for(i=0; iuart); - if (ret) { - goto err2; - } else { - struct device *dev; - dev = tty_register_device(spi_uart_tty_driver, port->uart.index, &port->spi->dev); - if (IS_ERR(dev)) { - spi_uart_port_remove(&port->uart); - ret = PTR_ERR(dev); - goto err2; - } - } - } - -#if SPI_UART_TEST - char b[20]; - sprintf(b, "spi_uart_workqueue"); - port->uart.spi_uart_workqueue = create_freezeable_workqueue(b); - if (!port->uart.spi_uart_workqueue) { - printk("cannot create workqueue\n"); - return -EBUSY; - } - INIT_WORK(&port->uart.spi_uart_work, spi_uart_work_handler); - - setup_timer(&port->uart.uart_timer, spi_testuart_timer, (unsigned long)port); - port->uart.uart_timer.expires = jiffies+2000; - add_timer(&port->uart.uart_timer); - -#endif - - - return 0; - -err2: - tty_unregister_driver(tty_drv); -err1: - put_tty_driver(tty_drv); - - return ret; - - -} -int spi_uart_unregister(struct spi_fpga_port *port) -{ - - return 0; -} - -MODULE_DESCRIPTION("Driver for spi2uart."); -MODULE_AUTHOR("luowei "); -MODULE_LICENSE("GPL"); diff --git a/drivers/headset_observe/Kconfig b/drivers/headset_observe/Kconfig index 08381d6db6d0..6c036f143582 100755 --- a/drivers/headset_observe/Kconfig +++ b/drivers/headset_observe/Kconfig @@ -4,15 +4,7 @@ menu "Headset device support" -config HEADSET_DET - depends on ARCH_RK2818 - tristate "RK2818 headset detech support" - ---help--- - only use on the rk2818 - config RK_HEADSET_DET - depends on !ARCH_RK2818 - default n tristate "RK headset detech support" ---help--- Universal headphone driver(write begin rk29) diff --git a/drivers/headset_observe/Makefile b/drivers/headset_observe/Makefile index 2acaac384887..bb15b12c4de5 100755 --- a/drivers/headset_observe/Makefile +++ b/drivers/headset_observe/Makefile @@ -1,3 +1 @@ -obj-$(CONFIG_HEADSET_DET) += rk2818_headset.o obj-$(CONFIG_RK_HEADSET_DET) += rk_headset.o - diff --git a/drivers/headset_observe/rk2818_headset.c b/drivers/headset_observe/rk2818_headset.c deleted file mode 100755 index 3aefdea53a93..000000000000 --- a/drivers/headset_observe/rk2818_headset.c +++ /dev/null @@ -1,252 +0,0 @@ -/* arch/arm/mach-rockchip/rk28_headset.c - * - * Copyright (C) 2009 Rockchip Corporation. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rk2818_headset.h" -#include - -/* Debug */ -#if 1 -#define DBG(x...) printk(x) -#else -#define DBG(x...) do { } while (0) -#endif - -#define BIT_HEADSET (1 << 0) -#define BIT_HEADSET_NO_MIC (1 << 1) - -struct rk2818_headset_dev{ - struct switch_dev sdev; - int cur_headset_status; - int pre_headset_status; - struct mutex mutex_lock; -}; - -static struct rk2818_headset_dev Headset_dev; -static struct delayed_work g_headsetobserve_work; -static struct rk2818_headset_data *prk2818_headset_info; -#if defined(CONFIG_MACH_BENGO_V2) || defined(CONFIG_MACH_BENGO) || defined(CONFIG_MACH_Z5) || defined(CONFIG_MACH_Z5_V2) || defined(CONFIG_MACH_A22) -extern void detect_HSMic(void); -#endif - -int headset_status(void) -{ - if(Headset_dev.cur_headset_status & BIT_HEADSET) - return 1; - else - return 0; -} - -EXPORT_SYMBOL_GPL(headset_status); - -static irqreturn_t headset_interrupt(int irq, void *dev_id) -{ -// DBG("---headset_interrupt---\n"); - schedule_delayed_work(&g_headsetobserve_work, msecs_to_jiffies(20)); - return IRQ_HANDLED; -} - -static int headset_change_irqtype(unsigned int irq_type) -{ - int ret = 0; -// DBG("--------%s----------\n",__FUNCTION__); - free_irq(prk2818_headset_info->irq,NULL); - - ret = request_irq(prk2818_headset_info->irq, headset_interrupt, irq_type, NULL, NULL); - if (ret) - { - DBG("headsetobserve: request irq failed\n"); - return ret; - } - return ret; -} - -static void headsetobserve_work(struct work_struct *work) -{ - int i,level = 0; - -// DBG("---headsetobserve_work---\n"); - mutex_lock(&Headset_dev.mutex_lock); - - for(i=0; i<3; i++) - { - level = gpio_get_value(prk2818_headset_info->gpio); - if(level < 0) - { - printk("%s:get pin level again,pin=%d,i=%d\n",__FUNCTION__,prk2818_headset_info->gpio,i); - msleep(1); - continue; - } - else - break; - } - if(level < 0) - { - printk("%s:get pin level err!\n",__FUNCTION__); - return; - } - - switch(prk2818_headset_info->headset_in_type) - { - case HEADSET_IN_HIGH: - if(level > 0) - {//in--High level - DBG("--- HEADSET_IN_HIGH headset in---\n"); - Headset_dev.cur_headset_status = BIT_HEADSET; - headset_change_irqtype(IRQF_TRIGGER_FALLING);// - } - else if(level == 0) - {//out--Low level - DBG("---HEADSET_IN_HIGH headset out---\n"); - Headset_dev.cur_headset_status = ~(BIT_HEADSET|BIT_HEADSET_NO_MIC); - headset_change_irqtype(IRQF_TRIGGER_RISING);// - } - break; - case HEADSET_IN_LOW: - if(level == 0) - {//in--High level - DBG("---HEADSET_IN_LOW headset in---\n"); - Headset_dev.cur_headset_status = BIT_HEADSET; - headset_change_irqtype(IRQF_TRIGGER_RISING);// - } - else if(level > 0) - {//out--High level - DBG("---HEADSET_IN_LOW headset out---\n"); - Headset_dev.cur_headset_status = ~(BIT_HEADSET|BIT_HEADSET_NO_MIC); - headset_change_irqtype(IRQF_TRIGGER_FALLING);// - } - break; - default: - DBG("---- ERROR: on headset headset_in_type error -----\n"); - break; - } - - if(Headset_dev.cur_headset_status != Headset_dev.pre_headset_status) - { - Headset_dev.pre_headset_status = Headset_dev.cur_headset_status; - switch_set_state(&Headset_dev.sdev, Headset_dev.cur_headset_status); - DBG("Headset_dev.cur_headset_status = %d\n",Headset_dev.cur_headset_status); -#if defined(CONFIG_MACH_BENGO_V2) || defined(CONFIG_MACH_BENGO) || defined(CONFIG_MACH_Z5) || defined(CONFIG_MACH_Z5_V2) || defined(CONFIG_MACH_A22) - detect_HSMic(); -#endif - } - mutex_unlock(&Headset_dev.mutex_lock); -} - -static ssize_t h2w_print_name(struct switch_dev *sdev, char *buf) -{ - return sprintf(buf, "Headset\n"); -} - -#ifdef CONFIG_HAS_EARLYSUSPEND -static void headset_early_resume(struct early_suspend *h) -{ - schedule_delayed_work(&g_headsetobserve_work, msecs_to_jiffies(10)); - //DBG(">>>>>headset_early_resume\n"); -} - -static struct early_suspend hs_early_suspend; -#endif - -static int rockchip_headsetobserve_probe(struct platform_device *pdev) -{ - int ret; - - DBG("RockChip headset observe driver\n"); - prk2818_headset_info = pdev->dev.platform_data; - - Headset_dev.cur_headset_status = 0; - Headset_dev.pre_headset_status = 0; - Headset_dev.sdev.name = "h2w"; - Headset_dev.sdev.print_name = h2w_print_name; - mutex_init(&Headset_dev.mutex_lock); - - ret = switch_dev_register(&Headset_dev.sdev); - if (ret < 0) - return ret; - - INIT_DELAYED_WORK(&g_headsetobserve_work, headsetobserve_work); - - ret = gpio_request(prk2818_headset_info->gpio, "headset_det"); - if (ret) - { - DBG("headsetobserve: request gpio_request failed\n"); - return ret; - } - gpio_pull_updown(prk2818_headset_info->gpio, GPIONormal); - gpio_direction_input(prk2818_headset_info->gpio); - prk2818_headset_info->irq = gpio_to_irq(prk2818_headset_info->gpio); - - if(prk2818_headset_info->headset_in_type == HEADSET_IN_HIGH) - prk2818_headset_info->irq_type = IRQF_TRIGGER_RISING; - else - prk2818_headset_info->irq_type = IRQF_TRIGGER_FALLING; - ret = request_irq(prk2818_headset_info->irq, headset_interrupt, prk2818_headset_info->irq_type, NULL, NULL); - if (ret) - { - DBG("headsetobserve: request irq failed\n"); - return ret; - } - - schedule_delayed_work(&g_headsetobserve_work, msecs_to_jiffies(500)); - -#ifdef CONFIG_HAS_EARLYSUSPEND - hs_early_suspend.suspend = NULL; - hs_early_suspend.resume = headset_early_resume; - hs_early_suspend.level = ~0x0; - register_early_suspend(&hs_early_suspend); -#endif - - return 0; -} - -static struct platform_driver rockchip_headsetobserve_driver = { - .probe = rockchip_headsetobserve_probe, - .driver = { - .name = "rk2818_headsetdet", - .owner = THIS_MODULE, - }, -}; - - -static int __init rockchip_headsetobserve_init(void) -{ - platform_driver_register(&rockchip_headsetobserve_driver); - return 0; -} -module_init(rockchip_headsetobserve_init); -MODULE_DESCRIPTION("Rockchip Headset Driver"); -MODULE_LICENSE("GPL"); diff --git a/drivers/headset_observe/rk2818_headset.h b/drivers/headset_observe/rk2818_headset.h deleted file mode 100755 index 0a2036752dc4..000000000000 --- a/drivers/headset_observe/rk2818_headset.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef RK2818_HEADSET_H -#define RK2818_HEADSET_H - -#define HEADSET_IN_HIGH 0x00000001 -#define HEADSET_IN_LOW 0x00000000 - -/* ¶ú»úÊý¾Ý½á¹¹Ìå */ -struct rk2818_headset_data { - unsigned int gpio; - unsigned int irq; - unsigned int irq_type; - unsigned int headset_in_type; -}; - -#endif diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 5a664c3ad756..9a1686e939cc 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -268,29 +268,6 @@ config I2C_POWERMAC tristate "Powermac I2C interface" depends on PPC_PMAC -config I2C_RK2818 - tristate "RK2818 i2c interface (I2C)" - depends on ARCH_RK2818 - default y - help - This supports the use of the I2C interface on rk2818 processors. - -if I2C_RK2818 - comment "Now, there are two I2C interfaces selected by developer." - - config I2C0_RK2818 - bool "RK2818 I2C0 interface support" - default y - depends on ARCH_RK2818 - help - This supports the use of the I2C0 interface on rk2818 processors. - config I2C1_RK2818 - bool "RK2818 I2C1 interface support" - default y - depends on ARCH_RK2818 - help - This supports the use of the I2C1 interface on rk2818 processors. -endif config I2C_RK29 tristate "RK29 i2c interface (I2C)" depends on ARCH_RK29 diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 69703292fe10..d69a5881bd43 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -1,10 +1,9 @@ # # Makefile for the i2c bus drivers. # -obj-$(CONFIG_I2C_RK2818) += i2c-rk2818.o obj-$(CONFIG_I2C_RK29) += i2c-rk29.o -obj-$(CONFIG_I2C_DEV_RK29) += i2c-dev-rk29.o -obj-y += i2c-gpio.o +obj-$(CONFIG_I2C_DEV_RK29) += i2c-dev-rk29.o +obj-y += i2c-gpio.o ifeq ($(CONFIG_I2C_DEBUG_BUS),y) EXTRA_CFLAGS += -DDEBUG diff --git a/drivers/i2c/busses/i2c-rk2818.c b/drivers/i2c/busses/i2c-rk2818.c deleted file mode 100755 index 4913063d7d68..000000000000 --- a/drivers/i2c/busses/i2c-rk2818.c +++ /dev/null @@ -1,820 +0,0 @@ -/* drivers/i2c/busses/i2c_rockchip.c - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "i2c-rockchip.h" -#define DRV_NAME "rockchip_i2c" - -#define RK2818_I2C_TIMEOUT (msecs_to_jiffies(500)) -#define RK2818_DELAY_TIME 2 - -#if 0 -#define i2c_dbg(dev, format, arg...) \ - dev_printk(KERN_INFO , dev , format , ## arg) -#else -#define i2c_dbg(dev, format, arg...) -#endif - -enum rockchip_error { - RK2818_ERROR_NONE = 0, - RK2818_ERROR_ARBITR_LOSE, - RK2818_ERROR_UNKNOWN -}; - -enum rockchip_event { - RK2818_EVENT_NONE = 0, - /* master has received ack(MTX mode) - means that data has been sent to slave. - */ - RK2818_EVENT_MTX_RCVD_ACK, - /* master needs to send ack to slave(MRX mode) - means that data has been received from slave. - */ - RK2818_EVENT_MRX_NEED_ACK, - RK2818_EVENT_MAX -}; - -struct rockchip_i2c_data { - struct device *dev; - struct i2c_adapter adap; - void __iomem *regs; - struct resource *ioarea; - - unsigned int suspended:1; - unsigned long scl_rate; - unsigned long i2c_rate; - struct clk *clk; - - unsigned int mode; - - unsigned int irq; - - spinlock_t cmd_lock; - struct completion cmd_complete; - enum rockchip_event cmd_event; - enum rockchip_error cmd_err; - - unsigned int msg_idx; - unsigned int msg_num; -#ifdef CONFIG_CPU_FREQ - struct notifier_block freq_transition; -#endif -}; - -static void rockchip_i2c_init_hw(struct rockchip_i2c_data *i2c); - -static inline void rockchip_i2c_disable_irqs(struct rockchip_i2c_data *i2c) -{ - unsigned long tmp; - - tmp = readl(i2c->regs + I2C_IER); - writel(tmp & IRQ_ALL_DISABLE, i2c->regs + I2C_IER); -} -static inline void rockchip_i2c_enable_irqs(struct rockchip_i2c_data *i2c) -{ - unsigned long tmp; - - tmp = readl(i2c->regs + I2C_IER); - writel(tmp | IRQ_MST_ENABLE, i2c->regs + I2C_IER); -} - -/* scl = pclk/(5 *(rem+1) * 2^(exp+1)) */ -static void rockchip_i2c_calcdivisor(unsigned long pclk, - unsigned long scl_rate, - unsigned long *real_rate, - unsigned int *rem, unsigned int *exp) -{ - unsigned int calc_rem = 0; - unsigned int calc_exp = 0; - - for(calc_exp = 0; calc_exp < I2CCDVR_EXP_MAX; calc_exp++) - { - calc_rem = pclk / (5 * scl_rate * (1 <<(calc_exp +1))); - if(calc_rem < I2CCDVR_REM_MAX) - break; - } - if(calc_rem >= I2CCDVR_REM_MAX || calc_exp >= I2CCDVR_EXP_MAX) - { - calc_rem = I2CCDVR_REM_MAX - 1; - calc_exp = I2CCDVR_EXP_MAX - 1; - } - *rem = calc_rem; - *exp = calc_exp; - *real_rate = pclk/(5 * (calc_rem + 1) * (1 <<(calc_exp +1))); - return; -} -/* set i2c bus scl rate */ -static void rockchip_i2c_clockrate(struct rockchip_i2c_data *i2c) -{ -#ifdef CONFIG_ARCH_RK2818 - struct rk2818_i2c_platform_data *pdata = i2c->dev->platform_data; -#else - struct rk29_i2c_platform_data *pdata = i2c->dev->platform_data; -#endif - unsigned int rem = 0, exp = 0; - unsigned long scl_rate, real_rate = 0, tmp; - - i2c->i2c_rate = clk_get_rate(i2c->clk); - - scl_rate = (i2c->scl_rate) ? i2c->scl_rate : ((pdata->scl_rate)? pdata->scl_rate:100000); - - rockchip_i2c_calcdivisor(i2c->i2c_rate, scl_rate, &real_rate, &rem, &exp); - - tmp = readl(i2c->regs + I2C_OPR); - tmp |= exp; - tmp |= rem<regs + I2C_OPR); - if(real_rate > 400000) - dev_warn(i2c->dev, "i2c_rate[%luKhz], scl_rate[%luKhz], real_rate[%luKhz] > 400Khz\n", - i2c->i2c_rate/1000, scl_rate/1000, real_rate/1000); - else - i2c_dbg(i2c->dev, "i2c_rate[%luKhz], scl_rate[%luKhz], real_rate[%luKhz]\n", - i2c->i2c_rate/1000, scl_rate/1000, real_rate/1000); - return; -} -static int rockchip_event_occurred(struct rockchip_i2c_data *i2c) -{ - unsigned long isr; - - isr = readl(i2c->regs + I2C_ISR); - i2c_dbg(i2c->dev,"event occurred, isr = %lx\n", isr); - if(isr & I2C_ISR_ARBITR_LOSE) - { - isr &= ~I2C_ISR_ARBITR_LOSE; - writel(isr, i2c->regs + I2C_ISR); - i2c->cmd_err = RK2818_ERROR_ARBITR_LOSE; - dev_err(i2c->dev, "arbitration loss\n"); - return 1; - } - - switch(i2c->cmd_event) - { - case RK2818_EVENT_MTX_RCVD_ACK: - if(isr & I2C_ISR_MTX_RCVD_ACK) - { - isr &= ~I2C_ISR_MTX_RCVD_ACK; - writel(isr, i2c->regs + I2C_ISR); - return 1; - } - break; - case RK2818_EVENT_MRX_NEED_ACK: - if(isr & I2C_ISR_MRX_NEED_ACK) - { - isr &= ~I2C_ISR_MRX_NEED_ACK; - writel(isr, i2c->regs + I2C_ISR); - return 1; - } - break; - default: - break; - } - i2c->cmd_err = RK2818_ERROR_UNKNOWN; - return 0; -} - -static irqreturn_t rockchip_i2c_irq(int irq, void *data) -{ - struct rockchip_i2c_data *i2c = (struct rockchip_i2c_data *)data; - int res; - - rockchip_i2c_disable_irqs(i2c); - spin_lock(&i2c->cmd_lock); - res = rockchip_event_occurred(i2c); - if(res) - //if(res || i2c->cmd_err != RK2818_ERROR_NONE) - complete(&i2c->cmd_complete); - spin_unlock(&i2c->cmd_lock); - return IRQ_HANDLED; -} -static int wait_for_completion_poll_timeout(struct rockchip_i2c_data *i2c, unsigned long timeout) -{ - unsigned int time = RK2818_DELAY_TIME; - int res; - - while(!time_after(jiffies, jiffies + timeout)) - { - res = rockchip_event_occurred(i2c); - if(res) - //if(res || (i2c->cmd_err != RK2818_ERROR_NONE && i2c->cmd_err != RK2818_ERROR_UNKNOWN)) - return 1; - udelay(time); - time *= 2; - } - return 0; - -} -static int rockchip_wait_event(struct rockchip_i2c_data *i2c, - enum rockchip_event mr_event) -{ - int ret = 0; - unsigned long flags; - if(i2c->mode == I2C_MODE_IRQ) - { - if(unlikely(irqs_disabled())) - { - dev_err(i2c->dev, "irqs are disabled on this system!\n"); - return -EIO; - } - } - spin_lock_irqsave(&i2c->cmd_lock,flags); - i2c->cmd_err = RK2818_ERROR_NONE; - i2c->cmd_event = mr_event; - - init_completion(&i2c->cmd_complete); - - spin_unlock_irqrestore(&i2c->cmd_lock,flags); - - rockchip_i2c_enable_irqs(i2c); - if(i2c->mode == I2C_MODE_IRQ) - ret = wait_for_completion_interruptible_timeout(&i2c->cmd_complete, - RK2818_I2C_TIMEOUT); - else - ret = wait_for_completion_poll_timeout(i2c, RK2818_I2C_TIMEOUT); - - if(ret < 0) - { - dev_err(i2c->dev, "i2c wait for event %04x, retrun %d \n", mr_event, ret); - return ret; - } - if(ret == 0) - { - return -ETIMEDOUT; - } - return 0; -} - -static int rockchip_wait_while_busy(struct rockchip_i2c_data *i2c) -{ - unsigned long timeout = jiffies + RK2818_I2C_TIMEOUT; - unsigned long lsr; - unsigned int time = RK2818_DELAY_TIME; - - while(!time_after(jiffies, timeout)) - { - lsr = readl(i2c->regs + I2C_LSR); - if(!(lsr & I2C_LSR_BUSY)) - return 0; - udelay(time); - time *= 2; - } - return -ETIMEDOUT; -} -static int rockchip_i2c_stop(struct rockchip_i2c_data *i2c) -{ - unsigned long timeout = jiffies + RK2818_I2C_TIMEOUT; - unsigned int time = RK2818_DELAY_TIME; - - writel(I2C_LCMR_STOP|I2C_LCMR_RESUME, i2c->regs + I2C_LCMR); - while(!time_after(jiffies, timeout)) - { - if(!(readl(i2c->regs + I2C_LCMR) & I2C_LCMR_STOP)) - { - i2c_dbg(i2c->dev, "i2c stop successfully\n"); - return 0; - } - udelay(time); - time *= 2; - } - return -ETIMEDOUT; - -} -static int rockchip_send_2nd_addr(struct rockchip_i2c_data *i2c, - struct i2c_msg *msg, int start) -{ - int ret = 0; - unsigned long addr_2nd = msg->addr & 0xff; - unsigned long conr = readl(i2c->regs + I2C_CONR); - - conr |= I2C_CONR_MTX_MODE; - //conr &= I2C_CONR_ACK; - writel(conr, i2c->regs + I2C_CONR); - - i2c_dbg(i2c->dev, "i2c send addr_2nd: %lx\n", addr_2nd); - writel(addr_2nd, i2c->regs + I2C_MTXR); - writel(I2C_LCMR_RESUME, i2c->regs + I2C_LCMR); - if((ret = rockchip_wait_event(i2c, RK2818_EVENT_MTX_RCVD_ACK)) != 0) - { - dev_err(i2c->dev, "after sent addr_2nd, i2c wait for ACK timeout\n"); - return ret; - } - return ret; -} -static int rockchip_send_address(struct rockchip_i2c_data *i2c, - struct i2c_msg *msg, int start) -{ - unsigned long addr_1st; - unsigned long conr = readl(i2c->regs + I2C_CONR); - int ret = 0; - - if(msg->flags & I2C_M_TEN) - addr_1st = (0xf0 | (((unsigned long) msg->addr & 0x300) >> 7)) & 0xff; - else - addr_1st = ((msg->addr << 1) & 0xff); - - if (msg->flags & I2C_M_RD) - addr_1st |= 0x01; - else - addr_1st &= (~0x01); - - conr |= I2C_CONR_MTX_MODE; - //conr &= I2C_CONR_ACK; - writel(conr, i2c->regs + I2C_CONR); - i2c_dbg(i2c->dev, "i2c send addr_1st: %lx\n", addr_1st); - - writel(addr_1st, i2c->regs + I2C_MTXR); - - if (start) - { - if((ret = rockchip_wait_while_busy(i2c)) != 0) - { - dev_err(i2c->dev, "i2c is busy, when send address\n"); - return ret; - } - writel(I2C_LCMR_START, i2c->regs + I2C_LCMR); - } - else - writel(I2C_LCMR_START|I2C_LCMR_RESUME, i2c->regs + I2C_LCMR); - - if((ret = rockchip_wait_event(i2c, RK2818_EVENT_MTX_RCVD_ACK)) != 0) - { - dev_err(i2c->dev, "after sent addr_1st, i2c wait for ACK timeout\n"); - return ret; - } - if(start && (msg->flags & I2C_M_TEN)) - ret = rockchip_send_2nd_addr(i2c, msg, start); - return ret; -} - -static int rockchip_i2c_send_msg(struct rockchip_i2c_data *i2c, struct i2c_msg *msg) -{ - int i, ret = 0; - unsigned long conr = readl(i2c->regs + I2C_CONR); - - conr = readl(i2c->regs + I2C_CONR); - conr |= I2C_CONR_MTX_MODE; - writel(conr, i2c->regs + I2C_CONR); - for(i = 0; i < msg->len; i++) - { - i2c_dbg(i2c->dev, "i2c send buf[%d]: %x\n", i, msg->buf[i]); - writel(msg->buf[i], i2c->regs + I2C_MTXR); - /* - conr = readl(i2c->regs + I2C_CONR); - conr &= I2C_CONR_ACK; - writel(conr, i2c->regs + I2C_CONR); - */ - writel(I2C_LCMR_RESUME, i2c->regs + I2C_LCMR); - - if((ret = rockchip_wait_event(i2c, RK2818_EVENT_MTX_RCVD_ACK)) != 0) - return ret; - } - return ret; -} -static int rockchip_i2c_recv_msg(struct rockchip_i2c_data *i2c, struct i2c_msg *msg) -{ - int i, ret = 0; - unsigned long conr = readl(i2c->regs + I2C_CONR); - - conr = readl(i2c->regs + I2C_CONR); - conr &= I2C_CONR_MRX_MODE; - writel(conr, i2c->regs + I2C_CONR); - - for(i = 0; i < msg->len; i++) - { - writel(I2C_LCMR_RESUME, i2c->regs + I2C_LCMR); - if((ret = rockchip_wait_event(i2c, RK2818_EVENT_MRX_NEED_ACK)) != 0) - return ret; - conr = readl(i2c->regs + I2C_CONR); - conr &= I2C_CONR_ACK; - writel(conr, i2c->regs + I2C_CONR); - msg->buf[i] = (uint8_t)readl(i2c->regs + I2C_MRXR); - i2c_dbg(i2c->dev, "i2c recv >>>>>>>>>>>> buf[%d]: %x\n", i, msg->buf[i]); - } - return ret; -} -static int rockchip_xfer_msg(struct i2c_adapter *adap, - struct i2c_msg *msg, int start, int stop) -{ - struct rockchip_i2c_data *i2c = (struct rockchip_i2c_data *)adap->algo_data; - unsigned long conr = readl(i2c->regs + I2C_CONR); - int ret = 0; - - #if defined (CONFIG_IOEXTEND_TCA6424) - struct tca6424_platform_data *pdata = adap->dev.platform_data; - #endif - - if(msg->len == 0) - { - ret = -EINVAL; - dev_err(i2c->dev, "msg->len = %d\n", msg->len); - goto exit; - } - - if((ret = rockchip_send_address(i2c, msg, start))!= 0) - { - dev_err(i2c->dev, "rockchip_send_address timeout\n"); - goto exit; - } - if(msg->flags & I2C_M_RD) - { - if((ret = rockchip_i2c_recv_msg(i2c, msg)) != 0) - { - dev_err(i2c->dev, "rockchip_i2c_recv_msg timeout\n"); - goto exit; - } - } - else - { - if((ret = rockchip_i2c_send_msg(i2c, msg)) != 0) - { - dev_err(i2c->dev, "rockchip_i2c_send_msg timeout\n"); - goto exit; - } - } - -exit: - if(stop) - { - conr = readl(i2c->regs + I2C_CONR); - conr |= I2C_CONR_NAK; - writel(conr, i2c->regs + I2C_CONR); - if((ret = rockchip_i2c_stop(i2c)) != 0) - { - dev_err(i2c->dev, "rockchip_i2c_stop timeout\n"); - } - - //not I2C code,add by sxj,used for extend gpio intrrupt,set SCL and SDA pin. - if(msg->flags & I2C_M_RD) - { - #if defined (CONFIG_IOEXTEND_TCA6424) - if (pdata && pdata->reseti2cpin) { - pdata->reseti2cpin(); - } - #endif - } - - } - return ret; - -} - -static int rockchip_i2c_xfer(struct i2c_adapter *adap, - struct i2c_msg *msgs, int num) -{ - int ret = -1; - int i; - struct rockchip_i2c_data *i2c = (struct rockchip_i2c_data *)adap->algo_data; - unsigned long conr = readl(i2c->regs + I2C_CONR); - /* - if(i2c->suspended ==1) - return -EIO; - */ - if(msgs[0].scl_rate <= 400000 && msgs[0].scl_rate > 0) - i2c->scl_rate = msgs[0].scl_rate; - else - i2c->scl_rate = 400000; - - conr |= I2C_CONR_MPORT_ENABLE; - writel(conr, i2c->regs + I2C_CONR); - - rockchip_i2c_init_hw(i2c); - - conr = readl(i2c->regs + I2C_CONR); - conr &= I2C_CONR_ACK; - writel(conr, i2c->regs + I2C_CONR); - - for (i = 0; i < num; i++) - { - ret = rockchip_xfer_msg(adap, &msgs[i], (i == 0), (i == (num - 1))); - if (ret != 0) - { - num = ret; - dev_err(i2c->dev, "rockchip_xfer_msg error, ret = %d\n", ret); - break; - } - } - conr = readl(i2c->regs + I2C_CONR); - conr &= I2C_CONR_MPORT_DISABLE; - writel(conr, i2c->regs + I2C_CONR); - return num; -} - -static u32 rockchip_i2c_func(struct i2c_adapter *adap) -{ - return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR; -} - -static const struct i2c_algorithm rockchip_i2c_algorithm = { - .master_xfer = rockchip_i2c_xfer, - .functionality = rockchip_i2c_func, -}; - -int i2c_suspended(struct i2c_adapter *adap) -{ - struct rockchip_i2c_data *i2c = (struct rockchip_i2c_data *)adap->algo_data; - if(adap->nr > 1) - return 1; - if(i2c == NULL) - return 1; - return i2c->suspended; -} -EXPORT_SYMBOL(i2c_suspended); - -static void rockchip_i2c_init_hw(struct rockchip_i2c_data *i2c) -{ - unsigned long lcmr = 0x00000000; - - unsigned long opr = readl(i2c->regs + I2C_OPR); - opr |= I2C_OPR_RESET_STATUS; - writel(opr, i2c->regs + I2C_OPR); - - writel(lcmr, i2c->regs + I2C_LCMR); - - rockchip_i2c_disable_irqs(i2c); - - rockchip_i2c_clockrate(i2c); - - opr = readl(i2c->regs + I2C_OPR); - opr |= I2C_OPR_CORE_ENABLE; - writel(opr, i2c->regs + I2C_OPR); - - return; -} - -#ifdef CONFIG_CPU_FREQ - -#define freq_to_i2c(_n) container_of(_n, struct rockchip_i2c_data, freq_transition) - -static int rockchip_i2c_cpufreq_transition(struct notifier_block *nb, - unsigned long val, void *data) -{ - struct rockchip_i2c_data *i2c = freq_to_i2c(nb); - unsigned long flags; - int delta_f; - delta_f = clk_get_rate(i2c->clk) - i2c->i2c_rate; - - if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) || - (val == CPUFREQ_PRECHANGE && delta_f > 0)) - { - spin_lock_irqsave(&i2c->cmd_lock, flags); - rockchip_i2c_clockrate(i2c); - spin_unlock_irqrestore(&i2c->cmd_lock, flags); - } - return 0; -} - -static inline int rockchip_i2c_register_cpufreq(struct rockchip_i2c_data *i2c) -{ - i2c->freq_transition.notifier_call = rockchip_i2c_cpufreq_transition; - - return cpufreq_register_notifier(&i2c->freq_transition, - CPUFREQ_TRANSITION_NOTIFIER); -} - -static inline void rockchip_i2c_unregister_cpufreq(struct rockchip_i2c_data *i2c) -{ - cpufreq_unregister_notifier(&i2c->freq_transition, - CPUFREQ_TRANSITION_NOTIFIER); -} - -#else -static inline int rockchip_i2c_register_cpufreq(struct rockchip_i2c_data *i2c) -{ - return 0; -} - -static inline void rockchip_i2c_unregister_cpufreq(struct rockchip_i2c_data *i2c) -{ - return; -} -#endif -static int rockchip_i2c_probe(struct platform_device *pdev) -{ - struct rockchip_i2c_data *i2c; -#ifdef CONFIG_ARCH_RK2818 - struct rk2818_i2c_platform_data *pdata = NULL; -#else - struct rk29_i2c_platform_data *pdata = NULL; -#endif - struct resource *res; - int ret; - - pdata = pdev->dev.platform_data; - if (!pdata) - { - dev_err(&pdev->dev, "no platform data\n"); - return -EINVAL; - } - i2c = kzalloc(sizeof(struct rockchip_i2c_data), GFP_KERNEL); - if (!i2c) - { - dev_err(&pdev->dev, "no memory for state\n"); - return -ENOMEM; - } - i2c->mode = pdata->mode; - i2c->scl_rate = (pdata->scl_rate) ? pdata->scl_rate : 100000; - - strlcpy(i2c->adap.name, DRV_NAME, sizeof(i2c->adap.name)); - i2c->adap.owner = THIS_MODULE; - i2c->adap.algo = &rockchip_i2c_algorithm; - i2c->adap.class = I2C_CLASS_HWMON; - spin_lock_init(&i2c->cmd_lock); - - i2c->dev = &pdev->dev; - - i2c->clk = clk_get(&pdev->dev, "i2c"); - if (IS_ERR(i2c->clk)) { - dev_err(&pdev->dev, "cannot get clock\n"); - ret = -ENOENT; - goto err_noclk; - } - - clk_enable(i2c->clk); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (res == NULL) { - dev_err(&pdev->dev, "cannot find IO resource\n"); - ret = -ENOENT; - goto err_clk; - } - - i2c->ioarea = request_mem_region(res->start, res->end - res->start + 1, - pdev->name); - - if (i2c->ioarea == NULL) { - dev_err(&pdev->dev, "cannot request IO\n"); - ret = -ENXIO; - goto err_clk; - } - - i2c->regs = ioremap(res->start, res->end - res->start + 1); - - if (i2c->regs == NULL) { - dev_err(&pdev->dev, "annot map IO\n"); - ret = -ENXIO; - goto err_ioarea; - } - i2c->adap.algo_data = i2c; - i2c->adap.dev.parent = &pdev->dev; - - if(pdata->io_init) - pdata->io_init(); - - rockchip_i2c_init_hw(i2c); - - i2c->irq = ret = platform_get_irq(pdev, 0); - if (ret <= 0) { - dev_err(&pdev->dev, "cannot find IRQ\n"); - goto err_iomap; - } - if(i2c->mode == I2C_MODE_IRQ) - { - ret = request_irq(i2c->irq, rockchip_i2c_irq, IRQF_DISABLED, - dev_name(&pdev->dev), i2c); - - if (ret != 0) { - dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); - goto err_iomap; - } - } - ret = rockchip_i2c_register_cpufreq(i2c); - if (ret < 0) { - dev_err(&pdev->dev, "failed to register cpufreq notifier\n"); - goto err_irq; - } - - i2c->adap.nr = pdata->bus_num; - ret = i2c_add_numbered_adapter(&i2c->adap); - if (ret < 0) { - dev_err(&pdev->dev, "failed to add bus to i2c core\n"); - goto err_cpufreq; - } - - platform_set_drvdata(pdev, i2c); - - dev_info(&pdev->dev, "%s: RK2818 I2C adapter\n", dev_name(&i2c->adap.dev)); - return 0; - - err_cpufreq: - rockchip_i2c_unregister_cpufreq(i2c); - - err_irq: - if(i2c->mode == I2C_MODE_IRQ) - free_irq(i2c->irq, i2c); - - err_iomap: - iounmap(i2c->regs); - - err_ioarea: - release_resource(i2c->ioarea); - kfree(i2c->ioarea); - - err_clk: - clk_disable(i2c->clk); - clk_put(i2c->clk); - - err_noclk: - kfree(i2c); - return ret; -} - - -static int rockchip_i2c_remove(struct platform_device *pdev) -{ - struct rockchip_i2c_data *i2c = platform_get_drvdata(pdev); - - rockchip_i2c_unregister_cpufreq(i2c); - - i2c_del_adapter(&i2c->adap); - if(i2c->mode == I2C_MODE_IRQ) - free_irq(i2c->irq, i2c); - - clk_disable(i2c->clk); - clk_put(i2c->clk); - - iounmap(i2c->regs); - - release_resource(i2c->ioarea); - kfree(i2c->ioarea); - kfree(i2c); - - return 0; -} - -#ifdef CONFIG_PM - -static int rockchip_i2c_suspend(struct platform_device *pdev, pm_message_t state) -{ - struct rockchip_i2c_data *i2c = platform_get_drvdata(pdev); - - i2c->suspended = 1; - return 0; -} -static int rockchip_i2c_resume(struct platform_device *pdev) -{ - struct rockchip_i2c_data *i2c = platform_get_drvdata(pdev); - - i2c->suspended = 0; - rockchip_i2c_init_hw(i2c); - - return 0; -} -#else -#define rockchip_i2c_suspend NULL -#define rockchip_i2c_resume NULL -#endif - - -static struct platform_driver rockchip_i2c_driver = { - .probe = rockchip_i2c_probe, - .remove = rockchip_i2c_remove, - .suspend = rockchip_i2c_suspend, - .resume = rockchip_i2c_resume, - .driver = { - .owner = THIS_MODULE, - .name = DRV_NAME, - }, -}; - -static int __init rockchip_i2c_adap_init(void) -{ - return platform_driver_register(&rockchip_i2c_driver); -} - -static void __exit rockchip_i2c_adap_exit(void) -{ - platform_driver_unregister(&rockchip_i2c_driver); -} - -subsys_initcall(rockchip_i2c_adap_init); -module_exit(rockchip_i2c_adap_exit); - -MODULE_DESCRIPTION("Driver for RK2818 I2C Bus"); -MODULE_AUTHOR("kfx, kfx@rock-chips.com"); -MODULE_LICENSE("GPL"); diff --git a/drivers/i2c/busses/i2c-rk2818.h b/drivers/i2c/busses/i2c-rk2818.h deleted file mode 100755 index 97bf03cd8fc2..000000000000 --- a/drivers/i2c/busses/i2c-rk2818.h +++ /dev/null @@ -1,73 +0,0 @@ -/* drivers/i2c/busses/i2c_rk2818.h - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __RK2818_I2C_H -#define __RK2818_I2C_H - -/* master transmit */ -#define I2C_MTXR (0x0000) -/* master receive */ -#define I2C_MRXR (0x0004) -/* slave address */ -#define I2C_SADDR (0x0010) -/* interrupt enable control */ -#define I2C_IER (0x0014) -#define I2C_IER_ARBITR_LOSE (1<<7) -#define I2C_IER_MRX_NEED_ACK (1<<1) -#define I2C_IER_MTX_RCVD_ACK (1<<0) - -#define IRQ_MST_ENABLE (I2C_IER_ARBITR_LOSE | \ - I2C_IER_MRX_NEED_ACK | \ - I2C_IER_MTX_RCVD_ACK) -#define IRQ_ALL_DISABLE (0x00) - -/* interrupt status, write 0 to clear */ -#define I2C_ISR (0x0018) -#define I2C_ISR_ARBITR_LOSE (1<<7) -#define I2C_ISR_MRX_NEED_ACK (1<<1) -#define I2C_ISR_MTX_RCVD_ACK (1<<0) - -/* stop/start/resume command, write 1 to set */ -#define I2C_LCMR (0x001c) -#define I2C_LCMR_RESUME (1<<2) -#define I2C_LCMR_STOP (1<<1) -#define I2C_LCMR_START (1<<0) - -/* i2c core status */ -#define I2C_LSR (0x0020) -#define I2C_LSR_RCV_NAK (1<<1) -#define I2C_LSR_RCV_ACK (~(1<<1)) -#define I2C_LSR_BUSY (1<<0) - -/* i2c config */ -#define I2C_CONR (0x0024) -#define I2C_CONR_NAK (1<<4) -#define I2C_CONR_ACK (~(1<<4)) -#define I2C_CONR_MTX_MODE (1<<3) -#define I2C_CONR_MRX_MODE (~(1<<3)) -#define I2C_CONR_MPORT_ENABLE (1<<2) -#define I2C_CONR_MPORT_DISABLE (~(1<<2)) - -/* i2c core config */ -#define I2C_OPR (0x0028) -#define I2C_OPR_RESET_STATUS (1<<7) -#define I2C_OPR_CORE_ENABLE (1<<6) - -#define I2CCDVR_REM_BITS (0x03) -#define I2CCDVR_REM_MAX (1<<(I2CCDVR_REM_BITS)) -#define I2CCDVR_EXP_BITS (0x03) -#define I2CCDVR_EXP_MAX (1<<(I2CCDVR_EXP_BITS)) - -#endif diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig index 1944bbe51c8f..85a3493615aa 100755 --- a/drivers/input/keyboard/Kconfig +++ b/drivers/input/keyboard/Kconfig @@ -449,35 +449,5 @@ config KEYBOARD_W90P910 To compile this driver as a module, choose M here: the module will be called w90p910_keypad. -config KEYBOARD_RK28ADC - tristate "RK2818 ADC Keypad support" - depends on RK28_ADC - default y - help - Say Y here to enable the adc keypad on SDK board - based on RK2818. - - To compile this driver as a module, choose M here: the - module will be called rk2818_adckey. -config HEADSET_KEY - tristate "RK2818 headset Keypad support" - depends on RK28_ADC - default y - help - Say Y here to enable the headset adc keypad on SDK board - based on RK2818. - - To compile this driver as a module, choose M here: the - module will be called rk2818_hskey. - -config KEYBOARD_RK28ADC_IT50 - tristate "RK2818 ADC Keypad it50 support" - depends on RK28_ADC - help - Say Y here to enable the adc keypad on SDK board - based on RK2818. - - To compile this driver as a module, choose M here: the - module will be called rk2818_adckey. endif diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile index 2c85c1194faf..0354fb555e09 100755 --- a/drivers/input/keyboard/Makefile +++ b/drivers/input/keyboard/Makefile @@ -39,8 +39,5 @@ obj-$(CONFIG_KEYBOARD_TOSA) += tosakbd.o obj-$(CONFIG_KEYBOARD_TWL4030) += twl4030_keypad.o obj-$(CONFIG_KEYBOARD_XTKBD) += xtkbd.o obj-$(CONFIG_KEYBOARD_W90P910) += w90p910_keypad.o -obj-$(CONFIG_KEYBOARD_RK28ADC) += rk2818_adckey.o -obj-$(CONFIG_KEYBOARD_RK28ADC_IT50) += rk2818_adckey_t50.o -obj-$(CONFIG_HEADSET_KEY) += rk2818_hskey.o obj-$(CONFIG_SYNAPTICS_SO340010) += synaptics_so340010.o diff --git a/drivers/input/keyboard/rk2818_adckey.c b/drivers/input/keyboard/rk2818_adckey.c deleted file mode 100755 index 70ba7e089f0d..000000000000 --- a/drivers/input/keyboard/rk2818_adckey.c +++ /dev/null @@ -1,411 +0,0 @@ -/* - * linux/drivers/input/keyboard/rk28_adckey.c - * - * This driver program support to AD key which use for rk28 chip - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#if 0 -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -#define KEY_PHYS_NAME "rk2818_adckey/input0" - -volatile int gADSampleTimes = 0; -volatile int gStatePlaykey = 0; -volatile unsigned int gCodeCount = 0; -volatile unsigned int gThisCode = 0; -volatile unsigned int gLastCode = 0; -volatile unsigned int gFlagShortPlay = 0; -volatile unsigned int gFlagLongPlay = 0; -volatile unsigned int gPlayCount = 0; - -//key code tab -struct rk28_adckey -{ - struct semaphore lock; - struct rk28_adc_client *client; - struct input_dev *input_dev; - struct timer_list timer; - unsigned char * keycodes; - void __iomem *mmio_base; -}; - -struct rk28_adckey *pRk28AdcKey; - -unsigned int rk28_get_keycode(unsigned int advalue,pADC_keyst ptab,struct adc_key_data *rk2818_adckey_data) -{ - while(ptab->adc_keycode != 0) - { - if((ptab->adc_value == 0)&&(advalue >= 0 && advalue <= 5)) - return ptab->adc_keycode; - if((advalue > ptab->adc_value - rk2818_adckey_data->adc_drift) && (advalue < ptab->adc_value + rk2818_adckey_data->adc_drift)) - return ptab->adc_keycode; - ptab++; - } - - return 0; -} - -EXPORT_SYMBOL_GPL(rk28_get_keycode); - -static irqreturn_t rk28_playkey_irq(int irq, void *handle) -{ - - //gFlagPlay = 1; - //DBG("Enter::%s,LINE=%d,KEY_PLAY_SHORT_PRESS=%d\n",__FUNCTION__,__LINE__,KEY_PLAY_SHORT_PRESS); - - return IRQ_HANDLED; -} - -void rk28_send_wakeup_key( void ) -{ - input_report_key(pRk28AdcKey->input_dev,KEY_WAKEUP,1); - input_sync(pRk28AdcKey->input_dev); - input_report_key(pRk28AdcKey->input_dev,KEY_WAKEUP,0); - input_sync(pRk28AdcKey->input_dev); - DBG("Wake up system\n"); -} - -static int rk28_adckey_open(struct input_dev *dev) -{ - //struct rk28_adckey *adckey = input_get_drvdata(dev); - - return 0; -} - -static void rk28_adckey_close(struct input_dev *dev) -{ - //struct rk28_adckey *adckey = input_get_drvdata(dev); -// -} - -#ifdef CONFIG_PM -static int rk28_adckey_suspend(struct platform_device *pdev, pm_message_t state) -{ - //struct rk28_adckey *adckey = platform_get_drvdata(pdev); - - return 0; -} - -static int rk28_adckey_resume(struct platform_device *pdev) -{ - //struct rk28_adckey *adckey = platform_get_drvdata(pdev); - //struct input_dev *input_dev = adckey->input_dev; -#if 0 - mutex_lock(&input_dev->mutex); - - mutex_unlock(&input_dev->mutex); -#endif - return 0; -} -#else -#define rk28_adckey_suspend NULL -#define rk28_adckey_resume NULL -#endif -static void rk28_adkeyscan_timer(unsigned long data) -{ - unsigned int adcvalue = -1, code; - struct adc_key_data *rk2818_adckey_data = (struct adc_key_data *)data; - - pRk28AdcKey->timer.expires = jiffies + msecs_to_jiffies(10); - add_timer(&pRk28AdcKey->timer); - - /*handle long press of play key*/ - if(gpio_get_value(rk2818_adckey_data->pin_playon) == rk2818_adckey_data->playon_level) - { - if(++gPlayCount > 20000) - gPlayCount = 101; - if((1 == gPlayCount) && (0 == gFlagShortPlay)) - { - gFlagShortPlay = 1; - } - else if((100 == gPlayCount) && (0 == gFlagLongPlay)) - { - gFlagLongPlay = 1; - gFlagShortPlay = 0; - input_report_key(pRk28AdcKey->input_dev,KEY_PLAY_LONG_PRESS,1); - input_sync(pRk28AdcKey->input_dev); - DBG("Enter::%s,LINE=%d,KEY_PLAY_LONG_PRESS=%d,1\n",__FUNCTION__,__LINE__,KEY_PLAY_LONG_PRESS); - } - } - else - { - if (1 == gFlagShortPlay) - { - input_report_key(pRk28AdcKey->input_dev,ENDCALL,1); - input_sync(pRk28AdcKey->input_dev); - input_report_key(pRk28AdcKey->input_dev,ENDCALL,0); - input_sync(pRk28AdcKey->input_dev); - DBG("Wake up system,ENDCALL=%d\n",ENDCALL); - - input_report_key(pRk28AdcKey->input_dev,KEY_PLAY_SHORT_PRESS,1); - input_sync(pRk28AdcKey->input_dev); - DBG("Enter::%s,LINE=%d,KEY_PLAY_SHORT_PRESS=%d,1\n",__FUNCTION__,__LINE__,KEY_PLAY_SHORT_PRESS); - input_report_key(pRk28AdcKey->input_dev,KEY_PLAY_SHORT_PRESS,0); - input_sync(pRk28AdcKey->input_dev); - DBG("Enter::%s,LINE=%d,KEY_PLAY_SHORT_PRESS=%d,0\n",__FUNCTION__,__LINE__,KEY_PLAY_SHORT_PRESS); - } - else if(1 == gFlagLongPlay) - { - input_report_key(pRk28AdcKey->input_dev,KEY_PLAY_LONG_PRESS,0); - input_sync(pRk28AdcKey->input_dev); - DBG("Enter::%s,LINE=%d,KEY_PLAY_LONG_PRESS=%d,0\n",__FUNCTION__,__LINE__,KEY_PLAY_LONG_PRESS); - } - - gFlagShortPlay = 0; - gFlagLongPlay = 0; - gPlayCount = 0; - } - - /*handle long press of adc key*/ - if (gADSampleTimes < 4) - { - gADSampleTimes ++; - return; - } - - gADSampleTimes = 0; - - //rk28_read_adc(pRk28AdcKey); - adcvalue = gAdcValue[rk2818_adckey_data->adc_chn]; - //printk("=========== adcvalue=0x%x ===========\n",adcvalue); - - if((adcvalue > rk2818_adckey_data->adc_empty) || (adcvalue < rk2818_adckey_data->adc_invalid)) - { - //DBG("adcvalue invalid !!!\n"); - if(gLastCode == 0) { - return; - } - else - { - if(gLastCode == KEYMENU) - { - if(gCodeCount > 31) - { - input_report_key(pRk28AdcKey->input_dev,ENDCALL,0); - input_sync(pRk28AdcKey->input_dev); - DBG("Enter::%s,LINE=%d,code=%d,ENDCALL,0\n",__FUNCTION__,__LINE__,gLastCode); - } - input_report_key(pRk28AdcKey->input_dev,gLastCode,1); - input_sync(pRk28AdcKey->input_dev); - DBG("Enter::%s,LINE=%d,code=%d,1\n",__FUNCTION__,__LINE__,gLastCode); - } - - input_report_key(pRk28AdcKey->input_dev,gLastCode,0); - input_sync(pRk28AdcKey->input_dev); - DBG("Enter::%s,LINE=%d,code=%d,0\n",__FUNCTION__,__LINE__,gLastCode); - gLastCode = 0; - gCodeCount = 0; - return; - } - } - - //DBG("adcvalue=0x%x\n",adcvalue); - - code=rk28_get_keycode(adcvalue,rk2818_adckey_data->adc_key_table,rk2818_adckey_data); - if(code) - { - if(code == KEYMENU) - { - gLastCode = code; - if(++gCodeCount == 31)//40ms * 30 =1.2s - { - input_report_key(pRk28AdcKey->input_dev,ENDCALL,1); - input_sync(pRk28AdcKey->input_dev); - DBG("Enter::%s,LINE=%d,code=%d,ENDCALL,1\n",__FUNCTION__,__LINE__,code); - } - } - else - { - gLastCode = code; - if(++gCodeCount == 2)//only one event once one touch - { - input_report_key(pRk28AdcKey->input_dev,code,1); - input_sync(pRk28AdcKey->input_dev); - DBG("Enter::%s,LINE=%d,code=%d,1\n",__FUNCTION__,__LINE__,code); - } - } - - } - -} - - -static int __devinit rk28_adckey_probe(struct platform_device *pdev) -{ - struct rk28_adckey *adckey; - struct input_dev *input_dev; - int error,i,irq_num; - struct rk2818_adckey_platform_data *pdata = pdev->dev.platform_data; - - if (!(pdata->adc_key)) - return -1; - - adckey = kzalloc(sizeof(struct rk28_adckey), GFP_KERNEL); - if (adckey == NULL) { - dev_err(&pdev->dev, "failed to allocate driver data\n"); - return -ENOMEM; - } - - //memcpy(adckey->keycodes, gInitKeyCode, sizeof(adckey->keycodes)); - adckey->keycodes = pdata->adc_key->initKeyCode; - - /* Create and register the input driver. */ - input_dev = input_allocate_device(); - if (!input_dev) { - dev_err(&pdev->dev, "failed to allocate input device\n"); - error = -ENOMEM; - goto failed_free; - } - - input_dev->name = pdata->name ? pdata->name : pdev->name; - //input_dev->id.bustype = BUS_HOST; - input_dev->open = rk28_adckey_open; - input_dev->close = rk28_adckey_close; - input_dev->dev.parent = &pdev->dev; - input_dev->phys = KEY_PHYS_NAME; - input_dev->id.vendor = 0x0001; - input_dev->id.product = 0x0001; - input_dev->id.version = 0x0100; - - input_dev->keycode = adckey->keycodes; - input_dev->keycodesize = sizeof(unsigned char); - input_dev->keycodemax = pdata->adc_key->adc_key_cnt; - for (i = 0; i < pdata->adc_key->adc_key_cnt; i++) - set_bit(pdata->adc_key->initKeyCode[i], input_dev->keybit); - clear_bit(0, input_dev->keybit); - - adckey->input_dev = input_dev; - input_set_drvdata(input_dev, adckey); - - input_dev->evbit[0] = BIT_MASK(EV_KEY); - -// rk28_adckey_build_keycode(adckey); - platform_set_drvdata(pdev, adckey); - - pRk28AdcKey = adckey; - - /* Register the input device */ - error = input_register_device(input_dev); - if (error) { - dev_err(&pdev->dev, "failed to register input device\n"); - goto failed_free_dev; - } - - error = gpio_request(pdata->adc_key->pin_playon, "play key gpio"); - if (error) { - dev_err(&pdev->dev, "failed to request play key gpio\n"); - goto free_gpio; - } - - irq_num = gpio_to_irq(pdata->adc_key->pin_playon); - - if(pdata->adc_key->playon_level) - { - gpio_pull_updown(pdata->adc_key->pin_playon,GPIOPullDown); - error = request_irq(irq_num,rk28_playkey_irq,IRQF_TRIGGER_RISING,NULL,NULL); - if(error) - { - printk("unable to request play key irq\n"); - goto free_gpio_irq; - } - } - else - { - gpio_pull_updown(pdata->adc_key->pin_playon,GPIOPullUp); - error = request_irq(irq_num,rk28_playkey_irq,IRQF_TRIGGER_FALLING,NULL,NULL); - if(error) - { - printk("unable to request play key irq\n"); - goto free_gpio_irq; - } - } - - enable_irq_wake(irq_num); // so play/wakeup key can wake up system - - setup_timer(&adckey->timer, rk28_adkeyscan_timer, (unsigned long)(pdata->adc_key)); - adckey->timer.expires = jiffies+50; - add_timer(&adckey->timer); - printk(KERN_INFO "rk2818_adckey: driver initialized\n"); - return 0; - -free_gpio_irq: - free_irq(irq_num,NULL); -free_gpio: - gpio_free(pdata->adc_key->pin_playon); -failed_free_dev: - platform_set_drvdata(pdev, NULL); - input_free_device(input_dev); -failed_free: - kfree(adckey); - return error; -} - -static int __devexit rk28_adckey_remove(struct platform_device *pdev) -{ - struct rk28_adckey *adckey = platform_get_drvdata(pdev); - struct rk2818_adckey_platform_data *pdata = pdev->dev.platform_data; - - input_unregister_device(adckey->input_dev); - input_free_device(adckey->input_dev); - platform_set_drvdata(pdev, NULL); - kfree(adckey); - free_irq(gpio_to_irq(pdata->adc_key->pin_playon), NULL); - gpio_free(pdata->adc_key->pin_playon); - return 0; -} - -static struct platform_driver rk28_adckey_driver = -{ - .probe = rk28_adckey_probe, - .remove = __devexit_p(rk28_adckey_remove), - .suspend = rk28_adckey_suspend, - .resume = rk28_adckey_resume, - .driver = { - .name = "rk2818-adckey", - .owner = THIS_MODULE, - }, -}; - - int __init rk28_adckey_init(void) -{ - return platform_driver_register(&rk28_adckey_driver); -} - -static void __exit rk28_adckey_exit(void) -{ - platform_driver_unregister(&rk28_adckey_driver); -} - -module_init(rk28_adckey_init); -module_exit(rk28_adckey_exit); - -MODULE_DESCRIPTION("rk2818 adc Key Controller Driver"); -MODULE_AUTHOR("luowei lw@rock-chips.com"); -MODULE_LICENSE("GPL"); - diff --git a/drivers/input/keyboard/rk2818_adckey_t50.c b/drivers/input/keyboard/rk2818_adckey_t50.c deleted file mode 100755 index e83a38a41171..000000000000 --- a/drivers/input/keyboard/rk2818_adckey_t50.c +++ /dev/null @@ -1,416 +0,0 @@ -/* - * linux/drivers/input/keyboard/rk28_adckey.c - * - * This driver program support to AD key which use for rk28 chip - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#if 0 -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -#define KEY_PHYS_NAME "rk2818_adckey/input0" - -volatile int gADSampleTimes = 0; -volatile int gStatePlaykey = 0; -volatile unsigned int gCodeCount = 0; -volatile unsigned int gThisCode = 0; -volatile unsigned int gLastCode = 0; -volatile unsigned int gFlagShortPlay = 0; -volatile unsigned int gFlagLongPlay = 0; -volatile unsigned int gPlayCount = 0; - -//key code tab -struct rk28_adckey -{ - struct semaphore lock; - struct rk28_adc_client *client; - struct input_dev *input_dev; - struct timer_list timer; - unsigned char * keycodes; - void __iomem *mmio_base; -}; - -struct rk28_adckey *pRk28AdcKey; - -unsigned int rk28_get_keycode(unsigned int advalue,pADC_keyst ptab,struct adc_key_data *rk2818_adckey_data) -{ - if(advalue >= 0 && advalue <= 5) - return ptab->adc_keycode; - - while(ptab->adc_keycode != 0) - { - - if((advalue > ptab->adc_value - rk2818_adckey_data->adc_drift) && (advalue < ptab->adc_value + rk2818_adckey_data->adc_drift)) - { - DBG("ptab->adc_keycode is :%d\n",ptab->adc_keycode); - return ptab->adc_keycode; - } - ptab++; - } - - return 0; -} - -static irqreturn_t rk28_playkey_irq(int irq, void *handle) -{ - - //gFlagPlay = 1; - //DBG("Enter::%s,LINE=%d,KEY_PLAY_SHORT_PRESS=%d\n",__FUNCTION__,__LINE__,KEY_PLAY_SHORT_PRESS); - - return IRQ_HANDLED; -} - -void rk28_send_wakeup_key( void ) -{ - input_report_key(pRk28AdcKey->input_dev,KEY_WAKEUP,1); - input_sync(pRk28AdcKey->input_dev); - input_report_key(pRk28AdcKey->input_dev,KEY_WAKEUP,0); - input_sync(pRk28AdcKey->input_dev); - DBG("Wake up system\n"); -} - -static int rk28_adckey_open(struct input_dev *dev) -{ - //struct rk28_adckey *adckey = input_get_drvdata(dev); - - return 0; -} - -static void rk28_adckey_close(struct input_dev *dev) -{ - //struct rk28_adckey *adckey = input_get_drvdata(dev); -// -} - -#ifdef CONFIG_PM -static int rk28_adckey_suspend(struct platform_device *pdev, pm_message_t state) -{ - //struct rk28_adckey *adckey = platform_get_drvdata(pdev); - - return 0; -} - -static int rk28_adckey_resume(struct platform_device *pdev) -{ - //struct rk28_adckey *adckey = platform_get_drvdata(pdev); - //struct input_dev *input_dev = adckey->input_dev; -#if 0 - mutex_lock(&input_dev->mutex); - - mutex_unlock(&input_dev->mutex); -#endif - return 0; -} -#else -#define rk28_adckey_suspend NULL -#define rk28_adckey_resume NULL -#endif -static void rk28_adkeyscan_timer(unsigned long data) -{ - unsigned int adcvalue = -1, code; - struct adc_key_data *rk2818_adckey_data = (struct adc_key_data *)data; - - pRk28AdcKey->timer.expires = jiffies + msecs_to_jiffies(10); - add_timer(&pRk28AdcKey->timer); - - /*handle long press of play key*/ - if(gpio_get_value(rk2818_adckey_data->pin_playon) == rk2818_adckey_data->playon_level) - { - if(++gPlayCount > 20000) - gPlayCount = 101; - if((2 == gPlayCount) && (0 == gFlagShortPlay)) - { - gFlagShortPlay = 1; - } - else if((100 == gPlayCount) && (0 == gFlagLongPlay)) - { - gFlagLongPlay = 1; - gFlagShortPlay = 0; - input_report_key(pRk28AdcKey->input_dev,KEY_PLAY_LONG_PRESS,1); - input_sync(pRk28AdcKey->input_dev); - DBG("Enter::%s,LINE=%d,KEY_PLAY_LONG_PRESS=%d,1\n",__FUNCTION__,__LINE__,KEY_PLAY_LONG_PRESS); - } - } - else - { - if (1 == gFlagShortPlay) - { - input_report_key(pRk28AdcKey->input_dev,ENDCALL,1); - input_sync(pRk28AdcKey->input_dev); - input_report_key(pRk28AdcKey->input_dev,ENDCALL,0); - input_sync(pRk28AdcKey->input_dev); - DBG("Wake up system,ENDCALL=%d\n",ENDCALL); - - input_report_key(pRk28AdcKey->input_dev,KEY_PLAY_SHORT_PRESS,1); - input_sync(pRk28AdcKey->input_dev); - DBG("Enter::%s,LINE=%d,KEY_PLAY_SHORT_PRESS=%d,1\n",__FUNCTION__,__LINE__,KEY_PLAY_SHORT_PRESS); - input_report_key(pRk28AdcKey->input_dev,KEY_PLAY_SHORT_PRESS,0); - input_sync(pRk28AdcKey->input_dev); - DBG("Enter::%s,LINE=%d,KEY_PLAY_SHORT_PRESS=%d,0\n",__FUNCTION__,__LINE__,KEY_PLAY_SHORT_PRESS); - } - else if(1 == gFlagLongPlay) - { - input_report_key(pRk28AdcKey->input_dev,KEY_PLAY_LONG_PRESS,0); - input_sync(pRk28AdcKey->input_dev); - DBG("Enter::%s,LINE=%d,KEY_PLAY_LONG_PRESS=%d,0\n",__FUNCTION__,__LINE__,KEY_PLAY_LONG_PRESS); - } - - gFlagShortPlay = 0; - gFlagLongPlay = 0; - gPlayCount = 0; - } - - /*handle long press of adc key*/ - if (gADSampleTimes < 4) - { - gADSampleTimes ++; - return; - } - - gADSampleTimes = 0; - - //rk28_read_adc(pRk28AdcKey); - adcvalue = gAdcValue[rk2818_adckey_data->adc_chn]; - //printk("=========== adcvalue=0x%x ===========\n",adcvalue); - - if(adcvalue > rk2818_adckey_data->adc_empty) - { - //DBG("adcvalue invalid !!!\n"); - if(gLastCode == 0) { - //DBG("(gLastCode == 0\n"); - return; - } - else - { - if(gLastCode == KEYMENU) - { - if(gCodeCount > 31) - { - input_report_key(pRk28AdcKey->input_dev,ENDCALL,0); - input_sync(pRk28AdcKey->input_dev); - DBG("Enter::%s,LINE=%d,code=%d,ENDCALL,0\n",__FUNCTION__,__LINE__,gLastCode); - } - input_report_key(pRk28AdcKey->input_dev,gLastCode,1); - input_sync(pRk28AdcKey->input_dev); - DBG("Enter::%s,LINE=%d,code=%d,1\n",__FUNCTION__,__LINE__,gLastCode); - } - - input_report_key(pRk28AdcKey->input_dev,gLastCode,0); - input_sync(pRk28AdcKey->input_dev); - DBG("Enter::%s,LINE=%d,code=%d,0\n",__FUNCTION__,__LINE__,gLastCode); - gLastCode = 0; - gCodeCount = 0; - return; - } - } - - DBG("adcvalue=0x%x\n",adcvalue); - - code=rk28_get_keycode(adcvalue,rk2818_adckey_data->adc_key_table,rk2818_adckey_data); - if(code) - { - if(code == KEYMENU) - { - gLastCode = code; - if(++gCodeCount == 31)//40ms * 30 =1.2s - { - input_report_key(pRk28AdcKey->input_dev,ENDCALL,1); - input_sync(pRk28AdcKey->input_dev); - DBG("Enter menu::%s,LINE=%d,code=%d,ENDCALL,1\n",__FUNCTION__,__LINE__,code); - } - } - else - { - DBG("Enter key ::%s,LINE=%d,gCodeCount=%d,1\n",__FUNCTION__,__LINE__,gCodeCount); - gLastCode = code; - if(++gCodeCount == 2)//only one event once one touch - { - input_report_key(pRk28AdcKey->input_dev,code,1); - input_sync(pRk28AdcKey->input_dev); - DBG("Enter key ::%s,LINE=%d,code=%d,1\n",__FUNCTION__,__LINE__,code); - } - } - - } - -} - - -static int __devinit rk28_adckey_probe(struct platform_device *pdev) -{ - struct rk28_adckey *adckey; - struct input_dev *input_dev; - int error,i,irq_num; - struct rk2818_adckey_platform_data *pdata = pdev->dev.platform_data; - - if (!(pdata->adc_key)) - return -1; - - adckey = kzalloc(sizeof(struct rk28_adckey), GFP_KERNEL); - if (adckey == NULL) { - dev_err(&pdev->dev, "failed to allocate driver data\n"); - return -ENOMEM; - } - - //memcpy(adckey->keycodes, gInitKeyCode, sizeof(adckey->keycodes)); - adckey->keycodes = pdata->adc_key->initKeyCode; - - /* Create and register the input driver. */ - input_dev = input_allocate_device(); - if (!input_dev) { - dev_err(&pdev->dev, "failed to allocate input device\n"); - error = -ENOMEM; - goto failed_free; - } - - input_dev->name = pdev->name; - //input_dev->id.bustype = BUS_HOST; - input_dev->open = rk28_adckey_open; - input_dev->close = rk28_adckey_close; - input_dev->dev.parent = &pdev->dev; - input_dev->phys = KEY_PHYS_NAME; - input_dev->id.vendor = 0x0001; - input_dev->id.product = 0x0001; - input_dev->id.version = 0x0100; - - input_dev->keycode = adckey->keycodes; - input_dev->keycodesize = sizeof(unsigned char); - input_dev->keycodemax = pdata->adc_key->adc_key_cnt; - for (i = 0; i < pdata->adc_key->adc_key_cnt; i++) - set_bit(pdata->adc_key->initKeyCode[i], input_dev->keybit); - clear_bit(0, input_dev->keybit); - - adckey->input_dev = input_dev; - input_set_drvdata(input_dev, adckey); - - input_dev->evbit[0] = BIT_MASK(EV_KEY); - -// rk28_adckey_build_keycode(adckey); - platform_set_drvdata(pdev, adckey); - - pRk28AdcKey = adckey; - - /* Register the input device */ - error = input_register_device(input_dev); - if (error) { - dev_err(&pdev->dev, "failed to register input device\n"); - goto failed_free_dev; - } - - error = gpio_request(pdata->adc_key->pin_playon, "play key gpio"); - if (error) { - dev_err(&pdev->dev, "failed to request play key gpio\n"); - goto free_gpio; - } - - irq_num = gpio_to_irq(pdata->adc_key->pin_playon); - - if(pdata->adc_key->playon_level) - { - gpio_pull_updown(pdata->adc_key->pin_playon,GPIOPullDown); - error = request_irq(irq_num,rk28_playkey_irq,IRQF_TRIGGER_RISING,NULL,NULL); - if(error) - { - printk("unable to request play key irq\n"); - goto free_gpio_irq; - } - } - else - { - gpio_pull_updown(pdata->adc_key->pin_playon,GPIOPullUp); - error = request_irq(irq_num,rk28_playkey_irq,IRQF_TRIGGER_FALLING,NULL,NULL); - if(error) - { - printk("unable to request play key irq\n"); - goto free_gpio_irq; - } - } - - enable_irq_wake(irq_num); // so play/wakeup key can wake up system - - setup_timer(&adckey->timer, rk28_adkeyscan_timer, (unsigned long)(pdata->adc_key)); - adckey->timer.expires = jiffies+50; - add_timer(&adckey->timer); - printk(KERN_INFO "rk2818_adckey: driver initialized\n"); - return 0; - -free_gpio_irq: - free_irq(irq_num,NULL); -free_gpio: - gpio_free(pdata->adc_key->pin_playon); -failed_free_dev: - platform_set_drvdata(pdev, NULL); - input_free_device(input_dev); -failed_free: - kfree(adckey); - return error; -} - -static int __devexit rk28_adckey_remove(struct platform_device *pdev) -{ - struct rk28_adckey *adckey = platform_get_drvdata(pdev); - struct rk2818_adckey_platform_data *pdata = pdev->dev.platform_data; - - input_unregister_device(adckey->input_dev); - input_free_device(adckey->input_dev); - platform_set_drvdata(pdev, NULL); - kfree(adckey); - free_irq(gpio_to_irq(pdata->adc_key->pin_playon), NULL); - gpio_free(pdata->adc_key->pin_playon); - return 0; -} - -static struct platform_driver rk28_adckey_driver = -{ - .probe = rk28_adckey_probe, - .remove = __devexit_p(rk28_adckey_remove), - .suspend = rk28_adckey_suspend, - .resume = rk28_adckey_resume, - .driver = { - .name = "rk2818-adckey", - .owner = THIS_MODULE, - }, -}; - - int __init rk28_adckey_init(void) -{ - return platform_driver_register(&rk28_adckey_driver); -} - -static void __exit rk28_adckey_exit(void) -{ - platform_driver_unregister(&rk28_adckey_driver); -} - -module_init(rk28_adckey_init); -module_exit(rk28_adckey_exit); - -MODULE_DESCRIPTION("rk2818 adc Key Controller Driver"); -MODULE_AUTHOR("luowei lw@rock-chips.com"); -MODULE_LICENSE("GPL"); - diff --git a/drivers/input/keyboard/rk2818_hskey.c b/drivers/input/keyboard/rk2818_hskey.c deleted file mode 100644 index f8bc0bde5dec..000000000000 --- a/drivers/input/keyboard/rk2818_hskey.c +++ /dev/null @@ -1,284 +0,0 @@ -/* - * linux/drivers/input/keyboard/rk28_adckey.c - * - * This driver program support to AD key which use for rk28 chip - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#if 1 -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -//#define KEY_PHYS_NAME "rk2818_adckey/input0" - -static unsigned int gLastKeyCode = 0; -static int gSampleTimes = 0; -static int gADValue = 0; -static struct rk28_hskey *phsKey; - -//key code tab -struct rk28_hskey -{ - struct input_dev *input_dev; - struct timer_list timer; - unsigned char * keycodes; -}; - -extern int headset_status(void); -extern unsigned int rk28_get_keycode(unsigned int advalue,pADC_keyst ptab,struct adc_key_data *rk2818_adckey_data); - -#if 0 -unsigned int rk28_get_keycode(unsigned int advalue,pADC_keyst ptab,struct adc_key_data *rk2818_adckey_data) -{ - while(ptab->adc_keycode != 0) - { - if((ptab->adc_value == 0)&&(advalue >= 0 && advalue <= 5)) - return ptab->adc_keycode; - if((advalue > ptab->adc_value - rk2818_adckey_data->adc_drift) && (advalue < ptab->adc_value + rk2818_adckey_data->adc_drift)) - return ptab->adc_keycode; - ptab++; - } - - return 0; -} - -void rk28_send_wakeup_key( void ) -{ - input_report_key(phsKey->input_dev,KEY_WAKEUP,1); - input_sync(phsKey->input_dev); - input_report_key(phsKey->input_dev,KEY_WAKEUP,0); - input_sync(phsKey->input_dev); - DBG("Wake up system\n"); -} -#endif - -static int rk28_Hskey_open(struct input_dev *dev) -{ - //struct rk28_adckey *adckey = input_get_drvdata(dev); - DBG("===========rk28_Hskey_open===========\n"); - return 0; -} - -static void rk28_Hskey_close(struct input_dev *dev) -{ - DBG("===========rk28_Hskey_close===========\n"); - //struct rk28_adckey *adckey = input_get_drvdata(dev); -// -} - -#ifdef CONFIG_PM -static int rk28_hskey_suspend(struct platform_device *pdev, pm_message_t state) -{ - //struct rk28_adckey *adckey = platform_get_drvdata(pdev); - - return 0; -} - -static int rk28_hskey_resume(struct platform_device *pdev) -{ - //struct rk28_adckey *adckey = platform_get_drvdata(pdev); - //struct input_dev *input_dev = adckey->input_dev; -#if 0 - mutex_lock(&input_dev->mutex); - - mutex_unlock(&input_dev->mutex); -#endif - return 0; -} -#else -#define rk28_hskey_suspend NULL -#define rk28_hskey_resume NULL -#endif -static void rk28_hskeyscan_timer(unsigned long data) -{ - unsigned int adcvalue = 0x3FF,code = 0; - struct adc_key_data *rk2818_adckey_data = (struct adc_key_data *)data; - - phsKey->timer.expires = jiffies + msecs_to_jiffies(10); - add_timer(&phsKey->timer); - - if(headset_status()) - { - if(gSampleTimes<4) - { - gADValue += gAdcValue[rk2818_adckey_data->adc_chn]; - gSampleTimes++; - } - else - { - gADValue = gADValue/4; - code=rk28_get_keycode(gADValue,rk2818_adckey_data->adc_key_table,rk2818_adckey_data); - gADValue = 0; - gSampleTimes = 0; - - if(code && !gLastKeyCode) - { - gLastKeyCode = code; - input_report_key(phsKey->input_dev,gLastKeyCode,1); - input_sync(phsKey->input_dev); - DBG("===========headset key press code=%d ===========\n",code); - } - else if(!code && gLastKeyCode) - { - input_report_key(phsKey->input_dev,gLastKeyCode,0); - input_sync(phsKey->input_dev); - gLastKeyCode = 0; - DBG("===========headset key release code=%d ===========\n",code); - } - } - } - else - { - if(gLastKeyCode) - { - input_report_key(phsKey->input_dev,code,0); - input_sync(phsKey->input_dev); - gLastKeyCode = 0; - DBG("===========headset key release code=%d ===========\n",code); - } - gADValue = 0; - gSampleTimes = 0; - } -} - -static int __devinit rk28_adckey_probe(struct platform_device *pdev) -{ - struct rk28_hskey *hskey; - struct input_dev *input_dev; - int error,i,irq_num; - struct rk2818_adckey_platform_data *pdata = pdev->dev.platform_data; - - if (!(pdata->adc_key)) - return -1; - - hskey = kzalloc(sizeof(struct rk28_hskey), GFP_KERNEL); - if (hskey == NULL) { - dev_err(&pdev->dev, "failed to allocate driver data\n"); - return -ENOMEM; - } - - hskey->keycodes = pdata->adc_key->initKeyCode; - - /* Create and register the input driver. */ - input_dev = input_allocate_device(); - if (!input_dev) { - dev_err(&pdev->dev, "failed to allocate input device\n"); - error = -ENOMEM; - goto failed_free; - } - - input_dev->name = pdev->name; - input_dev->open = rk28_Hskey_open; - input_dev->close = rk28_Hskey_close; - input_dev->dev.parent = &pdev->dev; - //input_dev->phys = KEY_PHYS_NAME; - input_dev->id.vendor = 0x0001; - input_dev->id.product = 0x0001; - input_dev->id.version = 0x0100; - - input_dev->keycode = hskey->keycodes; - input_dev->keycodesize = sizeof(unsigned char); - input_dev->keycodemax = pdata->adc_key->adc_key_cnt; - for (i = 0; i < pdata->adc_key->adc_key_cnt; i++) - set_bit(pdata->adc_key->initKeyCode[i], input_dev->keybit); - clear_bit(0, input_dev->keybit); - - hskey->input_dev = input_dev; - input_set_drvdata(input_dev, hskey); - - input_dev->evbit[0] = BIT_MASK(EV_KEY); - - platform_set_drvdata(pdev, hskey); - - phsKey = hskey; - - /* Register the input device */ - error = input_register_device(input_dev); - if (error) { - dev_err(&pdev->dev, "failed to register input device\n"); - goto failed_free_dev; - } - - setup_timer(&hskey->timer, rk28_hskeyscan_timer, (unsigned long)(pdata->adc_key)); - hskey->timer.expires = jiffies+50; - add_timer(&hskey->timer); - printk(KERN_INFO "rk2818_hskey: driver initialized\n"); - return 0; - -free_gpio_irq: - free_irq(irq_num,NULL); -free_gpio: - gpio_free(pdata->adc_key->pin_playon); -failed_free_dev: - platform_set_drvdata(pdev, NULL); - input_free_device(input_dev); -failed_free: - kfree(hskey); - return error; -} - -static int __devexit rk28_adckey_remove(struct platform_device *pdev) -{ - struct rk28_hskey *adckey = platform_get_drvdata(pdev); - struct rk2818_adckey_platform_data *pdata = pdev->dev.platform_data; - - input_unregister_device(adckey->input_dev); - input_free_device(adckey->input_dev); - platform_set_drvdata(pdev, NULL); - kfree(adckey); - return 0; -} - -static struct platform_driver rk28_hskey_driver = -{ - .probe = rk28_adckey_probe, - .remove = __devexit_p(rk28_adckey_remove), - .suspend = rk28_hskey_suspend, - .resume = rk28_hskey_resume, - .driver = { - .name = "rk2818-hskey", - .owner = THIS_MODULE, - }, -}; - -int __init rk28_hskey_init(void) -{ - return platform_driver_register(&rk28_hskey_driver); -} - -static void __exit rk28_hskey_exit(void) -{ - platform_driver_unregister(&rk28_hskey_driver); -} - -module_init(rk28_hskey_init); -module_exit(rk28_hskey_exit); - -MODULE_DESCRIPTION("rk2818 headset Key Controller Driver"); -MODULE_AUTHOR("luowei lw@rock-chips.com"); -MODULE_LICENSE("GPL"); - diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index 4d09c940026b..741273af3701 100755 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig @@ -63,31 +63,6 @@ config TOUCHSCREEN_XPT2046_SPI tristate "320X480 resolution" depends on TOUCHSCREEN_XPT2046_CBN_SPI -#choice -# prompt "XPT2046 based touchscreens: SPI Interface" -# default TOUCHSCREEN_XPT2046_CBN_SPI - -# config TOUCHSCREEN_XPT2046_SPI_NOCHOOSE -# bool "DO NOT CHOOSE TOUCHSCREEN_XPT2046" - -# config TOUCHSCREEN_XPT2046_SPI -# bool "800X480 TOUCHSCREEN" -# depends on SPIM_RK2818 || SPIM_RK29 - -# config TOUCHSCREEN_XPT2046_CBN_SPI -# bool "800X480 CALIBRATION TOUCHSCREEN" -# depends on SPIM_RK2818 || SPIM_RK29 - -# config TOUCHSCREEN_XPT2046_320X480_SPI -# bool "320X480 TOUCHSCREEN" -# depends on SPIM_RK2818 || SPIM_RK29 - -# config TOUCHSCREEN_XPT2046_320X480_CBN_SPI -# bool "320X480 CALIBRATION TOUCHSCREEN" -# depends on SPIM_RK2818 || SPIM_RK29 -#endchoice - - config TOUCHSCREEN_ADS7846 tristate "ADS7846/TSC2046 and ADS7843 based touchscreens" depends on SPI_MASTER diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig index 2cdc75d174df..b63c26c508d4 100755 --- a/drivers/media/video/Kconfig +++ b/drivers/media/video/Kconfig @@ -1069,14 +1069,6 @@ config VIDEO_OMAP2 ---help--- This is a v4l2 driver for the TI OMAP2 camera capture interface - -config VIDEO_RK2818 - tristate "RK2818 Camera Sensor Interface driver" - depends on VIDEO_DEV && ARCH_RK2818 && SOC_CAMERA && HAS_DMA - select VIDEOBUF_DMA_CONTIG - ---help--- - This is a v4l2 driver for the RK2818 Camera Sensor Interface - config VIDEO_RK29 tristate "RK29XX Camera Sensor Interface driver" depends on VIDEO_DEV && ARCH_RK29 && SOC_CAMERA && HAS_DMA diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile index 782dd3454255..9d3c5674e535 100755 --- a/drivers/media/video/Makefile +++ b/drivers/media/video/Makefile @@ -176,7 +176,6 @@ obj-$(CONFIG_VIDEO_MX1) += mx1_camera.o obj-$(CONFIG_VIDEO_MX3) += mx3_camera.o obj-$(CONFIG_VIDEO_PXA27x) += pxa_camera.o obj-$(CONFIG_VIDEO_SH_MOBILE_CEU) += sh_mobile_ceu_camera.o -obj-$(CONFIG_VIDEO_RK2818) += rk2818_camera.o obj-$(CONFIG_VIDEO_RK29_WORK_ONEFRAME) += rk29_camera_oneframe.o obj-$(CONFIG_VIDEO_RK29_WORK_PINGPONG) += rk29_camera_pingpong.o diff --git a/drivers/media/video/rk2818_camera.c b/drivers/media/video/rk2818_camera.c deleted file mode 100644 index f516a4588142..000000000000 --- a/drivers/media/video/rk2818_camera.c +++ /dev/null @@ -1,1128 +0,0 @@ -/* - * V4L2 Driver for RK28 camera host - * - * Copyright (C) 2006, Sascha Hauer, Pengutronix - * Copyright (C) 2008, Guennadi Liakhovetski - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - - -#define RK28_VIP_AHBR_CTRL 0x00 -#define RK28_VIP_INT_MASK 0x04 -#define RK28_VIP_INT_STS 0x08 -#define RK28_VIP_STS 0x0c -#define RK28_VIP_CTRL 0x10 -#define RK28_VIP_CAPTURE_F1SA_Y 0x14 -#define RK28_VIP_CAPTURE_F1SA_UV 0x18 -#define RK28_VIP_CAPTURE_F1SA_Cr 0x1c -#define RK28_VIP_CAPTURE_F2SA_Y 0x20 -#define RK28_VIP_CAPTURE_F2SA_UV 0x24 -#define RK28_VIP_CAPTURE_F2SA_Cr 0x28 -#define RK28_VIP_FB_SR 0x2c -#define RK28_VIP_FS 0x30 -#define RK28_VIP_VIPRESERVED 0x34 -#define RK28_VIP_CROP 0x38 -#define RK28_VIP_CRM 0x3c -#define RK28_VIP_RESET 0x40 -#define RK28_VIP_L_SFT 0x44 - -#define RK28_CPU_API_REG (RK2818_REGFILE_BASE+0x14) - - -//ctrl------------------- -#define DISABLE_CAPTURE 0x00000000 -#define ENABLE_CAPTURE 0x00000001 - -#define VSY_HIGH_ACTIVE 0x00000080 -#define VSY_LOW_ACTIVE 0x00000000 - -#define HSY_HIGH_ACTIVE 0x00000000 -#define HSY_LOW_ACTIVE 0x00000002 - -#define CCIR656 0x00000000 -#define SENSOR 0x00000004 - -#define SENSOR_UYVY 0x00000000 -#define SENSOR_YUYV 0x00000008 - -#define CON_OR_PIN 0x00000000 -#define ONEFRAME 0x00000020 - -#define VIPREGYUV420 0x00000000 -#define VIPREGYUV422 0x00000040 - -#define FIELD0_START 0x00000000 -#define FIELD1_START 0x00000080 - -#define CONTINUOUS 0x00000000 -#define PING_PONG 0x00000100 - -#define POSITIVE_EDGE 0x00000000 -#define NEGATIVE_EDGE 0x00000200 - -#define VIPREGNTSC 0x00000000 -#define VIPREGPAL 0x00000400 -//-------------------------- -#define CONFIG_RK28CAMERA_TR 0 -#define CONFIG_RK28CAMERA_DEBUG 0 -#if (CONFIG_RK28CAMERA_TR) - #define RK28CAMERA_TR(format, ...) printk(format, ## __VA_ARGS__) - #if (CONFIG_RK28CAMERA_DEBUG) - #define RK28CAMERA_DG(format, ...) printk(format, ## __VA_ARGS__) - #else - #define RK28CAMERA_DG(format, ...) - #endif -#else - #define RK28CAMERA_TR(format, ...) - #define RK28CAMERA_DG(format, ...) -#endif - -#define MIN(x,y) ((xy) ? x: y) -#define RK28_SENSOR_24MHZ 24 /* MHz */ -#define RK28_SENSOR_48MHZ 48 - - -#define RK28_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5) - -/* limit to rk28 hardware capabilities */ -#define RK28_CAM_BUS_PARAM (SOCAM_MASTER |\ - SOCAM_HSYNC_ACTIVE_HIGH |\ - SOCAM_HSYNC_ACTIVE_LOW |\ - SOCAM_VSYNC_ACTIVE_HIGH |\ - SOCAM_VSYNC_ACTIVE_LOW |\ - SOCAM_PCLK_SAMPLE_RISING |\ - SOCAM_PCLK_SAMPLE_FALLING|\ - SOCAM_DATA_ACTIVE_HIGH |\ - SOCAM_DATA_ACTIVE_LOW|\ - SOCAM_DATAWIDTH_8 |SOCAM_MCLK_24MHZ |SOCAM_MCLK_48MHZ) - -#define RK28_CAM_W_MIN 48 -#define RK28_CAM_H_MIN 32 -#define RK28_CAM_W_MAX 3856 /* ddl@rock-chips.com : 10M Pixel */ -#define RK28_CAM_H_MAX 2764 -#define RK28_CAM_FRAME_INVAL 3 /* ddl@rock-chips.com : */ - -static DEFINE_MUTEX(camera_lock); - - -#define write_vip_reg(addr, val) __raw_writel(val, addr+(rk28_camdev_info_ptr->base)) -#define read_vip_reg(addr) __raw_readl(addr+(rk28_camdev_info_ptr->base)) -#define mask_vip_reg addr, msk, val) write_vip_reg(addr, (val)|((~(msk))&read_vip_reg(addr))) - -#define set_vip_vsp(val) __raw_writel(((val) | __raw_readl(RK28_CPU_API_REG)), RK28_CPU_API_REG) - -extern void videobuf_dma_contig_free(struct videobuf_queue *q, struct videobuf_buffer *buf); -extern dma_addr_t videobuf_to_dma_contig(struct videobuf_buffer *buf); -extern void videobuf_queue_dma_contig_init(struct videobuf_queue *q, - struct videobuf_queue_ops *ops, - struct device *dev, - spinlock_t *irqlock, - enum v4l2_buf_type type, - enum v4l2_field field, - unsigned int msize, - void *priv); - -/* buffer for one video frame */ -struct rk28_buffer -{ - /* common v4l buffer stuff -- must be first */ - struct videobuf_buffer vb; - const struct soc_camera_data_format *fmt; - int inwork; -}; - -struct rk28_camera_dev -{ - struct soc_camera_host soc_host; - struct device *dev; - /* RK2827x is only supposed to handle one camera on its Quick Capture - * interface. If anyone ever builds hardware to enable more than - * one camera, they will have to modify this driver too */ - struct soc_camera_device *icd; - struct clk *clk; - void __iomem *base; - unsigned int frame_inval; /* ddl@rock-chips.com : The first frames is invalidate */ - unsigned int irq; - - struct rk28camera_platform_data *pdata; - struct resource *res; - - struct list_head capture; - - spinlock_t lock; - - struct videobuf_buffer *active; - struct videobuf_queue *vb_vidq_ptr; -}; - -static const char *rk28_cam_driver_description = "RK28_Camera"; -static struct rk28_camera_dev *rk28_camdev_info_ptr; -/* - * Videobuf operations - */ -static int rk28_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, - unsigned int *size) -{ - struct soc_camera_device *icd = vq->priv_data; - int bytes_per_pixel = (icd->current_fmt->depth + 7) >> 3; - - dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size); - - /* planar capture requires Y, U and V buffers to be page aligned */ - *size = PAGE_ALIGN( icd->user_width * icd->user_height * bytes_per_pixel); /* Y pages UV pages, yuv422*/ - - RK28CAMERA_DG("\n%s..%d.. size = %d\n",__FUNCTION__,__LINE__, *size); - - return 0; -} -static void rk28_videobuf_free(struct videobuf_queue *vq, struct rk28_buffer *buf) -{ - struct soc_camera_device *icd = vq->priv_data; - - dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %zd\n", __func__, - &buf->vb, buf->vb.baddr, buf->vb.bsize); - - /* ddl@rock-chips.com: buf_release called soc_camera_streamoff and soc_camera_close*/ - if (buf->vb.state == VIDEOBUF_NEEDS_INIT) - return; - - if (in_interrupt()) - BUG(); - - videobuf_dma_contig_free(vq, &buf->vb); - dev_dbg(&icd->dev, "%s freed\n", __func__); - buf->vb.state = VIDEOBUF_NEEDS_INIT; - -} -static int rk28_videobuf_prepare(struct videobuf_queue *vq, struct videobuf_buffer *vb, enum v4l2_field field) -{ - struct soc_camera_device *icd = vq->priv_data; - struct rk28_buffer *buf; - int ret; - - buf = container_of(vb, struct rk28_buffer, vb); - - dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %zd\n", __func__, - vb, vb->baddr, vb->bsize); - - //RK28CAMERA_TR("\n%s..%d.. \n",__FUNCTION__,__LINE__); - - /* Added list head initialization on alloc */ - WARN_ON(!list_empty(&vb->queue)); - - /* This can be useful if you want to see if we actually fill - * the buffer with something */ - //memset((void *)vb->baddr, 0xaa, vb->bsize); - - BUG_ON(NULL == icd->current_fmt); - - if (buf->fmt != icd->current_fmt || - vb->width != icd->user_width || - vb->height != icd->user_height || - vb->field != field) { - buf->fmt = icd->current_fmt; - vb->width = icd->user_width; - vb->height = icd->user_height; - vb->field = field; - vb->state = VIDEOBUF_NEEDS_INIT; - } - - vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3) ; /* ddl@rock-chips.com : fmt->depth is coorect */ - if (0 != vb->baddr && vb->bsize < vb->size) { - ret = -EINVAL; - goto out; - } - - if (vb->state == VIDEOBUF_NEEDS_INIT) { - ret = videobuf_iolock(vq, vb, NULL); - if (ret) { - goto fail; - } - vb->state = VIDEOBUF_PREPARED; - } - //RK28CAMERA_TR("\n%s..%d.. \n",__FUNCTION__,__LINE__); - return 0; -fail: - rk28_videobuf_free(vq, buf); -out: - return ret; -} - -static inline void rk28_videobuf_capture(struct videobuf_buffer *vb) -{ - unsigned int size; - - if (vb) { - size = vb->width * vb->height; /* Y pages UV pages, yuv422*/ - write_vip_reg(RK28_VIP_CAPTURE_F1SA_Y, vb->boff); - write_vip_reg(RK28_VIP_CAPTURE_F1SA_UV, vb->boff + size); - write_vip_reg(RK28_VIP_CAPTURE_F2SA_Y, vb->boff); - write_vip_reg(RK28_VIP_CAPTURE_F2SA_UV, vb->boff + size); - write_vip_reg(RK28_VIP_FB_SR, 0x00000002);//frame1 has been ready to receive data,frame 2 is not used - } -} - -static void rk28_videobuf_queue(struct videobuf_queue *vq, - struct videobuf_buffer *vb) -{ - struct soc_camera_device *icd = vq->priv_data; - struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); - struct rk28_camera_dev *pcdev = ici->priv; - unsigned long flags; - - dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %zd\n", __func__, - vb, vb->baddr, vb->bsize); - - vb->state = VIDEOBUF_ACTIVE; - spin_lock_irqsave(&pcdev->lock, flags); - if (!list_empty(&pcdev->capture)) { - list_add_tail(&vb->queue, &pcdev->capture); - } else { - if (list_entry(pcdev->capture.next, struct videobuf_buffer, queue) != vb) - list_add_tail(&vb->queue, &pcdev->capture); - else - BUG(); /* ddl@rock-chips.com : The same videobuffer queue again */ - } - - if (!pcdev->active) { - pcdev->active = vb; - rk28_videobuf_capture(vb); - } - spin_unlock_irqrestore(&pcdev->lock, flags); -} - -static irqreturn_t rk28_camera_irq(int irq, void *data) -{ - struct rk28_camera_dev *pcdev = data; - struct videobuf_buffer *vb; - - read_vip_reg(RK28_VIP_INT_STS); /* clear vip interrupte single */ - - /* ddl@rock-chps.com : Current VIP is run in One Frame Mode, Frame 1 is validate */ - if (read_vip_reg(RK28_VIP_FB_SR) & 0x01) { - - if (!pcdev->active) - goto RK28_CAMERA_IRQ_END; - - if ((pcdev->frame_inval>0) && (pcdev->frame_inval<=RK28_CAM_FRAME_INVAL)) { - pcdev->frame_inval--; - rk28_videobuf_capture(pcdev->active); - goto RK28_CAMERA_IRQ_END; - } else if (pcdev->frame_inval) { - printk("frame_inval : %0x",pcdev->frame_inval); - pcdev->frame_inval = 0; - } - - vb = pcdev->active; - list_del_init(&vb->queue); - - if (!list_empty(&pcdev->capture)) { - pcdev->active = list_entry(pcdev->capture.next, struct videobuf_buffer, queue); - } else { - pcdev->active = NULL; - } - - rk28_videobuf_capture(pcdev->active); - - vb->state = VIDEOBUF_DONE; - do_gettimeofday(&vb->ts); - vb->field_count++; - wake_up(&vb->done); - } - -RK28_CAMERA_IRQ_END: - return IRQ_HANDLED; -} - - -static void rk28_videobuf_release(struct videobuf_queue *vq, - struct videobuf_buffer *vb) -{ - struct rk28_buffer *buf = container_of(vb, struct rk28_buffer, vb); -#ifdef DEBUG - struct soc_camera_device *icd = vq->priv_data; - - dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, - vb, vb->baddr, vb->bsize); - - switch (vb->state) - { - case VIDEOBUF_ACTIVE: - dev_dbg(&icd->dev, "%s (active)\n", __func__); - break; - case VIDEOBUF_QUEUED: - dev_dbg(&icd->dev, "%s (queued)\n", __func__); - break; - case VIDEOBUF_PREPARED: - dev_dbg(&icd->dev, "%s (prepared)\n", __func__); - break; - default: - dev_dbg(&icd->dev, "%s (unknown)\n", __func__); - break; - } -#endif - - rk28_videobuf_free(vq, buf); -} - -static struct videobuf_queue_ops rk28_videobuf_ops = -{ - .buf_setup = rk28_videobuf_setup, - .buf_prepare = rk28_videobuf_prepare, - .buf_queue = rk28_videobuf_queue, - .buf_release = rk28_videobuf_release, -}; - -static void rk28_camera_init_videobuf(struct videobuf_queue *q, - struct soc_camera_device *icd) -{ - struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); - struct rk28_camera_dev *pcdev = ici->priv; - - /* We must pass NULL as dev pointer, then all pci_* dma operations - * transform to normal dma_* ones. */ - videobuf_queue_dma_contig_init(q, - &rk28_videobuf_ops, - ici->v4l2_dev.dev, &pcdev->lock, - V4L2_BUF_TYPE_VIDEO_CAPTURE, - V4L2_FIELD_NONE, - sizeof(struct rk28_buffer), - icd); - pcdev->vb_vidq_ptr = q; /* ddl@rock-chips.com */ -} -static int rk28_camera_activate(struct rk28_camera_dev *pcdev, struct soc_camera_device *icd) -{ - unsigned long sensor_bus_flags = SOCAM_MCLK_24MHZ; - struct clk *parent; - - RK28CAMERA_DG("\n%s..%d.. \n",__FUNCTION__,__LINE__); - if (!pcdev->clk || IS_ERR(pcdev->clk)) - RK28CAMERA_TR(KERN_ERR "failed to get vip_clk source\n"); - - //if (icd->ops->query_bus_param) /* ddl@rock-chips.com : Query Sensor's xclk */ - //sensor_bus_flags = icd->ops->query_bus_param(icd); - - if (sensor_bus_flags & SOCAM_MCLK_48MHZ) { - parent = clk_get(NULL, "clk48m"); - if (!parent || IS_ERR(parent)) - goto RK28_CAMERA_ACTIVE_ERR; - } else if (sensor_bus_flags & SOCAM_MCLK_27MHZ) { - parent = clk_get(NULL, "extclk"); - if (!parent || IS_ERR(parent)) - goto RK28_CAMERA_ACTIVE_ERR; - } else { - parent = clk_get(NULL, "xin24m"); - if (!parent || IS_ERR(parent)) - goto RK28_CAMERA_ACTIVE_ERR; - } - - clk_set_parent(pcdev->clk, parent); - - clk_enable(pcdev->clk); - rk2818_mux_api_set(GPIOF6_VIPCLK_SEL_NAME, IOMUXB_VIP_CLKOUT); - ndelay(10); - - write_vip_reg(RK28_VIP_RESET, 0x76543210); /* ddl@rock-chips.com : vip software reset */ - udelay(10); - - write_vip_reg(RK28_VIP_AHBR_CTRL, 0x07); /* ddl@rock-chips.com : vip ahb burst 16 */ - write_vip_reg(RK28_VIP_INT_MASK, 0x01); //capture complete interrupt enable - write_vip_reg(RK28_VIP_CRM, 0x00000000); //Y/CB/CR color modification - - return 0; -RK28_CAMERA_ACTIVE_ERR: - return -ENODEV; -} - -static void rk28_camera_deactivate(struct rk28_camera_dev *pcdev) -{ - pcdev->active = NULL; - - write_vip_reg(RK28_VIP_CTRL, 0); - read_vip_reg(RK28_VIP_INT_STS); //clear vip interrupte single - - rk2818_mux_api_set(GPIOF6_VIPCLK_SEL_NAME, IOMUXB_GPIO1_B6); - clk_disable(pcdev->clk); - - return; -} - -/* The following two functions absolutely depend on the fact, that - * there can be only one camera on RK28 quick capture interface */ -static int rk28_camera_add_device(struct soc_camera_device *icd) -{ - struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); - struct rk28_camera_dev *pcdev = ici->priv; - struct device *control = to_soc_camera_control(icd); - struct v4l2_subdev *sd; - int ret; - - mutex_lock(&camera_lock); - - if (pcdev->icd) { - ret = -EBUSY; - goto ebusy; - } - - dev_info(&icd->dev, "RK28 Camera driver attached to camera %d\n", - icd->devnum); - - pcdev->frame_inval = RK28_CAM_FRAME_INVAL; - pcdev->active = NULL; - pcdev->icd = NULL; - /* ddl@rock-chips.com: capture list must be reset, because this list may be not empty, - * if app havn't dequeue all videobuf before close camera device; - */ - INIT_LIST_HEAD(&pcdev->capture); - - ret = rk28_camera_activate(pcdev,icd); - if (ret) - goto ebusy; - - /* ddl@rock-chips.com : v4l2_subdev is not created when ici->ops->add called in soc_camera_probe */ - if (control) { - sd = dev_get_drvdata(control); - ret = v4l2_subdev_call(sd,core, init, 0); - if (ret) - goto ebusy; - } - - pcdev->icd = icd; - -ebusy: - mutex_unlock(&camera_lock); - - return ret; -} -static void rk28_camera_remove_device(struct soc_camera_device *icd) -{ - struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); - struct rk28_camera_dev *pcdev = ici->priv; - - BUG_ON(icd != pcdev->icd); - - dev_info(&icd->dev, "RK28 Camera driver detached from camera %d\n", - icd->devnum); - - rk28_camera_deactivate(pcdev); - - /* ddl@rock-chips.com: Call videobuf_mmap_free here for free the struct video_buffer which malloc in videobuf_alloc */ - if (pcdev->vb_vidq_ptr) { - videobuf_mmap_free(pcdev->vb_vidq_ptr); - pcdev->vb_vidq_ptr = NULL; - } - - pcdev->active = NULL; - pcdev->icd = NULL; - /* ddl@rock-chips.com: capture list must be reset, because this list may be not empty, - * if app havn't dequeue all videobuf before close camera device; - */ - INIT_LIST_HEAD(&pcdev->capture); - - return; -} - -static int rk28_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) -{ - unsigned long bus_flags, camera_flags, common_flags; - unsigned int vip_ctrl_val = 0; - int ret = 0; - - RK28CAMERA_DG("\n%s..%d..\n",__FUNCTION__,__LINE__); - - bus_flags = RK28_CAM_BUS_PARAM; - - camera_flags = icd->ops->query_bus_param(icd); - common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags); - if (!common_flags) { - ret = -EINVAL; - goto RK28_CAMERA_SET_BUS_PARAM_END; - } - - ret = icd->ops->set_bus_param(icd, common_flags); - if (ret < 0) - goto RK28_CAMERA_SET_BUS_PARAM_END; - - icd->buswidth = 8; - - vip_ctrl_val = read_vip_reg(RK28_VIP_CTRL); - if (common_flags & SOCAM_PCLK_SAMPLE_FALLING) - vip_ctrl_val |= NEGATIVE_EDGE; - if (common_flags & SOCAM_HSYNC_ACTIVE_LOW) - vip_ctrl_val |= HSY_LOW_ACTIVE; - if (common_flags & SOCAM_VSYNC_ACTIVE_HIGH) - set_vip_vsp(VSY_HIGH_ACTIVE); - - /* ddl@rock-chips.com : Don't enable capture here, enable in stream_on */ - //vip_ctrl_val |= ENABLE_CAPTURE; - - write_vip_reg(RK28_VIP_CTRL, vip_ctrl_val); - RK28CAMERA_DG("\n%s..CtrReg=%x \n",__FUNCTION__,read_vip_reg(RK28_VIP_CTRL)); - -RK28_CAMERA_SET_BUS_PARAM_END: - if (ret) - RK28CAMERA_TR("\n%s..%d.. ret = %d \n",__FUNCTION__,__LINE__, ret); - return ret; -} - -static int rk28_camera_try_bus_param(struct soc_camera_device *icd, __u32 pixfmt) -{ - unsigned long bus_flags, camera_flags; - int ret; - - bus_flags = RK28_CAM_BUS_PARAM; - - camera_flags = icd->ops->query_bus_param(icd); - ret = soc_camera_bus_param_compatible(camera_flags, bus_flags) ; - - if (ret < 0) - dev_warn(icd->dev.parent, - "Flags incompatible: camera %lx, host %lx\n", - camera_flags, bus_flags); - return ret; -} -static const struct soc_camera_data_format rk28_camera_formats[] = { - { - .name = "Planar YUV420 12 bit", - .depth = 12, - .fourcc = V4L2_PIX_FMT_YUV420, - .colorspace = V4L2_COLORSPACE_JPEG, - },{ - .name = "Planar YUV422 16 bit", - .depth = 16, - .fourcc = V4L2_PIX_FMT_YUV422P, - .colorspace = V4L2_COLORSPACE_JPEG, - }, -}; - -static void rk28_camera_setup_format(struct soc_camera_device *icd, __u32 host_pixfmt, __u32 cam_pixfmt, struct v4l2_rect *rect) -{ - unsigned int vip_fs,vip_crop; - unsigned int vip_ctrl_val = SENSOR | ONEFRAME |DISABLE_CAPTURE; - - switch (host_pixfmt) - { - case V4L2_PIX_FMT_YUV422P: - vip_ctrl_val |= VIPREGYUV422; - break; - case V4L2_PIX_FMT_YUV420: - vip_ctrl_val |= VIPREGYUV420; - break; - default: /* ddl@rock-chips.com : vip output format is hold when pixfmt is invalidate */ - vip_ctrl_val |= (read_vip_reg(RK28_VIP_CTRL) & VIPREGYUV422); - break; - } - - switch (cam_pixfmt) - { - case V4L2_PIX_FMT_UYVY: - vip_ctrl_val |= SENSOR_UYVY; - break; - case V4L2_PIX_FMT_YUYV: - vip_ctrl_val |= SENSOR_YUYV; - break; - default : - vip_ctrl_val |= (read_vip_reg(RK28_VIP_CTRL) & SENSOR_YUYV); - break; - } - - write_vip_reg(RK28_VIP_CTRL, vip_ctrl_val); /* ddl@rock-chips.com: VIP capture mode and capture format must be set before FS register set */ - - read_vip_reg(RK28_VIP_INT_STS); /* clear vip interrupte single */ - - if (vip_ctrl_val & ONEFRAME) { - vip_crop = ((rect->left<<16) + rect->top); - vip_fs = (((rect->width + rect->left)<<16) + (rect->height+rect->top)); - } else if (vip_ctrl_val & PING_PONG) { - WARN_ON(rect->left ||rect->top ); - RK28CAMERA_DG("\n %s..PingPang not support Crop \n",__FUNCTION__); - return; - } - - write_vip_reg(RK28_VIP_CROP, vip_crop); - write_vip_reg(RK28_VIP_FS, vip_fs); - - write_vip_reg(RK28_VIP_FB_SR, 0x00000003); - - RK28CAMERA_DG("\n%s.. crop:%x .. fs : %x\n",__FUNCTION__,vip_crop,vip_fs); -} - -static int rk28_camera_get_formats(struct soc_camera_device *icd, int idx, - struct soc_camera_format_xlate *xlate) -{ - struct device *dev = icd->dev.parent; - int formats = 0, buswidth, ret; - - buswidth = 8; - - ret = rk28_camera_try_bus_param(icd, buswidth); - if (ret < 0) - return 0; - - switch (icd->formats[idx].fourcc) { - case V4L2_PIX_FMT_UYVY: - case V4L2_PIX_FMT_YUYV: - formats++; - if (xlate) { - xlate->host_fmt = &rk28_camera_formats[0]; - xlate->cam_fmt = icd->formats + idx; - xlate->buswidth = buswidth; - xlate++; - dev_dbg(dev, "Providing format %s using %s\n", - rk28_camera_formats[0].name, - icd->formats[idx].name); - } - - formats++; - if (xlate) { - xlate->host_fmt = &rk28_camera_formats[1]; - xlate->cam_fmt = icd->formats + idx; - xlate->buswidth = buswidth; - xlate++; - dev_dbg(dev, "Providing format %s using %s\n", - rk28_camera_formats[1].name, - icd->formats[idx].name); - } - default: - break; - } - - return formats; -} - -static void rk28_camera_put_formats(struct soc_camera_device *icd) -{ - return; -} - -static int rk28_camera_set_crop(struct soc_camera_device *icd, - struct v4l2_crop *a) -{ - struct v4l2_subdev *sd = soc_camera_to_subdev(icd); - struct v4l2_format f; - struct v4l2_pix_format *pix = &f.fmt.pix; - int ret; - - f.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; - - ret = v4l2_subdev_call(sd, video, g_fmt, &f); - if (ret < 0) - return ret; - - if ((pix->width < (a->c.left + a->c.width)) || (pix->height < (a->c.top + a->c.height))) { - - pix->width = a->c.left + a->c.width; - pix->height = a->c.top + a->c.height; - - v4l_bound_align_image(&pix->width, 48, 2048, 1, - &pix->height, 32, 2048, 0, - icd->current_fmt->fourcc == V4L2_PIX_FMT_YUV422P ?4 : 0); - - ret = v4l2_subdev_call(sd, video, s_fmt, &f); - if (ret < 0) - return ret; - } - - rk28_camera_setup_format(icd, icd->current_fmt->fourcc, pix->pixelformat, &a->c); - - icd->user_width = pix->width; - icd->user_height = pix->height; - - return 0; -} - -static int rk28_camera_set_fmt(struct soc_camera_device *icd, - struct v4l2_format *f) -{ - struct device *dev = icd->dev.parent; - struct v4l2_subdev *sd = soc_camera_to_subdev(icd); - const struct soc_camera_data_format *cam_fmt = NULL; - const struct soc_camera_format_xlate *xlate = NULL; - struct v4l2_pix_format *pix = &f->fmt.pix; - struct v4l2_format cam_f = *f; - struct v4l2_rect rect; - int ret; - - RK28CAMERA_DG("\n%s..%d.. \n",__FUNCTION__,__LINE__); - - xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); - if (!xlate) { - dev_err(dev, "Format %x not found\n", pix->pixelformat); - ret = -EINVAL; - goto RK28_CAMERA_SET_FMT_END; - } - - cam_fmt = xlate->cam_fmt; - - cam_f.fmt.pix.pixelformat = cam_fmt->fourcc; - ret = v4l2_subdev_call(sd, video, s_fmt, &cam_f); - cam_f.fmt.pix.pixelformat = pix->pixelformat; - *pix = cam_f.fmt.pix; - - icd->sense = NULL; - - if (!ret) { - rect.left = 0; - rect.top = 0; - rect.width = pix->width; - rect.height = pix->height; - - RK28CAMERA_DG("\n%s..%s..%s \n",__FUNCTION__,xlate->host_fmt->name, cam_fmt->name); - rk28_camera_setup_format(icd, pix->pixelformat, cam_fmt->fourcc, &rect); - - icd->buswidth = xlate->buswidth; - icd->current_fmt = xlate->host_fmt; - } - -RK28_CAMERA_SET_FMT_END: - if (ret) - RK28CAMERA_TR("\n%s..%d.. ret = %d \n",__FUNCTION__,__LINE__, ret); - return ret; -} - -static int rk28_camera_try_fmt(struct soc_camera_device *icd, - struct v4l2_format *f) -{ - struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); - struct v4l2_subdev *sd = soc_camera_to_subdev(icd); - const struct soc_camera_format_xlate *xlate; - struct v4l2_pix_format *pix = &f->fmt.pix; - __u32 pixfmt = pix->pixelformat; - enum v4l2_field field; - int ret; - - RK28CAMERA_DG("\n%s..%d.. \n",__FUNCTION__,__LINE__); - - xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); - if (!xlate) { - dev_err(ici->v4l2_dev.dev, "Format %x not found\n", pixfmt); - ret = -EINVAL; - goto RK28_CAMERA_TRY_FMT_END; - } - /* limit to rk28 hardware capabilities */ - v4l_bound_align_image(&pix->width, RK28_CAM_W_MIN, RK28_CAM_W_MAX, 1, - &pix->height, RK28_CAM_H_MIN, RK28_CAM_H_MAX, 0, - pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0); - - pix->bytesperline = pix->width * - DIV_ROUND_UP(xlate->host_fmt->depth, 8); - pix->sizeimage = pix->height * pix->bytesperline; - - /* camera has to see its format, but the user the original one */ - pix->pixelformat = xlate->cam_fmt->fourcc; - /* limit to sensor capabilities */ - ret = v4l2_subdev_call(sd, video, try_fmt, f); - pix->pixelformat = pixfmt; - - field = pix->field; - - if (field == V4L2_FIELD_ANY) { - pix->field = V4L2_FIELD_NONE; - } else if (field != V4L2_FIELD_NONE) { - dev_err(icd->dev.parent, "Field type %d unsupported.\n", field); - ret = -EINVAL; - goto RK28_CAMERA_TRY_FMT_END; - } - -RK28_CAMERA_TRY_FMT_END: - if (ret) - RK28CAMERA_TR("\n%s..%d.. ret = %d \n",__FUNCTION__,__LINE__, ret); - return ret; -} - -static int rk28_camera_reqbufs(struct soc_camera_file *icf, - struct v4l2_requestbuffers *p) -{ - int i; - - /* This is for locking debugging only. I removed spinlocks and now I - * check whether .prepare is ever called on a linked buffer, or whether - * a dma IRQ can occur for an in-work or unlinked buffer. Until now - * it hadn't triggered */ - for (i = 0; i < p->count; i++) { - struct rk28_buffer *buf = container_of(icf->vb_vidq.bufs[i], - struct rk28_buffer, vb); - buf->inwork = 0; - INIT_LIST_HEAD(&buf->vb.queue); - } - - return 0; -} - -static unsigned int rk28_camera_poll(struct file *file, poll_table *pt) -{ - struct soc_camera_file *icf = file->private_data; - struct rk28_buffer *buf; - - buf = list_entry(icf->vb_vidq.stream.next, struct rk28_buffer, - vb.stream); - - poll_wait(file, &buf->vb.done, pt); - - if (buf->vb.state == VIDEOBUF_DONE || - buf->vb.state == VIDEOBUF_ERROR) - return POLLIN|POLLRDNORM; - - return 0; -} - -static int rk28_camera_querycap(struct soc_camera_host *ici, - struct v4l2_capability *cap) -{ - /* cap->name is set by the firendly caller:-> */ - strlcpy(cap->card, rk28_cam_driver_description, sizeof(cap->card)); - cap->version = RK28_CAM_VERSION_CODE; - cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; - - return 0; -} - -static int rk28_camera_suspend(struct soc_camera_device *icd, pm_message_t state) -{ - struct soc_camera_host *ici = - to_soc_camera_host(icd->dev.parent); - struct rk28_camera_dev *pcdev = ici->priv; - int ret = 0; - - if ((pcdev->icd) && (pcdev->icd->ops->suspend)) - ret = pcdev->icd->ops->suspend(pcdev->icd, state); - - return ret; -} - -static int rk28_camera_resume(struct soc_camera_device *icd) -{ - struct soc_camera_host *ici = - to_soc_camera_host(icd->dev.parent); - struct rk28_camera_dev *pcdev = ici->priv; - int ret = 0; - - if ((pcdev->icd) && (pcdev->icd->ops->resume)) - ret = pcdev->icd->ops->resume(pcdev->icd); - - return ret; -} - -static int rk28_camera_s_stream(struct soc_camera_device *icd, int enable) -{ - struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); - struct rk28_camera_dev *pcdev = ici->priv; - int vip_ctrl_val; - - WARN_ON(pcdev->icd != icd); - - vip_ctrl_val = read_vip_reg(RK28_VIP_CTRL); - if (enable) { - vip_ctrl_val |= ENABLE_CAPTURE; - } else { - vip_ctrl_val &= ~ENABLE_CAPTURE; - } - write_vip_reg(RK28_VIP_CTRL, vip_ctrl_val); - - RK28CAMERA_DG("%s.. enable : %d\n", __FUNCTION__, enable); - return 0; -} - -static struct soc_camera_host_ops rk28_soc_camera_host_ops = -{ - .owner = THIS_MODULE, - .add = rk28_camera_add_device, - .remove = rk28_camera_remove_device, - .suspend = rk28_camera_suspend, - .resume = rk28_camera_resume, - .set_crop = rk28_camera_set_crop, - .get_formats = rk28_camera_get_formats, - .put_formats = rk28_camera_put_formats, - .set_fmt = rk28_camera_set_fmt, - .try_fmt = rk28_camera_try_fmt, - .init_videobuf = rk28_camera_init_videobuf, - .reqbufs = rk28_camera_reqbufs, - .poll = rk28_camera_poll, - .querycap = rk28_camera_querycap, - .set_bus_param = rk28_camera_set_bus_param, - .s_stream = rk28_camera_s_stream /* ddl@rock-chips.com : Add stream control for host */ -}; -static int rk28_camera_probe(struct platform_device *pdev) -{ - struct rk28_camera_dev *pcdev; - struct resource *res; - int irq; - int err = 0; - - RK28CAMERA_DG("\n%s..%s..%d \n",__FUNCTION__,__FILE__,__LINE__); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - irq = platform_get_irq(pdev, 0); - if (!res || irq < 0) { - err = -ENODEV; - goto exit; - } - - pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL); - if (!pcdev) { - dev_err(&pdev->dev, "Could not allocate pcdev\n"); - err = -ENOMEM; - goto exit_alloc; - } - rk28_camdev_info_ptr = pcdev; - - /*config output clk*/ - pcdev->clk = clk_get(&pdev->dev, "vip"); - if (!pcdev->clk || IS_ERR(pcdev->clk)) { - RK28CAMERA_TR(KERN_ERR "failed to get vip_clk source\n"); - err = -ENOENT; - goto exit_eclkget; - } - - dev_set_drvdata(&pdev->dev, pcdev); - pcdev->res = res; - - pcdev->pdata = pdev->dev.platform_data; /* ddl@rock-chips.com : Request IO in init function */ - if (pcdev->pdata && pcdev->pdata->io_init) { - pcdev->pdata->io_init(); - } - - INIT_LIST_HEAD(&pcdev->capture); - spin_lock_init(&pcdev->lock); - - /* - * Request the regions. - */ - if (!request_mem_region(res->start, res->end - res->start + 1, - RK28_CAM_DRV_NAME)) { - err = -EBUSY; - goto exit_reqmem; - } - - pcdev->base = ioremap(res->start, res->end - res->start + 1); - if (pcdev->base == NULL) { - dev_err(pcdev->dev, "ioremap() of registers failed\n"); - err = -ENXIO; - goto exit_ioremap; - } - - pcdev->irq = irq; - pcdev->dev = &pdev->dev; - - /* config buffer address */ - /* request irq */ - err = request_irq(pcdev->irq, rk28_camera_irq, 0, RK28_CAM_DRV_NAME, - pcdev); - if (err) { - dev_err(pcdev->dev, "Camera interrupt register failed \n"); - goto exit_reqirq; - } - - pcdev->soc_host.drv_name = RK28_CAM_DRV_NAME; - pcdev->soc_host.ops = &rk28_soc_camera_host_ops; - pcdev->soc_host.priv = pcdev; - pcdev->soc_host.v4l2_dev.dev = &pdev->dev; - pcdev->soc_host.nr = pdev->id; - - err = soc_camera_host_register(&pcdev->soc_host); - if (err) - goto exit_free_irq; - - RK28CAMERA_DG("\n%s..%s..%d \n",__FUNCTION__,__FILE__,__LINE__); - return 0; - -exit_free_irq: - free_irq(pcdev->irq, pcdev); -exit_reqirq: - iounmap(pcdev->base); -exit_ioremap: - release_mem_region(res->start, res->end - res->start + 1); -exit_reqmem: - clk_put(pcdev->clk); -exit_eclkget: - kfree(pcdev); -exit_alloc: - rk28_camdev_info_ptr = NULL; -exit: - return err; -} - -static int __devexit rk28_camera_remove(struct platform_device *pdev) -{ - struct rk28_camera_dev *pcdev = platform_get_drvdata(pdev); - struct resource *res; - - free_irq(pcdev->irq, pcdev); - - soc_camera_host_unregister(&pcdev->soc_host); - - res = pcdev->res; - release_mem_region(res->start, res->end - res->start + 1); - - if (pcdev->pdata && pcdev->pdata->io_deinit) { /* ddl@rock-chips.com : Free IO in deinit function */ - pcdev->pdata->io_deinit(); - } - - kfree(pcdev); - rk28_camdev_info_ptr = NULL; - dev_info(&pdev->dev, "RK28 Camera driver unloaded\n"); - - return 0; -} - -static struct platform_driver rk28_camera_driver = -{ - .driver = { - .name = RK28_CAM_DRV_NAME, - }, - .probe = rk28_camera_probe, - .remove = __devexit_p(rk28_camera_remove), -}; - - -static int __devinit rk28_camera_init(void) -{ - RK28CAMERA_DG("\n%s..%s..%d \n",__FUNCTION__,__FILE__,__LINE__); - return platform_driver_register(&rk28_camera_driver); -} - -static void __exit rk28_camera_exit(void) -{ - platform_driver_unregister(&rk28_camera_driver); -} - -//module_init(rk28_camera_init); -device_initcall_sync(rk28_camera_init); -module_exit(rk28_camera_exit); - -MODULE_DESCRIPTION("RK2818 Soc Camera Host driver"); -MODULE_AUTHOR("ddl "); -MODULE_LICENSE("GPL"); diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index fd98a80234f3..c5886cdd7201 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -4,29 +4,6 @@ comment "MMC/SD/SDIO Host Controller Drivers" -config SDMMC_RK2818 - tristate "RK2818 SDMMC controller suppport" - depends on ARCH_RK2818 - help - This selects the RK2818 SDMMC controller. - SDMMC0 used for sd/mmc card, and SDMMC1 used for sdio. -if SDMMC_RK2818 - comment "Now, there are two SDMMC controllers selected, SDMMC0 and SDMMC1." - config SDMMC0_RK2818 - tristate "RK2818 SDMMC0 controller support(sdmmc)" - default y - depends on ARCH_RK2818 - help - This supports the use of the SDMMC0 controller on rk2818 processors. - - config SDMMC1_RK2818 - tristate "RK2818 SDMMC1 controller support(sdio)" - default y - depends on ARCH_RK2818 - help - This supports the use of the SDMMC1 controller on rk2818 processors. -endif - config SDMMC_RK29 tristate "RK29 SDMMC controller suppport" depends on ARCH_RK29 diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 1fdec539bbea..da0e75f63b78 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -12,7 +12,6 @@ else obj-$(CONFIG_SDMMC_RK29) += rk29_sdmmc.o endif -obj-$(CONFIG_SDMMC_RK2818) += rk2818-sdmmc.o obj-$(CONFIG_MMC_ARMMMCI) += mmci.o obj-$(CONFIG_MMC_PXA) += pxamci.o obj-$(CONFIG_MMC_IMX) += imxmmc.o diff --git a/drivers/mmc/host/rk2818-sdmmc.c b/drivers/mmc/host/rk2818-sdmmc.c deleted file mode 100755 index 4a514ea1fd6a..000000000000 --- a/drivers/mmc/host/rk2818-sdmmc.c +++ /dev/null @@ -1,2044 +0,0 @@ -/* drivers/mmc/host/rk2818-sdmmc.c - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "rk2818-sdmmc.h" - -struct mmc_host *wifi_mmc_host = NULL; - -int sdmmc0_disable_Irq_ForRemoval; -int hotplug_global_ctl; -struct rk2818_sdmmc_host *mmc0_host; - - -#define RK2818_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | SDMMC_INT_HTO | SDMMC_INT_SBE | SDMMC_INT_EBE) -#define RK2818_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | SDMMC_INT_RE | SDMMC_INT_HLE) -#define RK2818_MCI_ERROR_FLAGS (RK2818_MCI_DATA_ERROR_FLAGS | RK2818_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE) -#define RK2818_MCI_SEND_STATUS 1 -#define RK2818_MCI_RECV_STATUS 2 -#define RK2818_MCI_DMA_THRESHOLD 16 - -enum { - EVENT_CMD_COMPLETE = 0, - EVENT_XFER_COMPLETE, - EVENT_DATA_COMPLETE, - EVENT_DATA_ERROR, - EVENT_XFER_ERROR -}; - - -enum rk2818_sdmmc_state { - STATE_IDLE = 0, - STATE_SENDING_CMD, - STATE_SENDING_DATA, - STATE_DATA_BUSY, - STATE_SENDING_STOP, - STATE_DATA_ERROR, -}; - -struct rk2818_sdmmc_host { - struct device *dev; - struct clk *clk; - spinlock_t lock; - void __iomem *regs; - - struct scatterlist *sg; - unsigned int pio_offset; - struct resource *mem; - struct mmc_request *mrq; - struct mmc_command *cmd; - struct mmc_data *data; - - int dma_chn; - int id; - unsigned int use_dma:1; - unsigned int no_detect:1; - char dma_name[8]; - - u32 cmd_status; - u32 data_status; - u32 stop_cmdr; - u32 dir_status; - struct tasklet_struct tasklet; - unsigned long pending_events; - unsigned long completed_events; - enum rk2818_sdmmc_state state; - struct list_head queue; - - u32 bus_hz; - u32 current_speed; - struct platform_device *pdev; - - struct mmc_host *mmc; - u32 ctype; - - struct list_head queue_node; - - unsigned int clock; - unsigned long flags; -#define RK2818_MMC_CARD_PRESENT 0 -#define RK2818_MMC_CARD_NEED_INIT 1 -#define RK2818_MMC_SHUTDOWN 2 - int irq; - unsigned int cmd_tmo; - struct mmc_command stop_mannual; - - struct timer_list detect_timer; - unsigned int oldstatus; /* save old status */ -}; - -#define MMC_DEBUG 0 -#if MMC_DEBUG -#define xjhprintk(msg...) printk(msg) -#else -#define xjhprintk(msg...) -#endif - -#define rk2818_sdmmc_test_and_clear_pending(host, event) \ - test_and_clear_bit(event, &host->pending_events) -#define rk2818_sdmmc_set_completed(host, event) \ - set_bit(event, &host->completed_events) - -#define rk2818_sdmmc_set_pending(host, event) \ - set_bit(event, &host->pending_events) - -static void rk2818_sdmmc_read_data_pio(struct rk2818_sdmmc_host *host); -#if defined (CONFIG_DEBUG_FS) - -static int rk2818_sdmmc_req_show(struct seq_file *s, void *v) -{ - struct rk2818_sdmmc_host *host = s->private; - struct mmc_request *mrq; - struct mmc_command *cmd; - struct mmc_command *stop; - struct mmc_data *data; - - spin_lock(&host->lock); - mrq = host->mrq; - - if (mrq) { - cmd = mrq->cmd; - data = mrq->data; - stop = mrq->stop; - - if (cmd) - seq_printf(s, - "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", - cmd->opcode, cmd->arg, cmd->flags, - cmd->resp[0], cmd->resp[1], cmd->resp[2], - cmd->resp[2], cmd->error); - if (data) - seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", - data->bytes_xfered, data->blocks, - data->blksz, data->flags, data->error); - if (stop) - seq_printf(s, - "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", - stop->opcode, stop->arg, stop->flags, - stop->resp[0], stop->resp[1], stop->resp[2], - stop->resp[2], stop->error); - } - - spin_unlock(&host->lock); - - return 0; -} - -static int rk2818_sdmmc_req_open(struct inode *inode, struct file *file) -{ - return single_open(file, rk2818_sdmmc_req_show, inode->i_private); -} - -static const struct file_operations rk2818_sdmmc_req_fops = { - .owner = THIS_MODULE, - .open = rk2818_sdmmc_req_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int rk2818_sdmmc_regs_show(struct seq_file *s, void *v) -{ - struct rk2818_sdmmc_host *host = s->private; - - seq_printf(s, "STATUS: 0x%08x\n",readl(host->regs + SDMMC_STATUS)); - seq_printf(s, "RINTSTS: 0x%08x\n",readl(host->regs + SDMMC_RINTSTS)); - seq_printf(s, "CMD: 0x%08x\n", readl(host->regs + SDMMC_CMD)); - seq_printf(s, "CTRL: 0x%08x\n", readl(host->regs + SDMMC_CTRL)); - seq_printf(s, "INTMASK: 0x%08x\n", readl(host->regs + SDMMC_INTMASK)); - seq_printf(s, "CLKENA: 0x%08x\n", readl(host->regs + SDMMC_CLKENA)); - - return 0; -} - -static int rk2818_sdmmc_regs_open(struct inode *inode, struct file *file) -{ - return single_open(file, rk2818_sdmmc_regs_show, inode->i_private); -} - -static const struct file_operations rk2818_sdmmc_regs_fops = { - .owner = THIS_MODULE, - .open = rk2818_sdmmc_regs_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static void rk2818_sdmmc_init_debugfs(struct rk2818_sdmmc_host *host) -{ - struct mmc_host *mmc = host->mmc; - struct dentry *root; - struct dentry *node; - - root = mmc->debugfs_root; - if (!root) - return; - - node = debugfs_create_file("regs", S_IRUSR, root, host, - &rk2818_sdmmc_regs_fops); - if (IS_ERR(node)) - return; - if (!node) - goto err; - - node = debugfs_create_file("req", S_IRUSR, root, host, &rk2818_sdmmc_req_fops); - if (!node) - goto err; - - node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); - if (!node) - goto err; - - node = debugfs_create_x32("pending_events", S_IRUSR, root, - (u32 *)&host->pending_events); - if (!node) - goto err; - - node = debugfs_create_x32("completed_events", S_IRUSR, root, - (u32 *)&host->completed_events); - if (!node) - goto err; - - return; - -err: - dev_err(&mmc->class_dev, "failed to initialize debugfs for host\n"); -} -#endif -static void rk2818_show_regs(struct rk2818_sdmmc_host *host) -{ - unsigned long cpsr_tmp; - - xjhprintk("--------[xjh] SD/MMC/SDIO Registers-----------------\n"); - xjhprintk("SDMMC_CTRL:\t0x%x\n",readl(host->regs + SDMMC_CTRL)); - xjhprintk("SDMMC_PWREN:\t0x%x\n",readl(host->regs + SDMMC_PWREN)); - xjhprintk("SDMMC_CLKDIV:\t0x%x\n",readl(host->regs + SDMMC_CLKDIV)); - xjhprintk("SDMMC_CLKSRC:\t0x%x\n",readl(host->regs + SDMMC_CLKSRC)); - xjhprintk("SDMMC_CLKENA:\t0x%x\n",readl(host->regs + SDMMC_CLKENA)); - xjhprintk("SDMMC_TMOUT:\t0x%x\n",readl(host->regs + SDMMC_TMOUT)); - xjhprintk("SDMMC_CTYPE:\t0x%x\n",readl(host->regs + SDMMC_CTYPE)); - xjhprintk("SDMMC_BLKSIZ:\t0x%x\n",readl(host->regs + SDMMC_BLKSIZ)); - xjhprintk("SDMMC_BYTCNT:\t0x%x\n",readl(host->regs + SDMMC_BYTCNT)); - xjhprintk("SDMMC_INTMASK:\t0x%x\n",readl(host->regs + SDMMC_INTMASK)); - xjhprintk("SDMMC_CMDARG:\t0x%x\n",readl(host->regs + SDMMC_CMDARG)); - xjhprintk("SDMMC_CMD:\t0x%x\n",readl(host->regs + SDMMC_CMD)); - xjhprintk("SDMMC_RESP0:\t0x%x\n",readl(host->regs + SDMMC_RESP0)); - xjhprintk("SDMMC_RESP1:\t0x%x\n",readl(host->regs + SDMMC_RESP1)); - xjhprintk("SDMMC_RESP2:\t0x%x\n",readl(host->regs + SDMMC_RESP2)); - xjhprintk("SDMMC_RESP3:\t0x%x\n",readl(host->regs + SDMMC_RESP3)); - xjhprintk("SDMMC_MINTSTS:\t0x%x\n",readl(host->regs + SDMMC_MINTSTS)); - xjhprintk("SDMMC_RINTSTS:\t0x%x\n",readl(host->regs + SDMMC_RINTSTS)); - xjhprintk("SDMMC_STATUS:\t0x%x\n",readl(host->regs + SDMMC_STATUS)); - xjhprintk("SDMMC_FIFOTH:\t0x%x\n",readl(host->regs + SDMMC_FIFOTH)); - xjhprintk("SDMMC_CDETECT:\t0x%x\n",readl(host->regs + SDMMC_CDETECT)); - xjhprintk("SDMMC_WRTPRT:\t0x%x\n",readl(host->regs + SDMMC_WRTPRT)); - xjhprintk("SDMMC_TCBCNT:\t0x%x\n",readl(host->regs + SDMMC_TCBCNT)); - xjhprintk("SDMMC_TBBCNT:\t0x%x\n",readl(host->regs + SDMMC_TBBCNT)); - xjhprintk("SDMMC_DEBNCE:\t0x%x\n",readl(host->regs + SDMMC_DEBNCE)); - xjhprintk("-------- Host states-----------------\n"); - xjhprintk("host->state:\t0x%x\n",host->state); - xjhprintk("host->pending_events:\t0x%x\n",host->pending_events); - xjhprintk("host->cmd_status:\t0x%x\n",host->cmd_status); - xjhprintk("host->data_status:\t0x%x\n",host->data_status); - xjhprintk("host->stop_cmdr:\t0x%x\n",host->stop_cmdr); - xjhprintk("host->dir_status:\t0x%x\n",host->dir_status); - xjhprintk("host->completed_events:\t0x%x\n",host->completed_events); - xjhprintk("host->dma_chn:\t0x%x\n",host->dma_chn); - xjhprintk("host->use_dma:\t0x%x\n",host->use_dma); - xjhprintk("host->no_detect:\t0x%x\n",host->no_detect); - xjhprintk("host->bus_hz:\t0x%x\n",host->bus_hz); - xjhprintk("host->current_speed:\t0x%x\n",host->current_speed); - xjhprintk("host->ctype:\t0x%x\n",host->ctype); - xjhprintk("host->clock:\t0x%x\n",host->clock); - xjhprintk("host->flags:\t0x%x\n",host->flags); - xjhprintk("host->irq:\t0x%x\n",host->irq); - xjhprintk("-------- rk2818 CPU register-----------------\n"); - __asm__ volatile ("mrs %0, cpsr @ local_irq_save\n":"=r" (cpsr_tmp)::"memory", "cc" ); - xjhprintk("cpsr:\t0x%x\n",cpsr_tmp); - - - -} - -static void rk2818_sdmmc_set_power(struct rk2818_sdmmc_host *host, u32 ocr_avail) -{ - if(ocr_avail == 0) - writel(0, host->regs + SDMMC_PWREN); - else - writel(1, host->regs + SDMMC_PWREN); -} -static inline unsigned ns_to_clocks(unsigned clkrate, unsigned ns) -{ - u32 clks; - if (clkrate > 1000000) - clks = (ns * (clkrate / 1000000) + 999) / 1000; - else - clks = ((ns/1000) * (clkrate / 1000) + 999) / 1000; - - return clks; -} - -static void rk2818_sdmmc_set_timeout(struct rk2818_sdmmc_host *host, struct mmc_data *data) -{ - unsigned timeout; - - timeout = ns_to_clocks(host->clock, data->timeout_ns) + data->timeout_clks; - - dev_dbg(host->dev, "tmo req:%d + %d reg:%d clk:%d\n", - data->timeout_ns, data->timeout_clks, timeout, host->clock); - writel((timeout << 8) | (80), host->regs + SDMMC_TMOUT); -} - -static u32 rk2818_sdmmc_prepare_command(struct mmc_host *mmc, - struct mmc_command *cmd) -{ - struct mmc_data *data; - u32 cmdr; - - cmd->error = -EINPROGRESS; - cmdr = cmd->opcode; - - if(cmdr == 12) - cmdr |= SDMMC_CMD_STOP; - else if(cmdr == 13) - cmdr &= ~SDMMC_CMD_PRV_DAT_WAIT; - else - cmdr |= SDMMC_CMD_PRV_DAT_WAIT; - - if (cmd->flags & MMC_RSP_PRESENT) { - cmdr |= SDMMC_CMD_RESP_EXP; // expect the respond, need to set this bit - if (cmd->flags & MMC_RSP_136) - cmdr |= SDMMC_CMD_RESP_LONG; // expect long respond - - if(cmd->flags & MMC_RSP_CRC) - cmdr |= SDMMC_CMD_RESP_CRC; - } - - data = cmd->data; - if (data) { - cmdr |= SDMMC_CMD_DAT_EXP; - if (data->flags & MMC_DATA_STREAM) - cmdr |= SDMMC_CMD_STRM_MODE; // set stream mode - if (data->flags & MMC_DATA_WRITE) - cmdr |= SDMMC_CMD_DAT_WR; - - } - return cmdr; -} - - -static void rk2818_sdmmc_start_command(struct rk2818_sdmmc_host *host, - struct mmc_command *cmd, u32 cmd_flags) -{ - int tmo = 5000; - unsigned long flags; - int retry = 4; - host->cmd = cmd; - dev_dbg(host->dev, "start cmd:%d ARGR=0x%08x CMDR=0x%08x\n", - cmd->opcode, cmd->arg, cmd_flags); - local_irq_save(flags); - writel(cmd->arg, host->regs + SDMMC_CMDARG); // write to CMDARG register - writel(cmd_flags | SDMMC_CMD_START, host->regs + SDMMC_CMD); // write to CMD register - local_irq_restore(flags); - - /* wait until CIU accepts the command */ - while (--tmo && (readl(host->regs + SDMMC_CMD) & SDMMC_CMD_START)) - cpu_relax(); - if(!tmo) { - tmo = 5000; - xjhprintk("%s start cmd %d error. retry again!!!\n",__FUNCTION__ ,cmd->opcode); - rk2818_show_regs(host); - rk2818_sdmmc_set_completed(host, EVENT_CMD_COMPLETE); - host->cmd_status |= SDMMC_INT_RE; - tasklet_schedule(&host->tasklet); - retry --; - // if(retry) - // goto START_CMD; - } - #if 0 - tmo = 60; - host->cmd_tmo = 0; - while(--tmo && !host->cmd_tmo) - { - mdelay(5); - //cpu_relax(); - - } - if(!tmo) - { - xjhprintk("cmd %d response time out(not receive INT)\n",cmd->opcode); - rk2818_sdmmc_set_completed(host, EVENT_CMD_COMPLETE); - host->cmd_status |= SDMMC_INT_RE; - tasklet_schedule(&host->tasklet); - } - #endif -} - -static void send_stop_cmd(struct rk2818_sdmmc_host *host, struct mmc_data *data) -{ - unsigned long flags; - unsigned long fifo_left; - /*µÈ´ýÇ°Ãæ´«Êä´¦ÀíÍê³É*/ - int time_out =60; - while(readl(host->regs + SDMMC_STATUS) & (SDMMC_STAUTS_DATA_BUSY)) { - mdelay(5); - time_out --; - - if(!time_out){ - time_out =60; - xjhprintk("card busy now,can not issuse req! \nreset DMA and FIFO\n"); - local_irq_save(flags); - - // writel(readl(host->regs + SDMMC_CTRL) | ( SDMMC_CTRL_DMA_RESET ) & ~SDMMC_CTRL_DMA_ENABLE, host->regs + SDMMC_CTRL); - /* wait till resets clear */ - // while (readl(host->regs + SDMMC_CTRL) & ( SDMMC_CTRL_DMA_RESET)); - - writel(readl(host->regs + SDMMC_CTRL) | ( SDMMC_CTRL_FIFO_RESET ), host->regs + SDMMC_CTRL); - /* wait till resets clear */ - while (readl(host->regs + SDMMC_CTRL) & ( SDMMC_CTRL_FIFO_RESET)); - local_irq_restore(flags); - } - //cpu_relax(); - } - - #if 1 - - fifo_left = readl(host->regs + SDMMC_STATUS); - - if((fifo_left & SDMMC_STAUTS_FIFO_FULL) && (fifo_left & SDMMC_STAUTS_FIFO_RX_WATERMARK)) - { - xjhprintk("%s read operation reach water mark\n",__FUNCTION__); - rk2818_show_regs(host); - while(SDMMC_GET_FCNT(readl(host->regs + SDMMC_STATUS))>>2) - readl(host->regs + SDMMC_DATA); //discard the no use data - - rk2818_show_regs(host); - - } - #endif - /*¼ì²éFIFO,Èç¹û²»Îª¿Õ£¬Çå¿Õ*/ - if(!(readl(host->regs + SDMMC_STATUS) & SDMMC_STAUTS_FIFO_EMPTY)) { - xjhprintk("%s: FIFO not empty, clear it\n",__FUNCTION__); - rk2818_show_regs(host); - local_irq_save(flags); - // writel(readl(host->regs + SDMMC_CTRL) | ( SDMMC_CTRL_DMA_RESET ), host->regs + SDMMC_CTRL); - /* wait till resets clear */ - // while (readl(host->regs + SDMMC_CTRL) & ( SDMMC_CTRL_DMA_RESET)); - - writel(readl(host->regs + SDMMC_CTRL) | ( SDMMC_CTRL_FIFO_RESET ), host->regs + SDMMC_CTRL); - /* wait till resets clear */ - while (readl(host->regs + SDMMC_CTRL) & ( SDMMC_CTRL_FIFO_RESET)); - local_irq_restore(flags); - //cpu_relax(); - } - - rk2818_sdmmc_start_command(host, data->stop, host->stop_cmdr); -} - -static void rk2818_sdmmc_dma_cleanup(struct rk2818_sdmmc_host *host) -{ - struct mmc_data *data = host->data; - if (data) - dma_unmap_sg(host->dev, data->sg, data->sg_len, - ((data->flags & MMC_DATA_WRITE)? DMA_TO_DEVICE : DMA_FROM_DEVICE)); -} - -static void rk2818_sdmmc_stop_dma(struct rk2818_sdmmc_host *host) -{ - if (host->dma_chn >= 0) { - xjhprintk("[xjh] %s enter host->state %d\n", __FUNCTION__, host->state); - writel(readl(host->regs + SDMMC_CTRL) & ~SDMMC_CTRL_DMA_ENABLE, - host->regs +SDMMC_CTRL); - //disable_dma(host->dma_chn); - if (strncmp(host->dma_name, "sdio", strlen("sdio")) != 0) - free_dma(host->dma_chn); - host->dma_chn = -1; - rk2818_sdmmc_dma_cleanup(host); - rk2818_sdmmc_set_pending(host, EVENT_XFER_COMPLETE);//[xjh] Èç¹ûÊý¾Ý¶Áд¹ý³Ì±»°Îµô£¬ÐèÒªÉèÖÃÕâ¸ö״̬ - xjhprintk("[xjh] %s exit\n", __FUNCTION__); - } else { - /* Data transfer was stopped by the interrupt handler */ - rk2818_sdmmc_set_pending(host, EVENT_XFER_COMPLETE); - } -} - -/* This function is called by the DMA driver from tasklet context. */ -static void rk2818_sdmmc_dma_complete(int chn, void *arg) -{ - struct rk2818_sdmmc_host *host = arg; - struct mmc_data *data = host->data; - - dev_dbg(host->dev, "DMA complete\n"); - - spin_lock(&host->lock); - //disable dma - writel(readl(host->regs + SDMMC_CTRL) & ~SDMMC_CTRL_DMA_ENABLE, - host->regs +SDMMC_CTRL); - rk2818_sdmmc_dma_cleanup(host); - //disable_dma(host->dma_chn); - if (strncmp(host->dma_name, "sdio", strlen("sdio")) != 0) - free_dma(host->dma_chn); - host->dma_chn = -1; - if (data) { - - rk2818_sdmmc_set_pending(host, EVENT_XFER_COMPLETE); - tasklet_schedule(&host->tasklet); - } - spin_unlock(&host->lock); -} -static int rk2818_sdmmc_submit_data_dma(struct rk2818_sdmmc_host *host, struct mmc_data *data) -{ - struct scatterlist *sg; - unsigned int i; - dev_dbg(host->dev, "sg_len=%d\n", data->sg_len); - host->dma_chn = -1; - if(host->use_dma == 0) - return -ENOSYS; -#if 0 - if (data->blocks * data->blksz < RK2818_MCI_DMA_THRESHOLD) - return -EINVAL; -#endif - if (data->blksz & 3) - return -EINVAL; - for_each_sg(data->sg, sg, data->sg_len, i) { - if (sg->offset & 3 || sg->length & 3) - return -EINVAL; - } - if (strncmp(host->dma_name, "sdio", strlen("sdio")) != 0) { - for(i = 0; i < MAX_SG_CHN; i++) { - if(request_dma(i, host->dma_name) == 0) { - host->dma_chn = i; - break; - } - } - if(i == MAX_SG_CHN) - return -EINVAL; - } - else - host->dma_chn = 1; - dma_map_sg(host->dev, data->sg, data->sg_len, - (data->flags & MMC_DATA_READ)? DMA_FROM_DEVICE : DMA_TO_DEVICE); - for_each_sg(data->sg, sg, data->sg_len, i) { - dev_dbg(host->dev, "sg[%d] addr: 0x%08x, len: %d", i, sg->dma_address, sg->length); - } - set_dma_sg(host->dma_chn, data->sg, data->sg_len); - //printk("2.....\n"); - set_dma_mode(host->dma_chn, - (data->flags & MMC_DATA_READ)? DMA_MODE_READ : DMA_MODE_WRITE); - //printk("3.....\n"); - set_dma_handler(host->dma_chn, rk2818_sdmmc_dma_complete, (void *)host, DMA_IRQ_DELAY_MODE); - //printk("4.....\n"); - writel(readl(host->regs + SDMMC_CTRL) | SDMMC_CTRL_DMA_ENABLE, - host->regs +SDMMC_CTRL); - //printk("5.....\n"); - enable_dma(host->dma_chn); - //printk("6.....\n"); - dev_dbg(host->dev,"DMA enable, \n"); - return 0; -} - -static void rk2818_sdmmc_submit_data(struct rk2818_sdmmc_host *host, struct mmc_data *data) -{ - data->error = -EINPROGRESS; - - WARN_ON(host->data); - host->sg = NULL; - host->data = data; - - if (rk2818_sdmmc_submit_data_dma(host, data)) { - host->sg = data->sg; - host->pio_offset = 0; - if (data->flags & MMC_DATA_READ) - host->dir_status = RK2818_MCI_RECV_STATUS; - else - host->dir_status = RK2818_MCI_SEND_STATUS; - writel(readl(host->regs + SDMMC_CTRL) & ~SDMMC_CTRL_DMA_ENABLE, - host->regs +SDMMC_CTRL); - } -} -#if 0 -#define mci_send_cmd(host,cmd,arg) { \ - writel(arg, host->regs + SDMMC_CMDARG); \ - writel(SDMMC_CMD_START | cmd, host->regs + SDMMC_CMD); \ - while (readl(host->regs + SDMMC_CMD) & SDMMC_CMD_START); \ -} -#else -static void mci_send_cmd(struct rk2818_sdmmc_host *host,unsigned int cmd,int arg) -{ - int tmo = 5000; - int retry = 4; - - writel(arg, host->regs + SDMMC_CMDARG); - writel(SDMMC_CMD_START | cmd, host->regs + SDMMC_CMD); - while (--tmo && readl(host->regs + SDMMC_CMD) & SDMMC_CMD_START); - if(!tmo) { - tmo = 5000; - xjhprintk("%s set register error. retry again!!!\n",__FUNCTION__); - retry --; - // if(retry) - // goto START_CMD; - } -} - -#endif - -#if 1 -void inline rk2818_sdmmc_setup_bus(struct rk2818_sdmmc_host *host) -{ - ; -} -#else -void rk2818_sdmmc_setup_bus(struct rk2818_sdmmc_host *host) -{ - u32 div; - - if (host->clock != host->current_speed) { - div = (((host->bus_hz + (host->bus_hz / 5)) / host->clock)) >> 1; - - dev_dbg(host->dev, "Bus speed = %dHz div:%d (actual %dHz)\n", - host->clock, div, (host->bus_hz / div) >> 1); - xjhprintk("Bus speed = %dHz div:%d (actual %dHz)\n", - host->clock, div, (host->bus_hz / div) >> 1); - - /* store the actual clock for calculations */ - host->clock = (host->bus_hz / div) >> 1; - /* disable clock */ - writel(0, host->regs + SDMMC_CLKENA); - writel(0, host->regs + SDMMC_CLKSRC); - /* inform CIU */ - mci_send_cmd(host, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); - /* set clock to desired speed */ - writel(div, host->regs + SDMMC_CLKDIV); - /* inform CIU */ - mci_send_cmd(host, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); - /* enable clock */ - writel(SDMMC_CLKEN_ENABLE, host->regs + SDMMC_CLKENA); - /* inform CIU */ - mci_send_cmd(host, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); - - host->current_speed = host->clock; - } - - /* Set the current host bus width */ - writel(host->ctype, host->regs + SDMMC_CTYPE); -} -#endif - - -static void rk2818_sdmmc_start_request(struct rk2818_sdmmc_host *host) -{ - struct mmc_request *mrq; - struct mmc_command *cmd; - struct mmc_data *data; - u32 cmdflags; - unsigned long flags; - - int time_out =60; - - mrq = host->mrq; - - //rk2818_sdmmc_setup_bus(host); - - /*µÈ´ýÇ°Ãæ´«Êä´¦ÀíÍê³É*/ - while(readl(host->regs + SDMMC_STATUS) & (SDMMC_STAUTS_DATA_BUSY)) { - mdelay(5); - time_out --; - - if(!time_out){ - time_out =60; - xjhprintk("card busy now,can not issuse req! \nreset DMA and FIFO\n"); - local_irq_save(flags); - - // writel(readl(host->regs + SDMMC_CTRL) | ( SDMMC_CTRL_DMA_RESET ) & ~SDMMC_CTRL_DMA_ENABLE, host->regs + SDMMC_CTRL); - /* wait till resets clear */ - // while (readl(host->regs + SDMMC_CTRL) & ( SDMMC_CTRL_DMA_RESET)); - - writel(readl(host->regs + SDMMC_CTRL) | ( SDMMC_CTRL_FIFO_RESET ), host->regs + SDMMC_CTRL); - /* wait till resets clear */ - while (readl(host->regs + SDMMC_CTRL) & ( SDMMC_CTRL_FIFO_RESET)); - local_irq_restore(flags); - } - //cpu_relax(); - } - /*¼ì²éFIFO,Èç¹û²»Îª¿Õ£¬Çå¿Õ*/ - if(!(readl(host->regs + SDMMC_STATUS) & SDMMC_STAUTS_FIFO_EMPTY)) { - xjhprintk("%s: FIFO not empty, clear it\n",__FUNCTION__); - rk2818_show_regs(host); - local_irq_save(flags); - // writel(readl(host->regs + SDMMC_CTRL) | ( SDMMC_CTRL_DMA_RESET ), host->regs + SDMMC_CTRL); - /* wait till resets clear */ - // while (readl(host->regs + SDMMC_CTRL) & ( SDMMC_CTRL_DMA_RESET)); - - writel(readl(host->regs + SDMMC_CTRL) | ( SDMMC_CTRL_FIFO_RESET ), host->regs + SDMMC_CTRL); - /* wait till resets clear */ - while (readl(host->regs + SDMMC_CTRL) & ( SDMMC_CTRL_FIFO_RESET)); - local_irq_restore(flags); - //cpu_relax(); - } - - host->mrq = mrq; - - host->pending_events = 0; - host->completed_events = 0; - host->data_status = 0; - - data = mrq->data; - if (data) { - rk2818_sdmmc_set_timeout(host, data); - writel(data->blksz * data->blocks, host->regs + SDMMC_BYTCNT); - writel(data->blksz, host->regs + SDMMC_BLKSIZ); - } - - cmd = mrq->cmd; - cmdflags = rk2818_sdmmc_prepare_command(host->mmc, cmd); - - if (unlikely(test_and_clear_bit(RK2818_MMC_CARD_NEED_INIT, &host->flags))) - cmdflags |= SDMMC_CMD_INIT; - - if (data) - rk2818_sdmmc_submit_data(host, data); - - rk2818_sdmmc_start_command(host, cmd, cmdflags); - if (mrq->stop) - { - host->stop_cmdr = rk2818_sdmmc_prepare_command(host->mmc, mrq->stop); - dev_dbg(host->dev, "mrq stop: stop_cmdr = %d", host->stop_cmdr); - } - -} - - - -static void rk2818_sdmmc_queue_request(struct rk2818_sdmmc_host *host, struct mmc_request *mrq) -{ - dev_dbg(host->dev, "queue request: state=%d\n", - host->state); - - spin_lock(&host->lock); - host->mrq = mrq; - if (host->state == STATE_IDLE) { - host->state = STATE_SENDING_CMD; - rk2818_sdmmc_start_request(host); - } else { - list_add_tail(&host->queue_node, &host->queue); - } - spin_unlock(&host->lock); -} - - -static void rk2818_sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) -{ - struct rk2818_sdmmc_host *host = mmc_priv(mmc); - - WARN_ON(host->mrq); - #if 0 - if (!test_bit(RK2818_MMC_CARD_PRESENT, &host->flags)) { - mrq->cmd->error = -ENOMEDIUM; - mmc_request_done(mmc, mrq); - return; - } - #endif - - rk2818_sdmmc_queue_request(host, mrq); -} - -static void rk2818_sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) -{ - struct rk2818_sdmmc_host *host = mmc_priv(mmc); - u32 div; - unsigned long flags; - - xjhprintk("%s bus_width %x ios->clock %x host->clock %x ocr %x\n", - __FUNCTION__,ios->bus_width, ios->clock, host->clock, host->mmc->ocr_avail); - - host->ctype = 0; // set default 1 bit mode - switch (ios->bus_width) { - case MMC_BUS_WIDTH_1: - host->ctype = 0; - break; - case MMC_BUS_WIDTH_4: - host->ctype = SDMMC_CTYPE_4BIT; - break; - } - - spin_lock_irqsave(&host->lock,flags); - /* Set the current host bus width */ - writel(host->ctype, host->regs + SDMMC_CTYPE); - - if(ios->bus_mode == MMC_BUSMODE_OPENDRAIN) - writel(readl(host->regs + SDMMC_CTRL) | SDMMC_CTRL_OD_PULLUP, host->regs + SDMMC_CTRL); - else - writel(readl(host->regs + SDMMC_CTRL) & ~SDMMC_CTRL_OD_PULLUP, host->regs + SDMMC_CTRL); - spin_unlock_irqrestore(&host->lock,flags); - - if (ios->clock && (host->current_speed != ios->clock)) { - /* - * Use mirror of ios->clock to prevent race with mmc - * core ios update when finding the minimum. - */ - div = (((host->bus_hz + (host->bus_hz / 5)) / ios->clock)) >> 1; - xjhprintk("Bus speed = %dHz div:%d (actual %dHz)\n", - host->clock, div, (host->bus_hz / div) >> 1); - - /* store the actual clock for calculations */ - host->clock = (host->bus_hz / div) >> 1; - /*µÈ´ý¿¨Æ¬´«ÊäÍê³É*/ - while(readl(host->regs + SDMMC_STATUS) & (SDMMC_STAUTS_MC_BUSY | SDMMC_STAUTS_DATA_BUSY)){ - udelay(10); - xjhprintk("SD/MMC busy now(status 0x%x),can not change clock\n",readl(host->regs + SDMMC_STATUS)); - //cpu_relax(); - } - spin_lock_irqsave(&host->lock,flags); - /* disable clock */ - writel(0, host->regs + SDMMC_CLKENA); - writel(0, host->regs + SDMMC_CLKSRC); - /* inform CIU */ - mci_send_cmd(host, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); - /* set clock to desired speed */ - writel(div, host->regs + SDMMC_CLKDIV); - /* inform CIU */ - mci_send_cmd(host, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); - /* enable clock */ - if(host->pdev->id == 0) //sdmmc0 endable low power mode - writel(SDMMC_CLKEN_LOW_PWR | SDMMC_CLKEN_ENABLE, host->regs + SDMMC_CLKENA); - else - writel(SDMMC_CLKEN_ENABLE, host->regs + SDMMC_CLKENA); - /* inform CIU */ - mci_send_cmd(host, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); - - host->current_speed= ios->clock; - - spin_unlock_irqrestore(&host->lock,flags); - - } - #if 0 - else { - spin_lock(&host->lock); - host->clock = 0; - spin_unlock(&host->lock); - } - #endif - spin_lock_irqsave(&host->lock,flags); - - switch (ios->power_mode) { - case MMC_POWER_UP: - set_bit(RK2818_MMC_CARD_NEED_INIT, &host->flags); - rk2818_sdmmc_set_power(host, host->mmc->ocr_avail); - break; - default: - //rk2818_sdmmc_set_power(host, 0); - break; - } - spin_unlock_irqrestore(&host->lock,flags); - -} - - - -static int rk2818_sdmmc_get_ro(struct mmc_host *mmc) -{ - struct rk2818_sdmmc_host *host = mmc_priv(mmc); - u32 wrtprt = readl(host->regs + SDMMC_WRTPRT); - - return (wrtprt & SDMMC_WRITE_PROTECT)?1:0; -} - - -static int rk2818_sdmmc_get_cd(struct mmc_host *mmc) -{ - struct rk2818_sdmmc_host *host = mmc_priv(mmc); - u32 cdetect = readl(host->regs + SDMMC_CDETECT); - -#if defined(CONFIG_MACH_RAHO)||defined(CONFIG_MACH_RAHOSDK) - return 1; -#else - return (cdetect & SDMMC_CARD_DETECT_N)?0:1; -#endif - -} - -static void rk2818_sdmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) -{ - u32 intmask; - unsigned long flags; - struct rk2818_sdmmc_host *host = mmc_priv(mmc); - spin_lock_irqsave(&host->lock, flags); - intmask = readl(host->regs + SDMMC_INTMASK); - if(enable) - writel(intmask | SDMMC_INT_SDIO, host->regs + SDMMC_INTMASK); - else - writel(intmask & ~SDMMC_INT_SDIO, host->regs + SDMMC_INTMASK); - spin_unlock_irqrestore(&host->lock, flags); -} - -static const struct mmc_host_ops rk2818_sdmmc_ops[] = { - { - .request = rk2818_sdmmc_request, - .set_ios = rk2818_sdmmc_set_ios, - .get_ro = rk2818_sdmmc_get_ro, - .get_cd = rk2818_sdmmc_get_cd, - }, - { - .request = rk2818_sdmmc_request, - .set_ios = rk2818_sdmmc_set_ios, - .enable_sdio_irq = rk2818_sdmmc_enable_sdio_irq, - }, -}; - -static void rk2818_sdmmc_request_end(struct rk2818_sdmmc_host *host, struct mmc_request *mrq) - __releases(&host->lock) - __acquires(&host->lock) -{ - struct mmc_host *prev_mmc = host->mmc; - unsigned long flags; - int time_out =60; - unsigned long fifo_left; - - WARN_ON(host->cmd || host->data); - host->mrq = NULL; - - - /*µÈ´ýÇ°Ãæ´«Êä´¦ÀíÍê³É*/ - while(readl(host->regs + SDMMC_STATUS) & (SDMMC_STAUTS_DATA_BUSY)) { - mdelay(5); - time_out --; - - if(!time_out){ - time_out =60; - xjhprintk("req done:card busy for a long time!!!reset DMA and FIFO\n"); - local_irq_save(flags); - - // writel(readl(host->regs + SDMMC_CTRL) | ( SDMMC_CTRL_DMA_RESET ) & ~SDMMC_CTRL_DMA_ENABLE, host->regs + SDMMC_CTRL); - /* wait till resets clear */ - // while (readl(host->regs + SDMMC_CTRL) & ( SDMMC_CTRL_DMA_RESET)); - - writel(readl(host->regs + SDMMC_CTRL) | ( SDMMC_CTRL_FIFO_RESET ), host->regs + SDMMC_CTRL); - /* wait till resets clear */ - while (readl(host->regs + SDMMC_CTRL) & ( SDMMC_CTRL_FIFO_RESET)); - local_irq_restore(flags); - } - //cpu_relax(); - } - - #if 1 - fifo_left = readl(host->regs + SDMMC_STATUS); - - if((fifo_left & SDMMC_STAUTS_FIFO_FULL) && (fifo_left & SDMMC_STAUTS_FIFO_RX_WATERMARK)) - { - xjhprintk("%s read operation reach water mark\n",__FUNCTION__); - rk2818_show_regs(host); - while(SDMMC_GET_FCNT(readl(host->regs + SDMMC_STATUS))>>2) - readl(host->regs + SDMMC_DATA); //discard the no use data - rk2818_show_regs(host); - - } - #endif - /*¼ì²éFIFO,Èç¹û²»Îª¿Õ£¬Çå¿Õ*/ - if(!(readl(host->regs + SDMMC_STATUS) & SDMMC_STAUTS_FIFO_EMPTY)) { - xjhprintk("%s: FIFO not empty, clear it\n",__FUNCTION__); - rk2818_show_regs(host); - local_irq_save(flags); - // writel(readl(host->regs + SDMMC_CTRL) | ( SDMMC_CTRL_DMA_RESET ), host->regs + SDMMC_CTRL); - /* wait till resets clear */ - // while (readl(host->regs + SDMMC_CTRL) & ( SDMMC_CTRL_DMA_RESET)); - - writel(readl(host->regs + SDMMC_CTRL) | ( SDMMC_CTRL_FIFO_RESET ), host->regs + SDMMC_CTRL); - /* wait till resets clear */ - while (readl(host->regs + SDMMC_CTRL) & ( SDMMC_CTRL_FIFO_RESET)); - local_irq_restore(flags); - //cpu_relax(); - } - - if (!list_empty(&host->queue)) { - host = list_entry(host->queue.next, - struct rk2818_sdmmc_host, queue_node); - list_del(&host->queue_node); - dev_dbg(host->dev, "list not empty: %s is next\n", - mmc_hostname(host->mmc)); - host->state = STATE_SENDING_CMD; - rk2818_sdmmc_start_request(host); - } else { - dev_dbg(host->dev, "list empty\n"); - host->state = STATE_IDLE; - } - - spin_unlock(&host->lock); - mmc_request_done(prev_mmc, mrq); - - spin_lock(&host->lock); -} - -static void rk2818_sdmmc_command_complete(struct rk2818_sdmmc_host *host, - struct mmc_command *cmd) -{ - u32 status = host->cmd_status; - - host->cmd_status = 0; - - if(cmd->flags & MMC_RSP_PRESENT) { - - if(cmd->flags & MMC_RSP_136) { - - cmd->resp[3] = readl(host->regs + SDMMC_RESP0); - cmd->resp[2] = readl(host->regs + SDMMC_RESP1); - cmd->resp[1] = readl(host->regs + SDMMC_RESP2); - cmd->resp[0] = readl(host->regs + SDMMC_RESP3); - } else { - cmd->resp[0] = readl(host->regs + SDMMC_RESP0); - cmd->resp[1] = 0; - cmd->resp[2] = 0; - cmd->resp[3] = 0; - } - } - - if (status & SDMMC_INT_RTO) - cmd->error = -ETIMEDOUT; - else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) - cmd->error = -EILSEQ; - else if (status & SDMMC_INT_RE) - cmd->error = -EIO; - else if(status & SDMMC_INT_HLE) - cmd->error = -EIO; - else - cmd->error = 0; - - if (cmd->error) { - dev_dbg(host->dev, - "command error: status=0x%08x resp=0x%08x\n" - "cmd=0x%08x arg=0x%08x flg=0x%08x err=%d\n", - status, cmd->resp[0], - cmd->opcode, cmd->arg, cmd->flags, cmd->error); - - - if (cmd->data) { - host->data = NULL; - rk2818_sdmmc_stop_dma(host); - } - } -} - -static void rk2818_sdmmc_tasklet_func(unsigned long priv) -{ - struct rk2818_sdmmc_host *host = (struct rk2818_sdmmc_host *)priv; - struct mmc_request *mrq = host->mrq; - struct mmc_data *data = host->data; - enum rk2818_sdmmc_state state = host->state; - enum rk2818_sdmmc_state prev_state; - u32 status; - int timeout=5000; - - spin_lock(&host->lock); - - state = host->state; - do { - prev_state = state; - timeout --; - if(!timeout) - { - timeout = 5000; - xjhprintk("%s\n",__FUNCTION__); - } - - switch (state) { - case STATE_IDLE: - break; - - case STATE_SENDING_CMD: - if (!rk2818_sdmmc_test_and_clear_pending(host, - EVENT_CMD_COMPLETE)) - break; - - host->cmd = NULL; - rk2818_sdmmc_set_completed(host, EVENT_CMD_COMPLETE); - rk2818_sdmmc_command_complete(host, mrq->cmd); - //if (!mrq->data || cmd->error) { - if (!mrq->data || mrq->cmd->error) { - rk2818_sdmmc_request_end(host, host->mrq); - goto unlock; - } - - prev_state = state = STATE_SENDING_DATA; - /* fall through */ - - case STATE_SENDING_DATA: - if (rk2818_sdmmc_test_and_clear_pending(host, - EVENT_DATA_ERROR)) { - xjhprintk("[xjh] %s data->stop %p\n", __FUNCTION__,data->stop); - rk2818_sdmmc_stop_dma(host); - #if 0 - if (data->stop) - send_stop_cmd(host, data); - #else - if (data->stop) - send_stop_cmd(host, data); - else //cmd17 or cmd24 - { - xjhprintk("%s>> send stop command mannualy\n",__FUNCTION__); - host->stop_mannual.opcode = MMC_STOP_TRANSMISSION; - host->stop_mannual.arg = 0; - host->stop_mannual.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC; - host->stop_cmdr = 0x414c; - - host->mrq->stop = &host->stop_mannual; - data->stop = &host->stop_mannual; - send_stop_cmd(host, data); - } - #endif - state = STATE_DATA_ERROR; - xjhprintk("[xjh] %s sendging data error\n", __FUNCTION__); - break; - } - - if (!rk2818_sdmmc_test_and_clear_pending(host, - EVENT_XFER_COMPLETE)) - break; - rk2818_sdmmc_set_completed(host, EVENT_XFER_COMPLETE); - prev_state = state = STATE_DATA_BUSY; - /* fall through */ - - case STATE_DATA_BUSY: - if (!rk2818_sdmmc_test_and_clear_pending(host, - EVENT_DATA_COMPLETE)) - break; - - host->data = NULL; - rk2818_sdmmc_set_completed(host, EVENT_DATA_COMPLETE); - status = host->data_status; - - if (unlikely(status & RK2818_MCI_DATA_ERROR_FLAGS)) { - xjhprintk("[xjh] %s data error\n", __FUNCTION__); - if (status & SDMMC_INT_DRTO) { - dev_err(host->dev, - "data timeout error\n"); - data->error = -ETIMEDOUT; - } else if (status & SDMMC_INT_DCRC) { - dev_err(host->dev, - "data CRC error\n"); - data->error = -EILSEQ; - } else { - dev_err(host->dev, - "data FIFO error (status=%08x)\n", - status); - data->error = -EIO; - } - } - else { - data->bytes_xfered = data->blocks * data->blksz; - data->error = 0; - } - - if (!data->stop) { - rk2818_sdmmc_request_end(host, host->mrq); - goto unlock; - } - - prev_state = state = STATE_SENDING_STOP; - if (!data->error) - send_stop_cmd(host, data); - /* fall through */ - - case STATE_SENDING_STOP: - if (!rk2818_sdmmc_test_and_clear_pending(host, - EVENT_CMD_COMPLETE)) - break; - - //xjhprintk("[xjh] %s sending stop cmd end\n", __FUNCTION__); - host->cmd = NULL; - rk2818_sdmmc_command_complete(host, mrq->stop); - rk2818_sdmmc_request_end(host, host->mrq); - goto unlock; - case STATE_DATA_ERROR: - if (!rk2818_sdmmc_test_and_clear_pending(host, - EVENT_XFER_COMPLETE)) - break; - #if 0 - //[xjh] cmd17ûÓвúÉúDTOÖжϣ¬EVENT_DATA_COMPLETEûÓб»ÉèÖã¬ÐèÒªÊÖ¹¤ÉèÖà - //ΪºÎcmd17³ö´íºó²»ÄܲúÉúDTOÖжϣ¬ÐèÒª½øÒ»²½²éÃ÷??????? - if((host->mrq->cmd->opcode == 17)) { - xjhprintk("%s cmd%d was interrupt(host->pending_events %x)\n", - __FUNCTION__,host->mrq->cmd->opcode,host->pending_events); - // rk2818_sdmmc_set_pending(host, EVENT_DATA_COMPLETE); - } - #endif - - state = STATE_DATA_BUSY; - break; - } - } while (state != prev_state); - - host->state = state; - -unlock: - spin_unlock(&host->lock); - -} - - - -inline static void rk2818_sdmmc_push_data(struct rk2818_sdmmc_host *host, void *buf, int cnt) -{ - u32* pData = (u32*)buf; - - dev_dbg(host->dev, "push data(cnt=%d)\n",cnt); - - if (cnt % 4 != 0) - cnt = (cnt>>2) +1; - else - cnt = cnt >> 2; - while (cnt > 0) { - writel(*pData++, host->regs + SDMMC_DATA); - cnt--; - } -} - -inline static void rk2818_sdmmc_pull_data(struct rk2818_sdmmc_host *host, void *buf,int cnt) -{ - u32* pData = (u32*)buf; - - dev_dbg(host->dev, "pull data(cnt=%d)\n",cnt); - - - if (cnt % 4 != 0) - cnt = (cnt>>2) +1; - else - cnt = cnt >> 2; - while (cnt > 0) { - *pData++ = readl(host->regs + SDMMC_DATA); - cnt--; - } -} - -static void rk2818_sdmmc_read_data_pio(struct rk2818_sdmmc_host *host) -{ - struct scatterlist *sg = host->sg; - void *buf = sg_virt(sg); - unsigned int offset = host->pio_offset; - struct mmc_data *data = host->data; - u32 status; - unsigned int nbytes = 0,len,old_len,count =0; - xjhprintk("[xjh] %s enter,sg->length 0x%x\n", __FUNCTION__, sg->length); - - do { - len = SDMMC_GET_FCNT(readl(host->regs + SDMMC_STATUS)) << 2; - if(count == 0) - old_len = len; - if (likely(offset + len <= sg->length)) { - rk2818_sdmmc_pull_data(host, (void *)(buf + offset),len); - - offset += len; - nbytes += len; - - if (offset == sg->length) { - flush_dcache_page(sg_page(sg)); - host->sg = sg = sg_next(sg); - if (!sg) - goto done; - offset = 0; - buf = sg_virt(sg); - } - } else { - unsigned int remaining = sg->length - offset; - rk2818_sdmmc_pull_data(host, (void *)(buf + offset),remaining); - nbytes += remaining; - - flush_dcache_page(sg_page(sg)); - host->sg = sg = sg_next(sg); - if (!sg) - goto done; - offset = len - remaining; - buf = sg_virt(sg); - rk2818_sdmmc_pull_data(host, buf, offset); - nbytes += offset; - } - - status = readl(host->regs + SDMMC_MINTSTS); - writel(SDMMC_INT_RXDR, host->regs + SDMMC_RINTSTS); // clear RXDR interrupt - if (status & RK2818_MCI_DATA_ERROR_FLAGS) { - host->data_status = status; - data->bytes_xfered += nbytes; - smp_wmb(); - rk2818_sdmmc_set_pending(host, EVENT_DATA_ERROR); - tasklet_schedule(&host->tasklet); - return; - } - count ++; - } while (status & SDMMC_INT_RXDR); // if the RXDR is ready let read again - len = SDMMC_GET_FCNT(readl(host->regs + SDMMC_STATUS)); - host->pio_offset = offset; - data->bytes_xfered += nbytes; - xjhprintk("[xjh] %s exit-1\n", __FUNCTION__); - return; - -done: - data->bytes_xfered += nbytes; - smp_wmb(); - rk2818_sdmmc_set_pending(host, EVENT_XFER_COMPLETE); - xjhprintk("[xjh] %s exit-2\n", __FUNCTION__); -} - -static void rk2818_sdmmc_write_data_pio(struct rk2818_sdmmc_host *host) -{ - struct scatterlist *sg = host->sg; - void *buf = sg_virt(sg); - unsigned int offset = host->pio_offset; - struct mmc_data *data = host->data; - u32 status; - unsigned int nbytes = 0,len; - - do { - - len = SDMMC_FIFO_SZ - (SDMMC_GET_FCNT(readl(host->regs + SDMMC_STATUS)) << 2); - if (likely(offset + len <= sg->length)) { - rk2818_sdmmc_push_data(host, (void *)(buf + offset),len); - - offset += len; - nbytes += len; - if (offset == sg->length) { - host->sg = sg = sg_next(sg); - if (!sg) - goto done; - - offset = 0; - buf = sg_virt(sg); - } - } else { - unsigned int remaining = sg->length - offset; - - rk2818_sdmmc_push_data(host, (void *)(buf + offset), remaining); - nbytes += remaining; - - host->sg = sg = sg_next(sg); - if (!sg) { - goto done; - } - - offset = len - remaining; - buf = sg_virt(sg); - rk2818_sdmmc_push_data(host, (void *)buf, offset); - nbytes += offset; - } - - status = readl(host->regs + SDMMC_MINTSTS); - writel(SDMMC_INT_TXDR, host->regs + SDMMC_RINTSTS); // clear RXDR interrupt - if (status & RK2818_MCI_DATA_ERROR_FLAGS) { - host->data_status = status; - data->bytes_xfered += nbytes; - smp_wmb(); - rk2818_sdmmc_set_pending(host, EVENT_DATA_ERROR); - tasklet_schedule(&host->tasklet); - return; - } - } while (status & SDMMC_INT_TXDR); // if TXDR, let write again - - host->pio_offset = offset; - data->bytes_xfered += nbytes; - - return; - -done: - data->bytes_xfered += nbytes; - smp_wmb(); - rk2818_sdmmc_set_pending(host, EVENT_XFER_COMPLETE); -} - -static void rk2818_sdmmc_cmd_interrupt(struct rk2818_sdmmc_host *host, u32 status) -{ - if(!host->cmd_status) - host->cmd_status = status; - smp_wmb(); - rk2818_sdmmc_set_pending(host, EVENT_CMD_COMPLETE); - tasklet_schedule(&host->tasklet); -} - -static irqreturn_t rk2818_sdmmc_interrupt(int irq, void *data) -{ - struct rk2818_sdmmc_host *host = data; - u32 status, pending; - unsigned int pass_count = 0; - bool present; - bool present_old; - - spin_lock(&host->lock); - do { - status = readl(host->regs + SDMMC_RINTSTS); - pending = readl(host->regs + SDMMC_MINTSTS);// read only mask reg - if (!pending) - break; - if(pending & SDMMC_INT_CD) { - writel(SDMMC_INT_CD, host->regs + SDMMC_RINTSTS); // clear interrupt - - present = rk2818_sdmmc_get_cd(host->mmc); - present_old = test_bit(RK2818_MMC_CARD_PRESENT, &host->flags); - if(present != present_old) { - - if (present != 0) { - set_bit(RK2818_MMC_CARD_PRESENT, &host->flags); - } else { - clear_bit(RK2818_MMC_CARD_PRESENT, &host->flags); - } - - if(host->pdev->id ==0) { //sdmmc0 - xjhprintk("[xjh] %s >> %s >> %d sd/mmc insert/remove occur: Removal %d present %d present_old %d\n", - __FILE__, __FUNCTION__,__LINE__,sdmmc0_disable_Irq_ForRemoval,present,present_old); - if(0 == sdmmc0_disable_Irq_ForRemoval) { - mod_timer(&host->detect_timer, jiffies + msecs_to_jiffies(20)); - if(!test_bit(RK2818_MMC_CARD_PRESENT, &host->flags)) - sdmmc0_disable_Irq_ForRemoval = 1; - } - else - mod_timer(&host->detect_timer, jiffies + msecs_to_jiffies(RK28_SDMMC0_SWITCH_POLL_DELAY)); - } else { //sdio - mod_timer(&host->detect_timer, jiffies + msecs_to_jiffies(20)); - } - } - } - - if(pending & RK2818_MCI_CMD_ERROR_FLAGS) { - writel(RK2818_MCI_CMD_ERROR_FLAGS, host->regs + SDMMC_RINTSTS); // clear interrupt - if(status & SDMMC_INT_HLE) - { - xjhprintk("[xjh] %s :cmd transfer error(int status 0x%x cmd %d host->state %d pending_events %d)\n", - __FUNCTION__,status,host->cmd->opcode,host->state,host->pending_events); - - } - host->cmd_status = status; - smp_wmb(); - rk2818_sdmmc_set_pending(host, EVENT_CMD_COMPLETE); - tasklet_schedule(&host->tasklet); - host->cmd_tmo = 1; - xjhprintk("[xjh] %s :cmd transfer error(int status 0x%x cmd %d host->state %d pending_events %d)\n", - __FUNCTION__,status,host->cmd->opcode,host->state,host->pending_events); - } - - if (pending & RK2818_MCI_DATA_ERROR_FLAGS) { // if there is an error, let report DATA_ERROR - writel(RK2818_MCI_DATA_ERROR_FLAGS, host->regs + SDMMC_RINTSTS); // clear interrupt - host->data_status = status; - smp_wmb(); - rk2818_sdmmc_set_pending(host, EVENT_DATA_ERROR); - tasklet_schedule(&host->tasklet); - xjhprintk("[xjh] %s :data transfer error(int status 0x%x host->state %d pending_events %d)\n", - __FUNCTION__,status,host->state,host->pending_events); - } - - - if(pending & SDMMC_INT_DTO) { - writel(SDMMC_INT_DTO, host->regs + SDMMC_RINTSTS); // clear interrupt - if (!host->data_status) - host->data_status = status; - smp_wmb(); - /* if(host->dir_status == RK2818_MCI_RECV_STATUS) { - if(host->sg) - rk2818_sdmmc_read_data_pio(host); - }*/ - rk2818_sdmmc_set_pending(host, EVENT_DATA_COMPLETE); - tasklet_schedule(&host->tasklet); - } - - if (pending & SDMMC_INT_RXDR) { - writel(SDMMC_INT_RXDR, host->regs + SDMMC_RINTSTS); // clear interrupt - if(host->sg) - rk2818_sdmmc_read_data_pio(host); - } - - if (pending & SDMMC_INT_TXDR) { - writel(SDMMC_INT_TXDR, host->regs + SDMMC_RINTSTS); // clear interrupt - if(host->sg) { - rk2818_sdmmc_write_data_pio(host); - } - } - - if (pending & SDMMC_INT_CMD_DONE) { - writel(SDMMC_INT_CMD_DONE, host->regs + SDMMC_RINTSTS); // clear interrupt - rk2818_sdmmc_cmd_interrupt(host, status); - host->cmd_tmo = 1; - - } - if(pending & SDMMC_INT_SDIO) { - writel(SDMMC_INT_SDIO, host->regs + SDMMC_RINTSTS); - mmc_signal_sdio_irq(host->mmc); - } - } while (pass_count++ < 5); - - spin_unlock(&host->lock); - - - //return IRQ_HANDLED; - return pass_count ? IRQ_HANDLED : IRQ_NONE; -} - -static void rk2818_sdmmc_detect_change(unsigned long host_data) -{ - struct rk2818_sdmmc_host *host = (struct rk2818_sdmmc_host *) host_data; - //bool present; - //bool present_old; - //unsigned long flags; - #if 0 - mrq = host->mrq; - if (mrq) { - - host->data = NULL; - host->cmd = NULL; - xjhprintk("[xjh] %s >> %s >> %d stage 2\n", __FILE__, __FUNCTION__,__LINE__); - - switch (host->state) { - case STATE_IDLE: - break; - case STATE_SENDING_CMD: - mrq->cmd->error = -ENOMEDIUM; - if (!mrq->data) - break; - /* fall through */ - case STATE_SENDING_DATA: - mrq->data->error = -ENOMEDIUM; - xjhprintk("[xjh] %s host %p\n", __FUNCTION__,host); - rk2818_sdmmc_stop_dma(host); - break; - case STATE_DATA_BUSY: - case STATE_DATA_ERROR: - if (mrq->data->error == -EINPROGRESS) - mrq->data->error = -ENOMEDIUM; - if (!mrq->stop) - break; - case STATE_SENDING_STOP: - mrq->stop->error = -ENOMEDIUM; - break; - } - - rk2818_sdmmc_request_end(host, mrq); - } - #endif - - // spin_lock( &sdmmc0_spinlock); -// xjhprintk("%s....%s....%d **** timer open, then enable IRQ_OF_removal/insertion*****xbw****\n",__FUNCTION__,__FILE__,__LINE__); -// sdmmc0_disable_Irq_ForRemoval = 0; //´ò¿ªÖÐ¶Ï -// spin_unlock( &sdmmc0_spinlock); - - mmc_detect_change(host->mmc, 0); - -} - - -/*--------------------add communication interface with applications ---------------------------------*/ -int resetTimes = 0;//ͳ¼ÆÁ¬ÐøresetµÄ´ÎÊý¡£ -ssize_t sdmmc_reset_store(struct kobject *kobj, struct kobj_attribute *attr, - const char *buf, size_t count) -{ - //»òÕß´Ókobj×·Ëݵ½rk2818_sdmmc_host£¬½ÓÏÂÀ´³¢ÊÔ - struct rk2818_sdmmc_host *host = mmc0_host; - struct mmc_host *mmc = host->mmc; - int currentTimes=0; - unsigned long flags; - - if( !strncmp(buf,"RemoveDone" , strlen("RemoveDone")) ) - { - xjhprintk("%s------mmc receive the message of %s -----\n", __func__ , buf); - - local_irq_save(flags); - del_timer(&host->detect_timer); - sdmmc0_disable_Irq_ForRemoval = 0; //´ò¿ªÖÐ¶Ï - local_irq_restore(flags); - - //Ö÷¶¯Ö´ÐÐÒ»´Î¼ì²â, ÈôÓп¨´æÔÚ - if(rk2818_sdmmc_get_cd(host->mmc)) { - // mod_timer(&host->detect_timer, jiffies + msecs_to_jiffies(20)); - set_bit(RK2818_MMC_CARD_PRESENT, &host->flags); - mmc_detect_change(mmc, 0); - } - } - else if( !strncmp(buf,"Removing" , strlen("Removing")) ) - { - xjhprintk("%s------mmc receive the message of %s -----\n", __func__ , buf); - - //vold is removing, so modify the timer. - mod_timer(&host->detect_timer, jiffies +msecs_to_jiffies(RK28_SDMMC0_SWITCH_POLL_DELAY)); - } - else if( !strncmp(buf,"to_reset!" , strlen("to_reset!")) ) - { - xjhprintk("%s------mmc receive the message of %s -----\n", __func__ , buf); - - //ÉèÖÃresetµÄÔÊÐí´ÎÊý - ++resetTimes; - currentTimes = resetTimes; - - //Á¬Ðøµ÷ÓÃreset³¬¹ý´ÎÊý£¬²»Ö´ÐС£ - if(currentTimes <= 3) - { - xjhprintk("%s....%s....%d **** Begin to call rk28_sdmmc_reset() Times=%d *****xbw****\n",__FUNCTION__,__FILE__,__LINE__, resetTimes); - // rk28_sdmmc_reset(); - } - } - else if(!strncmp(buf,"mounted!" , strlen("mounted!"))) - { - xjhprintk("%s------mmc receive the message of %s -----\n", __func__ , buf); - resetTimes = 0; - } - else if(!strncmp(buf,"dump_reg" , strlen("dump_reg"))) - { - unsigned long cpsr_tmp; - xjhprintk("-------- SD/MMC/SDIO dump Registers-----------------\n"); - xjhprintk("SDMMC_CTRL:\t0x%x\n",readl(host->regs + SDMMC_CTRL)); - xjhprintk("SDMMC_PWREN:\t0x%x\n",readl(host->regs + SDMMC_PWREN)); - xjhprintk("SDMMC_CLKDIV:\t0x%x\n",readl(host->regs + SDMMC_CLKDIV)); - xjhprintk("SDMMC_CLKSRC:\t0x%x\n",readl(host->regs + SDMMC_CLKSRC)); - xjhprintk("SDMMC_CLKENA:\t0x%x\n",readl(host->regs + SDMMC_CLKENA)); - xjhprintk("SDMMC_TMOUT:\t0x%x\n",readl(host->regs + SDMMC_TMOUT)); - xjhprintk("SDMMC_CTYPE:\t0x%x\n",readl(host->regs + SDMMC_CTYPE)); - xjhprintk("SDMMC_BLKSIZ:\t0x%x\n",readl(host->regs + SDMMC_BLKSIZ)); - xjhprintk("SDMMC_BYTCNT:\t0x%x\n",readl(host->regs + SDMMC_BYTCNT)); - xjhprintk("SDMMC_INTMASK:\t0x%x\n",readl(host->regs + SDMMC_INTMASK)); - xjhprintk("SDMMC_CMDARG:\t0x%x\n",readl(host->regs + SDMMC_CMDARG)); - xjhprintk("SDMMC_CMD:\t0x%x\n",readl(host->regs + SDMMC_CMD)); - xjhprintk("SDMMC_RESP0:\t0x%x\n",readl(host->regs + SDMMC_RESP0)); - xjhprintk("SDMMC_RESP1:\t0x%x\n",readl(host->regs + SDMMC_RESP1)); - xjhprintk("SDMMC_RESP2:\t0x%x\n",readl(host->regs + SDMMC_RESP2)); - xjhprintk("SDMMC_RESP3:\t0x%x\n",readl(host->regs + SDMMC_RESP3)); - xjhprintk("SDMMC_MINTSTS:\t0x%x\n",readl(host->regs + SDMMC_MINTSTS)); - xjhprintk("SDMMC_RINTSTS:\t0x%x\n",readl(host->regs + SDMMC_RINTSTS)); - xjhprintk("SDMMC_STATUS:\t0x%x\n",readl(host->regs + SDMMC_STATUS)); - xjhprintk("SDMMC_FIFOTH:\t0x%x\n",readl(host->regs + SDMMC_FIFOTH)); - xjhprintk("SDMMC_CDETECT:\t0x%x\n",readl(host->regs + SDMMC_CDETECT)); - xjhprintk("SDMMC_WRTPRT:\t0x%x\n",readl(host->regs + SDMMC_WRTPRT)); - xjhprintk("SDMMC_TCBCNT:\t0x%x\n",readl(host->regs + SDMMC_TCBCNT)); - xjhprintk("SDMMC_TBBCNT:\t0x%x\n",readl(host->regs + SDMMC_TBBCNT)); - xjhprintk("SDMMC_DEBNCE:\t0x%x\n",readl(host->regs + SDMMC_DEBNCE)); - xjhprintk("-------- Host states-----------------\n"); - xjhprintk("host->state:\t0x%x\n",host->state); - xjhprintk("host->pending_events:\t0x%x\n",host->pending_events); - xjhprintk("host->cmd_status:\t0x%x\n",host->cmd_status); - xjhprintk("host->data_status:\t0x%x\n",host->data_status); - xjhprintk("host->stop_cmdr:\t0x%x\n",host->stop_cmdr); - xjhprintk("host->dir_status:\t0x%x\n",host->dir_status); - xjhprintk("host->completed_events:\t0x%x\n",host->completed_events); - xjhprintk("host->dma_chn:\t0x%x\n",host->dma_chn); - xjhprintk("host->use_dma:\t0x%x\n",host->use_dma); - xjhprintk("host->no_detect:\t0x%x\n",host->no_detect); - xjhprintk("host->bus_hz:\t0x%x\n",host->bus_hz); - xjhprintk("host->current_speed:\t0x%x\n",host->current_speed); - xjhprintk("host->ctype:\t0x%x\n",host->ctype); - xjhprintk("host->clock:\t0x%x\n",host->clock); - xjhprintk("host->flags:\t0x%x\n",host->flags); - xjhprintk("host->irq:\t0x%x\n",host->irq); - xjhprintk("-------- rk2818 CPU register-----------------\n"); - __asm__ volatile ("mrs %0, cpsr @ local_irq_save\n":"=r" (cpsr_tmp)::"memory", "cc" ); - xjhprintk("cpsr:\t0x%x\n",cpsr_tmp); - - - } - - return count; -} - - - -struct kobj_attribute mmc_reset_attrs = -{ - .attr = { - .name = "rescan", - .mode = 0777}, - .show = NULL, - .store = sdmmc_reset_store, -}; -struct attribute *mmc_attrs[] = -{ - &mmc_reset_attrs.attr, - NULL -}; - -static struct kobj_type mmc_kset_ktype = { - .sysfs_ops = &kobj_sysfs_ops, - .default_attrs = &mmc_attrs[0], -}; -static int rk28_sdmmc0_add_attr( struct platform_device *pdev ) -{ - int result; - struct kobject *parentkobject; - struct kobject * me = kmalloc(sizeof(struct kobject) , GFP_KERNEL ); - if( !me ) - return -ENOMEM; - memset(me ,0,sizeof(struct kobject)); - kobject_init( me , &mmc_kset_ktype ); - //result = kobject_add( me , &pdev->dev.kobj , "%s", "RESET" ); - parentkobject = &pdev->dev.kobj ; - result = kobject_add( me , parentkobject->parent->parent, "%s", "resetSdCard" ); - return result; -} - -static void rk2818_sdmmc_check_status(unsigned long data) -{ - struct rk2818_sdmmc_host *host = (struct rk2818_sdmmc_host *)data; - struct rk2818_sdmmc_platform_data *pdata = host->pdev->dev.platform_data; - unsigned int status; - - if (!pdata->status) - { - mmc_detect_change(host->mmc, 0); - return; - } - - status = pdata->status(mmc_dev(host->mmc)); - - if (status ^ host->oldstatus) - { - pr_info("%s: slot status change detected(%d-%d)\n",mmc_hostname(host->mmc), host->oldstatus, status); - if (status) - mmc_detect_change(host->mmc, 100); - else - mmc_detect_change(host->mmc, 0); - } - - host->oldstatus = status; - -} - -static void rk2818_sdmmc_status_notify_cb(int card_present, void *dev_id) -{ - struct rk2818_sdmmc_host *host = dev_id; - printk(KERN_INFO "%s, card_present %d\n", mmc_hostname(host->mmc), card_present); - rk2818_sdmmc_check_status((unsigned long)host); -} - -/*-------------------end of add communication interface with applications ---------------------------------*/ - -static int rk2818_sdmmc_probe(struct platform_device *pdev) -{ - struct rk2818_sdmmc_host *host = NULL; - struct mmc_host *mmc; - struct resource *res; - struct rk2818_sdmmc_platform_data *pdata; - int ret = 0; - int tmo = 200; - - pdata = pdev->dev.platform_data; - if (!pdata) { - dev_err(&pdev->dev, "No platform data\n"); - return -EINVAL; - } - if(pdata->io_init) - pdata->io_init(); - - mmc = mmc_alloc_host(sizeof(struct rk2818_sdmmc_host), &pdev->dev); - if (!mmc) - { - dev_err(&pdev->dev, "Mmc alloc host failture\n"); - return -ENOMEM; - } - host = mmc_priv(mmc); - - host->mmc = mmc; - host->pdev = pdev; - host->dev = &pdev->dev; - host->dma_chn = -1; - - host->use_dma = pdata->use_dma; - host->no_detect = pdata->no_detect; - memcpy(host->dma_name, pdata->dma_name, 8); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - { - dev_err(&pdev->dev, "Cannot find IO resource\n"); - ret = -ENOENT; - goto err_free_host; - } - host->mem = request_mem_region(res->start, resource_size(res), pdev->name); - if(host->mem == NULL) - { - dev_err(&pdev->dev, "Cannot request IO\n"); - ret = -ENXIO; - goto err_free_host; - } - host->regs = ioremap(res->start, res->end - res->start + 1); - if (!host->regs) - { - dev_err(&pdev->dev, "Cannot map IO\n"); - ret = -ENXIO; - goto err_release_resource; - } - - host->irq = ret = platform_get_irq(pdev, 0); - if (ret < 0) - { - dev_err(&pdev->dev, "Cannot find IRQ\n"); - goto err_free_map; - } - - /* setup wifi card detect change */ - if (pdata->register_status_notify) - { - pdata->register_status_notify(rk2818_sdmmc_status_notify_cb, host); - } - - spin_lock_init(&host->lock); - INIT_LIST_HEAD(&host->queue); - - host->clk = clk_get(&pdev->dev, "sdmmc"); - if (IS_ERR(host->clk)) { - dev_err(&pdev->dev, "failed to find clock source.\n"); - ret = PTR_ERR(host->clk); - host->clk = NULL; - goto err_free_map; - } - clk_enable(host->clk); - host->bus_hz = clk_get_rate(host->clk); - - writel((SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET | SDMMC_CTRL_INT_ENABLE), host->regs + SDMMC_CTRL); - while (--tmo && readl(host->regs + SDMMC_CTRL) & - (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET)) - udelay(5); - if(--tmo < 0){ - dev_err(&pdev->dev, "failed to reset controller and fifo(timeout = 1ms).\n"); - goto err_free_clk; - } - - writel(0xFFFFFFFF, host->regs + SDMMC_RINTSTS); - writel(0, host->regs + SDMMC_INTMASK); // disable all mmc interrupt first - - /* Put in max timeout */ - writel(0xFFFFFFFF, host->regs + SDMMC_TMOUT); - - /* DMA Size = 8, RXMark = 15, TXMark = 16 */ - writel((3 << 28) | (15 << 16) | 16, host->regs + SDMMC_FIFOTH); - /* disable clock to CIU */ - writel(0, host->regs + SDMMC_CLKENA); - writel(0, host->regs + SDMMC_CLKSRC); - - tasklet_init(&host->tasklet, rk2818_sdmmc_tasklet_func, (unsigned long)host); - - ret = request_irq(host->irq, rk2818_sdmmc_interrupt, 0, dev_name(&pdev->dev), host); - if (ret){ - dev_err(&pdev->dev, "Cannot claim IRQ %d.\n", host->irq); - goto err_free_clk; - } - - - platform_set_drvdata(pdev, host); - dev_dbg(host->dev, "pdev->id = %d\n", pdev->id); - mmc->ops = &(rk2818_sdmmc_ops[pdev->id]); - - mmc->f_min = host->bus_hz/510; - mmc->f_max = host->bus_hz/2; - dev_dbg(&pdev->dev, "bus_hz = %u\n", host->bus_hz); - mmc->ocr_avail = pdata->host_ocr_avail; - mmc->caps = pdata->host_caps; - - mmc->max_phys_segs = 64; - mmc->max_hw_segs = 64; - mmc->max_blk_size = 4095; - mmc->max_blk_count = 512; - mmc->max_req_size = 4095 * 512; - mmc->max_seg_size = 4095 * 4; - - rk2818_sdmmc_set_power(host, 0); - - /* Create card detect handler thread for the host */ - setup_timer(&host->detect_timer, rk2818_sdmmc_detect_change, - (unsigned long)host); - - writel(0xFFFFFFFF, host->regs + SDMMC_RINTSTS); - writel(SDMMC_INT_CMD_DONE | SDMMC_INT_DTO | RK2818_MCI_ERROR_FLAGS | SDMMC_INT_CD, - host->regs + SDMMC_INTMASK); - - if((strncmp(host->dma_name, "sdio", strlen("sdio")) == 0) && - (readl(host->regs + SDMMC_STATUS) & SDMMC_STAUTS_DATA_BUSY)) - { - dev_err(host->dev, "sdio is busy, fail to init sdio.please check if wifi_d0's level is high?\n"); - ret = -EINVAL; - return ret; - } -#if 0 - /* Assume card is present initially */ - if(rk2818_sdmmc_get_cd(host->mmc) == 0 &&strncmp(host->dma_name, "sdio", strlen("sdio")) == 0) - { - dev_err(&pdev->dev, "failed to detect sdio.\n"); - return 0; - } - else if(rk2818_sdmmc_get_cd(host->mmc) != 0) - set_bit(RK2818_MMC_CARD_PRESENT, &host->flags); - else - clear_bit(RK2818_MMC_CARD_PRESENT, &host->flags); -#endif - - ret = mmc_add_host(mmc); - - - if (strncmp(host->dma_name, "sdio", strlen("sdio")) == 0) - { - wifi_mmc_host = mmc; - if(request_dma(1, host->dma_name) == 0) - host->dma_chn = 1; - else - { - ret = -EINVAL; - goto err_remove_host; - } - } - - if(ret) - { - dev_err(&pdev->dev, "failed to add mmc host.\n"); - goto err_free_irq; - } - if (strncmp(host->dma_name, "sd_mmc", strlen("sd_mmc")) == 0) { - xjhprintk("[xjh] sdmmc0 add interface with application\n"); - sdmmc0_disable_Irq_ForRemoval = 0; //´ò¿ªÖÐ¶Ï - mmc0_host = host; - rk28_sdmmc0_add_attr(pdev); - } - -#if defined (CONFIG_DEBUG_FS) - rk2818_sdmmc_init_debugfs(host); -#endif - writel(SDMMC_CTRL_INT_ENABLE, host->regs + SDMMC_CTRL); // enable mci interrupt - - dev_info(&pdev->dev, "RK2818 MMC controller used as %s, at irq %d\n", - host->dma_name, host->irq); - return 0; -err_remove_host: - mmc_remove_host(host->mmc); -err_free_irq: - free_irq(host->irq, host); -err_free_clk: - clk_disable(host->clk); - clk_put(host->clk); -err_free_map: - iounmap(host->regs); -err_release_resource: - release_resource(host->mem); -err_free_host: - kfree(host); - return ret; -} - -static int __exit rk2818_sdmmc_remove(struct platform_device *pdev) -{ - struct rk2818_sdmmc_host *host = platform_get_drvdata(pdev); - - if (strncmp(host->dma_name, "sdio", 4) == 0) - wifi_mmc_host = NULL; - - writel(0xFFFFFFFF, host->regs + SDMMC_RINTSTS); - writel(0, host->regs + SDMMC_INTMASK); // disable all mmc interrupt first - - platform_set_drvdata(pdev, NULL); - - dev_dbg(&pdev->dev, "remove host\n"); - - writel(0, host->regs + SDMMC_CLKENA); - writel(0, host->regs + SDMMC_CLKSRC); - - del_timer_sync(&host->detect_timer); - set_bit(RK2818_MMC_SHUTDOWN, &host->flags); - mmc_remove_host(host->mmc); - mmc_free_host(host->mmc); - - clk_disable(host->clk); - clk_put(host->clk); - free_irq(host->irq, host); - iounmap(host->regs); - release_resource(host->mem); - kfree(host); - return 0; -} - -static int rk2818_sdmmc_suspend(struct platform_device *pdev, pm_message_t state) -{ - struct rk2818_sdmmc_host *host = platform_get_drvdata(pdev); -#ifdef CONFIG_PM - writel(0, host->regs + SDMMC_CLKENA); - clk_disable(host->clk); -#endif - return 0; -} - -static int rk2818_sdmmc_resume(struct platform_device *pdev) -{ - struct rk2818_sdmmc_host *host = platform_get_drvdata(pdev); -#ifdef CONFIG_PM - clk_enable(host->clk); - writel(SDMMC_CLKEN_ENABLE, host->regs + SDMMC_CLKENA); -#endif - return 0; -} - -static struct platform_driver rk2818_sdmmc_driver = { - .probe = rk2818_sdmmc_probe, - .suspend = rk2818_sdmmc_suspend, - .resume = rk2818_sdmmc_resume, - .remove = __exit_p(rk2818_sdmmc_remove), - .driver = { - .name = "rk2818_sdmmc", - }, -}; - -static int __init rk2818_sdmmc_init(void) -{ - return platform_driver_register(&rk2818_sdmmc_driver); -} - -static void __exit rk2818_sdmmc_exit(void) -{ - platform_driver_unregister(&rk2818_sdmmc_driver); -} - -module_init(rk2818_sdmmc_init); -module_exit(rk2818_sdmmc_exit); - -MODULE_DESCRIPTION("Driver for RK2818 SDMMC controller"); -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("kfx kfx@rock-chips.com"); - diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 623a645b808e..28cf68cf6884 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -360,11 +360,6 @@ config MTD_NAND_ATMEL_ECC_NONE endchoice -config MTD_NAND_RK2818 - tristate "NAND Flash support for RK2818" - depends on ARCH_RK2818 - help - This enables the NAND flash controller on the RK2818 SoC config MTD_NAND_RK29 tristate "NAND Flash support for RK29sdk" depends on ARCH_RK29 diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 36ee8b51a510..e107371e06ec 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -42,6 +42,5 @@ obj-$(CONFIG_MTD_NAND_SOCRATES) += socrates_nand.o obj-$(CONFIG_MTD_NAND_TXX9NDFMC) += txx9ndfmc.o obj-$(CONFIG_MTD_NAND_W90P910) += w90p910_nand.o obj-$(CONFIG_MTD_NAND_NOMADIK) += nomadik_nand.o -obj-$(CONFIG_MTD_NAND_RK2818) += rk2818_nand.o obj-$(CONFIG_MTD_NAND_RK29) += rk29_nand.o nand-objs := nand_base.o nand_bbt.o diff --git a/drivers/mtd/nand/rk2818_nand.c b/drivers/mtd/nand/rk2818_nand.c deleted file mode 100755 index fe5f320c011f..000000000000 --- a/drivers/mtd/nand/rk2818_nand.c +++ /dev/null @@ -1,1088 +0,0 @@ - -/* - * drivers/mtd/nand/rk2818_nand.c - * - * Copyright (C) 2010 RockChip, Inc. - * Author: hxy@rock-chips.com - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#define PROGRAM_BUSY_COUNT 10000 -#define ERASE_BUSY_COUNT 20000 -#define READ_BUSY_COUNT 5000 -#define RESET_BUSY_COUNT 20000 - -/* Define delays in microsec for NAND device operations */ -#define TROP_US_DELAY 2000 - - -#ifdef CONFIG_DM9000_USE_NAND_CONTROL -static DEFINE_MUTEX(rknand_mutex); -#define RKNAND_LOCK() do { int panic = in_interrupt() | in_atomic(); if (!panic) mutex_lock(&rknand_mutex); } while (0) -#define RKNAND_UNLOCK() do { int panic = in_interrupt() | in_atomic(); if (!panic) mutex_unlock(&rknand_mutex); } while (0) -#else -#define RKNAND_LOCK() do {} while (0) -#define RKNAND_UNLOCK() do {} while (0) -#endif - -struct rk2818_nand_mtd { - struct mtd_info mtd; - struct nand_chip nand; - struct mtd_partition *parts; - struct device *dev; - const struct rk2818_nand_flash *flash_info; - - struct clk *clk; - unsigned long clk_rate; - void __iomem *regs; - int cs; // support muliple nand chip,record current chip select - u_char accesstime; -#ifdef CONFIG_CPU_FREQ - struct notifier_block freq_transition; -#endif - -}; - -/* OOB placement block for use with software ecc generation */ -static struct nand_ecclayout nand_sw_eccoob_8 = { - .eccbytes = 48, - .eccpos = { 8, 9, 10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31, - 32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55}, - .oobfree = {{0,8},{56, 72}} -}; - -/* OOB placement block for use with hardware ecc generation */ -static struct nand_ecclayout nand_hw_eccoob_16 = { - .eccbytes = 28, - .eccpos = { 4, 5, 6, 7, 8, 9, 10,11,12,13,14,15,16,17, - 18,19,20,21,22,23,24,25,26,27,28,29,30,31}, - .oobfree = {{0, 4}} -}; - -#ifdef CONFIG_MTD_PARTITIONS -static const char *part_probes[] = { "cmdlinepart", NULL }; -#endif - - -static void rk2818_nand_wait_busy(struct mtd_info *mtd, uint32_t timeout) -{ - - struct nand_chip *nand_chip = mtd->priv; - struct rk2818_nand_mtd *master = nand_chip->priv; - pNANDC pRK28NC= (pNANDC)(master->regs); - - while (timeout > 0) - { - timeout--; - udelay(10); - if ( pRK28NC->FMCTL& FMC_FRDY) - break; - - } - - return; -} - -static void rk2818_nand_wait_bchdone(struct mtd_info *mtd, uint32_t timeout) -{ - - struct nand_chip *nand_chip = mtd->priv; - struct rk2818_nand_mtd *master = nand_chip->priv; - pNANDC pRK28NC= (pNANDC)(master->regs); - - while (timeout > 0) - { - timeout--; - udelay(1); - if(pRK28NC->BCHST &(1<<1)) - break; - } - - return; -} - -// only for dma mode -static void wait_op_done(struct mtd_info *mtd, int max_retries, uint16_t param) -{ - struct nand_chip *nand_chip = mtd->priv; - struct rk2818_nand_mtd *master = nand_chip->priv; - pNANDC pRK28NC= (pNANDC)(master->regs); - - while (max_retries-- > 0) { - udelay(1); - if (pRK28NC->FLCTL & FL_RDY) - break; - } -} - -static int rk2818_nand_dev_ready(struct mtd_info *mtd) -{ - struct nand_chip *nand_chip = mtd->priv; - struct rk2818_nand_mtd *master = nand_chip->priv; - pNANDC pRK28NC= (pNANDC)(master->regs); - - if(pRK28NC->FMCTL& FMC_FRDY) - return 1; - else - return 0; -} - -/* -* ÉèÖÃƬѡ -*/ -static void rk2818_nand_select_chip(struct mtd_info *mtd, int chip) -{ - struct nand_chip *nand_chip = mtd->priv; - struct rk2818_nand_mtd *master = nand_chip->priv; - pNANDC pRK28NC= (pNANDC)(master->regs); - - - if( chip<0 ) - pRK28NC->FMCTL &=0xffffff00; // release chip select - else - { - master->cs = chip; - pRK28NC->FMCTL &=0xffffff00; - pRK28NC ->FMCTL |= 0x1<priv; - struct rk2818_nand_mtd *master = nand_chip->priv; - pNANDC pRK28NC= (pNANDC)(master->regs); - - u_char ret = 0; - - ret = (u_char)(pRK28NC ->chip[master->cs].data); - - return ret; -} - -/* - * ¶ÁÒ»¸öword ³¤¶ÈÊý¾Ý -*/ -static u16 rk2818_nand_read_word(struct mtd_info *mtd) -{ - struct nand_chip *nand_chip = mtd->priv; - struct rk2818_nand_mtd *master = nand_chip->priv; - pNANDC pRK28NC= (pNANDC)(master->regs); - - - u_char tmp1 = 0,tmp2=0; - u16 ret=0; - - tmp1 = (u_char)(pRK28NC ->chip[master->cs].data); - tmp2 = (u_char)(pRK28NC ->chip[master->cs].data); - - ret = (tmp2 <<8)|tmp1; - - return ret; -} - -static void rk2818_nand_read_buf(struct mtd_info *mtd, u_char* const buf, int len) -{ - struct nand_chip *nand_chip = mtd->priv; - struct rk2818_nand_mtd *master = nand_chip->priv; - pNANDC pRK28NC= (pNANDC)(master->regs); - uint32_t i, chipnr; - - RKNAND_LOCK(); - - chipnr = master->cs ; - - rk2818_nand_select_chip(mtd,chipnr); - - - - if ( len < mtd->writesize ) // read oob - { - pRK28NC ->BCHCTL = BCH_RST; - pRK28NC ->FLCTL = (0<<4)|FL_COR_EN|(0x1<<5)|FL_BYPASS|FL_START ; - wait_op_done(mtd,TROP_US_DELAY,0); - rk2818_nand_wait_bchdone(mtd,TROP_US_DELAY) ; - memcpy(buf,(u_char *)(pRK28NC->spare),4); // only use nandc sram0 - } - else - { - pRK28NC->FLCTL |= FL_BYPASS; // dma mode - for(i=0;iwritesize/0x400;i++) - { - pRK28NC ->BCHCTL = BCH_RST; - pRK28NC ->FLCTL = (0<<4)|FL_COR_EN|(0x1<<5)|FL_BYPASS|FL_START ; - wait_op_done(mtd,TROP_US_DELAY,0); - rk2818_nand_wait_bchdone(mtd,TROP_US_DELAY) ; - memcpy(buf+i*0x400,(u_char *)(pRK28NC->buf),0x400); // only use nandc sram0 - } - } - - - - rk2818_nand_select_chip(mtd,-1); - - RKNAND_UNLOCK(); - - - return; - -} - -static void rk2818_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct nand_chip *nand_chip = mtd->priv; - struct rk2818_nand_mtd *master = nand_chip->priv; - pNANDC pRK28NC= (pNANDC)(master->regs); - - uint32_t i = 0, chipnr; - - - RKNAND_LOCK(); - - chipnr = master->cs ; - - rk2818_nand_select_chip(mtd,chipnr); - - pRK28NC->FLCTL |= FL_BYPASS; // dma mode - - - for(i=0;iwritesize/0x400;i++) - { - memcpy((u_char *)(pRK28NC->buf),buf+i*0x400,0x400); // only use nandc sram0 - pRK28NC ->BCHCTL =BCH_WR|BCH_RST; - pRK28NC ->FLCTL = (0<<4)|FL_COR_EN|0x1<<5|FL_RDN|FL_BYPASS|FL_START; - wait_op_done(mtd,TROP_US_DELAY,0); - } - - - - rk2818_nand_select_chip(mtd,-1); - - RKNAND_UNLOCK(); - - -} - - -static void rk2818_nand_cmdfunc(struct mtd_info *mtd, unsigned command,int column, int page_addr) -{ - struct nand_chip *nand_chip = mtd->priv; - struct rk2818_nand_mtd *master = nand_chip->priv; - pNANDC pRK28NC= (pNANDC)(master->regs); - - uint32_t timeout = 1000; - char status,ret; - - - switch (command) { - - case NAND_CMD_READID: - pRK28NC ->chip[master->cs].cmd = command; - pRK28NC ->chip[master->cs].addr = 0x0; - while (timeout>0) - { - timeout --; - udelay(1); - if(pRK28NC->FLCTL&FL_INTCLR) - break; - - } - - rk2818_nand_wait_busy(mtd,READ_BUSY_COUNT); - break; - - case NAND_CMD_READ0: - pRK28NC ->chip[master->cs].cmd = command; - if ( column>= 0 ) - { - pRK28NC ->chip[master->cs].addr = column & 0xff; - if( mtd->writesize > 512) - pRK28NC ->chip[master->cs].addr = (column >> 8) & 0xff; - } - if ( page_addr>=0 ) - { - pRK28NC ->chip[master->cs].addr = page_addr & 0xff; - pRK28NC ->chip[master->cs].addr = (page_addr >> 8) & 0xFF; - pRK28NC ->chip[master->cs].addr = (page_addr >> 16) & 0xff; - } - if( mtd->writesize > 512) - pRK28NC ->chip[0].cmd = NAND_CMD_READSTART; - - rk2818_nand_wait_busy(mtd,READ_BUSY_COUNT); - - break; - - case NAND_CMD_READ1: - pRK28NC ->chip[master->cs].cmd = command; - break; - - case NAND_CMD_READOOB: - pRK28NC ->BCHCTL = 0x0; - if( mtd->writesize > 512 ) - command = NAND_CMD_READ0; // È«²¿¶Á£¬°üÀ¨¶Áoob - - pRK28NC ->chip[master->cs].cmd = command; - - if ( mtd->writesize >512 ) - { - if ( column>= 0 ) - { - pRK28NC ->chip[master->cs].addr = column & 0xff; - pRK28NC ->chip[master->cs].addr = ( column >> 8) & 0xff; - } - if ( page_addr>=0 ) - { - pRK28NC ->chip[master->cs].addr = page_addr & 0xff; - pRK28NC ->chip[master->cs].addr = (page_addr >> 8) & 0xFF; - pRK28NC ->chip[master->cs].addr = (page_addr >> 16) & 0xff; - } - pRK28NC ->chip[master->cs].cmd = NAND_CMD_READSTART; - } - else - { - pRK28NC ->chip[master->cs].addr = column; - } - - rk2818_nand_wait_busy(mtd,READ_BUSY_COUNT); - - - break; - - case NAND_CMD_PAGEPROG: - pRK28NC ->FMCTL |= FMC_WP; //½â³ýд±£»¤ - pRK28NC ->chip[master->cs].cmd = command; - rk2818_nand_wait_busy(mtd,PROGRAM_BUSY_COUNT); - - pRK28NC ->chip[master->cs].cmd = NAND_CMD_STATUS; - status = pRK28NC ->chip[master->cs].data; - - if(status&0x1) - ret = -1; - else - ret =0; - - break; - - case NAND_CMD_ERASE1: - pRK28NC ->FMCTL |= FMC_WP; //½â³ýд±£»¤ - pRK28NC ->BCHCTL = 0x0; - pRK28NC ->chip[master->cs].cmd = command; - if ( page_addr>=0 ) - { - pRK28NC ->chip[master->cs].addr = page_addr & 0xff; - pRK28NC ->chip[master->cs].addr = (page_addr>>8)&0xff; - pRK28NC ->chip[master->cs].addr = (page_addr>>16)&0xff; - } - break; - - case NAND_CMD_ERASE2: - pRK28NC ->FMCTL |= FMC_WP; //½â³ýд±£»¤ - pRK28NC ->chip[master->cs].cmd = command; - rk2818_nand_wait_busy(mtd,ERASE_BUSY_COUNT); - pRK28NC ->chip[master->cs].cmd = NAND_CMD_STATUS; - status = pRK28NC ->chip[master->cs].data; - - if(status&0x1) - ret = -1; - else - ret =0; - - break; - - case NAND_CMD_SEQIN: - pRK28NC ->FMCTL |= FMC_WP; //½â³ýд±£»¤ - pRK28NC ->chip[master->cs].cmd = command; - udelay(1); - if ( column>= 0 ) - { - pRK28NC ->chip[master->cs].addr = column; - if( mtd->writesize > 512) - pRK28NC ->chip[master->cs].addr = (column >> 8) & 0xff; - } - if( page_addr>=0 ) - { - pRK28NC ->chip[master->cs].addr = page_addr & 0xff; - pRK28NC ->chip[master->cs].addr = (page_addr>>8)&0xff; - pRK28NC ->chip[master->cs].addr = (page_addr>>16)&0xff; - } - - break; - - case NAND_CMD_STATUS: - pRK28NC ->BCHCTL = 0x0; - pRK28NC ->chip[master->cs].cmd = command; - while (timeout>0) - { - timeout --; - udelay(1); - if(pRK28NC->FLCTL&FL_INTCLR) - break; - - } - break; - - case NAND_CMD_RESET: - pRK28NC ->chip[master->cs].cmd = command; - while (timeout>0) - { - timeout --; - udelay(1); - if(pRK28NC->FLCTL&FL_INTCLR) - break; - - } - rk2818_nand_wait_busy(mtd,RESET_BUSY_COUNT); - break; - - /* This applies to read commands */ - default: - pRK28NC ->chip[master->cs].cmd = command; - break; - } - - udelay (1); - -} - -int rk2818_nand_calculate_ecc(struct mtd_info *mtd,const uint8_t *dat,uint8_t *ecc_code) -{ - struct nand_chip *nand_chip = mtd->priv; - struct rk2818_nand_mtd *master = nand_chip->priv; - pNANDC pRK28NC= (pNANDC)(master->regs); - - int eccdata[7],i; - - for(i=0;i<7;i++) - { - eccdata[i] = pRK28NC->spare[i+1]; - - - ecc_code[i*4] = eccdata[i]& 0xff; - ecc_code[i*4+1] = (eccdata[i]>> 8)& 0xff; - ecc_code[i*4+2] = (eccdata[i]>>16)& 0xff; - ecc_code[i*4+3] = (eccdata[i]>>24)& 0xff; - - } - - return 0; -} - - void rk2818_nand_hwctl_ecc(struct mtd_info *mtd, int mode) - { - struct nand_chip *nand_chip = mtd->priv; - struct rk2818_nand_mtd *master = nand_chip->priv; - pNANDC pRK28NC= (pNANDC)(master->regs); - - pRK28NC->BCHCTL = 1; // reset bch and enable hw ecc - - return; - } - - int rk2818_nand_correct_data(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,uint8_t *calc_ecc) - { - struct nand_chip *nand_chip = mtd->priv; - struct rk2818_nand_mtd *master = nand_chip->priv; - pNANDC pRK28NC= (pNANDC)(master->regs); - - // hw correct data - if( pRK28NC->BCHST & (1<<2) ) - { - DEBUG(MTD_DEBUG_LEVEL0, - "rk2818 nand :hw ecc uncorrectable error\n"); - return -1; - } - - return 0; - } - - int rk2818_nand_read_page(struct mtd_info *mtd,struct nand_chip *chip,uint8_t *buf, int page) - { - struct nand_chip *nand_chip = mtd->priv; - struct rk2818_nand_mtd *master = nand_chip->priv; - pNANDC pRK28NC= (pNANDC)(master->regs); - - int i,chipnr; - - - RKNAND_LOCK(); - - chipnr = master->cs ; - - rk2818_nand_select_chip(mtd,chipnr); - - - rk2818_nand_wait_busy(mtd,READ_BUSY_COUNT); - - pRK28NC->FLCTL |= FL_BYPASS; // dma mode - - for(i=0;iwritesize/0x400;i++) - { - pRK28NC ->BCHCTL = BCH_RST; - pRK28NC ->FLCTL = (0<<4)|FL_COR_EN|(0x1<<5)|FL_BYPASS|FL_START ; - wait_op_done(mtd,TROP_US_DELAY,0); - rk2818_nand_wait_bchdone(mtd,TROP_US_DELAY) ; - - memcpy(buf+i*0x400,(u_char *)(pRK28NC->buf),0x400); // only use nandc sram0 - } - - - rk2818_nand_select_chip(mtd,-1); - - RKNAND_UNLOCK(); - - return 0; - - } - -void rk2818_nand_write_page(struct mtd_info *mtd,struct nand_chip *chip,const uint8_t *buf) - { - struct nand_chip *nand_chip = mtd->priv; - struct rk2818_nand_mtd *master = nand_chip->priv; - pNANDC pRK28NC= (pNANDC)(master->regs); - uint32_t i = 0, chipnr; - - RKNAND_LOCK(); - - chipnr = master->cs ; - - rk2818_nand_select_chip(mtd,chipnr); - - pRK28NC->FLCTL |= FL_BYPASS; // dma mode - - - for(i=0;iwritesize/0x400;i++) - { - memcpy((u_char *)(pRK28NC->buf),(buf+i*0x400),0x400); // only use nandc sram0 - if(i==0) - memcpy((u_char *)(pRK28NC->spare),(u_char *)(chip->oob_poi + chip->ops.ooboffs),4); - - pRK28NC ->BCHCTL = BCH_WR|BCH_RST; - pRK28NC ->FLCTL = (0<<4)|FL_COR_EN|(0x1<<5)|FL_RDN|FL_BYPASS|FL_START; - wait_op_done(mtd,TROP_US_DELAY,0); - } - - pRK28NC ->chip[0].cmd = NAND_CMD_PAGEPROG; - - - - rk2818_nand_wait_busy(mtd,PROGRAM_BUSY_COUNT); - - rk2818_nand_select_chip(mtd,-1); - - RKNAND_UNLOCK(); - - return; - - } - -int rk2818_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, int page, int sndcmd) -{ - struct nand_chip *nand_chip = mtd->priv; - struct rk2818_nand_mtd *master = nand_chip->priv; - pNANDC pRK28NC= (pNANDC)(master->regs); - int i,chipnr; - - - if (sndcmd) { - chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); - sndcmd = 0; - } - - RKNAND_LOCK(); - - chipnr = master->cs ; - - rk2818_nand_select_chip(mtd,chipnr); - - rk2818_nand_wait_busy(mtd,READ_BUSY_COUNT); - - - pRK28NC->FLCTL |= FL_BYPASS; // dma mode - - - - - for(i=0;iwritesize/0x400;i++) - { - pRK28NC ->BCHCTL = BCH_RST; - pRK28NC ->FLCTL = (0<<4)|FL_COR_EN|(0x1<<5)|FL_BYPASS|FL_START ; - wait_op_done(mtd,TROP_US_DELAY,0); - rk2818_nand_wait_bchdone(mtd,TROP_US_DELAY) ; - if(i==0) - memcpy((u_char *)(chip->oob_poi+ chip->ops.ooboffs),(u_char *)(pRK28NC->spare),4); - } - - - rk2818_nand_select_chip(mtd,-1); - - RKNAND_UNLOCK(); - - - return sndcmd; -} - -int rk2818_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int page) -{ - struct nand_chip *nand_chip = mtd->priv; - struct rk2818_nand_mtd *master = nand_chip->priv; - pNANDC pRK28NC= (pNANDC)(master->regs); - - int i,chipnr; - - - RKNAND_LOCK(); - - chipnr = master->cs ; - - rk2818_nand_select_chip(mtd,chipnr); - - rk2818_nand_wait_busy(mtd,READ_BUSY_COUNT); - - pRK28NC->FLCTL |= FL_BYPASS; // dma mode - - - - for(i=0;iwritesize/0x400;i++) - { - pRK28NC ->BCHCTL = BCH_RST; - pRK28NC ->FLCTL = (0<<4)|FL_COR_EN|(0x1<<5)|FL_BYPASS|FL_START ; - wait_op_done(mtd,TROP_US_DELAY,0); - rk2818_nand_wait_bchdone(mtd,TROP_US_DELAY) ; - memcpy(buf+i*0x400,(u_char *)(pRK28NC->buf),0x400); // only use nandc sram0 - if(i==0) - memcpy((u_char *)(chip->oob_poi+ chip->ops.ooboffs),(u_char *)(pRK28NC->spare),4); - } - - - rk2818_nand_select_chip(mtd,-1); - RKNAND_UNLOCK(); - - - return 0; -} - -static int rk2818_nand_setrate(struct rk2818_nand_mtd *info) -{ - pNANDC pRK28NC= (pNANDC)(info->regs); - - unsigned long clkrate = clk_get_rate(info->clk); - - u_char accesstime,rwpw,csrw,rwcs; - - unsigned int ns=0,timingcfg; - - unsigned long flags; - - //scan nand flash access time - if ( info->accesstime ==0x00 ) - accesstime=50; - else if ( info->accesstime==0x80) - accesstime=25; - else if ( info->accesstime==0x08) - accesstime=20; - else - accesstime=60; //60ns - - info->clk_rate = clkrate; - clkrate /= 1000000; /* turn clock into MHz for ease of use */ - - if(clkrate>0 && clkrate<200) - ns= 1000/clkrate; // ns - else - return -1; - - timingcfg = (accesstime + ns -1)/ns; - - timingcfg = (timingcfg>=3) ? (timingcfg-2) : timingcfg; //csrw+1, rwcs+1 - - rwpw = timingcfg-timingcfg/4; - csrw = timingcfg/4; - rwcs = (timingcfg/4 >=1)?(timingcfg/4):1; - - RKNAND_LOCK(); - - pRK28NC ->FMWAIT |= (rwcs<clk); - - if (val == CPUFREQ_POSTCHANGE && newclk != info->clk_rate) - { - rk2818_nand_setrate(info); - } - - return 0; -} - -static inline int rk2818_nand_cpufreq_register(struct rk2818_nand_mtd *info) -{ - info->freq_transition.notifier_call = rk2818_nand_cpufreq_transition; - - return cpufreq_register_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER); -} - -static inline void rk2818_nand_cpufreq_deregister(struct rk2818_nand_mtd *info) -{ - cpufreq_unregister_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER); -} - -#else -static inline int rk2818_nand_cpufreq_register(struct rk2818_nand_mtd *info) -{ - return 0; -} - -static inline void rk2818_nand_cpufreq_deregister(struct rk2818_nand_mtd *info) -{ -} -#endif - - -static int rk2818_nand_probe(struct platform_device *pdev) -{ - struct nand_chip *this; - struct mtd_info *mtd; - struct rk2818_nand_platform_data *pdata = pdev->dev.platform_data; - struct rk2818_nand_mtd *master; - struct resource *res; - int err = 0; - pNANDC pRK28NC; - u_char maf_id,dev_id,ext_id3,ext_id4; - struct nand_chip *chip; - -#ifdef CONFIG_MTD_PARTITIONS - struct mtd_partition *partitions = NULL; - int num_partitions = 0; -#endif - - /* Allocate memory for MTD device structure and private data */ - master = kzalloc(sizeof(struct rk2818_nand_mtd), GFP_KERNEL); - if (!master) - return -ENOMEM; - - master->dev = &pdev->dev; - /* structures must be linked */ - this = &master->nand; - mtd = &master->mtd; - mtd->priv = this; - mtd->owner = THIS_MODULE; - mtd->name = dev_name(&pdev->dev); - - /* 50 us command delay time */ - this->chip_delay = 5; - - this->priv = master; - this->dev_ready = rk2818_nand_dev_ready; - this->cmdfunc = rk2818_nand_cmdfunc; - this->select_chip = rk2818_nand_select_chip; - this->read_byte = rk2818_nand_read_byte; - this->read_word = rk2818_nand_read_word; - this->write_buf = rk2818_nand_write_buf; - this->read_buf = rk2818_nand_read_buf; - this->options |= NAND_USE_FLASH_BBT; // open bbt options - - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - err = -ENODEV; - goto outres; - } - - master->regs = ioremap(res->start, res->end - res->start + 1); - if (!master->regs) { - err = -EIO; - goto outres; - } - - if (pdata->hw_ecc) { - this->ecc.calculate = rk2818_nand_calculate_ecc; - this->ecc.hwctl = rk2818_nand_hwctl_ecc; - this->ecc.correct = rk2818_nand_correct_data; - this->ecc.mode = NAND_ECC_HW; - this->ecc.read_page = rk2818_nand_read_page; - this->ecc.write_page = rk2818_nand_write_page; - this->ecc.read_oob = rk2818_nand_read_oob; - this->ecc.read_page_raw = rk2818_nand_read_page_raw; - this->ecc.size = 1024; - this->ecc.bytes = 28; - this->ecc.layout = &nand_hw_eccoob_16; - } else { - this->ecc.size = 256; - this->ecc.bytes = 3; - this->ecc.layout = &nand_sw_eccoob_8; - this->ecc.mode = NAND_ECC_SOFT; - } - - - - master->clk = clk_get(NULL, "nandc"); - - clk_enable(master->clk); - - pRK28NC = (pNANDC)(master->regs); - pRK28NC ->FMCTL = FMC_WP|FMC_FRDY; - pRK28NC ->FMWAIT |= (1<BCHCTL = 0x1; - - this->select_chip(mtd, 0); - this->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); - maf_id = this->read_byte(mtd); - dev_id = this->read_byte(mtd); - ext_id3 = this->read_byte(mtd); - ext_id4 = this->read_byte(mtd); - - master->accesstime = ext_id4&0x88; - - rk2818_nand_setrate(master); - - /* Reset NAND */ - this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); - /* NAND bus width determines access funtions used by upper layer */ - if (pdata->width == 2) { - this->options |= NAND_BUSWIDTH_16; - this->ecc.layout = &nand_hw_eccoob_16; - } - // iomux flash cs1~cs7 - if (pdata && pdata->io_init) { - pdata->io_init(); - } - - /* Scan to find existence of the device */ - if (nand_scan(mtd, 8)) { // rk2818 nandc support max 8 cs - - DEBUG(MTD_DEBUG_LEVEL0, - "RK2818 NAND: Unable to find any NAND device.\n"); - err = -ENXIO; - goto outscan; - } - - //¸ù¾ÝƬѡÇé¿ö»Ö¸´IO MUXԭʼֵ -#if 0 - chip = mtd->priv; - switch(chip->numchips) - { - case 1: - rk2818_mux_api_mode_resume(GPIOA5_FLASHCS1_SEL_NAME); - case 2: - rk2818_mux_api_mode_resume(GPIOA6_FLASHCS2_SEL_NAME); - case 3: - rk2818_mux_api_mode_resume(GPIOA7_FLASHCS3_SEL_NAME); - case 4: - rk2818_mux_api_mode_resume(GPIOE_SPI1_FLASH_SEL1_NAME); - case 5: - case 6: - rk2818_mux_api_mode_resume(GPIOE_SPI1_FLASH_SEL_NAME); - case 7: - case 8: - break; - default: - DEBUG(MTD_DEBUG_LEVEL0, "RK2818 NAND: numchips error!!!\n"); - } -#endif -#if 0 - // rk281x dma mode bch must (1k data + 32 oob) bytes align , so cheat system writesize =1024,oobsize=32 - mtd->writesize = 1024; - mtd->oobsize = 32; -#endif - -#ifdef CONFIG_MTD_PARTITIONS - num_partitions = parse_mtd_partitions(mtd, part_probes, &partitions, 0); - if (num_partitions > 0) { - printk(KERN_INFO "Using commandline partition definition\n"); - add_mtd_partitions(mtd, partitions, num_partitions); - if(partitions) - kfree(partitions); - } else if (pdata->nr_parts) { - printk(KERN_INFO "Using board partition definition\n"); - add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts); - } else -#endif - { - printk(KERN_INFO "no partition info available, registering whole flash at once\n"); - add_mtd_device(mtd); - } - - platform_set_drvdata(pdev, master); - - err =rk2818_nand_cpufreq_register(master); - if (err < 0) { - printk(KERN_ERR"rk2818 nand failed to init cpufreq support\n"); - goto outscan; - } - - return 0; - -outres: -outscan: - iounmap(master->regs); - kfree(master); - - return err; - -} - -static int rk2818_nand_remove(struct platform_device *pdev) -{ - struct rk2818_nand_mtd *master = platform_get_drvdata(pdev); - - platform_set_drvdata(pdev, NULL); - - if(master == NULL) - return 0; - - rk2818_nand_cpufreq_deregister(master); - - - nand_release(&master->mtd); - - if(master->regs!=NULL){ - iounmap(master->regs); - master->regs = NULL; - } - - if (master->clk != NULL && !IS_ERR(master->clk)) { - clk_disable(master->clk); - clk_put(master->clk); - } - - kfree(master); - - return 0; -} - -#ifdef CONFIG_PM -static int rk2818_nand_suspend(struct platform_device *pdev, pm_message_t state) -{ - struct mtd_info *info = platform_get_drvdata(pdev); - int ret = 0; - - DEBUG(MTD_DEBUG_LEVEL0, "RK2818_NAND : NAND suspend\n"); - if (info) - ret = info->suspend(info); - return ret; -} - -static int rk2818_nand_resume(struct platform_device *pdev) -{ - struct mtd_info *info = platform_get_drvdata(pdev); - int ret = 0; - - DEBUG(MTD_DEBUG_LEVEL0, "RK2818_NAND : NAND resume\n"); - /* Enable the NFC clock */ - - if (info) - info->resume(info); - - return ret; -} -#else -#define rk2818_nand_suspend NULL -#define rk2818_nand_resume NULL -#endif /* CONFIG_PM */ - - -static struct platform_driver rk2818_nand_driver = { - .driver = { - .name = "rk2818-nand", - }, - .probe = rk2818_nand_probe, - .remove = rk2818_nand_remove, - .suspend = rk2818_nand_suspend, - .resume = rk2818_nand_resume, -}; - -static int __init rk2818_nand_init(void) -{ - /* Register the device driver structure. */ - printk("rk2818_nand_init\n"); - return platform_driver_register(&rk2818_nand_driver);; -} - -static void __exit rk2818_nand_exit(void) -{ - /* Unregister the device structure */ - platform_driver_unregister(&rk2818_nand_driver); -} - -#ifdef CONFIG_DM9000_USE_NAND_CONTROL -// nandc dma cs mutex for dm9000 interface -void rk2818_nand_status_mutex_lock(void) -{ - pNANDC pRK28NC= (pNANDC)RK2818_NANDC_BASE; - mutex_lock(&rknand_mutex); - pRK28NC->FMCTL &=0xffffff00; // release chip select - -} - -int rk2818_nand_status_mutex_trylock(void) -{ - pNANDC pRK28NC= (pNANDC)RK2818_NANDC_BASE; - if( mutex_trylock(&rknand_mutex)) - { - pRK28NC->FMCTL &=0xffffff00; // release chip select - return 1; // ready - } - else - return 0; // busy -} - -void rk2818_nand_status_mutex_unlock(void) -{ - mutex_unlock(&rknand_mutex); - return; -} -#endif - -module_init(rk2818_nand_init); -module_exit(rk2818_nand_exit); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("hxy "); -MODULE_DESCRIPTION("MTD NAND driver for rk2818 device"); - diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c index f023d7b42ff9..3a80d0a3418e 100755 --- a/drivers/net/dm9000.c +++ b/drivers/net/dm9000.c @@ -38,7 +38,6 @@ #include #include #include -#include #include "dm9000.h" @@ -105,12 +104,6 @@ typedef struct board_info { int debug_level; enum dm9000_type type; - -#ifdef CONFIG_DM9000_USE_NAND_CONTROL - void *dev_id; - struct work_struct dm9k_work; - struct workqueue_struct *dm9000_wq; -#endif void (*inblk)(void __iomem *port, void *data, int length); void (*outblk)(void __iomem *port, void *data, int length); @@ -147,16 +140,6 @@ typedef struct board_info { } \ } while (0) -#if defined(CONFIG_DM9000_USE_NAND_CONTROL) && defined(CONFIG_MTD_NAND_RK2818) -extern void rk2818_nand_status_mutex_lock(void); -extern int rk2818_nand_status_mutex_trylock(void); -extern void rk2818_nand_status_mutex_unlock(void); -#else -static void rk2818_nand_status_mutex_lock(void){return;} -static int rk2818_nand_status_mutex_trylock(void) {return 1;} -static void rk2818_nand_status_mutex_unlock(void) {return;} -#endif - static inline board_info_t *to_dm9000_board(struct net_device *dev) { return netdev_priv(dev); @@ -323,15 +306,11 @@ dm9000_read_locked(board_info_t *db, int reg) { unsigned long flags; unsigned int ret; - - rk2818_nand_status_mutex_lock(); spin_lock_irqsave(&db->lock, flags); ret = ior(db, reg); spin_unlock_irqrestore(&db->lock, flags); - rk2818_nand_status_mutex_unlock(); - return ret; } @@ -384,8 +363,6 @@ dm9000_read_eeprom(board_info_t *db, int offset, u8 *to) mutex_lock(&db->addr_lock); - rk2818_nand_status_mutex_lock(); - spin_lock_irqsave(&db->lock, flags); iow(db, DM9000_EPAR, offset); @@ -393,15 +370,11 @@ dm9000_read_eeprom(board_info_t *db, int offset, u8 *to) spin_unlock_irqrestore(&db->lock, flags); - rk2818_nand_status_mutex_unlock(); - dm9000_wait_eeprom(db); /* delay for at-least 150uS */ msleep(1); - rk2818_nand_status_mutex_lock(); - spin_lock_irqsave(&db->lock, flags); iow(db, DM9000_EPCR, 0x0); @@ -411,8 +384,6 @@ dm9000_read_eeprom(board_info_t *db, int offset, u8 *to) spin_unlock_irqrestore(&db->lock, flags); - rk2818_nand_status_mutex_unlock(); - mutex_unlock(&db->addr_lock); } @@ -429,8 +400,6 @@ dm9000_write_eeprom(board_info_t *db, int offset, u8 *data) mutex_lock(&db->addr_lock); - rk2818_nand_status_mutex_lock(); - spin_lock_irqsave(&db->lock, flags); iow(db, DM9000_EPAR, offset); iow(db, DM9000_EPDRH, data[1]); @@ -438,20 +407,14 @@ dm9000_write_eeprom(board_info_t *db, int offset, u8 *data) iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW); spin_unlock_irqrestore(&db->lock, flags); - rk2818_nand_status_mutex_unlock(); - dm9000_wait_eeprom(db); mdelay(1); /* wait at least 150uS to clear */ - rk2818_nand_status_mutex_lock(); - spin_lock_irqsave(&db->lock, flags); iow(db, DM9000_EPCR, 0); spin_unlock_irqrestore(&db->lock, flags); - rk2818_nand_status_mutex_unlock(); - mutex_unlock(&db->addr_lock); } @@ -514,13 +477,7 @@ static int dm9000_set_rx_csum_unlocked(struct net_device *dev, uint32_t data) if (dm->can_csum) { dm->rx_csum = data; - - rk2818_nand_status_mutex_lock(); - - spin_lock_irqsave(&dm->lock, flags); iow(dm, DM9000_RCSR, dm->rx_csum ? RCSR_CSUM : 0); - spin_unlock_irqrestore(&dm->lock, flags); - rk2818_nand_status_mutex_unlock(); return 0; } @@ -731,8 +688,6 @@ dm9000_hash_table_unlocked(struct net_device *dev) dm9000_dbg(db, 1, "entering %s\n", __func__); - rk2818_nand_status_mutex_lock(); - for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) iow(db, oft, dev->dev_addr[i]); @@ -773,8 +728,6 @@ dm9000_hash_table(struct net_device *dev) spin_lock_irqsave(&db->lock, flags); dm9000_hash_table_unlocked(dev); spin_unlock_irqrestore(&db->lock, flags); - - rk2818_nand_status_mutex_unlock(); } /* @@ -838,9 +791,6 @@ static void dm9000_timeout(struct net_device *dev) /* Save previous register address */ reg_save = readb(db->io_addr); - - rk2818_nand_status_mutex_lock(); - spin_lock_irqsave(&db->lock, flags); netif_stop_queue(dev); @@ -853,8 +803,6 @@ static void dm9000_timeout(struct net_device *dev) /* Restore previous register address */ writeb(reg_save, db->io_addr); spin_unlock_irqrestore(&db->lock, flags); - - rk2818_nand_status_mutex_unlock(); } static void dm9000_send_packet(struct net_device *dev, @@ -892,15 +840,9 @@ dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev) dm9000_dbg(db, 3, "%s:\n", __func__); - if (db->tx_pkt_cnt > 1) { - dev_dbg(db->dev, "netdev tx busy\n"); + if (db->tx_pkt_cnt > 1) return NETDEV_TX_BUSY; - } - if (!rk2818_nand_status_mutex_trylock()) { - dev_dbg(db->dev, "fun:%s, nand busy\n", __func__); - return NETDEV_TX_BUSY; - } spin_lock_irqsave(&db->lock, flags); /* Move data to DM9000 TX RAM */ @@ -922,8 +864,6 @@ dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev) spin_unlock_irqrestore(&db->lock, flags); - rk2818_nand_status_mutex_unlock(); - /* free this SKB */ dev_kfree_skb(skb); @@ -992,17 +932,15 @@ dm9000_rx(struct net_device *dev) dev_warn(db->dev, "status check fail: %d\n", rxbyte); #if 0 iow(db, DM9000_RCR, 0x00); /* Stop Device */ - iow(db, DM9000_IMR, IMR_PAR); /* Stop INT request */ + iow(db, DM9000_ISR, IMR_PAR); /* Stop INT request */ #else dm9000_reset(db); #endif return; } - if (!(rxbyte & DM9000_PKT_RDY)) { - //printk("packet not ready to receive\n"); + if (!(rxbyte & DM9000_PKT_RDY)) return; - } /* A packet ready now & Get status/length */ GoodPacket = true; @@ -1079,81 +1017,6 @@ dm9000_rx(struct net_device *dev) } while (rxbyte & DM9000_PKT_RDY); } -#ifdef CONFIG_DM9000_USE_NAND_CONTROL -static void dm9000_interrupt_work(struct work_struct *work) -{ - board_info_t *db = container_of(work, board_info_t, dm9k_work); - struct net_device *dev = db->dev_id; - int int_status; - unsigned long flags; - u8 reg_save; - - //printk("entering %s\n", __FUNCTION__); - - /* A real interrupt coming */ - - /* holders of db->lock must always block IRQs */ - - rk2818_nand_status_mutex_lock(); - - spin_lock_irqsave(&db->lock, flags); - - /* Save previous register address */ - reg_save = readb(db->io_addr); - - /* Disable all interrupts */ - iow(db, DM9000_IMR, IMR_PAR); - - /* Got DM9000 interrupt status */ - int_status = ior(db, DM9000_ISR); /* Got ISR */ - iow(db, DM9000_ISR, int_status); /* Clear ISR status */ - - if (netif_msg_intr(db)) - dev_dbg(db->dev, "interrupt status %02x\n", int_status); - - /* Received the coming packet */ - if (int_status & ISR_PRS) - dm9000_rx(dev); - - /* Trnasmit Interrupt check */ - if (int_status & ISR_PTS) - dm9000_tx_done(dev, db); - - if (db->type != TYPE_DM9000E) { - if (int_status & ISR_LNKCHNG) { - /* fire a link-change request */ - schedule_delayed_work(&db->phy_poll, 1); - } - } - - /* Re-enable interrupt mask */ - iow(db, DM9000_IMR, db->imr_all); - - /* Restore previous register address */ - writeb(reg_save, db->io_addr); - - spin_unlock_irqrestore(&db->lock, flags); - - rk2818_nand_status_mutex_unlock(); - - enable_irq(dev->irq); - -} - -static irqreturn_t dm9000_interrupt(int irq, void *dev_id) -{ - struct net_device *dev = dev_id; - board_info_t *db = netdev_priv(dev); - - //printk("enter : %s\n", __FUNCTION__); - - db->dev_id = dev_id; - disable_irq_nosync(irq); - queue_work(db->dm9000_wq, &(db->dm9k_work)); - - return IRQ_HANDLED; -} -#else static irqreturn_t dm9000_interrupt(int irq, void *dev_id) { struct net_device *dev = dev_id; @@ -1207,7 +1070,6 @@ static irqreturn_t dm9000_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -#endif #ifdef CONFIG_NET_POLL_CONTROLLER /* @@ -1231,11 +1093,6 @@ dm9000_open(struct net_device *dev) board_info_t *db = netdev_priv(dev); unsigned long irqflags = db->irq_res->flags & IRQF_TRIGGER_MASK; - #ifdef CONFIG_DM9000_USE_NAND_CONTROL - db->dm9000_wq = create_workqueue("dm9000 wq"); - INIT_WORK(&(db->dm9k_work), dm9000_interrupt_work); - #endif - if (netif_msg_ifup(db)) dev_dbg(db->dev, "enabling %s\n", dev->name); @@ -1290,8 +1147,6 @@ dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg) mutex_lock(&db->addr_lock); - rk2818_nand_status_mutex_lock(); - spin_lock_irqsave(&db->lock,flags); /* Save previous register address */ @@ -1304,15 +1159,10 @@ dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg) writeb(reg_save, db->io_addr); spin_unlock_irqrestore(&db->lock,flags); - - rk2818_nand_status_mutex_unlock(); dm9000_msleep(db, 1); /* Wait read complete */ - rk2818_nand_status_mutex_lock(); - spin_lock_irqsave(&db->lock,flags); - reg_save = readb(db->io_addr); iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */ @@ -1323,8 +1173,6 @@ dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg) /* restore the previous address */ writeb(reg_save, db->io_addr); spin_unlock_irqrestore(&db->lock,flags); - - rk2818_nand_status_mutex_unlock(); mutex_unlock(&db->addr_lock); @@ -1346,8 +1194,6 @@ dm9000_phy_write(struct net_device *dev, dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value); mutex_lock(&db->addr_lock); - rk2818_nand_status_mutex_lock(); - spin_lock_irqsave(&db->lock,flags); /* Save previous register address */ @@ -1364,15 +1210,10 @@ dm9000_phy_write(struct net_device *dev, writeb(reg_save, db->io_addr); spin_unlock_irqrestore(&db->lock, flags); - - rk2818_nand_status_mutex_unlock(); dm9000_msleep(db, 1); /* Wait write complete */ - rk2818_nand_status_mutex_lock(); - - spin_lock_irqsave(&db->lock,flags); - + spin_lock_irqsave(&db->lock,flags); reg_save = readb(db->io_addr); iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */ @@ -1381,8 +1222,6 @@ dm9000_phy_write(struct net_device *dev, writeb(reg_save, db->io_addr); spin_unlock_irqrestore(&db->lock, flags); - - rk2818_nand_status_mutex_unlock(); mutex_unlock(&db->addr_lock); } @@ -1420,10 +1259,6 @@ dm9000_stop(struct net_device *ndev) dm9000_shutdown(ndev); - #ifdef CONFIG_DM9000_USE_NAND_CONTROL - destroy_workqueue(db->dm9000_wq); - #endif - return 0; } diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index fdf06cfe66c4..2717e933c221 100755 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -148,6 +148,7 @@ config BATTERY_BQ3060 depends on I2C && ARCH_RK29 help Say Y here to enable support for batteries with BQ3060(I2C) chip. + config CHECK_BATT_CAPACITY tristate "check the capacity in BQ27510 battery if 1000mah write capacity for BATT_CAPACITY_MAH" depends on BATTERY_BQ27510 || BATTERY_BQ3060 @@ -157,17 +158,12 @@ config BATT_CAPACITY_MAH depends on CHECK_BATT_CAPACITY int "battery capacity (in mah)" default 2200 - + config NO_BATTERY_IC tristate "no BQ27510 battery ic in board" depends on BATTERY_BQ27510 || BATTERY_BQ3060 default n help Say no BQ27510(I2C) chip in board . - -config BATTERY_RK2818 - tristate "RK2818 battery" - depends on RK28_ADC - help - Say Y to enable support for the battery on the RK2818. + endif # POWER_SUPPLY diff --git a/drivers/power/Makefile b/drivers/power/Makefile index 6f0fec325923..bd027a37cedf 100755 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -31,7 +31,6 @@ obj-$(CONFIG_BATTERY_BQ27x00) += bq27x00_battery.o obj-$(CONFIG_BATTERY_DA9030) += da9030_battery.o obj-$(CONFIG_BATTERY_MAX17040) += max17040_battery.o obj-$(CONFIG_CHARGER_PCF50633) += pcf50633-charger.o -obj-$(CONFIG_BATTERY_RK2818) += rk2818_battery.o obj-$(CONFIG_BATTERY_STC3100) += stc3100_battery.o obj-$(CONFIG_BATTERY_BQ27510) += bq27510_battery.o -obj-$(CONFIG_BATTERY_BQ3060) += bq3060_battery.o +obj-$(CONFIG_BATTERY_BQ3060) += bq3060_battery.o diff --git a/drivers/power/rk2818_battery.c b/drivers/power/rk2818_battery.c deleted file mode 100755 index 3e720519db44..000000000000 --- a/drivers/power/rk2818_battery.c +++ /dev/null @@ -1,737 +0,0 @@ -/* drivers/power/rk2818_battery.c - * - * battery detect driver for the rk2818 - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if 0 -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -/*******************ÒÔϲÎÊý¿ÉÒÔÐÞ¸Ä******************************/ -#define TIMER_MS_COUNTS 50 //¶¨Ê±Æ÷µÄ³¤¶Èms -#define SLOPE_SECOND_COUNTS 120 //ͳ¼ÆµçѹбÂʵÄʱ¼ä¼ä¸ôs -#define TIME_UPDATE_STATUS 5000 //¸üеç³Ø״̬µÄʱ¼ä¼ä¸ôms -#define BATT_MAX_VOL_VALUE 4180 //ÂúµçʱµÄµç³Øµçѹ FOR A7 -#define BATT_ZERO_VOL_VALUE 3500 //¹Ø»úʱµÄµç³Øµçѹ -#define BATT_NOMAL_VOL_VALUE 3800 -#define THRESHOLD_VOLTAGE_LEVEL0 4050 -#define THRESHOLD_VOLTAGE_LEVEL1 3950 -#define THRESHOLD_VOLTAGE_LEVEL2 3850 -#define THRESHOLD_VOLTAGE_LEVEL3 BATT_ZERO_VOL_VALUE -#define THRESHOLD_SLOPE_HIGH 10 //бÂÊÖµ = µçѹ½µµÍµÄËÙ¶È -#define THRESHOLD_SLOPE_MID 5 //< THRESHOLD_SLOPE_HIGH -#define THRESHOLD_SLOPE_LOW 0 //< THRESHOLD_SLOPE_MID - -/*************************************************************/ -#define CHN_BAT_ADC 0 -#define CHN_USB_ADC 2 -#define BATT_LEVEL_EMPTY 0 -#define BATT_PRESENT_TRUE 1 -#define BATT_PRESENT_FALSE 0 -#define BAT_1V2_VALUE 1270 - -#define BAT_LOADER_STATUS 0 //Óõç״̬ -#define BAT_CHANGE_STATUS 1 //²¨¶¯×´Ì¬ -#define BAT_CHARGE_STATUS 2 //³äµç״̬ -#define BAT_RELEASE_STATUS 3 //µç³ØºÄ¾¡×´Ì¬ - -#define SLOPE_HIGH_LEVEL 0 //µçѹ±ä»¯Ð±Âʵȼ¶ -#define SLOPE_MID_LEVEL 1 -#define SLOPE_LOW_LEVEL 2 - -#define VOLTAGE_HIGH_LEVEL 0 //µçѹ¸ßµÍµÈ¼¶ -#define VOLTAGE_MID_LEVEL 1 -#define VOLTAGE_LOW_LEVEL 2 -#define VOLTAGE_RELEASE_LEVEL 3 - -#define NUM_VOLTAGE_SAMPLE ((1000*SLOPE_SECOND_COUNTS) / TIMER_MS_COUNTS) //´æ´¢µÄ²ÉÑùµã¸öÊý - -static int gBatFullFlag = 0; - -static int gBatLastStatus = 0; -static int gBatStatus = POWER_SUPPLY_STATUS_UNKNOWN; -static int gBatHealth = POWER_SUPPLY_HEALTH_GOOD; -static int gBatLastPresent = 0; -static int gBatPresent = BATT_PRESENT_TRUE; -static int gBatLastVoltage = 0; -static int gBatVoltage = BATT_NOMAL_VOL_VALUE; -static int gBatLastCapacity = 0; -static int gBatCapacity = ((BATT_NOMAL_VOL_VALUE-BATT_ZERO_VOL_VALUE)*100/(BATT_MAX_VOL_VALUE-BATT_ZERO_VOL_VALUE)); - -static int gBatVoltageSamples[NUM_VOLTAGE_SAMPLE+2]; //add 2 to handle one bug -static int gBatSlopeValue = 0; -static int gBatVoltageValue[2]={0,0}; -static int *pSamples = &gBatVoltageSamples[0]; //²ÉÑùµãÖ¸Õë -static int gFlagLoop = 0; //²ÉÑù×ã¹»±êÖ¾ -static int gNumSamples = 0; -static int gNumCharge = 0; -static int gMaxCharge = 0; -static int gNumLoader = 0; -static int gMaxLoader = 0; - -static int gBatSlopeLevel = SLOPE_LOW_LEVEL; -static int gBatVoltageLevel = VOLTAGE_MID_LEVEL; -static int gBatUseStatus = BAT_LOADER_STATUS; - -static struct regulator *pChargeregulator; -static int gVbuscharge = 0; - -extern int dwc_vbus_status(void); -extern int get_msc_connect_flag(void); - -struct rk2818_battery_data { - int irq; - spinlock_t lock; - struct work_struct timer_work; - struct timer_list timer; - struct power_supply battery; - struct power_supply usb; - struct power_supply ac; - - int charge_ok_pin; - int charge_ok_level; - - int adc_bat_divider; - int bat_max; - int bat_min; -}; - - -/* temporary variable used between rk2818_battery_probe() and rk2818_battery_open() */ -static struct rk2818_battery_data *gBatteryData; - -enum { - BATTERY_STATUS = 0, - BATTERY_HEALTH = 1, - BATTERY_PRESENT = 2, - BATTERY_CAPACITY = 3, - BATTERY_AC_ONLINE = 4, - BATTERY_STATUS_CHANGED = 5, - AC_STATUS_CHANGED = 6, - BATTERY_INT_STATUS = 7, - BATTERY_INT_ENABLE = 8, -}; - -typedef enum { - CHARGER_BATTERY = 0, - CHARGER_USB, - CHARGER_AC -} charger_type_t; - -static int rk2818_get_charge_status(void) -{ - struct regulator * rdev = pChargeregulator; - //DBG("gAdcValue[CHN_USB_ADC]=%d\n",gAdcValue[CHN_USB_ADC]); - /*if(gAdcValue[CHN_USB_ADC] > 250) - { //about 0.5V - return 1; - } - else */ - if((1 == dwc_vbus_status())&& (0 == get_msc_connect_flag())) - { - DBG("CHARGE!\n"); - if(gVbuscharge !=1) { - if(!IS_ERR(rdev)) - regulator_set_current_limit(rdev,0,1200000); - } - gVbuscharge = 1; - return 1; - } - else - { - DBG("NOT CHARGING!\n"); - if(gVbuscharge !=0 ) { - if(!IS_ERR(rdev)) - regulator_set_current_limit(rdev,0,475000); - } - gVbuscharge = 0; - return 0; - } - -} - -static void rk2818_get_bat_status(struct rk2818_battery_data *bat) -{ - if(rk2818_get_charge_status() == 1) - { - //local_irq_disable(); - if (gBatFullFlag == 0) { - gBatStatus = POWER_SUPPLY_STATUS_CHARGING; - } else { - gBatStatus = POWER_SUPPLY_STATUS_FULL; - } - //local_irq_enable(); - DBG("Battery is Charging!\n"); - } - else { - gBatFullFlag = 0; - gBatStatus = POWER_SUPPLY_STATUS_NOT_CHARGING; - DBG("Battery is Not Charging!\n"); - } -} - -static void rk2818_get_bat_health(struct rk2818_battery_data *bat) -{ - gBatHealth = POWER_SUPPLY_HEALTH_GOOD; -} - -static void rk2818_get_bat_present(struct rk2818_battery_data *bat) -{ - if(gBatVoltage < bat->bat_min) - gBatPresent = 0; - else - gBatPresent = 1; -} - -static void rk2818_get_bat_voltage(struct rk2818_battery_data *bat) -{ - unsigned long value; - int i,*pSamp,*pStart = &gBatVoltageSamples[0],num = 0; - int temp[2] = {0,0}; - value = gAdcValue[CHN_BAT_ADC]; - if(0 != gAdcValue[3]) -#if defined(CONFIG_MACH_RAHO)||defined(CONFIG_MACH_RAHOSDK) - gBatVoltage = (value * BAT_1V2_VALUE * 3)/(gAdcValue[3]*2); -#else - gBatVoltage = (value * BAT_1V2_VALUE * 2)/gAdcValue[3]; // channel 3 is about 1.42v,need modified -#endif - - /*Ïû³ýë´Ìµçѹ*/ - if(gBatVoltage >= BATT_MAX_VOL_VALUE + 10) - gBatVoltage = BATT_MAX_VOL_VALUE + 10; - else if(gBatVoltage <= BATT_ZERO_VOL_VALUE - 10) - gBatVoltage = BATT_ZERO_VOL_VALUE - 10; - - *pSamples = gBatVoltage; - num = ++pSamples - pStart; - if(num > NUM_VOLTAGE_SAMPLE) - { - pSamples = pStart; - gFlagLoop = 1; - } - - if(gFlagLoop != 1) //δ²É¼¯µ½ NUM_VOLTAGE_SAMPLE¸öµçѹֵ - { - for(i=(num>>1); i>1); - gBatCapacity = ((gBatVoltage - bat->bat_min) * 100) / (bat->bat_max - bat->bat_min); - if(gBatCapacity >= 100) - gBatCapacity = 100; - else if(gBatCapacity < 0) - gBatCapacity = 0; - } - //DBG("gBatVoltage=%d,gBatCapacity=%d,num=%d\n",gBatVoltage,gBatCapacity,num); - } - else - { - //compute the average voltage after samples-count is larger than NUM_VOLTAGE_SAMPLE - pSamp = pSamples; - for(i=0; i<(NUM_VOLTAGE_SAMPLE >> 1); i++) - { - temp[0] += *pSamp; - if((++pSamp - pStart) > NUM_VOLTAGE_SAMPLE) - pSamp = pStart; - } - - gBatVoltageValue[0] = temp[0] / (NUM_VOLTAGE_SAMPLE >> 1); - for(i=0; i<(NUM_VOLTAGE_SAMPLE >> 1); i++) - { - temp[1] += *pSamp; - if((++pSamp - pStart) > NUM_VOLTAGE_SAMPLE) - pSamp = pStart; - } - - gBatVoltageValue[1] = temp[1] / (NUM_VOLTAGE_SAMPLE >> 1); - - gBatVoltage = gBatVoltageValue[1]; - - gBatSlopeValue = gBatVoltageValue[0] - gBatVoltageValue[1]; - //DBG("gBatSlopeValue=%d,gBatVoltageValue[1]=%d\n",gBatSlopeValue,gBatVoltageValue[1]); - - if(gBatVoltageValue[1] < BATT_ZERO_VOL_VALUE) - { - gBatUseStatus = BAT_RELEASE_STATUS; //µç³ØºÄ¾¡×´Ì¬ - } - else - { - if(gBatSlopeValue < 0) - { - gNumLoader = 0; - - //Á¬Ðø¶à´Îµçѹ½µµÍÂÊΪ¸º±íʾ³äµç״̬ - if(gBatVoltageValue[1] >= THRESHOLD_VOLTAGE_LEVEL0) - gMaxCharge = 2; - else if(gBatVoltageValue[1] >= THRESHOLD_VOLTAGE_LEVEL1) - gMaxCharge = 3; - else if(gBatVoltageValue[1] >= THRESHOLD_VOLTAGE_LEVEL2) - gMaxCharge = 4; - else if(gBatVoltageValue[1] >= THRESHOLD_VOLTAGE_LEVEL3) - gMaxCharge = 2; - if((++gNumCharge >= gMaxCharge) && (gBatStatus != POWER_SUPPLY_STATUS_NOT_CHARGING)) - { - gBatUseStatus = BAT_CHARGE_STATUS; //³äµç״̬ - gNumCharge = gMaxCharge ; - } - else - { - gBatUseStatus = BAT_CHANGE_STATUS; //²¨¶¯×´Ì¬ - } - - } - else - { - gNumCharge = 0; - //Á¬Ðø¶à´Îµçѹ½µµÍÂÊΪÕý±íʾÓõç״̬ - if(gBatVoltageValue[1] >= THRESHOLD_VOLTAGE_LEVEL0) - gMaxCharge = 2; - else if(gBatVoltageValue[1] >= THRESHOLD_VOLTAGE_LEVEL1) - gMaxCharge = 3; - else if(gBatVoltageValue[1] >= THRESHOLD_VOLTAGE_LEVEL2) - gMaxCharge = 4; - else if(gBatVoltageValue[1] >= THRESHOLD_VOLTAGE_LEVEL3) - gMaxLoader = 2; - - if((++gNumLoader >= gMaxLoader) && (gBatStatus == POWER_SUPPLY_STATUS_NOT_CHARGING)) - { - gBatUseStatus = BAT_LOADER_STATUS; - gNumLoader = gMaxLoader; - } - else - { - gBatUseStatus = BAT_CHANGE_STATUS; //²¨¶¯×´Ì¬ - } - - } - } - } - - -} - -static void rk2818_get_bat_capacity(struct rk2818_battery_data *bat) -{ - if(gFlagLoop) - { - if(gBatUseStatus == BAT_LOADER_STATUS) - { - //Óõç״̬ϳöÏÖ¸ºÔرäСÈÝÁ¿±ä´óʱ£¬²»¸üÐÂÈÝÁ¿Öµ - if((gBatLastVoltage == 0) || (gBatVoltage <= gBatLastVoltage)) - { - gBatCapacity = ((gBatVoltage - bat->bat_min) * 100) / (bat->bat_max - bat->bat_min); - if(gBatCapacity >= 100) - gBatCapacity = 100; - else if(gBatCapacity < 0) - gBatCapacity = 0; - gBatLastVoltage = gBatVoltage; - } - - } - else if(gBatUseStatus == BAT_CHARGE_STATUS) - { - //³äµç״̬ÏÂÈÝÁ¿½µµÍʱ£¬²»¸üÐÂÈÝÁ¿Öµ - if((gBatLastVoltage == 0) || (gBatVoltage >= gBatLastVoltage)) - { - gBatCapacity = ((gBatVoltage - bat->bat_min) * 100) / (bat->bat_max - bat->bat_min); - if(gBatCapacity >= 100) - gBatCapacity = 100; - else if(gBatCapacity < 0) - gBatCapacity = 0; - gBatLastVoltage = gBatVoltage; - //DBG("BAT_CHARGE_STATUS\n"); - } - - } - - //±ä»¯×´Ì¬²»¸üÐÂÈÝÁ¿ - //DBG("BAT_CHANGE_STATUS\n"); - } - else - { - gBatCapacity = ((gBatVoltage - bat->bat_min) * 100) / (bat->bat_max - bat->bat_min); - if(gBatCapacity >= 100) - gBatCapacity = 100; - else if(gBatCapacity < 0) - gBatCapacity = 0; - } -} - - -static void rk2818_battery_timer_work(struct work_struct *work) -{ - rk2818_get_bat_status(gBatteryData); - rk2818_get_bat_health(gBatteryData); - rk2818_get_bat_present(gBatteryData); - rk2818_get_bat_voltage(gBatteryData); - rk2818_get_bat_capacity(gBatteryData); - - /*update battery parameter after adc and capacity has been changed*/ - if((gBatStatus != gBatLastStatus) || (gBatPresent != gBatLastPresent) || (gBatCapacity != gBatLastCapacity)) - { - //gNumSamples = 0; - gBatLastStatus = gBatStatus; - gBatLastPresent = gBatPresent; - gBatLastCapacity = gBatCapacity; - power_supply_changed(&gBatteryData->battery); - - } - -} - - -static void rk2818_batscan_timer(unsigned long data) -{ - gBatteryData->timer.expires = jiffies + msecs_to_jiffies(TIMER_MS_COUNTS); - add_timer(&gBatteryData->timer); - schedule_work(&gBatteryData->timer_work); -} - - -static int rk2818_usb_get_property(struct power_supply *psy, - enum power_supply_property psp, - union power_supply_propval *val) -{ - charger_type_t charger; - charger = CHARGER_USB; - - switch (psp) { - case POWER_SUPPLY_PROP_ONLINE: - if (psy->type == POWER_SUPPLY_TYPE_USB) - val->intval = dwc_vbus_status(); - DBG("%s:%d\n",__FUNCTION__,val->intval); - break; - - default: - return -EINVAL; - } - - return 0; - -} - - -static int rk2818_ac_get_property(struct power_supply *psy, - enum power_supply_property psp, - union power_supply_propval *val) -{ -// struct rk2818_battery_data *data = container_of(psy, -// struct rk2818_battery_data, ac); - int ret = 0; - charger_type_t charger; - charger = CHARGER_USB; - switch (psp) { - case POWER_SUPPLY_PROP_ONLINE: - if (psy->type == POWER_SUPPLY_TYPE_MAINS) - { - if(gAdcValue[CHN_USB_ADC] > 250) - val->intval = 1; - else - val->intval = 0; - } - DBG("%s:%d\n",__FUNCTION__,val->intval); - break; - - default: - ret = -EINVAL; - break; - } - return ret; -} - -static int rk2818_battery_get_property(struct power_supply *psy, - enum power_supply_property psp, - union power_supply_propval *val) -{ - struct rk2818_battery_data *data = container_of(psy, - struct rk2818_battery_data, battery); - int ret = 0; - - switch (psp) { - case POWER_SUPPLY_PROP_STATUS: - val->intval = gBatStatus; - DBG("gBatStatus=%d\n",val->intval); - break; - case POWER_SUPPLY_PROP_HEALTH: - val->intval = gBatHealth; - DBG("gBatHealth=%d\n",val->intval); - break; - case POWER_SUPPLY_PROP_PRESENT: - val->intval = gBatPresent; - DBG("gBatPresent=%d\n",val->intval); - break; - case POWER_SUPPLY_PROP_VOLTAGE_NOW: - if(gBatVoltageValue[1] == 0) - val ->intval = gBatVoltage; - else - val ->intval = gBatVoltageValue[1]; - DBG("gBatVoltage=%d\n",val->intval); - break; - case POWER_SUPPLY_PROP_TECHNOLOGY: - val->intval = POWER_SUPPLY_TECHNOLOGY_LION; - break; - case POWER_SUPPLY_PROP_CAPACITY: - val->intval = gBatCapacity; - DBG("gBatCapacity=%d%%\n",val->intval); - break; - case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN: - val->intval = data->bat_max; - break; - case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN: - val->intval = data->bat_min; - break; - default: - ret = -EINVAL; - break; - } - - return ret; -} - -static enum power_supply_property rk2818_battery_props[] = { - POWER_SUPPLY_PROP_STATUS, - POWER_SUPPLY_PROP_HEALTH, - POWER_SUPPLY_PROP_PRESENT, - POWER_SUPPLY_PROP_VOLTAGE_NOW, - POWER_SUPPLY_PROP_TECHNOLOGY, - POWER_SUPPLY_PROP_CAPACITY, - POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, - POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN, -}; - -static enum power_supply_property rk2818_usb_props[] = { - POWER_SUPPLY_PROP_ONLINE, -}; - - -static enum power_supply_property rk2818_ac_props[] = { - POWER_SUPPLY_PROP_ONLINE, -}; - - -#ifdef CONFIG_PM -static int rk2818_battery_suspend(struct platform_device *dev, pm_message_t state) -{ - /* flush all pending status updates */ - flush_scheduled_work(); - return 0; -} - -static int rk2818_battery_resume(struct platform_device *dev) -{ - /* things may have changed while we were away */ - schedule_work(&gBatteryData->timer_work); - return 0; -} -#else -#define rk2818_battery_suspend NULL -#define rk2818_battery_resume NULL -#endif - -static irqreturn_t rk2818_battery_interrupt(int irq, void *dev_id) -{ - if((1 == dwc_vbus_status())&& (0 == get_msc_connect_flag())) {//detech when charging - gBatFullFlag = 1; - } - - DBG(KERN_INFO "-----battery is full-----\n"); - - return 0; -} - -static int rk2818_battery_probe(struct platform_device *pdev) -{ - int ret; - struct rk2818_battery_data *data; - struct rk2818_battery_platform_data *pdata = pdev->dev.platform_data; - int irq_flag; - - if (pdata && pdata->io_init) { - ret = pdata->io_init(); - if (ret) - goto err_free_gpio1; - } - - ret = gpio_request(pdata->charge_ok_pin, NULL); - if (ret) { - printk("failed to request charge_ok gpio\n"); - goto err_free_gpio1; - } - - gpio_pull_updown(pdata->charge_ok_pin, GPIOPullUp);//important - ret = gpio_direction_input(pdata->charge_ok_pin); - if (ret) { - printk("failed to set gpio charge_ok input\n"); - goto err_free_gpio1; - } - - data = kzalloc(sizeof(*data), GFP_KERNEL); - if (data == NULL) { - ret = -ENOMEM; - goto err_data_alloc_failed; - } - spin_lock_init(&data->lock); - - memset(gBatVoltageSamples, 0, sizeof(gBatVoltageSamples)); - - data->battery.properties = rk2818_battery_props; - data->battery.num_properties = ARRAY_SIZE(rk2818_battery_props); - data->battery.get_property = rk2818_battery_get_property; - data->battery.name = "battery"; - data->battery.type = POWER_SUPPLY_TYPE_BATTERY; - data->adc_bat_divider = 414; - data->bat_max = BATT_MAX_VOL_VALUE; - data->bat_min = BATT_ZERO_VOL_VALUE; - DBG("bat_min = %d\n",data->bat_min); - - data->usb.properties = rk2818_usb_props; - data->usb.num_properties = ARRAY_SIZE(rk2818_ac_props); - data->usb.get_property = rk2818_usb_get_property; - data->usb.name = "usb"; - data->usb.type = POWER_SUPPLY_TYPE_USB; - - data->ac.properties = rk2818_ac_props; - data->ac.num_properties = ARRAY_SIZE(rk2818_ac_props); - data->ac.get_property = rk2818_ac_get_property; - data->ac.name = "ac"; - data->ac.type = POWER_SUPPLY_TYPE_MAINS; - - data->charge_ok_pin = pdata->charge_ok_pin; - data->charge_ok_level = pdata->charge_ok_level; - - irq_flag = (!pdata->charge_ok_level) ? IRQF_TRIGGER_RISING : IRQF_TRIGGER_FALLING; - ret = request_irq(gpio_to_irq(pdata->charge_ok_pin), rk2818_battery_interrupt, irq_flag, "rk2818_battery", data); - if (ret) { - printk("failed to request irq\n"); - goto err_irq_failed; - } - - ret = power_supply_register(&pdev->dev, &data->ac); - if (ret) - { - printk(KERN_INFO "fail to power_supply_register\n"); - goto err_ac_failed; - } - - ret = power_supply_register(&pdev->dev, &data->usb); - if (ret) - { - printk(KERN_INFO "fail to power_supply_register\n"); - goto err_usb_failed; - } - - ret = power_supply_register(&pdev->dev, &data->battery); - if (ret) - { - printk(KERN_INFO "fail to power_supply_register\n"); - goto err_battery_failed; - } - platform_set_drvdata(pdev, data); - - - pChargeregulator = regulator_get(&pdev->dev, "battery"); - if(IS_ERR(pChargeregulator)) - printk(KERN_ERR"fail to get regulator battery\n"); - else - regulator_set_current_limit(pChargeregulator,0,475000); - - INIT_WORK(&data->timer_work, rk2818_battery_timer_work); - gBatteryData = data; - - setup_timer(&data->timer, rk2818_batscan_timer, (unsigned long)data); - data->timer.expires = jiffies+100; - add_timer(&data->timer); - printk(KERN_INFO "rk2818_battery: driver initialized\n"); - - return 0; - -err_battery_failed: - power_supply_unregister(&data->usb); -err_usb_failed: - power_supply_unregister(&data->ac); -err_ac_failed: - free_irq(gpio_to_irq(pdata->charge_ok_pin), data); -err_irq_failed: - kfree(data); -err_data_alloc_failed: - -err_free_gpio1: - gpio_free(pdata->charge_ok_pin); - return ret; -} - -static int rk2818_battery_remove(struct platform_device *pdev) -{ - struct rk2818_battery_data *data = platform_get_drvdata(pdev); - struct rk2818_battery_platform_data *pdata = pdev->dev.platform_data; - - power_supply_unregister(&data->battery); - power_supply_unregister(&data->usb); - power_supply_unregister(&data->ac); - free_irq(data->irq, data); - gpio_free(pdata->charge_ok_pin); - kfree(data); - gBatteryData = NULL; - return 0; -} - -static struct platform_driver rk2818_battery_device = { - .probe = rk2818_battery_probe, - .remove = rk2818_battery_remove, - .suspend = rk2818_battery_suspend, - .resume = rk2818_battery_resume, - .driver = { - .name = "rk2818-battery", - .owner = THIS_MODULE, - } -}; - -static int __init rk2818_battery_init(void) -{ - return platform_driver_register(&rk2818_battery_device); -} - -static void __exit rk2818_battery_exit(void) -{ - platform_driver_unregister(&rk2818_battery_device); -} - -module_init(rk2818_battery_init); -module_exit(rk2818_battery_exit); - -MODULE_DESCRIPTION("Battery detect driver for the rk2818"); -MODULE_AUTHOR("luowei lw@rock-chips.com"); -MODULE_LICENSE("GPL"); - diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 8d42b4e1cd56..4a85306bfb28 100755 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -1477,32 +1477,6 @@ config SERIAL_BCM63XX_CONSOLE If you have enabled the serial port on the bcm63xx CPU you can make it the console by answering Y to this option. -config SERIAL_RK2818 - bool "RockChip rk2818 serial port support" - depends on ARM && ARCH_RK2818 - select SERIAL_CORE - -config UART0_RK2818 - bool "RockChip rk2818 serial port 0 support" - depends on SERIAL_RK2818 - -config UART1_RK2818 - bool "RockChip rk2818 serial port 1 support" - depends on SERIAL_RK2818 - -config UART2_RK2818 - bool "RockChip rk2818 serial port 2 support" - depends on SERIAL_RK2818 - -config UART3_RK2818 - bool "RockChip rk2818 serial port 3 support" - depends on SERIAL_RK2818 - -config SERIAL_RK2818_CONSOLE - bool "Rockchip rk2818 serial console support" - depends on SERIAL_RK2818=y - select SERIAL_CORE_CONSOLE - config SERIAL_RK29 bool "RockChip rk29 serial port support" depends on ARM && ARCH_RK29 diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index d417dd356dfa..04c88bd3e6ad 100755 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -80,7 +80,6 @@ obj-$(CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL) += nwpserial.o obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o obj-$(CONFIG_SERIAL_QE) += ucc_uart.o -obj-$(CONFIG_SERIAL_RK2818) += rk2818_serial.o ifeq ($(CONFIG_SERIAL_RK29_STANDARD),y) obj-$(CONFIG_SERIAL_RK29) += rk_serial.o else diff --git a/drivers/serial/rk2818_serial.c b/drivers/serial/rk2818_serial.c deleted file mode 100755 index b3c4c116215e..000000000000 --- a/drivers/serial/rk2818_serial.c +++ /dev/null @@ -1,708 +0,0 @@ -/* - * drivers/serial/rk2818_serial.c - driver for rk2818 serial device and console - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#if defined(CONFIG_SERIAL_RK2818_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) -#define SUPPORT_SYSRQ -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rk2818_serial.h" - -/* - * We wrap our port structure around the generic uart_port. - */ -struct rk2818_port { - struct uart_port uart; - char name[16]; - struct clk *clk; - unsigned int imr; -}; - -#define UART_TO_RK2818(uart_port) ((struct rk2818_port *) uart_port) -#define RK2818_SERIAL_MAJOR TTY_MAJOR -#define RK2818_SERIAL_MINOR 64 - - -static inline void rk2818_uart_write(struct uart_port *port, unsigned int val, - unsigned int off) -{ - __raw_writel(val, port->membase + off); -} - -static inline unsigned int rk2818_uart_read(struct uart_port *port, unsigned int off) -{ - return __raw_readl(port->membase + off); -} - -static int rk2818_set_baud_rate(struct uart_port *port, unsigned int baud) -{ - unsigned int uartTemp; - - rk2818_uart_write(port,rk2818_uart_read(port,UART_LCR) | LCR_DLA_EN,UART_LCR); - uartTemp = port->uartclk / (16 * baud); - rk2818_uart_write(port,uartTemp & 0xff,UART_DLL); - rk2818_uart_write(port,(uartTemp>>8) & 0xff,UART_DLH); - rk2818_uart_write(port,rk2818_uart_read(port,UART_LCR) & (~LCR_DLA_EN),UART_LCR); - return baud; -} - -/* - * ÅжϷ¢ËÍ»º³åÇøÊÇ·ñΪ¿Õ - *ÏÈÒÔFIFO´ò¿ª×ö£¬ºóÃæ¿ÉÒÔ×ö³ÉFIFO¹Ø»òFIFO¿ª¡£ - */ -static u_int rk2818_serial_tx_empty(struct uart_port *port) -{ - while(!(rk2818_uart_read(port,UART_USR)&UART_TRANSMIT_FIFO_EMPTY)) - cpu_relax(); - if(rk2818_uart_read(port,UART_USR)&UART_TRANSMIT_FIFO_EMPTY) - { - return (1);///1£º¿Õ - }else{ - return (0);///0:·Ç¿Õ - } -} - -/* - * Power / Clock management. - */ -static void rk2818_serial_pm(struct uart_port *port, unsigned int state, - unsigned int oldstate) -{ - struct rk2818_port *rk2818_port = UART_TO_RK2818(port); - - switch (state) { - case 0: - /* - * Enable the peripheral clock for this serial port. - * This is called on uart_open() or a resume event. - */ - clk_enable(rk2818_port->clk); - break; - case 3: - /* - * Disable the peripheral clock for this serial port. - * This is called on uart_close() or a suspend event. - */ - clk_disable(rk2818_port->clk); - break; - default: - printk(KERN_ERR "rk2818_serial: unknown pm %d\n", state); - } -} - -/* - * Return string describing the specified port - */ -static const char *rk2818_serial_type(struct uart_port *port) -{ - return (port->type == PORT_RK2818) ? "RK2818_SERIAL" : NULL; -} - -static void rk2818_serial_enable_ms(struct uart_port *port) -{ - #ifdef DEBUG_LHH - printk("Enter::%s\n",__FUNCTION__); - #endif -} - -/* no modem control lines */ -static unsigned int rk2818_serial_get_mctrl(struct uart_port *port) -{ - unsigned int result = 0; - unsigned int status; - - status = rk2818_uart_read(port,UART_MSR); - if (status & UART_MSR_URCTS) - { - result = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; - printk("UART_GET_MSR:0x%x\n",result); - }else{ - result = TIOCM_CAR | TIOCM_DSR; - printk("UART_GET_MSR:0x%x\n",result); - } - return result; -} - -static void rk2818_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) -{ - #ifdef DEBUG_LHH - printk("Enter::%s\n",__FUNCTION__); - #endif -} - -/* - * Stop transmitting. - */ -static void rk2818_serial_stop_tx(struct uart_port *port) -{ - #ifdef DEBUG_LHH - printk("Enter::%s\n",__FUNCTION__); - #endif -} - -/* - * Start transmitting. - */ -static void rk2818_serial_start_tx(struct uart_port *port) -{ - struct circ_buf *xmit = &port->state->xmit; - while(!(uart_circ_empty(xmit))) - { - while (!(rk2818_uart_read(port,UART_USR) & UART_TRANSMIT_FIFO_NOT_FULL)){ - rk2818_uart_write(port,UART_IER_RECV_DATA_AVAIL_INT_ENABLE|UART_IER_SEND_EMPTY_INT_ENABLE,UART_IER); - return; - } - rk2818_uart_write(port,xmit->buf[xmit->tail],UART_THR); - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); - port->icount.tx++; - } - if((uart_circ_empty(xmit))) - rk2818_uart_write(port,UART_IER_RECV_DATA_AVAIL_INT_ENABLE,UART_IER); - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) - uart_write_wakeup(port); -} - -/* - * Stop receiving - port is in process of being closed. - */ -static void rk2818_serial_stop_rx(struct uart_port *port) -{ - #ifdef DEBUG_LHH - printk("Enter::%s\n",__FUNCTION__); - #endif -} - -/* - * Control the transmission of a break signal - */ -static void rk2818_serial_break_ctl(struct uart_port *port, int break_state) -{ - unsigned int temp; - temp = rk2818_uart_read(port,UART_LCR); - if (break_state != 0) - temp = temp & (~BREAK_CONTROL_BIT);/* start break */ - else - temp = temp | BREAK_CONTROL_BIT; /* stop break */ - rk2818_uart_write(port,temp,UART_LCR); -} - - -/* - * Characters received (called from interrupt handler) - */ -static void rk2818_rx_chars(struct uart_port *port) -{ - unsigned int ch, flag; - while((rk2818_uart_read(port,UART_USR) & UART_RECEIVE_FIFO_NOT_EMPTY) == UART_RECEIVE_FIFO_NOT_EMPTY) - { - u32 lsr = rk2818_uart_read(port, UART_LSR); - ch = rk2818_uart_read(port,UART_RBR); - flag = TTY_NORMAL; - port->icount.rx++; - if (lsr & UART_BREAK_INT_BIT) { - port->icount.brk++; - if (uart_handle_break(port)) - continue; - } - if (uart_handle_sysrq_char(port, ch)) - { - continue; - } - uart_insert_char(port, 0, 0, ch, flag); - } - tty_flip_buffer_push(port->state->port.tty); - -} - -/* - * Interrupt handler - */ -static irqreturn_t rk2818_uart_interrupt(int irq, void *dev_id) -{ - struct uart_port *port = dev_id; - unsigned int status, pending; - - status = rk2818_uart_read(port,UART_IIR); - pending = status & 0x0f; - if((pending == UART_IIR_RECV_AVAILABLE) || (pending == UART_IIR_CHAR_TIMEOUT)) - rk2818_rx_chars(port); - if(pending == UART_IIR_THR_EMPTY) - rk2818_serial_start_tx(port); - return IRQ_HANDLED; -} - -/* - * Disable the port - */ -static void rk2818_serial_shutdown(struct uart_port *port) -{ - struct rk2818_port *rk2818_port = UART_TO_RK2818(port); - rk2818_uart_write(port,0x00,UART_IER); - clk_disable(rk2818_port->clk); - free_irq(port->irq, port); -} -/* - * Perform initialization and enable port for reception - */ -static int rk2818_serial_startup(struct uart_port *port) -{ - struct rk2818_port *rk2818_port = UART_TO_RK2818(port); - struct tty_struct *tty = port->state->port.tty; - int retval; - - retval = request_irq(port->irq,rk2818_uart_interrupt,IRQF_SHARED, - tty ? tty->name : "rk2818_serial",port); - if(retval) - { - printk("\nrk2818_serial_startup err \n"); - rk2818_serial_shutdown(port); - return retval; - } - clk_enable(rk2818_port->clk); - rk2818_uart_write(port,0xf1,UART_FCR); - rk2818_uart_write(port,0x01,UART_SFE);///enable fifo - rk2818_uart_write(port,UART_IER_RECV_DATA_AVAIL_INT_ENABLE,UART_IER); //enable uart recevice IRQ - return 0; -} - -/* - * Change the port parameters - */ -static void rk2818_serial_set_termios(struct uart_port *port, struct ktermios *termios, - struct ktermios *old) -{ - unsigned long flags; - unsigned int mode, baud; - unsigned int umcon,fcr; - /* Get current mode register */ - mode = rk2818_uart_read(port,UART_LCR) & (BREAK_CONTROL_BIT | EVEN_PARITY_SELECT | PARITY_ENABLED - | ONE_HALF_OR_TWO_BIT | UART_DATABIT_MASK); - - baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); - /* byte size */ - switch (termios->c_cflag & CSIZE) { - case CS5: - mode |= LCR_WLS_5; - break; - case CS6: - mode |= LCR_WLS_6; - break; - case CS7: - mode |= LCR_WLS_7; - break; - default: - mode |= LCR_WLS_8; - break; - } - - /* stop bits */ - if (termios->c_cflag & CSTOPB) - mode |= ONE_STOP_BIT; - - /* parity */ - if (termios->c_cflag & PARENB) - { - mode |= PARITY_ENABLED; - if (termios->c_cflag & PARODD) - mode |= ODD_PARITY; - else - mode |= EVEN_PARITY; - } - spin_lock_irqsave(&port->lock, flags); - if(termios->c_cflag & CRTSCTS) - { - /*¿ªÆôuart0Ó²¼þÁ÷¿Ø*/ - printk("start CRTSCTS control and baudrate is %d\n",baud); - umcon=rk2818_uart_read(port,UART_MCR); - printk("UART_GET_MCR umcon=0x%x\n",umcon); - umcon |= UART_MCR_AFCEN; - umcon |= UART_MCR_URRTS; - umcon &=~UART_SIR_ENABLE; - rk2818_uart_write(port,umcon,UART_MCR); - printk("UART_GET_MCR umcon=0x%x\n",umcon); - fcr=rk2818_uart_read(port,UART_FCR); - printk("UART_GET_MCR fcr=0x%x\n",fcr); - fcr |= UART_FCR_FIFO_ENABLE; - rk2818_uart_write(port,fcr,UART_FCR); - printk("UART_GET_MCR fcr=0x%x\n",fcr); - } - mode = mode | LCR_DLA_EN; - while(rk2818_uart_read(port,UART_USR)&UART_USR_BUSY) - cpu_relax(); - rk2818_uart_write(port,mode,UART_LCR); - baud = rk2818_set_baud_rate(port, baud); - uart_update_timeout(port, termios->c_cflag, baud); - spin_unlock_irqrestore(&port->lock, flags); -} - - -static void rk2818_serial_release_port(struct uart_port *port) -{ - struct platform_device *pdev = to_platform_device(port->dev); - struct resource *resource; - resource_size_t size; - - resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (unlikely(!resource)) - return; - size = resource->end - resource->start + 1; - - release_mem_region(port->mapbase, size); - iounmap(port->membase); - port->membase = NULL; -} - -static int rk2818_serial_request_port(struct uart_port *port) -{ - struct platform_device *pdev = to_platform_device(port->dev); - struct resource *resource; - resource_size_t size; - - resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (unlikely(!resource)) - return -ENXIO; - size = resource->end - resource->start + 1; - - if (unlikely(!request_mem_region(port->mapbase, size, "rk2818_serial"))) - return -EBUSY; - - port->membase = ioremap(port->mapbase, size); - if (!port->membase) { - release_mem_region(port->mapbase, size); - return -EBUSY; - } - - return 0; -} - -/* - * Configure/autoconfigure the port. - */ -static void rk2818_serial_config_port(struct uart_port *port, int flags) -{ - if (flags & UART_CONFIG_TYPE) { - port->type = PORT_RK2818; - rk2818_serial_request_port(port); - } -} - -/* - * Verify the new serial_struct (for TIOCSSERIAL). - */ -static int rk2818_serial_verify_port(struct uart_port *port, struct serial_struct *ser) -{ - int ret = 0; - if (ser->type != PORT_UNKNOWN && ser->type != PORT_RK2818) - ret = -EINVAL; - if (port->irq != ser->irq) - ret = -EINVAL; - if (ser->io_type != SERIAL_IO_MEM) - ret = -EINVAL; - if (port->uartclk / 16 != ser->baud_base) - ret = -EINVAL; - if ((void *)port->mapbase != ser->iomem_base) - ret = -EINVAL; - if (port->iobase != ser->port) - ret = -EINVAL; - if (ser->hub6 != 0) - ret = -EINVAL; - return ret; -} - -#ifdef CONFIG_CONSOLE_POLL -/* - * Console polling routines for writing and reading from the uart while - * in an interrupt or debug context. - */ - -static int rk2818_serial_poll_get_char(struct uart_port *port) -{ - while (!((rk2818_uart_read(port, UART_USR) & UART_RECEIVE_FIFO_NOT_EMPTY) == UART_RECEIVE_FIFO_NOT_EMPTY)) - barrier(); - return rk2818_uart_read(port, UART_RBR); -} - -static void rk2818_serial_poll_put_char(struct uart_port *port, unsigned char c) -{ - while (!(rk2818_uart_read(port, UART_USR) & UART_TRANSMIT_FIFO_NOT_FULL)) - barrier(); - rk2818_uart_write(port, c, UART_THR); -} -#endif /* CONFIG_CONSOLE_POLL */ - -static struct uart_ops rk2818_uart_pops = { - .tx_empty = rk2818_serial_tx_empty, - .set_mctrl = rk2818_serial_set_mctrl, - .get_mctrl = rk2818_serial_get_mctrl, - .stop_tx = rk2818_serial_stop_tx, - .start_tx = rk2818_serial_start_tx, - .stop_rx = rk2818_serial_stop_rx, - .enable_ms = rk2818_serial_enable_ms, - .break_ctl = rk2818_serial_break_ctl, - .startup = rk2818_serial_startup, - .shutdown = rk2818_serial_shutdown, - .set_termios = rk2818_serial_set_termios, - .type = rk2818_serial_type, - .release_port = rk2818_serial_release_port, - .request_port = rk2818_serial_request_port, - .config_port = rk2818_serial_config_port, - .verify_port = rk2818_serial_verify_port, - .pm = rk2818_serial_pm, -#ifdef CONFIG_CONSOLE_POLL - .poll_get_char = rk2818_serial_poll_get_char, - .poll_put_char = rk2818_serial_poll_put_char, -#endif -}; - - -static struct rk2818_port rk2818_uart_ports[] = { - { - .uart = { - .iotype = UPIO_MEM, - .ops = &rk2818_uart_pops, - .flags = UPF_BOOT_AUTOCONF, - .fifosize = 32, - .line = 0, - }, - }, - { - .uart = { - .iotype = UPIO_MEM, - .ops = &rk2818_uart_pops, - .flags = UPF_BOOT_AUTOCONF, - .fifosize = 32, - .line = 1, - }, - }, - { - .uart = { - .iotype = UPIO_MEM, - .ops = &rk2818_uart_pops, - .flags = UPF_BOOT_AUTOCONF, - .fifosize = 32, - .line = 2, - }, - }, - { - .uart = { - .iotype = UPIO_MEM, - .ops = &rk2818_uart_pops, - .flags = UPF_BOOT_AUTOCONF, - .fifosize = 32, - .line = 3, - }, - }, -}; - -#define UART_NR ARRAY_SIZE(rk2818_uart_ports) - -static inline struct uart_port *get_port_from_line(unsigned int line) -{ - return &rk2818_uart_ports[line].uart; -} - -#ifdef CONFIG_SERIAL_RK2818_CONSOLE -static void rk2818_console_putchar(struct uart_port *port, int ch) -{ - while (!(rk2818_uart_read(port,UART_USR) & UART_TRANSMIT_FIFO_NOT_FULL)) - cpu_relax(); - rk2818_uart_write(port,ch,UART_THR); -} - -/* - * Interrupts are disabled on entering - */ -static void rk2818_console_write(struct console *co, const char *s, u_int count) -{ - struct uart_port *port; - struct rk2818_port *rk2818_port; - - BUG_ON(co->index < 0 || co->index >= UART_NR); - - port = get_port_from_line(co->index); - rk2818_port = UART_TO_RK2818(port); - - spin_lock(&port->lock); - uart_console_write(port, s, count, rk2818_console_putchar); - spin_unlock(&port->lock); -} - -static int __init rk2818_console_setup(struct console *co, char *options) -{ - struct uart_port *port; - int baud, flow, bits, parity; - - if (unlikely(co->index >= UART_NR || co->index < 0)) - return -ENXIO; - - port = get_port_from_line(co->index); - - if (unlikely(!port->membase)) - return -ENXIO; - - port->cons = co; - - //rk2818_init_clock(port); - - if (options) - uart_parse_options(options, &baud, &parity, &bits, &flow); - - bits = 8; - parity = 'n'; - flow = 'n'; - rk2818_uart_write(port,rk2818_uart_read(port,UART_LCR) | LCR_WLS_8 | PARITY_DISABLED | ONE_STOP_BIT,UART_LCR); /* 8N1 */ - if (baud < 300 || baud > 115200) - baud = 115200; - rk2818_set_baud_rate(port, baud); - - printk(KERN_INFO "rk2818_serial: console setup on port %d\n", port->line); - - return uart_set_options(port, co, baud, parity, bits, flow); -} - -static struct uart_driver rk2818_uart_driver; - -static struct console rk2818_console = { - .name = "ttyS", - .write = rk2818_console_write, - .device = uart_console_device, - .setup = rk2818_console_setup, - .flags = CON_PRINTBUFFER, - .index = 1, - .data = &rk2818_uart_driver, -}; - -#define RK2818_CONSOLE (&rk2818_console) - -#else -#define RK2818_CONSOLE NULL -#endif - -static struct uart_driver rk2818_uart_driver = { - .owner = THIS_MODULE, - .driver_name = "rk2818_serial", - .dev_name = "ttyS", - .nr = UART_NR, - .cons = RK2818_CONSOLE, - .major = RK2818_SERIAL_MAJOR, - .minor = RK2818_SERIAL_MINOR, -}; - -static int __devinit rk2818_serial_probe(struct platform_device *pdev) -{ - struct rk2818_port *rk2818_port; - struct resource *resource; - struct uart_port *port; - struct rk2818_serial_platform_data *pdata = pdev->dev.platform_data; - - if (unlikely(pdev->id < 0 || pdev->id >= UART_NR)) - return -ENXIO; - - printk(KERN_INFO "rk2818_serial: detected port %d\n", pdev->id); - - if (pdata && pdata->io_init) - pdata->io_init(); - - port = get_port_from_line(pdev->id); - port->dev = &pdev->dev; - rk2818_port = UART_TO_RK2818(port); - - rk2818_port->clk = clk_get(&pdev->dev, "uart"); - if (unlikely(IS_ERR(rk2818_port->clk))) - return PTR_ERR(rk2818_port->clk); - port->uartclk = clk_get_rate(rk2818_port->clk); - - resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (unlikely(!resource)) - return -ENXIO; - port->mapbase = resource->start; - - port->irq = platform_get_irq(pdev, 0); - if (unlikely(port->irq < 0)) - return -ENXIO; - - platform_set_drvdata(pdev, port); - - return uart_add_one_port(&rk2818_uart_driver, port); -} - -static int __devexit rk2818_serial_remove(struct platform_device *pdev) -{ - struct rk2818_port *rk2818_port = platform_get_drvdata(pdev); - - clk_put(rk2818_port->clk); - - return 0; -} - -static struct platform_driver rk2818_platform_driver = { - .remove = rk2818_serial_remove, - .driver = { - .name = "rk2818_serial", - .owner = THIS_MODULE, - }, -}; - -static int __init rk2818_serial_init(void) -{ - int ret; - ret = uart_register_driver(&rk2818_uart_driver); - if (unlikely(ret)) - return ret; - - ret = platform_driver_probe(&rk2818_platform_driver, rk2818_serial_probe); - if (unlikely(ret)) - uart_unregister_driver(&rk2818_uart_driver); - - printk(KERN_INFO "rk2818_serial: driver initialized\n"); - - return ret; -} - -static void __exit rk2818_serial_exit(void) -{ - #ifdef CONFIG_SERIAL_RK2818_CONSOLE - unregister_console(&rk2818_console); - #endif - platform_driver_unregister(&rk2818_platform_driver); - uart_unregister_driver(&rk2818_uart_driver); -} - -/* - * While this can be a module, if builtin it's most likely the console - * So let's leave module_exit but move module_init to an earlier place - */ -arch_initcall(rk2818_serial_init); -module_exit(rk2818_serial_exit); - -MODULE_AUTHOR("lhh lhh@rock-chips.com"); -MODULE_DESCRIPTION("Rockchip RK2818 Serial port driver"); -MODULE_LICENSE("GPL"); diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 519f9bfb2551..633c9f52300e 100755 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -248,12 +248,6 @@ config SPI_XILINX # Add new SPI master controllers in alphabetical order above this line # -config SPIM_RK2818 - tristate "RK2818 SPI master controller core support" - depends on ARCH_RK2818 && SPI_MASTER - help - general driver for SPI controller core from DesignWare - config SPIM_RK29 tristate "RK29 SPI master controller core support" depends on ARCH_RK29 && SPI_MASTER diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 95d4d091e73c..510da55c41e0 100755 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -16,7 +16,6 @@ obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o obj-$(CONFIG_SPI_AU1550) += au1550_spi.o obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o -obj-$(CONFIG_SPIM_RK2818) += rk2818_spim.o obj-$(CONFIG_SPIM_RK29) += rk29_spim.o obj-$(CONFIG_SPI_GPIO) += spi_gpio.o obj-$(CONFIG_SPI_IMX) += spi_imx.o diff --git a/drivers/spi/rk2818_spim.c b/drivers/spi/rk2818_spim.c deleted file mode 100755 index ef72157a0bd2..000000000000 --- a/drivers/spi/rk2818_spim.c +++ /dev/null @@ -1,1528 +0,0 @@ -/*drivers/serial/rk2818_spim.c - driver for rk2818 spim device - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "rk2818_spim.h" -#include -#include - -#ifdef CONFIG_DEBUG_FS -#include -#endif - -/*Ô­ÓеÄspiÇý¶¯Ð§ÂʱȽϵͣ¬ -ÎÞ·¨Âú×ã´óÊý¾ÝÁ¿µÄ´«Ê䣻 -QUICK_TRANSFERÓÃÓÚ¿ìËÙ´«Ê䣬ͬʱ¿ÉÖ¸¶¨°ëË«¹¤»òÈ«Ë«¹¤£¬ -ĬÈÏʹÓðëË«¹¤ -*/ - -#define QUICK_TRANSFER - -#if 0 -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - - -#define START_STATE ((void *)0) -#define RUNNING_STATE ((void *)1) -#define DONE_STATE ((void *)2) -#define ERROR_STATE ((void *)-1) - -#define QUEUE_RUNNING 0 -#define QUEUE_STOPPED 1 - -#define MRST_SPI_DEASSERT 0 -#define MRST_SPI_ASSERT 1 ///CS0 -#define MRST_SPI_ASSERT1 2 ///CS1 - -/* Slave spi_dev related */ -struct chip_data { - u16 cr0; - u8 cs; /* chip select pin */ - u8 n_bytes; /* current is a 1/2/4 byte op */ - u8 tmode; /* TR/TO/RO/EEPROM */ - u8 type; /* SPI/SSP/MicroWire */ - - u8 poll_mode; /* 1 means use poll mode */ - - u32 dma_width; - u32 rx_threshold; - u32 tx_threshold; - u8 enable_dma; - u8 bits_per_word; - u16 clk_div; /* baud rate divider */ - u32 speed_hz; /* baud rate */ - int (*write)(struct rk2818_spi *dws); - int (*read)(struct rk2818_spi *dws); - void (*cs_control)(struct rk2818_spi *dws, u32 cs, u8 flag); -}; - -#ifdef CONFIG_DEBUG_FS -static int spi_show_regs_open(struct inode *inode, struct file *file) -{ - file->private_data = inode->i_private; - return 0; -} - -#define SPI_REGS_BUFSIZE 1024 -static ssize_t spi_show_regs(struct file *file, char __user *user_buf, - size_t count, loff_t *ppos) -{ - struct rk2818_spi *dws; - char *buf; - u32 len = 0; - ssize_t ret; - - dws = file->private_data; - - buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL); - if (!buf) - return 0; - - len += printk(buf + len, SPI_REGS_BUFSIZE - len, - "MRST SPI0 registers:\n"); - len += printk(buf + len, SPI_REGS_BUFSIZE - len, - "=================================\n"); - len += printk(buf + len, SPI_REGS_BUFSIZE - len, - "CTRL0: \t\t0x%08x\n", rk2818_readl(dws, SPIM_CTRLR0)); - len += printk(buf + len, SPI_REGS_BUFSIZE - len, - "CTRL1: \t\t0x%08x\n", rk2818_readl(dws, SPIM_CTRLR1)); - len += printk(buf + len, SPI_REGS_BUFSIZE - len, - "SSIENR: \t0x%08x\n", rk2818_readl(dws, SPIM_SPIENR)); - len += printk(buf + len, SPI_REGS_BUFSIZE - len, - "SER: \t\t0x%08x\n", rk2818_readl(dws, SPIM_SER)); - len += printk(buf + len, SPI_REGS_BUFSIZE - len, - "BAUDR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_BAUDR)); - len += printk(buf + len, SPI_REGS_BUFSIZE - len, - "TXFTLR: \t0x%08x\n", rk2818_readl(dws, SPIM_TXFTLR)); - len += printk(buf + len, SPI_REGS_BUFSIZE - len, - "RXFTLR: \t0x%08x\n", rk2818_readl(dws, SPIM_RXFTLR)); - len += printk(buf + len, SPI_REGS_BUFSIZE - len, - "TXFLR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_TXFLR)); - len += printk(buf + len, SPI_REGS_BUFSIZE - len, - "RXFLR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_RXFLR)); - len += printk(buf + len, SPI_REGS_BUFSIZE - len, - "SR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_SR)); - len += printk(buf + len, SPI_REGS_BUFSIZE - len, - "IMR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_IMR)); - len += printk(buf + len, SPI_REGS_BUFSIZE - len, - "ISR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_ISR)); - len += printk(buf + len, SPI_REGS_BUFSIZE - len, - "DMACR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_DMACR)); - len += printk(buf + len, SPI_REGS_BUFSIZE - len, - "DMATDLR: \t0x%08x\n", rk2818_readl(dws, SPIM_DMATDLR)); - len += printk(buf + len, SPI_REGS_BUFSIZE - len, - "DMARDLR: \t0x%08x\n", rk2818_readl(dws, SPIM_DMARDLR)); - len += printk(buf + len, SPI_REGS_BUFSIZE - len, - "=================================\n"); - - ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); - kfree(buf); - return ret; -} - -static const struct file_operations mrst_spi_regs_ops = { - .owner = THIS_MODULE, - .open = spi_show_regs_open, - .read = spi_show_regs, -}; - -static int mrst_spi_debugfs_init(struct rk2818_spi *dws) -{ - dws->debugfs = debugfs_create_dir("mrst_spi", NULL); - if (!dws->debugfs) - return -ENOMEM; - - debugfs_create_file("registers", S_IFREG | S_IRUGO, - dws->debugfs, (void *)dws, &mrst_spi_regs_ops); - return 0; -} - -static void mrst_spi_debugfs_remove(struct rk2818_spi *dws) -{ - if (dws->debugfs) - debugfs_remove_recursive(dws->debugfs); -} - -#else -static inline int mrst_spi_debugfs_init(struct rk2818_spi *dws) -{ - return 0; -} - -static inline void mrst_spi_debugfs_remove(struct rk2818_spi *dws) -{ -} -#endif /* CONFIG_DEBUG_FS */ - -static void wait_till_not_busy(struct rk2818_spi *dws) -{ - unsigned long end = jiffies + 1 + usecs_to_jiffies(1000); - - while (time_before(jiffies, end)) { - if (!(rk2818_readw(dws, SPIM_SR) & SR_BUSY)) - return; - } - dev_err(&dws->master->dev, - "DW SPI: Status keeps busy for 1000us after a read/write!\n"); -} - -static void wait_till_tf_empty(struct rk2818_spi *dws) -{ - unsigned long end = jiffies + 1 + usecs_to_jiffies(1000); - - while (time_before(jiffies, end)) { - if (rk2818_readw(dws, SPIM_SR) & SR_TF_EMPT) - return; - } - dev_err(&dws->master->dev, - "DW SPI: Status keeps busy for 1000us after a read/write!\n"); -} - -static void flush(struct rk2818_spi *dws) -{ - while (rk2818_readw(dws, SPIM_SR) & SR_RF_NOT_EMPT) - rk2818_readw(dws, SPIM_DR0); - - wait_till_not_busy(dws); -} - -static void spi_cs_control(struct rk2818_spi *dws, u32 cs, u8 flag) -{ - #ifdef CONFIG_MACH_RK2818INFO_IT50 - return; - #else - struct rk2818_spi_platform_data *pdata = dws->master->dev.platform_data; - struct spi_cs_gpio *cs_gpios = pdata->chipselect_gpios; - - if (flag == 0) - gpio_direction_output(cs_gpios[cs].cs_gpio, GPIO_HIGH); - else - gpio_direction_output(cs_gpios[cs].cs_gpio, GPIO_LOW); - #endif -} - -static int null_writer(struct rk2818_spi *dws) -{ - u8 n_bytes = dws->n_bytes; - - if (!(rk2818_readw(dws, SPIM_SR) & SR_TF_NOT_FULL) - || (dws->tx == dws->tx_end)) - return 0; - rk2818_writew(dws, SPIM_DR0, 0); - dws->tx += n_bytes; - //wait_till_not_busy(dws); - - return 1; -} - -static int null_reader(struct rk2818_spi *dws) -{ - u8 n_bytes = dws->n_bytes; - while ((rk2818_readw(dws, SPIM_SR) & SR_RF_NOT_EMPT) - && (dws->rx < dws->rx_end)) { - rk2818_readw(dws, SPIM_DR0); - dws->rx += n_bytes; - } - wait_till_not_busy(dws); - return dws->rx == dws->rx_end; -} - -static int u8_writer(struct rk2818_spi *dws) -{ - if (!(rk2818_readw(dws, SPIM_SR) & SR_TF_NOT_FULL) - || (dws->tx == dws->tx_end)) - return 0; - rk2818_writew(dws, SPIM_DR0, *(u8 *)(dws->tx)); - ++dws->tx; - //wait_till_not_busy(dws); - - return 1; -} - -static int u8_reader(struct rk2818_spi *dws) -{ - while ((rk2818_readw(dws, SPIM_SR) & SR_RF_NOT_EMPT) - && (dws->rx < dws->rx_end)) { - *(u8 *)(dws->rx) = rk2818_readw(dws, SPIM_DR0); - ++dws->rx; - } - - wait_till_not_busy(dws); - return dws->rx == dws->rx_end; -} - -static int u16_writer(struct rk2818_spi *dws) -{ - if (!(rk2818_readw(dws, SPIM_SR) & SR_TF_NOT_FULL) - || (dws->tx == dws->tx_end)) - return 0; - - rk2818_writew(dws, SPIM_DR0, *(u16 *)(dws->tx)); - dws->tx += 2; - //wait_till_not_busy(dws); - - return 1; -} - -static int u16_reader(struct rk2818_spi *dws) -{ - u16 temp; - - while ((rk2818_readw(dws, SPIM_SR) & SR_RF_NOT_EMPT) - && (dws->rx < dws->rx_end)) { - temp = rk2818_readw(dws, SPIM_DR0); - *(u16 *)(dws->rx) = temp; - dws->rx += 2; - } - - wait_till_not_busy(dws); - return dws->rx == dws->rx_end; -} - -static void *next_transfer(struct rk2818_spi *dws) -{ - struct spi_message *msg = dws->cur_msg; - struct spi_transfer *trans = dws->cur_transfer; - - /* Move to next transfer */ - if (trans->transfer_list.next != &msg->transfers) { - dws->cur_transfer = - list_entry(trans->transfer_list.next, - struct spi_transfer, - transfer_list); - return RUNNING_STATE; - } else - return DONE_STATE; -} - -/* - * Note: first step is the protocol driver prepares - * a dma-capable memory, and this func just need translate - * the virt addr to physical - */ -static int map_dma_buffers(struct rk2818_spi *dws) -{ - if (!dws->cur_msg->is_dma_mapped || !dws->dma_inited - || !dws->cur_chip->enable_dma) - return 0; - - if (dws->cur_transfer->tx_dma) - dws->tx_dma = dws->cur_transfer->tx_dma; - - if (dws->cur_transfer->rx_dma) - dws->rx_dma = dws->cur_transfer->rx_dma; - - return 1; -} - -/* Caller already set message->status; dma and pio irqs are blocked */ -static void giveback(struct rk2818_spi *dws) -{ - struct spi_transfer *last_transfer; - unsigned long flags; - struct spi_message *msg; - - spin_lock_irqsave(&dws->lock, flags); - msg = dws->cur_msg; - dws->cur_msg = NULL; - dws->cur_transfer = NULL; - dws->prev_chip = dws->cur_chip; - dws->cur_chip = NULL; - dws->dma_mapped = 0; - queue_work(dws->workqueue, &dws->pump_messages); - spin_unlock_irqrestore(&dws->lock, flags); - - last_transfer = list_entry(msg->transfers.prev, - struct spi_transfer, - transfer_list); - - if (!last_transfer->cs_change) - dws->cs_control(dws,msg->spi->chip_select,MRST_SPI_DEASSERT); - - msg->state = NULL; - if (msg->complete) - msg->complete(msg->context); -} - -static void int_error_stop(struct rk2818_spi *dws, const char *msg) -{ - /* Stop and reset hw */ - flush(dws); - spi_enable_chip(dws, 0); - - dev_err(&dws->master->dev, "%s\n", msg); - dws->cur_msg->state = ERROR_STATE; - tasklet_schedule(&dws->pump_transfers); -} - -static void transfer_complete(struct rk2818_spi *dws) -{ - /* Update total byte transfered return count actual bytes read */ - dws->cur_msg->actual_length += dws->len; - - /* Move to next transfer */ - dws->cur_msg->state = next_transfer(dws); - - /* Handle end of message */ - if (dws->cur_msg->state == DONE_STATE) { - dws->cur_msg->status = 0; - giveback(dws); - } else - tasklet_schedule(&dws->pump_transfers); -} - -static irqreturn_t interrupt_transfer(struct rk2818_spi *dws) -{ - u16 irq_status, irq_mask = 0x3f; - u32 int_level = dws->fifo_len / 2; - u32 left; - - irq_status = rk2818_readw(dws, SPIM_ISR) & irq_mask; - /* Error handling */ - if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) { - rk2818_readw(dws, SPIM_TXOICR); - rk2818_readw(dws, SPIM_RXOICR); - rk2818_readw(dws, SPIM_RXUICR); - int_error_stop(dws, "interrupt_transfer: fifo overrun"); - return IRQ_HANDLED; - } - - if (irq_status & SPI_INT_TXEI) { - spi_mask_intr(dws, SPI_INT_TXEI); - - left = (dws->tx_end - dws->tx) / dws->n_bytes; - left = (left > int_level) ? int_level : left; - - while (left--) { - dws->write(dws); - wait_till_not_busy(dws); - } - dws->read(dws); - - /* Re-enable the IRQ if there is still data left to tx */ - if (dws->tx_end > dws->tx) - spi_umask_intr(dws, SPI_INT_TXEI); - else - transfer_complete(dws); - } - - return IRQ_HANDLED; -} - -static irqreturn_t rk2818_spi_irq(int irq, void *dev_id) -{ - struct rk2818_spi *dws = dev_id; - - if (!dws->cur_msg) { - spi_mask_intr(dws, SPI_INT_TXEI); - /* Never fail */ - return IRQ_HANDLED; - } - - return dws->transfer_handler(dws); -} - -/* Must be called inside pump_transfers() */ -static void poll_transfer(struct rk2818_spi *dws) -{ - while (dws->write(dws)) { - wait_till_not_busy(dws); - dws->read(dws); - } - transfer_complete(dws); -} - -static void dma_transfer(struct rk2818_spi *dws, struct spi_transfer *xfer) //int cs_change) -{ - -} - -static void spi_chip_sel(struct rk2818_spi *dws, u16 cs) -{ - if(cs >= dws->master->num_chipselect) - return; - - if (dws->cs_control){ - dws->cs_control(dws, cs, 1); - } - //rk2818_writel(dws, SPIM_SER, 1 << cs); - rk2818_writel(dws, SPIM_SER, 1 << 0); -} - -static void pump_transfers(unsigned long data) -{ - struct rk2818_spi *dws = (struct rk2818_spi *)data; - struct spi_message *message = NULL; - struct spi_transfer *transfer = NULL; - struct spi_transfer *previous = NULL; - struct spi_device *spi = NULL; - struct chip_data *chip = NULL; - u8 bits = 0; - u8 imask = 0; - u8 cs_change = 0; - u16 txint_level = 0; - u16 clk_div = 0; - u32 speed = 0; - u32 cr0 = 0; - - /* Get current state information */ - message = dws->cur_msg; - transfer = dws->cur_transfer; - chip = dws->cur_chip; - spi = message->spi; - if (unlikely(!chip->clk_div)) - chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz; - if (message->state == ERROR_STATE) { - message->status = -EIO; - goto early_exit; - } - - /* Handle end of message */ - if (message->state == DONE_STATE) { - message->status = 0; - goto early_exit; - } - - /* Delay if requested at end of transfer*/ - if (message->state == RUNNING_STATE) { - previous = list_entry(transfer->transfer_list.prev, - struct spi_transfer, - transfer_list); - if (previous->delay_usecs) - udelay(previous->delay_usecs); - } - - dws->n_bytes = chip->n_bytes; - dws->dma_width = chip->dma_width; - dws->cs_control = chip->cs_control; - - dws->rx_dma = transfer->rx_dma; - dws->tx_dma = transfer->tx_dma; - dws->tx = (void *)transfer->tx_buf; - dws->tx_end = dws->tx + transfer->len; - dws->rx = transfer->rx_buf; - dws->rx_end = dws->rx + transfer->len; - dws->write = dws->tx ? chip->write : null_writer; - dws->read = dws->rx ? chip->read : null_reader; - dws->cs_change = transfer->cs_change; - dws->len = dws->cur_transfer->len; - if (chip != dws->prev_chip) - cs_change = 1; - - cr0 = chip->cr0; - - /* Handle per transfer options for bpw and speed */ - if (transfer->speed_hz) { - speed = chip->speed_hz; - - if (transfer->speed_hz != speed) { - speed = transfer->speed_hz; - if (speed > clk_get_rate(dws->clock_spim)) { - printk(KERN_ERR "MRST SPI0: unsupported" - "freq: %dHz\n", speed); - message->status = -EIO; - goto early_exit; - } - - /* clk_div doesn't support odd number */ - clk_div = clk_get_rate(dws->clock_spim) / speed; - clk_div = (clk_div + 1) & 0xfffe; - - chip->speed_hz = speed; - chip->clk_div = clk_div; - } - } - if (transfer->bits_per_word) { - bits = transfer->bits_per_word; - - switch (bits) { - case 8: - dws->n_bytes = 1; - dws->dma_width = 1; - dws->read = (dws->read != null_reader) ? - u8_reader : null_reader; - dws->write = (dws->write != null_writer) ? - u8_writer : null_writer; - break; - case 16: - dws->n_bytes = 2; - dws->dma_width = 2; - dws->read = (dws->read != null_reader) ? - u16_reader : null_reader; - dws->write = (dws->write != null_writer) ? - u16_writer : null_writer; - break; - default: - printk(KERN_ERR "MRST SPI0: unsupported bits:" - "%db\n", bits); - message->status = -EIO; - goto early_exit; - } - - cr0 = (bits - 1) - | (chip->type << SPI_FRF_OFFSET) - | (spi->mode << SPI_MODE_OFFSET) - | (chip->tmode << SPI_TMOD_OFFSET); - } - message->state = RUNNING_STATE; - - /* - * Adjust transfer mode if necessary. Requires platform dependent - * chipselect mechanism. - */ - if (dws->cs_control) { - if (dws->rx && dws->tx) - chip->tmode = 0x00; - else if (dws->rx) - chip->tmode = 0x02; - else - chip->tmode = 0x01; - - cr0 &= ~(0x3 << SPI_MODE_OFFSET); - cr0 |= (chip->tmode << SPI_TMOD_OFFSET); - } - /* Check if current transfer is a DMA transaction */ - dws->dma_mapped = map_dma_buffers(dws); - - /* - * Interrupt mode - * we only need set the TXEI IRQ, as TX/RX always happen syncronizely - */ - if (!dws->dma_mapped && !chip->poll_mode) { - int templen = dws->len / dws->n_bytes; - txint_level = dws->fifo_len / 2; - txint_level = (templen > txint_level) ? txint_level : templen; - - imask |= SPI_INT_TXEI; - dws->transfer_handler = interrupt_transfer; - } - - /* - * Reprogram registers only if - * 1. chip select changes - * 2. clk_div is changed - * 3. control value changes - */ - if (rk2818_readw(dws, SPIM_CTRLR0) != cr0 || cs_change || clk_div || imask) { - spi_enable_chip(dws, 0); - if (rk2818_readw(dws, SPIM_CTRLR0) != cr0) - rk2818_writew(dws, SPIM_CTRLR0, cr0); - - spi_set_clk(dws, clk_div ? clk_div : chip->clk_div); - spi_chip_sel(dws, spi->chip_select); - /* Set the interrupt mask, for poll mode just diable all int */ - spi_mask_intr(dws, 0xff); - if (imask) - spi_umask_intr(dws, imask); - if (txint_level) - rk2818_writew(dws, SPIM_TXFTLR, txint_level); - - spi_enable_chip(dws, 1); - if (cs_change) - dws->prev_chip = chip; - } - - if (dws->dma_mapped) - dma_transfer(dws, transfer); ///cs_change); - - if (chip->poll_mode) - poll_transfer(dws); - - return; - -early_exit: - giveback(dws); - return; -} - -static void pump_messages(struct work_struct *work) -{ - struct rk2818_spi *dws = - container_of(work, struct rk2818_spi, pump_messages); - unsigned long flags; - - /* Lock queue and check for queue work */ - spin_lock_irqsave(&dws->lock, flags); - if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) { - dws->busy = 0; - spin_unlock_irqrestore(&dws->lock, flags); - return; - } - - /* Make sure we are not already running a message */ - if (dws->cur_msg) { - spin_unlock_irqrestore(&dws->lock, flags); - return; - } - - /* Extract head of queue */ - dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue); - list_del_init(&dws->cur_msg->queue); - - /* Initial message state*/ - dws->cur_msg->state = START_STATE; - dws->cur_transfer = list_entry(dws->cur_msg->transfers.next, - struct spi_transfer, - transfer_list); - dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi); - dws->prev_chip = NULL; //ÿ¸öpump messageʱǿÖƸüÐÂcs dxj - - /* Mark as busy and launch transfers */ - tasklet_schedule(&dws->pump_transfers); - - dws->busy = 1; - spin_unlock_irqrestore(&dws->lock, flags); -} - -/* spi_device use this to queue in their spi_msg */ -static int rk2818_spi_transfer(struct spi_device *spi, struct spi_message *msg) -{ - struct rk2818_spi *dws = spi_master_get_devdata(spi->master); - unsigned long flags; - - spin_lock_irqsave(&dws->lock, flags); - - if (dws->run == QUEUE_STOPPED) { - spin_unlock_irqrestore(&dws->lock, flags); - return -ESHUTDOWN; - } - - msg->actual_length = 0; - msg->status = -EINPROGRESS; - msg->state = START_STATE; - - list_add_tail(&msg->queue, &dws->queue); - - if (dws->run == QUEUE_RUNNING && !dws->busy) { - - if (dws->cur_transfer || dws->cur_msg) - queue_work(dws->workqueue, - &dws->pump_messages); - else { - /* If no other data transaction in air, just go */ - spin_unlock_irqrestore(&dws->lock, flags); - pump_messages(&dws->pump_messages); - return 0; - } - } - - spin_unlock_irqrestore(&dws->lock, flags); - - return 0; -} - -#if defined(QUICK_TRANSFER) -static void do_read(struct rk2818_spi *dws) -{ - int count = 0; - - spi_enable_chip(dws, 0); - rk2818_writew(dws, SPIM_CTRLR1, dws->rx_end-dws->rx-1); - spi_enable_chip(dws, 1); - rk2818_writew(dws, SPIM_DR0, 0); - while (1) { - if (dws->read(dws)) - break; - if (count ++ == 0x20) { - printk("+++++++++++spi receive data time out+++++++++++++\n"); - break; - } - - } -} - -static void do_write(struct rk2818_spi *dws) -{ - while (dws->txtx_end) { - dws->write(dws); - } -} - -/* Caller already set message->status; dma and pio irqs are blocked */ -static void msg_giveback(struct rk2818_spi *dws) -{ - struct spi_transfer *last_transfer; - struct spi_message *msg; - - DBG("+++++++++++++++enter %s++++++++++++++++++\n", __func__); - - msg = dws->cur_msg; - dws->cur_msg = NULL; - dws->cur_transfer = NULL; - dws->prev_chip = dws->cur_chip; - dws->cur_chip = NULL; - dws->dma_mapped = 0; - dws->busy = 0; - - last_transfer = list_entry(msg->transfers.prev, - struct spi_transfer, - transfer_list); - - if (!last_transfer->cs_change) - dws->cs_control(dws,msg->spi->chip_select,MRST_SPI_DEASSERT); - - msg->state = NULL; -} - -/* Must be called inside pump_transfers() */ -static int do_full_transfer(struct rk2818_spi *dws) -{ - if ((dws->read(dws))) { - goto comple; - } - - while (dws->txtx_end){ - dws->write(dws); - dws->read(dws); - } - - if (dws->rx < dws->rx_end) { - dws->read(dws); - } - -comple: - - dws->cur_msg->actual_length += dws->len; - - /* Move to next transfer */ - dws->cur_msg->state = next_transfer(dws); - - if (dws->cur_msg->state == DONE_STATE) { - dws->cur_msg->status = 0; - //msg_giveback(dws); - return 0; - } - else { - return -1; - } - -} - - -/* Must be called inside pump_transfers() */ -static int do_half_transfer(struct rk2818_spi *dws) -{ - if (dws->rx) { - if (dws->tx) { - do_write(dws); - } - wait_till_tf_empty(dws); - wait_till_not_busy(dws); - do_read(dws); - } - else { - do_write(dws); - wait_till_tf_empty(dws); - wait_till_not_busy(dws); - } - - dws->cur_msg->actual_length += dws->len; - - /* Move to next transfer */ - dws->cur_msg->state = next_transfer(dws); - - if (dws->cur_msg->state == DONE_STATE) { - dws->cur_msg->status = 0; - //msg_giveback(dws); - return 0; - } - else { - return -1; - } -} - - -static int rk2818_pump_transfers(struct rk2818_spi *dws, int mode) -{ - struct spi_message *message = NULL; - struct spi_transfer *transfer = NULL; - struct spi_transfer *previous = NULL; - struct spi_device *spi = NULL; - struct chip_data *chip = NULL; - u8 bits = 0; - u8 cs_change = 0; - u16 clk_div = 0; - u32 speed = 0; - u32 cr0 = 0; - - DBG("+++++++++++++++enter %s++++++++++++++++++\n", __func__); - - /* Get current state information */ - message = dws->cur_msg; - transfer = dws->cur_transfer; - chip = dws->cur_chip; - spi = message->spi; - - if (unlikely(!chip->clk_div)) - chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz; - if (message->state == ERROR_STATE) { - message->status = -EIO; - goto early_exit; - } - - /* Handle end of message */ - if (message->state == DONE_STATE) { - message->status = 0; - goto early_exit; - } - - /* Delay if requested at end of transfer*/ - if (message->state == RUNNING_STATE) { - previous = list_entry(transfer->transfer_list.prev, - struct spi_transfer, - transfer_list); - if (previous->delay_usecs) - udelay(previous->delay_usecs); - } - - dws->n_bytes = chip->n_bytes; - dws->dma_width = chip->dma_width; - dws->cs_control = chip->cs_control; - - dws->rx_dma = transfer->rx_dma; - dws->tx_dma = transfer->tx_dma; - dws->tx = (void *)transfer->tx_buf; - dws->tx_end = dws->tx + transfer->len; - dws->rx = transfer->rx_buf; - dws->rx_end = dws->rx + transfer->len; - dws->write = dws->tx ? chip->write : null_writer; - dws->read = dws->rx ? chip->read : null_reader; - if (dws->rx && dws->tx) { - int temp_len = transfer->len; - int len; - unsigned char *tx_buf; - for (len=0; *tx_buf++ != 0; len++); - dws->tx_end = dws->tx + len; - dws->rx_end = dws->rx + temp_len - len; - } - dws->cs_change = transfer->cs_change; - dws->len = dws->cur_transfer->len; - if (chip != dws->prev_chip) - cs_change = 1; - - cr0 = chip->cr0; - - /* Handle per transfer options for bpw and speed */ - if (transfer->speed_hz) { - speed = chip->speed_hz; - - if (transfer->speed_hz != speed) { - speed = transfer->speed_hz; - if (speed > clk_get_rate(dws->clock_spim)) { - printk(KERN_ERR "MRST SPI0: unsupported" - "freq: %dHz\n", speed); - message->status = -EIO; - goto early_exit; - } - - /* clk_div doesn't support odd number */ - clk_div = clk_get_rate(dws->clock_spim) / speed; - clk_div = (clk_div + 1) & 0xfffe; - - chip->speed_hz = speed; - chip->clk_div = clk_div; - } - } - if (transfer->bits_per_word) { - bits = transfer->bits_per_word; - - switch (bits) { - case 8: - dws->n_bytes = 1; - dws->dma_width = 1; - dws->read = (dws->read != null_reader) ? - u8_reader : null_reader; - dws->write = (dws->write != null_writer) ? - u8_writer : null_writer; - break; - case 16: - dws->n_bytes = 2; - dws->dma_width = 2; - dws->read = (dws->read != null_reader) ? - u16_reader : null_reader; - dws->write = (dws->write != null_writer) ? - u16_writer : null_writer; - break; - default: - printk(KERN_ERR "MRST SPI0: unsupported bits:" - "%db\n", bits); - message->status = -EIO; - goto early_exit; - } - - cr0 = (bits - 1) - | (chip->type << SPI_FRF_OFFSET) - | (spi->mode << SPI_MODE_OFFSET) - | (chip->tmode << SPI_TMOD_OFFSET); - } - message->state = RUNNING_STATE; - - /* - * Adjust transfer mode if necessary. Requires platform dependent - * chipselect mechanism. - */ - if (dws->cs_control) { - if (dws->rx && dws->tx) - chip->tmode = 0x00; - else if (dws->rx) - chip->tmode = 0x02; - else - chip->tmode = 0x01; - - cr0 &= ~(0x3 << SPI_MODE_OFFSET); - cr0 |= (chip->tmode << SPI_TMOD_OFFSET); - } - - /* - * Reprogram registers only if - * 1. chip select changes - * 2. clk_div is changed - * 3. control value changes - */ - spi_enable_chip(dws, 0); - if (rk2818_readw(dws, SPIM_CTRLR0) != cr0) - rk2818_writew(dws, SPIM_CTRLR0, cr0); - - spi_set_clk(dws, clk_div ? clk_div : chip->clk_div); - spi_chip_sel(dws, spi->chip_select); - rk2818_writew(dws, SPIM_CTRLR1, 0);//add by lyx - spi_enable_chip(dws, 1); - if (cs_change) - dws->prev_chip = chip; - - if (mode) - return do_full_transfer(dws); - else - return do_half_transfer(dws); -early_exit: - - //msg_giveback(dws); - - return 0; -} - -static void rk2818_pump_messages(struct rk2818_spi *dws, int mode) -{ - DBG("+++++++++++++++enter %s++++++++++++++++++\n", __func__); - - if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) { - dws->busy = 0; - return; - } - - /* Make sure we are not already running a message */ - if (dws->cur_msg) { - return; - } - - /* Extract head of queue */ - dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue); - list_del_init(&dws->cur_msg->queue); - - /* Initial message state*/ - dws->cur_msg->state = START_STATE; - dws->cur_transfer = list_entry(dws->cur_msg->transfers.next, - struct spi_transfer, - transfer_list); - dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi); - dws->prev_chip = NULL; //ÿ¸öpump messageʱǿÖƸüÐÂcs dxj - - /* Mark as busy and launch transfers */ - dws->busy = 1; - - while (rk2818_pump_transfers(dws, mode)) ; -} - -/* spi_device use this to queue in their spi_msg */ -static int rk2818_spi_quick_transfer(struct spi_device *spi, struct spi_message *msg) -{ - struct rk2818_spi *dws = spi_master_get_devdata(spi->master); - unsigned long flags; - struct rk2818_spi_chip *chip_info = spi->controller_data; - struct spi_message *mmsg; - - DBG("+++++++++++++++enter %s++++++++++++++++++\n", __func__); - - spin_lock_irqsave(&dws->lock, flags); - - if (dws->run == QUEUE_STOPPED) { - spin_unlock_irqrestore(&dws->lock, flags); - return -ESHUTDOWN; - } - - msg->actual_length = 0; - msg->status = -EINPROGRESS; - msg->state = START_STATE; - - list_add_tail(&msg->queue, &dws->queue); - - if (chip_info && (chip_info->transfer_mode == RK2818_SPI_FULL_DUPLEX)) { - rk2818_pump_messages(dws,1); - //printk("+++++++++++++full transfer++++++++++++++\n"); - } - else { - rk2818_pump_messages(dws,0); - //printk("+++++++++++++half transfer++++++++++++++\n"); - } - - mmsg = dws->cur_msg; - msg_giveback(dws); - - spin_unlock_irqrestore(&dws->lock, flags); - - if (mmsg->complete) - mmsg->complete(mmsg->context); - - return 0; -} -#endif - -/* This may be called twice for each spi dev */ -static int rk2818_spi_setup(struct spi_device *spi) -{ - struct rk2818_spi_chip *chip_info = NULL; - struct chip_data *chip; - - if (spi->bits_per_word != 8 && spi->bits_per_word != 16) - return -EINVAL; - - /* Only alloc on first setup */ - chip = spi_get_ctldata(spi); - if (!chip) { - chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); - if (!chip) - return -ENOMEM; - - chip->cs_control = spi_cs_control; - chip->enable_dma = 1; //0; - } - - /* - * Protocol drivers may change the chip settings, so... - * if chip_info exists, use it - */ - chip_info = spi->controller_data; - - /* chip_info doesn't always exist */ - if (chip_info) { - if (chip_info->cs_control) - chip->cs_control = chip_info->cs_control; - - chip->poll_mode = chip_info->poll_mode; - chip->type = chip_info->type; - - chip->rx_threshold = 0; - chip->tx_threshold = 0; - - chip->enable_dma = chip_info->enable_dma; - } - - if (spi->bits_per_word <= 8) { - chip->n_bytes = 1; - chip->dma_width = 1; - chip->read = u8_reader; - chip->write = u8_writer; - } else if (spi->bits_per_word <= 16) { - chip->n_bytes = 2; - chip->dma_width = 2; - chip->read = u16_reader; - chip->write = u16_writer; - } else { - /* Never take >16b case for MRST SPIC */ - dev_err(&spi->dev, "invalid wordsize\n"); - return -EINVAL; - } - chip->bits_per_word = spi->bits_per_word; - - if (!spi->max_speed_hz) { - dev_err(&spi->dev, "No max speed HZ parameter\n"); - return -EINVAL; - } - chip->speed_hz = spi->max_speed_hz; - - chip->tmode = 0; /* Tx & Rx */ - /* Default SPI mode is SCPOL = 0, SCPH = 0 */ - chip->cr0 = (chip->bits_per_word - 1) - | (chip->type << SPI_FRF_OFFSET) - | (spi->mode << SPI_MODE_OFFSET) - | (chip->tmode << SPI_TMOD_OFFSET); - - spi_set_ctldata(spi, chip); - return 0; -} - -static void rk2818_spi_cleanup(struct spi_device *spi) -{ - struct chip_data *chip = spi_get_ctldata(spi); - kfree(chip); -} - -static int __devinit init_queue(struct rk2818_spi *dws) -{ - INIT_LIST_HEAD(&dws->queue); - spin_lock_init(&dws->lock); - - dws->run = QUEUE_STOPPED; - dws->busy = 0; - - tasklet_init(&dws->pump_transfers, - pump_transfers, (unsigned long)dws); - - INIT_WORK(&dws->pump_messages, pump_messages); - dws->workqueue = create_singlethread_workqueue( - dev_name(dws->master->dev.parent)); - if (dws->workqueue == NULL) - return -EBUSY; - - return 0; -} - -static int start_queue(struct rk2818_spi *dws) -{ - unsigned long flags; - - spin_lock_irqsave(&dws->lock, flags); - - if (dws->run == QUEUE_RUNNING || dws->busy) { - spin_unlock_irqrestore(&dws->lock, flags); - return -EBUSY; - } - - dws->run = QUEUE_RUNNING; - dws->cur_msg = NULL; - dws->cur_transfer = NULL; - dws->cur_chip = NULL; - dws->prev_chip = NULL; - spin_unlock_irqrestore(&dws->lock, flags); - - queue_work(dws->workqueue, &dws->pump_messages); - - return 0; -} - -static int stop_queue(struct rk2818_spi *dws) -{ - unsigned long flags; - unsigned limit = 50; - int status = 0; - - spin_lock_irqsave(&dws->lock, flags); - dws->run = QUEUE_STOPPED; - while (!list_empty(&dws->queue) && dws->busy && limit--) { - spin_unlock_irqrestore(&dws->lock, flags); - msleep(10); - spin_lock_irqsave(&dws->lock, flags); - } - - if (!list_empty(&dws->queue) || dws->busy) - status = -EBUSY; - spin_unlock_irqrestore(&dws->lock, flags); - - return status; -} - -static int destroy_queue(struct rk2818_spi *dws) -{ - int status; - - status = stop_queue(dws); - if (status != 0) - return status; - destroy_workqueue(dws->workqueue); - return 0; -} - -/* Restart the controller, disable all interrupts, clean rx fifo */ -static void spi_hw_init(struct rk2818_spi *dws) -{ - spi_enable_chip(dws, 0); - spi_mask_intr(dws, 0xff); - spi_enable_chip(dws, 1); - flush(dws); - - /* - * Try to detect the FIFO depth if not set by interface driver, - * the depth could be from 2 to 32 from HW spec - */ - if (!dws->fifo_len) { - u32 fifo; - for (fifo = 2; fifo <= 31; fifo++) { - rk2818_writew(dws, SPIM_TXFTLR, fifo); - if (fifo != rk2818_readw(dws, SPIM_TXFTLR)) - break; - } - - dws->fifo_len = (fifo == 31) ? 0 : fifo; - rk2818_writew(dws, SPIM_TXFTLR, 0); - } -} - -/* cpufreq driver support */ -#ifdef CONFIG_CPU_FREQ - -static int rk2818_spim_cpufreq_transition(struct notifier_block *nb, unsigned long val, void *data) -{ - struct rk2818_spi *info; - unsigned long newclk; - - info = container_of(nb, struct rk2818_spi, freq_transition); - newclk = clk_get_rate(info->clock_spim); - - return 0; -} - -static inline int rk2818_spim_cpufreq_register(struct rk2818_spi *info) -{ - info->freq_transition.notifier_call = rk2818_spim_cpufreq_transition; - - return cpufreq_register_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER); -} - -static inline void rk2818_spim_cpufreq_deregister(struct rk2818_spi *info) -{ - cpufreq_unregister_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER); -} - -#else -static inline int rk2818_spim_cpufreq_register(struct rk2818_spi *info) -{ - return 0; -} - -static inline void rk2818_spim_cpufreq_deregister(struct rk2818_spi *info) -{ -} -#endif -static int __init rk2818_spim_probe(struct platform_device *pdev) -{ - struct resource *regs; - struct rk2818_spi *dws; - struct spi_master *master; - int irq; - int ret; - struct rk2818_spi_platform_data *pdata = pdev->dev.platform_data; - - if (pdata && pdata->io_init) { - ret = pdata->io_init(pdata->chipselect_gpios, pdata->num_chipselect); - if (ret) { - return -ENXIO; - } - } - - regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!regs) - return -ENXIO; - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; - /* setup spi core then atmel-specific driver state */ - ret = -ENOMEM; - master = spi_alloc_master(&pdev->dev, sizeof *dws); - if (!master) { - ret = -ENOMEM; - goto exit; - } - platform_set_drvdata(pdev, master); - dws = spi_master_get_devdata(master); - dws->clock_spim = clk_get(&pdev->dev, "spi"); - clk_enable(dws->clock_spim); - if (IS_ERR(dws->clock_spim)) - return PTR_ERR(dws->clock_spim); - dws->regs = ioremap(regs->start, (regs->end - regs->start) + 1); - if (!dws->regs){ - release_mem_region(regs->start, (regs->end - regs->start) + 1); - return -EBUSY; - } - dws->irq = irq; - dws->master = master; - dws->type = SSI_MOTO_SPI; - dws->prev_chip = NULL; - dws->dma_inited = 1; ///0; - ///dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60); - ret = request_irq(dws->irq, rk2818_spi_irq, 0, - "rk2818_spim", dws); - if (ret < 0) { - dev_err(&master->dev, "can not get IRQ\n"); - goto err_free_master; - } - master->mode_bits = SPI_CPOL | SPI_CPHA; - master->bus_num = pdev->id; - master->num_chipselect = pdata->num_chipselect; - master->dev.platform_data = pdata; - master->cleanup = rk2818_spi_cleanup; - master->setup = rk2818_spi_setup; - #if defined(QUICK_TRANSFER) - master->transfer = rk2818_spi_quick_transfer; - #else - master->transfer = rk2818_spi_transfer; - #endif - - dws->pdev = pdev; - /* Basic HW init */ - spi_hw_init(dws); - /* Initial and start queue */ - ret = init_queue(dws); - if (ret) { - dev_err(&master->dev, "problem initializing queue\n"); - goto err_diable_hw; - } - ret = start_queue(dws); - if (ret) { - dev_err(&master->dev, "problem starting queue\n"); - goto err_diable_hw; - } - spi_master_set_devdata(master, dws); - ret = spi_register_master(master); - if (ret) { - dev_err(&master->dev, "problem registering spi master\n"); - goto err_queue_alloc; - } - - ret =rk2818_spim_cpufreq_register(dws); - if (ret < 0) { - printk(KERN_ERR"rk2818 spim failed to init cpufreq support\n"); - goto err_queue_alloc; - } - printk(KERN_INFO "rk2818_spim: driver initialized\n"); - mrst_spi_debugfs_init(dws); - return 0; - -err_queue_alloc: - destroy_queue(dws); -err_diable_hw: - spi_enable_chip(dws, 0); - free_irq(dws->irq, dws); -err_free_master: - spi_master_put(master); - iounmap(dws->regs); -exit: - return ret; -} - -static void __exit rk2818_spim_remove(struct platform_device *pdev) -{ - struct spi_master *master = platform_get_drvdata(pdev); - struct rk2818_spi *dws = spi_master_get_devdata(master); - int status = 0; - - if (!dws) - return; - rk2818_spim_cpufreq_deregister(dws); - mrst_spi_debugfs_remove(dws); - - /* Remove the queue */ - status = destroy_queue(dws); - if (status != 0) - dev_err(&dws->master->dev, "rk2818_spi_remove: workqueue will not " - "complete, message memory not freed\n"); - clk_put(dws->clock_spim); - clk_disable(dws->clock_spim); - spi_enable_chip(dws, 0); - /* Disable clk */ - spi_set_clk(dws, 0); - free_irq(dws->irq, dws); - - /* Disconnect from the SPI framework */ - spi_unregister_master(dws->master); - iounmap(dws->regs); -} - - -#ifdef CONFIG_PM - -static int rk2818_spim_suspend(struct platform_device *pdev, pm_message_t mesg) -{ - struct spi_master *master = platform_get_drvdata(pdev); - struct rk2818_spi *dws = spi_master_get_devdata(master); - struct rk2818_spi_platform_data *pdata = pdev->dev.platform_data; - int status; - - status = stop_queue(dws); - if (status != 0) - return status; - clk_disable(dws->clock_spim); - if (pdata && pdata->io_fix_leakage_bug) - { - pdata->io_fix_leakage_bug( ); - } - return 0; -} - -static int rk2818_spim_resume(struct platform_device *pdev) -{ - struct spi_master *master = platform_get_drvdata(pdev); - struct rk2818_spi *dws = spi_master_get_devdata(master); - struct rk2818_spi_platform_data *pdata = pdev->dev.platform_data; - int ret; - - clk_enable(dws->clock_spim); - spi_hw_init(dws); - ret = start_queue(dws); - if (ret) - dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret); - if (pdata && pdata->io_resume_leakage_bug) - { - pdata->io_resume_leakage_bug( ); - } - return ret; -} - -#else -#define rk2818_spim_suspend NULL -#define rk2818_spim_resume NULL -#endif - -static struct platform_driver rk2818_platform_spim_driver = { - .remove = __exit_p(rk2818_spim_remove), - .driver = { - .name = "rk2818_spim", - .owner = THIS_MODULE, - }, - .suspend = rk2818_spim_suspend, - .resume = rk2818_spim_resume, -}; - -static int __init rk2818_spim_init(void) -{ - int ret; - ret = platform_driver_probe(&rk2818_platform_spim_driver, rk2818_spim_probe); - return ret; -} - -static void __exit rk2818_spim_exit(void) -{ - platform_driver_unregister(&rk2818_platform_spim_driver); -} - -subsys_initcall(rk2818_spim_init); -module_exit(rk2818_spim_exit); - -MODULE_AUTHOR("lhh lhh@rock-chips.com"); -MODULE_DESCRIPTION("Rockchip RK2818 spim port driver"); -MODULE_LICENSE("GPL");; - diff --git a/drivers/spi/rk2818_spim.h b/drivers/spi/rk2818_spim.h deleted file mode 100755 index 0912245eb9fb..000000000000 --- a/drivers/spi/rk2818_spim.h +++ /dev/null @@ -1,217 +0,0 @@ -/* drivers/spi/rk2818_spim.h - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __DRIVERS_SPIM_RK2818_HEADER_H -#define __DRIVERS_SPIM_RK2818_HEADER_H -#include - -/* Bit fields in CTRLR0 */ -#define SPI_DFS_OFFSET 0 - -#define SPI_FRF_OFFSET 4 -#define SPI_FRF_SPI 0x0 -#define SPI_FRF_SSP 0x1 -#define SPI_FRF_MICROWIRE 0x2 -#define SPI_FRF_RESV 0x3 - -#define SPI_MODE_OFFSET 6 -#define SPI_SCPH_OFFSET 6 -#define SPI_SCOL_OFFSET 7 -#define SPI_TMOD_OFFSET 8 -#define SPI_TMOD_TR 0x0 /* xmit & recv */ -#define SPI_TMOD_TO 0x1 /* xmit only */ -#define SPI_TMOD_RO 0x2 /* recv only */ -#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */ - -#define SPI_SLVOE_OFFSET 10 -#define SPI_SRL_OFFSET 11 -#define SPI_CFS_OFFSET 12 - -/* Bit fields in SR, 7 bits */ -#define SR_MASK 0x7f /* cover 7 bits */ -#define SR_BUSY (1 << 0) -#define SR_TF_NOT_FULL (1 << 1) -#define SR_TF_EMPT (1 << 2) -#define SR_RF_NOT_EMPT (1 << 3) -#define SR_RF_FULL (1 << 4) -#define SR_TX_ERR (1 << 5) -#define SR_DCOL (1 << 6) - -/* Bit fields in ISR, IMR, RISR, 7 bits */ -#define SPI_INT_TXEI (1 << 0) -#define SPI_INT_TXOI (1 << 1) -#define SPI_INT_RXUI (1 << 2) -#define SPI_INT_RXOI (1 << 3) -#define SPI_INT_RXFI (1 << 4) -#define SPI_INT_MSTI (1 << 5) - -/* TX RX interrupt level threshhold, max can be 256 */ -#define SPI_INT_THRESHOLD 32 - -#define SPIM_CTRLR0 0x0000 -#define SPIM_CTRLR1 0x0004 -#define SPIM_SPIENR 0x0008 -#define SPIM_MWCR 0x000c -#define SPIM_SER 0x0010 -#define SPIM_BAUDR 0x0014 -#define SPIM_TXFTLR 0x0018 -#define SPIM_RXFTLR 0x001c -#define SPIM_TXFLR 0x0020 -#define SPIM_RXFLR 0x0024 -#define SPIM_SR 0x0028 -#define SPIM_IMR 0x002c -#define SPIM_ISR 0x0030 -#define SPIM_RISR 0x0034 -#define SPIM_TXOICR 0x0038 -#define SPIM_RXOICR 0x003c -#define SPIM_RXUICR 0x0040 -#define SPIM_MSTICR 0x0044 -#define SPIM_ICR 0x0048 -#define SPIM_DMACR 0x004c -#define SPIM_DMATDLR 0x0050 -#define SPIM_DMARDLR 0x0054 -#define SPIM_IDR0 0x0058 -#define SPIM_COMP_VERSION 0x005c -#define SPIM_DR0 0x0060 - -enum rk2818_ssi_type { - SSI_MOTO_SPI = 0, - SSI_TI_SSP, - SSI_NS_MICROWIRE, -}; - -struct rk2818_spi { - struct spi_master *master; - struct spi_device *cur_dev; - enum rk2818_ssi_type type; - - void __iomem *regs; - unsigned long paddr; - u32 iolen; - int irq; - u32 fifo_len; /* depth of the FIFO buffer */ - struct clk *clock_spim; /* clk apb */ - struct platform_device *pdev; - - /* Driver message queue */ - struct workqueue_struct *workqueue; - struct work_struct pump_messages; - spinlock_t lock; - struct list_head queue; - int busy; - int run; - - /* Message Transfer pump */ - struct tasklet_struct pump_transfers; - - /* Current message transfer state info */ - struct spi_message *cur_msg; - struct spi_transfer *cur_transfer; - struct chip_data *cur_chip; - struct chip_data *prev_chip; - size_t len; - void *tx; - void *tx_end; - void *rx; - void *rx_end; - int dma_mapped; - dma_addr_t rx_dma; - dma_addr_t tx_dma; - size_t rx_map_len; - size_t tx_map_len; - u8 n_bytes; /* current is a 1/2 bytes op */ - u8 max_bits_per_word; /* maxim is 16b */ - u32 dma_width; - int cs_change; - int (*write)(struct rk2818_spi *dws); - int (*read)(struct rk2818_spi *dws); - irqreturn_t (*transfer_handler)(struct rk2818_spi *dws); - void (*cs_control)(struct rk2818_spi *dws, u32 cs, u8 flag); - - /* Dma info */ - int dma_inited; - struct dma_chan *txchan; - struct dma_chan *rxchan; - int txdma_done; - int rxdma_done; - u64 tx_param; - u64 rx_param; - struct device *dma_dev; - dma_addr_t dma_addr; - - /* Bus interface info */ - void *priv; -#ifdef CONFIG_DEBUG_FS - struct dentry *debugfs; -#endif -#ifdef CONFIG_CPU_FREQ - struct notifier_block freq_transition; -#endif -}; - -#define rk2818_readl(dw, off) \ - __raw_readl(dw->regs + off) -#define rk2818_writel(dw,off,val) \ - __raw_writel(val, dw->regs + off) -#define rk2818_readw(dw, off) \ - __raw_readw(dw->regs + off) -#define rk2818_writew(dw,off,val) \ - __raw_writel(val, dw->regs + off) - -static inline void spi_enable_chip(struct rk2818_spi *dws, int enable) -{ - rk2818_writel(dws, SPIM_SPIENR, (enable ? 1 : 0)); -} - -static inline void spi_set_clk(struct rk2818_spi *dws, u16 div) -{ - rk2818_writel(dws, SPIM_BAUDR, div); -} - -/* Disable IRQ bits */ -static inline void spi_mask_intr(struct rk2818_spi *dws, u32 mask) -{ - u32 new_mask; - - new_mask = rk2818_readl(dws, SPIM_IMR) & ~mask; - rk2818_writel(dws, SPIM_IMR, new_mask); -} - -/* Enable IRQ bits */ -static inline void spi_umask_intr(struct rk2818_spi *dws, u32 mask) -{ - u32 new_mask; - - new_mask = rk2818_readl(dws, SPIM_IMR) | mask; - rk2818_writel(dws, SPIM_IMR, new_mask); -} - -//spi transfer mode add by lyx -#define RK2818_SPI_HALF_DUPLEX 0 -#define RK2818_SPI_FULL_DUPLEX 1 - -/* - * Each SPI slave device to work with rk2818_api controller should - * has such a structure claiming its working mode (PIO/DMA etc), - * which can be save in the "controller_data" member of the - * struct spi_device - */ -struct rk2818_spi_chip { - u8 transfer_mode;/*full or half duplex*/ - u8 poll_mode; /* 0 for contoller polling mode */ - u8 type; /* SPI/SSP/Micrwire */ - u8 enable_dma; - void (*cs_control)(struct rk2818_spi *dws, u32 cs, u8 flag); -}; - -#endif /* __DRIVERS_SPIM_RK2818_HEADER_H */ diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index 35fb8174dc1a..4b415577350e 100755 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -123,12 +123,6 @@ source "drivers/staging/sep/Kconfig" source "drivers/staging/iio/Kconfig" -source "drivers/staging/rk2818/rk2818_dsp/Kconfig" - -source "drivers/staging/rk2818/rk1000_control/Kconfig" - -source "drivers/staging/rk2818/rk2818_power/Kconfig" - source "drivers/staging/rk29/vivante/Kconfig" source "drivers/staging/rk29/ipp/Kconfig" endif # !STAGING_EXCLUDE_BUILD diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index a8951fb6bf76..2b630f9e31b0 100755 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -43,9 +43,5 @@ obj-$(CONFIG_VME_BUS) += vme/ obj-$(CONFIG_RAR_REGISTER) += rar/ obj-$(CONFIG_DX_SEP) += sep/ obj-$(CONFIG_IIO) += iio/ -obj-$(CONFIG_RK2818_DSP) += rk2818/rk2818_dsp/ -obj-$(CONFIG_RK1000_CONTROL) += rk2818/rk1000_control/ -obj-$(CONFIG_RK1000_TVOUT) += rk2818/rk1000_tv/ -obj-$(CONFIG_RK2818_POWER) += rk2818/rk2818_power/ -obj-$(CONFIG_VIVANTE) += rk29/vivante/ -obj-$(CONFIG_RK29_IPP) += rk29/ipp/ +obj-$(CONFIG_VIVANTE) += rk29/vivante/ +obj-$(CONFIG_RK29_IPP) += rk29/ipp/ diff --git a/drivers/staging/rk2818/rk1000_control/Kconfig b/drivers/staging/rk2818/rk1000_control/Kconfig deleted file mode 100755 index 033c8044f858..000000000000 --- a/drivers/staging/rk2818/rk1000_control/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -menu "RK1000 control" -config RK1000_CONTROL - tristate "ROCKCHIP RK1000 CONTROL" - default n - help - rk1000 control module. -endmenu diff --git a/drivers/staging/rk2818/rk1000_control/Makefile b/drivers/staging/rk2818/rk1000_control/Makefile deleted file mode 100755 index 3c56204d5848..000000000000 --- a/drivers/staging/rk2818/rk1000_control/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# -# Makefile for the rk1000 control. -# -obj-$(CONFIG_RK1000_CONTROL) += rk1000_control.o \ No newline at end of file diff --git a/drivers/staging/rk2818/rk1000_control/rk1000_control.c b/drivers/staging/rk2818/rk1000_control/rk1000_control.c deleted file mode 100755 index b6b4cf96832c..000000000000 --- a/drivers/staging/rk2818/rk1000_control/rk1000_control.c +++ /dev/null @@ -1,93 +0,0 @@ -#include -#include -#include -#include -#include - -int reg_send_data(struct i2c_client *client, const char start_reg, - const char *buf, int count, unsigned int scl_rate) -{ - int ret; - struct i2c_adapter *adap = client->adapter; - struct i2c_msg msg; - char tx_buf[count + 1]; - - tx_buf[0] = start_reg; - memcpy(tx_buf+1, buf, count); - - msg.addr = client->addr; - msg.buf = tx_buf; - msg.len = count +1; - msg.flags = client->flags; - msg.scl_rate = scl_rate; - - ret = i2c_transfer(adap, &msg, 1); - - return ret; -} -static int rk1000_control_probe(struct i2c_client *client, - const struct i2c_device_id *id) -{ - int ret; - /* reg[0x00] = 0x88, --> ADC_CON - reg[0x01] = 0x0d, --> CODEC_CON - reg[0x02] = 0x22, --> I2C_CON - reg[0x03] = 0x00, --> TVE_CON - */ - char data[4] = {0x88, 0x0d, 0x22, 0x00}; - char start_reg = 0x00; - unsigned int scl_rate = 100 * 10000; /* 100kHz */ - - #if (CONFIG_SND_SOC_RK1000) - data[1] = 0x00; - #endif - if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) - { - dev_err(&client->dev, "i2c bus does not support the rk1000_control\n"); - return -EIO; - } - mdelay(10); - ret = reg_send_data(client, start_reg, data, 4, scl_rate); - if (ret > 0) - ret = 0; - return ret; -} - -static int rk1000_control_remove(struct i2c_client *client) -{ - return 0; -} - -static const struct i2c_device_id rk1000_control_id[] = { - { "rk1000_control", 0 }, - { } -}; -MODULE_DEVICE_TABLE(i2c, rk1000_control_id); - -static struct i2c_driver rk1000_control_driver = { - .driver = { - .name = "rk1000_control", - }, - .probe = rk1000_control_probe, - .remove = rk1000_control_remove, - .id_table = rk1000_control_id, -}; - -static int __init rk1000_control_init(void) -{ - return i2c_add_driver(&rk1000_control_driver); -} - -static void __exit rk1000_control_exit(void) -{ - i2c_del_driver(&rk1000_control_driver); -} - -module_init(rk1000_control_init); -module_exit(rk1000_control_exit); - - -MODULE_DESCRIPTION("RK1000 control driver"); -MODULE_AUTHOR("Rock-chips, "); -MODULE_LICENSE("GPL"); - diff --git a/drivers/staging/rk2818/rk1000_tv/Kconfig b/drivers/staging/rk2818/rk1000_tv/Kconfig deleted file mode 100755 index 6841184bc9fa..000000000000 --- a/drivers/staging/rk2818/rk1000_tv/Kconfig +++ /dev/null @@ -1,6 +0,0 @@ -menu "RK1000 TV CONTROL" -config RK1000_TVOUT - tristate "ROCKCHIP RK1000 TV CONTROL" - depends on RK1000_CONTROL - default n -endmenu diff --git a/drivers/staging/rk2818/rk1000_tv/Makefile b/drivers/staging/rk2818/rk1000_tv/Makefile deleted file mode 100755 index 0bf612403cd3..000000000000 --- a/drivers/staging/rk2818/rk1000_tv/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the RK1000 tv control. -# - -obj-$(CONFIG_RK1000_TVOUT) += rk1000_tv.o diff --git a/drivers/staging/rk2818/rk1000_tv/rk1000_tv.c b/drivers/staging/rk2818/rk1000_tv/rk1000_tv.c deleted file mode 100755 index bd01d5ac7536..000000000000 --- a/drivers/staging/rk2818/rk1000_tv/rk1000_tv.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * rk1000_tv.c - * - * Driver for rockchip rk1000 tv control - * Copyright (C) 2009 - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rk1000_tv.h" - -#define DRV_NAME "rk1000_tvout" - -//#define DEBUG -#ifdef DEBUG -#define D(fmt, arg...) printk("<7>%s:%d: " fmt, __FILE__, __LINE__, ##arg) -#else -#define D(fmt, arg...) -#endif -#define E(fmt, arg...) printk("<3>!!!%s:%d: " fmt, __FILE__, __LINE__, ##arg) - - -static volatile int rk1000_tv_output_status = RK28_LCD; - -struct i2c_client *rk1000_tv_i2c_client = NULL; - - -int rk1000_tv_control_set_reg(struct i2c_client *client, u8 reg, u8 const buf[], u8 len) -{ - int ret; - u8 i2c_buf[8]; - struct i2c_msg msgs[1] = { - { client->addr, 0, len + 1, i2c_buf } - }; - - D("reg = 0x%.2X,value = 0x%.2X\n", reg, buf[0]); - i2c_buf[0] = reg; - memcpy(&i2c_buf[1], &buf[0], len); - - ret = i2c_transfer(client->adapter, msgs, 1); - if (ret > 0) - ret = 0; - - return ret; -} -#if 0 -int rk1000_tv_write_block(u8 addr, u8 *buf, u8 len) -{ - int i; - int ret = 0; - - if(rk1000_tv_i2c_client == NULL){ - printk("<3>rk1000_tv_i2c_client not init!\n"); - return -1; - } - - for(i=0; irk1000_tv_control_set_reg err, addr=0x%.x, val=0x%.x", addr+i, buf[i]); - break; - } - } - - return ret; -} -EXPORT_SYMBOL(rk1000_tv_write_block); - -/* drivers/video/rk28_fb.c */ -extern int win0fb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg); -extern int get_lcd_width(void); -extern int get_lcd_height(void); - -/* drivers/video/rk28_backlight.c */ -extern void rk28_bl_suspend(void *); -extern void rk28_bl_resume(void *); - -int rk28_tvout_win0fb_set_par(int x, int y, int w, int h) -{ - int ret; - struct fb_info *info = registered_fb[1]; // fb1 - struct fb_var_screeninfo var; - - var = info->var; - var.nonstd = ((y << 20) & 0xfff00000) + - ((x << 8 )& 0xfff00) + 3; //win0 ypos & xpos & format (ypos<<20 + xpos<<8 + format) // 2 - var.grayscale = ((h << 20) & 0xfff00000) + - ((w << 8) & 0xfff00) + 0; //win0 xsize & ysize; - - acquire_console_sem(); - info->flags |= FBINFO_MISC_USEREVENT; - ret = fb_set_var(info, &var); - info->flags &= ~FBINFO_MISC_USEREVENT; - release_console_sem(); - - if(ret < 0){ - E("fb_set_var err!\n"); - } - - return ret; -} - - -int rk1000_tv_set_output(int type) -{ - struct fb_info *info = registered_fb[1]; // fb1 - int ret = 0; - - D("type = %d\n", type); - - switch(type){ - case RK28_LCD: - if(rk1000_tv_output_status == RK28_LCD){ - break; - } - rk1000_tv_output_status = RK28_LCD; - win0fb_ioctl(info, 0x5001, 0); - rk28_tvout_win0fb_set_par(0, 0, get_lcd_width(), get_lcd_height()); - rk28_bl_resume((void *)0); - break; - case Cvbs_NTSC: - if(rk1000_tv_output_status == Cvbs_NTSC){ - break; - } - rk28_bl_suspend((void *)0); - rk1000_tv_output_status = Cvbs_NTSC; - win0fb_ioctl(info, 0x5001, 1); - rk28_tvout_win0fb_set_par(0, 0, 720, 480); - break; - case Cvbs_PAL: - if(rk1000_tv_output_status == Cvbs_PAL){ - break; - } - rk28_bl_suspend((void *)0); - rk1000_tv_output_status = Cvbs_PAL; - win0fb_ioctl(info, 0x5001, 2); - rk28_tvout_win0fb_set_par(0, 0, 720, 576); - break; - case Ypbpr480: - if(rk1000_tv_output_status == Ypbpr480){ - break; - } - rk28_bl_suspend((void *)0); - rk1000_tv_output_status = Ypbpr480; - win0fb_ioctl(info, 0x5001, 3); - rk28_tvout_win0fb_set_par(0, 0, 720, 480); - break; - case Ypbpr576: - if(rk1000_tv_output_status == Ypbpr576){ - break; - } - rk28_bl_suspend((void *)0); - rk1000_tv_output_status = Ypbpr576; - win0fb_ioctl(info, 0x5001, 4); - rk28_tvout_win0fb_set_par(0, 0, 720, 576); - break; - case Ypbpr720: - if(rk1000_tv_output_status == Ypbpr720){ - break; - } - rk28_bl_suspend((void *)0); - rk1000_tv_output_status = Ypbpr720; - win0fb_ioctl(info, 0x5001, 5); - rk28_tvout_win0fb_set_par(0, 0, 1280, 720); - break; - default: - ret = -EINVAL; - E("Invalid type, type = %d\n", type); - break; - } - - return ret; -} - -int rk1000_tv_get_output_status(void) -{ - return rk1000_tv_output_status; -} - -int rk1000_tv_open(struct inode *inode, struct file *filp) -{ - return 0; -} - -ssize_t rk1000_tv_write(struct file *filp, const char __user *buff, size_t count, loff_t *offp) -{ - char c = 0; - int ret; - - ret = copy_from_user(&c, buff, 1); - if(ret < 0){ - E("copy_from_user err!\n"); - return ret; - } - - rk1000_tv_set_output(c - '0'); - - return 1; -} - -int rk1000_tv_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) -{ - int ret = 0; - - switch (cmd){ - case RK1000_TV_SET_OUTPUT: - ret = rk1000_tv_set_output(arg); - break; - default: - E("unknown ioctl cmd!\n"); - ret = -EINVAL; - break; - } - - return ret; -} - -int rk1000_tv_release(struct inode *inode, struct file *filp) -{ - return 0; -} - -static struct file_operations rk1000_tv_fops = { - .owner = THIS_MODULE, - .open = rk1000_tv_open, - .write = rk1000_tv_write, - .ioctl = rk1000_tv_ioctl, - .release = rk1000_tv_release, -}; - -struct miscdevice rk1000_tv_misc_dev = { - .minor = MISC_DYNAMIC_MINOR, - .name = DRV_NAME, - .fops = &rk1000_tv_fops, -}; -#endif -static int rk1000_tv_control_remove(struct i2c_client *client) -{ - return 0; -} - -static int rk1000_tv_control_probe(struct i2c_client *client,const struct i2c_device_id *id) -{ - int rc = 0; - u8 buff; - - if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { - rc = -ENODEV; - goto failout; - } - - rk1000_tv_i2c_client = client; - - //standby tv - buff = 0x07; - rk1000_tv_control_set_reg(client, 0x03, &buff, 1); - printk("rk1000_tv_control probe ok\n"); - return 0; - -failout: - kfree(client); - return rc; -} - -static const struct i2c_device_id rk1000_tv_control_id[] = { - { DRV_NAME, 0 }, - { } -}; -MODULE_DEVICE_TABLE(i2c, rk1000_control_id); - -static struct i2c_driver rk1000_tv_control_driver = { - .driver = { - .name = DRV_NAME, - }, - .id_table = rk1000_tv_control_id, - .probe = rk1000_tv_control_probe, - .remove = rk1000_tv_control_remove, -}; - -static int __init rk1000_tv_init(void) -{ - int ret; - ret = i2c_add_driver(&rk1000_tv_control_driver); - if(ret < 0){ - E("i2c_add_driver err, ret = %d\n", ret); - goto err1; - } - - //ret = misc_register(&rk1000_tv_misc_dev); - //if(ret < 0){ - // E("misc_register err, ret = %d\n", ret); - // goto err2; - //} - - return 0; - -err2: - i2c_del_driver(&rk1000_tv_control_driver); -err1: - return ret; -} - -static void __exit rk1000_tv_exit(void) -{ - //misc_deregister(&rk1000_tv_misc_dev); - i2c_del_driver(&rk1000_tv_control_driver); -} - -module_init(rk1000_tv_init); -module_exit(rk1000_tv_exit); -/* Module information */ -MODULE_DESCRIPTION("ROCKCHIP rk1000 tv "); -MODULE_LICENSE("GPL"); - diff --git a/drivers/staging/rk2818/rk1000_tv/rk1000_tv.h b/drivers/staging/rk2818/rk1000_tv/rk1000_tv.h deleted file mode 100755 index 46e46ac513d0..000000000000 --- a/drivers/staging/rk2818/rk1000_tv/rk1000_tv.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef _RK1000_TV_H -#define _RK1000_TV_H -#include - -/******************* TVOUT ioctl CMD ************************/ -#define TVOUT_MAGIC 'T' - -#define RK1000_TV_SET_OUTPUT _IOW(TVOUT_MAGIC, 1, int) - -/******************* TVOUT OUTPUT TYPE **********************/ -#define RK28_LCD 0 -#define Cvbs_NTSC 1 -#define Cvbs_PAL 2 -#define Ypbpr480 3 -#define Ypbpr576 4 -#define Ypbpr720 5 - -int rk1000_tv_get_output_status(void); - -#endif - diff --git a/drivers/staging/rk2818/rk2818_dsp/Kconfig b/drivers/staging/rk2818/rk2818_dsp/Kconfig deleted file mode 100644 index fe5d6843ebc2..000000000000 --- a/drivers/staging/rk2818/rk2818_dsp/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -menu "DSP" -config RK2818_DSP - tristate "ROCKCHIP RK2818 DSP" - default y - help - rk28 dsp module. -endmenu diff --git a/drivers/staging/rk2818/rk2818_dsp/Makefile b/drivers/staging/rk2818/rk2818_dsp/Makefile deleted file mode 100644 index efd55bf38793..000000000000 --- a/drivers/staging/rk2818/rk2818_dsp/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# Makefile for the dsp core. -# - -obj-$(CONFIG_RK2818_DSP) += rk2818dsp.o -rk2818dsp-objs := rk2818_dsp.o queue.o \ No newline at end of file diff --git a/drivers/staging/rk2818/rk2818_dsp/queue.c b/drivers/staging/rk2818/rk2818_dsp/queue.c deleted file mode 100644 index 533b40904cd3..000000000000 --- a/drivers/staging/rk2818/rk2818_dsp/queue.c +++ /dev/null @@ -1,180 +0,0 @@ -/****************************************************************************** - * queue.c - * - * Copyright (c) 2009 Fuzhou Rockchip Co.,Ltd. - * - * DESCRIPTION: - - * Functions used to manage a FIFO queue . - * - * modification history - * -------------------- - * Keith Lin, Feb 27, 2009, Initial version - * -------------------- - ******************************************************************************/ - -#include -#include -#include -#include -#include "queue.h" - -DEFINE_SPINLOCK(lock); -unsigned long flag; - -/** - * queue initialize, - * return Queue pointer on success and NULL on error. - */ -Queue *queue_init(int32_t max_nb_item, void (*destruct)(void *, void *), void *param) -{ - Queue *q = NULL; - spin_lock_irqsave(&lock, flag); - - q = kmalloc(sizeof(*q), GFP_DMA); - if(NULL == q) { - spin_unlock_irqrestore(&lock, flag); - return NULL; - } - - q->items = kmalloc(max_nb_item * sizeof(*q->items), GFP_DMA); - - if(NULL == q->items) - { - kfree(q); - spin_unlock_irqrestore(&lock, flag); - return NULL; - } - - q->first = q->last = 0; - q->nb_item = 0; - q->max_nb_item = max_nb_item; - q->size = 0; - q->destruct = (void (*)(void *, void *))destruct; - q->param = param; - spin_unlock_irqrestore(&lock, flag); - return q; -} - -/** - * put an element to the queue, - * return 0 on success and -1 on error. - */ -int32_t queue_put(Queue *q, void *elem, int32_t size) -{ - spin_lock_irqsave(&lock, flag); - if(q->nb_item >= q->max_nb_item) { - spin_unlock_irqrestore(&lock, flag); - return -1; - } - - q->items[q->last].elem = elem; - q->items[q->last].size = size; - q->last = (q->last + 1) % q->max_nb_item; - q->size += size; - q->nb_item++; - - spin_unlock_irqrestore(&lock, flag); - return 0; -} - -/** - * get an element from the queue. - * return element pointer on success and NULL on error. - */ -void *queue_get(Queue *q) -{ - Item *item; - - spin_lock_irqsave(&lock, flag); - if(q->nb_item <= 0) { - spin_unlock_irqrestore(&lock, flag); - return NULL; - } - - item = &(q->items[q->first]); - q->first = (q->first + 1) % q->max_nb_item; - q->size -= item->size; - q->nb_item--; - - spin_unlock_irqrestore(&lock, flag); - return item->elem; -} - -/** - * Flush the queue. - */ -void queue_flush(Queue *q) -{ - spin_lock_irqsave(&lock, flag); - /* destruct all elements in the queue */ - if (NULL != q->destruct) - { - for(; q->nb_item > 0; q->nb_item --) - { - q->destruct(q->param, q->items[q->first].elem); - q->first = (q->first + 1) % q->max_nb_item; - } - } - - q->first = q->last = 0; - q->nb_item = 0; - q->size = 0; - spin_unlock_irqrestore(&lock, flag); -} - -/** - * Destroy the queue. - */ -void queue_destroy(Queue *q) -{ - spin_lock_irqsave(&lock, flag); - /* destruct all elements first */ - if (NULL != q->destruct) - { - for(; q->nb_item > 0; q->nb_item--) - { - q->destruct(q->param, q->items[q->first].elem); - q->first = (q->first + 1) % q->max_nb_item; - } - } - - if(NULL != q) - { - if(NULL != q->items) - { - kfree(q->items); - q->items = NULL; - } - kfree(q); - q = NULL; - } - spin_unlock_irqrestore(&lock, flag); -} - -int32_t queue_is_full(Queue *q) -{ - int32_t ret = 0; - spin_lock_irqsave(&lock, flag); - ret = (q->nb_item >= q->max_nb_item) ? 1 : 0; - spin_unlock_irqrestore(&lock, flag); - return ret; -} - -int32_t queue_is_empty(Queue *q) -{ - int32_t ret = 0; - spin_lock_irqsave(&lock, flag); - ret = (q->nb_item == 0); - spin_unlock_irqrestore(&lock, flag); - return ret; -} - -int32_t queue_size(Queue *q) -{ - int32_t ret = 0; - spin_lock_irqsave(&lock, flag); - ret = q->size; - spin_unlock_irqrestore(&lock, flag); - return ret; -} - diff --git a/drivers/staging/rk2818/rk2818_dsp/queue.h b/drivers/staging/rk2818/rk2818_dsp/queue.h deleted file mode 100644 index 33d691c8b341..000000000000 --- a/drivers/staging/rk2818/rk2818_dsp/queue.h +++ /dev/null @@ -1,62 +0,0 @@ -/****************************************************************************** - * queue.h - * - * Copyright (c) 2009 Fuzhou Rockchip Co.,Ltd. - * - * DESCRIPTION: - - * Functions used to manage a FIFO queue. - * - * modification history - * -------------------- - * Keith Lin, Feb 27, 2009, Initial version - * -------------------- - ******************************************************************************/ - -#ifndef QUEUE_H -#define QUEUE_H - - -typedef struct Item -{ - void *elem; - - /* data size of the element */ - int32_t size; -}Item; - -typedef struct Queue -{ - Item *items; - - /** - * first - the first item of the queue, - * last - the last item of the queue. - */ - int32_t first, last; - - /* the number of items in the queue */ - int32_t nb_item; - - /* max item number */ - int32_t max_nb_item; - - /* total data size in the queue */ - int32_t size; - - /* parameter for destruct function */ - void *param; - - /* call this call back to destruct elements before flush */ - void (*destruct)(void *, void *); -} Queue; - -Queue *queue_init(int32_t max_nb_item, void (*destruct)(void *, void *), void *param); -int32_t queue_put(Queue *q, void *elem, int32_t size); -void *queue_get(Queue *q); -void queue_flush(Queue *q); -void queue_destroy(Queue *q); -int32_t queue_is_full(Queue *q); -int32_t queue_is_empty(Queue *q); -int32_t queue_size(Queue *q); - -#endif /* QUEUE_H */ diff --git a/drivers/staging/rk2818/rk2818_dsp/rk2818_dsp.c b/drivers/staging/rk2818/rk2818_dsp/rk2818_dsp.c deleted file mode 100755 index 1552a46e69c5..000000000000 --- a/drivers/staging/rk2818/rk2818_dsp/rk2818_dsp.c +++ /dev/null @@ -1,1251 +0,0 @@ -/* drivers/staging/rk2818/rk2818_dsp/rk2818_dsp.c - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rk2818_dsp.h" -#include "queue.h" - - -#if 0 - #define dspprintk(msg...) printk(msg); -#else - #define dspprintk(msg...) -#endif - -#define CONFIG_CHIP_RK2818 1 //the 32 kernel for rk2818 - -#define USE_PLL_REG 0 //ÊÇ·ñÖ±½Ó¿ØÖÆPLL¼Ä´æÆ÷ -#define ENTER_SLOW 0 //ÊÇ·ñ²»Ê¹ÓÃDSPµÄʱºòÁ¢¼´½øÈëSLOW MODE(DSP PLL BYPASS) -#define FIXED_REQ 560 //ʹÓù̶¨ÆµÂÊÖµ, 0Ϊ½ûÓà -#define CLOSE_CLK_GATE 0 //ÊÍ·ÅDSPʱÊÇ·ñÁ¬clock gateÒ»Æð¹Øµô - -struct rk28dsp_inf { - struct miscdevice miscdev; - struct device dev; - - void *piu_base; - void *pmu_base; - void *l1_dbase; - void *l2_idbase; - void *scu_base; - void *regfile_base; - - int irq0; - int irq1; - - void *bootaddress; - void *codeprogramaddress; - void *codetableaddress; - void *codedataaddress; - - struct rk28dsp_msg rcvmsg; - Queue *rcvmsg_q; - - int cur_req; - pid_t cur_pid; - int cur_freq; - struct file *cur_file; - int req_waited; - - char req1fwname[20]; - - struct timer_list dsp_timer; - int dsp_status; - - struct clk *clk; - int clk_enabled; - - int in_suspend; -}; - -#define SCU_BASE_ADDR_VA RK2818_SCU_BASE -#define REG_FILE_BASE_ADDR_VA RK2818_REGFILE_BASE - -#define SET_BOOT_VECTOR(v) __raw_writel(v,REG_FILE_BASE_ADDR_VA + 0x18); -#define DSP_BOOT_CTRL() __raw_writel(__raw_readl(REG_FILE_BASE_ADDR_VA + 0x14) | (1<<4),REG_FILE_BASE_ADDR_VA + 0x14); -#define DSP_BOOT_CLR() __raw_writel(__raw_readl(REG_FILE_BASE_ADDR_VA + 0x14) & (~(1<<4)),REG_FILE_BASE_ADDR_VA + 0x14); - - -#define CODEC_SECTION_NO 0x5 -#define DSP_MAJOR 232 - - -/* CEVA memory map base address for ARM */ -#define DSP_BASE_ADDR RK2818_DSP_PHYS -#define DSP_L2_IMEM_BASE (RK2818_DSP_PHYS + 0x200000) -#define DSP_L2_DMEM_BASE (RK2818_DSP_PHYS + 0x400000) -#define SDRAM_BASE_ADDR RK2818_SDRAM_PHYS -#define APB_SCU_BASE 0x18018000 -#define APB_REG_FILE_BASE 0x18019000 - -#ifndef PIU_BASE_ADDR -#define PIU_BASE_ADDR (RK2818_DSP_PHYS + 0x132000) -#endif - -#ifndef PMU_BASE_ADDR -#define PMU_BASE_ADDR (RK2818_DSP_PHYS + 0x130000) -#endif - - - -#define PIU_PUT_IMASK(port,v) __raw_writel(v,inf->piu_base+PIU_IMASK_OFFSET); - -#define PIU_GET_STATUS_REPX(channel) \ - (__raw_readl(inf->piu_base + PIU_STATUS_OFFSET) & (1 << ((channel) + PIU_STATUS_R0WRS))) - -#define PIU_READ_REPX_VAL(channel) \ - __raw_readl(inf->piu_base + PIU_REPLY0_OFFSET + ((channel) << 2)) - -#define PIU_CLR_STATUS_REPX(channel) \ - __raw_writel(__raw_readl(inf->piu_base + PIU_STATUS_OFFSET) | (1 << ((channel) + PIU_STATUS_R0WRS)), \ - inf->piu_base+PIU_STATUS_OFFSET) - -#define PIU_SEND_CMD(channel, cmd) \ - __raw_writel(cmd,inf->piu_base+PIU_CMD0_OFFSET + (channel << 2)) - -#define DSP_CLOCK_ENABLE() if(!inf->clk_enabled) { clk_enable(inf->clk); inf->clk_enabled = 1; } -#define DSP_CLOCK_DISABLE() if(inf->clk_enabled) { clk_disable(inf->clk); inf->clk_enabled = 0; } - - -typedef enum _DSP_STATUS { - DS_NORMAL = 0, - DS_TOSLEEP, - DS_SLEEP, -} DSP_STATUS; - -typedef enum _DSP_PWR_CTL { - DPC_NORMAL = 0, - DPC_SLEEP, -} DSP_PWR_CTL; - - -static struct rk28dsp_inf *g_inf = NULL; - -static DECLARE_WAIT_QUEUE_HEAD(wq); -static int wq_condition = 1; - -static DECLARE_WAIT_QUEUE_HEAD(wq2); -static int wq2_condition = 0; - -static DECLARE_WAIT_QUEUE_HEAD(wq3); -static int wq3_condition = 0; - -static DECLARE_MUTEX(sem); - -static int rcv_quit = 0; - - - -void dsp_powerctl(int ctl, int arg); - -static int video_type = 0;//h264:1 ,rv40:2 , other: 0. - -//need reset reg value when finishing the video play -static void resetRegValueForVideo() -{ -#ifdef CONFIG_CHIP_RK2818 - struct rk28dsp_inf *inf = g_inf; - if(!inf) return; - //disable the AXI bus - //__raw_writel((__raw_readl(r1+0x20) & (~0x08000000)) , r1+0x20); - // - //__raw_writel((__raw_readl(r3+0x14) & (~0x20002000)) , r3+0x14); - if(video_type) - { - __raw_writel((__raw_readl(inf->scu_base+0x20) | (1<<25)) , inf->scu_base+0x20); - - if(video_type == 2) - { - //mdelay(10); - __raw_writel((__raw_readl(inf->scu_base+0x1c) | (0x400)) , inf->scu_base+0x1c); - dspprintk("close rv40 hardware advice\n"); - } - else - { - __raw_writel((__raw_readl(inf->scu_base+0x20) | (1<<20)) , inf->scu_base+0x20); - dspprintk("close h264 hardware advice\n"); - } - video_type = 0; - } -#endif - return; -} -//add by Charles Chen for test 281x play RMVB -static void setRegValueForVideo(unsigned long type) -{ -#ifdef CONFIG_CHIP_RK2818 - /* - 0x18018020 »òÉÏ 0x08000000 - 0x18018028 ÏÈ»òÉÏ 0x00000110 - µÈ´ýһЩʱ¼äÔÙÓëÉÏ ¡«0x00000110 - 0x18019018 »òÉÏ 0x00200000 - */ - struct rk28dsp_inf *inf = g_inf; - if(!inf) return; - - video_type = 1; - //axi bus - __raw_writel((__raw_readl(inf->scu_base+0x20) | (0x08000000)) , inf->scu_base+0x20); - - //mc dma - __raw_writel((__raw_readl(inf->scu_base+0x20) & ~(1<<25)) , inf->scu_base+0x20); - //printk("------->0x18018020 value 0x%08x\n",__raw_readl(r1+0x20)); - if(!type) - { - video_type ++; - //rv deblocking clock - __raw_writel((__raw_readl(inf->scu_base+0x1c) & (~0x400)) , inf->scu_base+0x1c); - mdelay(1); - - __raw_writel((__raw_readl(inf->scu_base+0x28) | (0x00000100)) , inf->scu_base+0x28); - - mdelay(5); - - __raw_writel((__raw_readl(inf->scu_base+0x28) & (~0x00000100)) , inf->scu_base+0x28); - - //rv deblocking bridge select - __raw_writel((__raw_readl(inf->regfile_base+0x14) | (0x20002000)) , inf->regfile_base+0x14); - - - dspprintk("%s this is rm 9 video\n",__func__); - } - else - { - //h264 hardware - __raw_writel((__raw_readl(inf->scu_base+0x20) & ~(1<<20)) , inf->scu_base+0x20); - dspprintk("%s this is h264 video\n",__func__); - } - -#endif - return; -} - -static int CheckDSPLIBHead(char *buff) -{ - if ((buff[0] != 'r') - || (buff[1] != 'k') - || (buff[2] != 'd') - || (buff[3] != 's') - || (buff[4] != 'p') - || (buff[5] != ' ') - || (buff[6] != 'X') - || (buff[7] != 'X')) - { - return -1; - } - else - { - return 0; - } -} - -void dsp_set_clk(int clkrate) -{ -#if USE_PLL_REG - //old: 0x01830310 300mhz 0x01820310 400mhz 0x01810290 500mhz 0x01982300 560mhz 0x01982580 600mhz - //0x00030310 300mhz 0x00020310 400mhz 0x00010290 500mhz 0x00182300 560mhz 0x00182580 600mhz - unsigned int freqreg = 0; - int cnt = 0; - - if(0==clkrate) { - /* pll set 300M */ - freqreg = ( __raw_readl(SCU_BASE_ADDR_VA+0x04)&(~0x003FFFFE) ) | 0x00030310; - __raw_writel(freqreg, SCU_BASE_ADDR_VA+0x04); - udelay(10); - - /* dsp pll disable */ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x04) | (0x01u<<22)) , SCU_BASE_ADDR_VA+0x04); - udelay(10); - return; - } - - if(clkrate) { - clkrate = FIXED_REQ ? FIXED_REQ : clkrate; - } - - /* dsp pll enable */ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x04) & (~(0x01u<<22))) , SCU_BASE_ADDR_VA+0x04); - udelay(300); //0.3ms - - /* dsp set clk */ - switch(clkrate) { - case 300: freqreg = 0x00030310; break; - case 400: freqreg = 0x00020310; break; - case 560: freqreg = 0x00182300; break; - case 600: freqreg = 0x00182580; break; - case 500: - default: freqreg = 0x00010290; break; - } - freqreg = ( __raw_readl(SCU_BASE_ADDR_VA+0x04)&(~0x003FFFFE) ) | freqreg; - __raw_writel(freqreg, SCU_BASE_ADDR_VA+0x04); - mdelay(15); - - /* wait dsp pll lock */ - while(!(__raw_readl(REG_FILE_BASE_ADDR_VA) & 0x00000100)) { - if(cnt++>30) { - printk("wait dsp pll lock ... \n"); - /* dsp pll disable */ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x04) | (0x01u<<22)) , SCU_BASE_ADDR_VA+0x04); - udelay(300); - /* dsp pll enable */ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x04) & (~(0x01u<<22))) , SCU_BASE_ADDR_VA+0x04); - udelay(300); - cnt = 0; - } - udelay(10); - } -#else - struct rk28dsp_inf *inf = g_inf; - if(clkrate) { - clkrate = FIXED_REQ ? FIXED_REQ : clkrate; - } - if(inf) { - if(inf->clk) clk_set_rate(inf->clk, clkrate*1000000); - } -#endif -} - -#ifdef CONFIG_CHIP_RK2818 -static void __tcmfunc dsp_open_power( void ) -{ - unsigned long flags; - dspprintk("enter %s!!\n",__func__); - local_irq_save(flags); - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0xc) &(~0xc)) , SCU_BASE_ADDR_VA+0xc); - ddr_pll_delay(1); //¿ªÖ®Ç°Ò²µÃ¼Ó,±ÜÃâ×ÜÏß»¹ÔÚ·ÃÎÊ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x10) & (~0x21)) , SCU_BASE_ADDR_VA+0x10); - ddr_pll_delay(24); //¹ØÖжÏʱ¼ä²»ÄÜÌ«³¤ (6000´ó¸ÅΪ1us) - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0xc) |(1<<2)) , SCU_BASE_ADDR_VA+0xc); - local_irq_restore(flags); - dspprintk("exit %s!!\n",__func__); -} -#endif - -void dsp_powerctl(int ctl, int arg) -{ - struct rk28dsp_inf *inf = g_inf; - if(!inf) return; - - switch(ctl) - { - case DPC_NORMAL: - { -#ifdef CONFIG_CHIP_RK2818 //coreµçѹ²»ÎÈʱ,dspÉϵç»áµ¼ÖÂAHBÈ¡Ö¸´íÎó,ËùÒÔdspÉϵçºóµ½Îȶ¨Æڼ䲻²Ù×÷AHB - /* dsp subsys power on 0x21*/ - dsp_open_power(); - mdelay(10); -#else - /* dsp subsys power on 0x21*/ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x10) & (~0x21)) , SCU_BASE_ADDR_VA+0x10); - mdelay(15); -#endif - /* dsp clock enable 0x12*/ - DSP_CLOCK_ENABLE(); - - /* dsp core & peripheral rst */ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x28) | 0x02000030) , SCU_BASE_ADDR_VA+0x28); - - /* dsp set clk */ - dsp_set_clk(arg); - mdelay(5); - - /* dsp peripheral urst */ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x28) & (~0x02000020)) , SCU_BASE_ADDR_VA+0x28); - mdelay(1); - - /* dsp ahb bus clock enable*/ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x24) & (~0x04)) , SCU_BASE_ADDR_VA+0x24); - -#ifdef CONFIG_CHIP_RK2818 - /* dsp master interface bridge clock enable */ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x20) & (~0x40000000)) , SCU_BASE_ADDR_VA+0x20); - /* dsp slave interface bridge clock enable */ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x20) & (~0x20000000)) , SCU_BASE_ADDR_VA+0x20); - /* dsp timer clock enable */ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x20) & (~0x10000000)) , SCU_BASE_ADDR_VA+0x20); -#endif - - /* sram arm clock enable */ - //__raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x1c) & (~0x08)) , SCU_BASE_ADDR_VA+0x1c); - /* sram dsp clock enable */ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x1c) & (~0x10)) , SCU_BASE_ADDR_VA+0x1c); - - /* set CXCLK, XHCLK, XPCLK */ - __raw_writel(0, inf->pmu_base+0x08); //CXCLK_DIV (clki:ceva) - __raw_writel(2, inf->pmu_base+0x0c); //XHCLK_DIV (ceva:hclk) - __raw_writel(1, inf->pmu_base+0x10); //XPCLK_DIV (hclk:pclk) - - } - break; - - case DPC_SLEEP: - { - /* dsp work mode :slow mode*/ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x0c) & (~0x03)) , SCU_BASE_ADDR_VA+0x0c); - /* dsp core/peripheral rest*/ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x28) | 0x02000030) , SCU_BASE_ADDR_VA+0x28); - - /* dsp ahb bus clock disable */ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x24) | (0x04)) , SCU_BASE_ADDR_VA+0x24); -#ifdef CONFIG_CHIP_RK2818 - /* dsp master interface bridge clock disable */ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x20) | (0x40000000)) , SCU_BASE_ADDR_VA+0x20); - /* dsp slave interface bridge clock disable */ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x20) | (0x20000000)) , SCU_BASE_ADDR_VA+0x20); - /* dsp timer clock disable */ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x20) | (0x10000000)) , SCU_BASE_ADDR_VA+0x20); -#endif - - /* sram arm clock disable */ - //__raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x1c) | (0x08)) , SCU_BASE_ADDR_VA+0x1c); - /* sram dsp clock disable */ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x1c) | (0x10)) , SCU_BASE_ADDR_VA+0x1c); - udelay(10); - /* dsp clock disable */ - DSP_CLOCK_DISABLE(); - - /* dsp pll close */ - dsp_set_clk(0); - - /* dsp subsys power off 0x21*/ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x10) | (0x21)) , SCU_BASE_ADDR_VA+0x10); - - /* close rv/h264 hardware advice after dsp has closed */ - udelay(10); - resetRegValueForVideo(); - } - break; - default: - break; - } -} - - -static int _down_firmware(char *fwname, struct rk28dsp_inf *inf) -{ - static char lst_fwname[20] = {0}; - int ret = 0; - - if(NULL==fwname) return -EINVAL; - if(0==strcmp(fwname, "")) return -EINVAL; - if((0==strcmp(lst_fwname, fwname)) && (DS_SLEEP!=inf->dsp_status)) { - if(1==inf->cur_req) { - dspprintk("%s already down, not redown! \n", fwname); - -#if CLOSE_CLK_GATE - /* sram dsp clock enable */ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x1c) & (~0x10)) , SCU_BASE_ADDR_VA+0x1c); - /* dsp ahb bus clock enable*/ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x24) & (~0x04)) , SCU_BASE_ADDR_VA+0x24); - /* dsp clock enable 0x12*/ - DSP_CLOCK_ENABLE(); -#endif - /* change dsp & arm to normal mode */ - inf->dsp_status = DS_NORMAL; - __raw_writel(0x5, SCU_BASE_ADDR_VA+0x0c); - return 0; - } - } - - if(DS_SLEEP==inf->dsp_status) dspprintk("dsp : sleep -> normal \n"); - inf->dsp_status = DS_NORMAL; - - dspprintk("down firmware (%s) ... \n", fwname); - { - if(0==strcmp(fwname,"rk28_rv40.rkl")) - { - setRegValueForVideo(0); - } - else if((0 == strcmp(fwname,"rk28_h264.rkl"))||(0 == strcmp(fwname,"rk28_h264_db.rkl"))) - { - setRegValueForVideo(1); - } - } - { - const struct firmware *fw; - char *buf,*code_buf; - int *pfile,*pboot; - int indexoffset,dataOffset; - int *pcodeprograml1,*pcodedatal1,*pcodetable; - int address,length,indexNo,loadNo,i,j; - int *fpIndexFile,*fpDataFile; - - __raw_writel((__raw_readl(REG_FILE_BASE_ADDR_VA + 0x10) | (0x6d8)), REG_FILE_BASE_ADDR_VA + 0x10); // 0x6d8 - dsp_powerctl(DPC_NORMAL, inf->cur_freq); - - /* down dsp boot */ - dspprintk("request_firmware ... \n"); - ret = request_firmware(&fw, "DspBoot.rkl", &inf->dev); - if (ret) { - printk(KERN_ERR "Failed to load boot image \"DspBoot.rkl\" err %d\n",ret); - return -ENOMEM; - } - buf = (char*)fw->data; - if(CheckDSPLIBHead(buf) != 0){ - printk("dsp boot head failed ! \n"); - return -ENOMEM; - } - pboot = (int*)inf->bootaddress; - indexoffset = *(buf+8+32); - dataOffset = *(buf+8+32+4); - pfile = (int *)(buf+dataOffset); - memcpy((char *)(pboot+16),(char *)(pfile),2000); /*copy boot to *pboot point*/ - SET_BOOT_VECTOR(__pa(pboot+16)); /*set dsp boot program address*/ - dspprintk("%s [%d]--%x\n",__FUNCTION__,__LINE__,__raw_readl(REG_FILE_BASE_ADDR_VA + 0x18)); - release_firmware(fw); - - /* down dsp codec */ - pcodeprograml1 = (int*)inf->codeprogramaddress; - pcodedatal1 = (int*)inf->codedataaddress; - pcodetable = (int*)inf->codetableaddress; - *(pboot+13) = __pa(pcodetable); /*set decode table address */ - *(pboot+14) = __pa(pcodeprograml1); /*set decode program address */ - *(pboot+15) = __pa(pcodedatal1); /*set decode data address */ - ret = request_firmware(&fw, fwname, &inf->dev); - if (ret) { - printk(KERN_ERR "Failed to load image \"%s\" err %d\n",fwname, ret); - return ret; - } - code_buf = (char*)fw->data; - if(CheckDSPLIBHead(code_buf) != 0){ - printk("dsp code head failed ! \n"); - return -ENOMEM; - } - - loadNo = CODEC_SECTION_NO; - i=8+16; - while ((loadNo--) != 0x0) - { - indexoffset = *((int *)(code_buf + i)); - dataOffset = *((int *)(code_buf + i + 4)); - //dspprintk("%s [%d]-- indexoffset=0x%x dataOffset=0x%x loadNo=%d \n",__FUNCTION__,__LINE__,indexoffset,dataOffset,loadNo); - i = i + 8; - if ((indexoffset != 0x0) && (dataOffset != 0x0)) - { - fpIndexFile = (int *)(code_buf + indexoffset); - fpDataFile = (int *)(code_buf + dataOffset); - indexNo = *(fpIndexFile + 1); - j = 0; - while ((indexNo--) != 0x0) - { - if(indexNo<0) break; - address = *(fpIndexFile + 2 + j*2); - length = *(fpIndexFile + 2 + 1 + j*2); - j = j + 1; - //dspprintk("%s [%d]-- address=0x%x length =0x%x indexNo=0x%x\n",__FUNCTION__,__LINE__,address,length,indexNo); - if(loadNo == (CODEC_SECTION_NO - 0x1)){ - /* Èç¹ûΪL1 data MEMµÄ´úÂë¶Î£¬¿½±´µ½¹Ì¼þµÄλÖà */ - memcpy((char *)(pcodeprograml1),(char *)(fpDataFile),length); - } else { - if (loadNo == (CODEC_SECTION_NO - 0x2)) { - /* Èç¹ûΪL1 data MEMµÄÊý¾Ý¶Î£¬¿½±´µ½¹Ì¼þµÄλÖà */ - memcpy((char *)(pcodedatal1),(char *)(fpDataFile),length); - } else { - /* Èç¹ûΪCEVAµÄÄÚ´æÇøÓò£¬ÐèÒª½øÐеØַת»» */ - if (address < SDRAM_BASE_ADDR) { -#if 1 - int k; - int *buffL2; - address = (unsigned int)inf->l2_idbase + (address - 0x200000); - buffL2 = (int *)address; - for (k=0; k<(length >> 2); k++) - { - buffL2[k] = fpDataFile[k]; - } - fpDataFile = (int *)((int)fpDataFile + length); -#else - address = (unsigned int)inf->l2_idbase + (address - 0x200000); - memcpy((char *)(address), (char *)fpDataFile, length); -#endif - } else { - /* Èç¹ûΪsdramÖУ¬ÔòÖ»ÄÜÂë±í£¬ÇÒµØÖ·Î޹أ¬ - ²¢ÇÒÖ»ÄÜÓÐÒ»¶Î(¼´µØÖ·Á¬Ðø), ·ñÔòÒýÆðϵͳ±ÀÀ£ - ÔÚÍ˳öÊÓƵ»òÕß¼ÓÔز»³É¹¦ºó£¬¼ÇµÃ°Ñ´ËBuffÊͷŵô */ - memcpy((char *)pcodetable, (char *)fpDataFile, length); - } - } - } - - } - } - } - release_firmware(fw); - } - - DSP_BOOT_CTRL(); - mdelay(10); - -#if ENTER_SLOW - /* dsp work mode :slow mode*/ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x0c) & (~0x03)) , SCU_BASE_ADDR_VA+0x0c); - mdelay(1); -#endif - - /* dsp core urst*/ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x28) & (~0x00000010)) , SCU_BASE_ADDR_VA+0x28); - mdelay(1); - - /* change dsp & arm to normal mode */ - __raw_writel(0x5, SCU_BASE_ADDR_VA+0x0c); - - strcpy(lst_fwname, fwname); - - return 0; -} - - -void dsptimer_callback(unsigned long arg) -{ - struct rk28dsp_inf *inf = g_inf; - if(!inf) return; - - switch(inf->dsp_status) - { - case DS_NORMAL: - break; - case DS_TOSLEEP: - dsp_powerctl(DPC_SLEEP, 0); - inf->dsp_status = DS_SLEEP; - dspprintk("dsp : normal -> sleep \n"); - break; - case DS_SLEEP: - break; - default: - inf->dsp_status = DS_NORMAL; - break; - } -} - - -static int dsp_mmap(struct file *file, struct vm_area_struct *vma) -{ - struct rk28dsp_inf *inf; - unsigned long vma_size = vma->vm_end - vma->vm_start; - unsigned long pageFrameNo = 0; - unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; - - if(!g_inf) return -EAGAIN; - inf = g_inf; - - switch(vma_size) - { - case 0x10000: //l1_dbase - offset += DSP_BASE_ADDR; - pageFrameNo = (offset >> PAGE_SHIFT); - //dspprintk("dsp_mmap l1_dbase \n"); - break; - case 0x400000: //l2_idbase - offset += DSP_L2_IMEM_BASE; - pageFrameNo = (offset >> PAGE_SHIFT); - //dspprintk("dsp_mmap l2_idbase \n"); - break; - case 0x600000: //dsp_base - offset += DSP_BASE_ADDR; - pageFrameNo = (offset >> PAGE_SHIFT); - //dspprintk("dsp_mmap dsp_base \n"); - break; - default: //pmu_base (0x3000) - offset += PMU_BASE_ADDR; - pageFrameNo = (offset >> PAGE_SHIFT); - //dspprintk("dsp_mmap pmu_base \n"); - break; - } - vma->vm_pgoff = pageFrameNo; - vma->vm_flags |= VM_IO|VM_RESERVED|VM_LOCKED; - vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); - - if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, vma->vm_end - vma->vm_start, vma->vm_page_prot)) { - printk("remap_pfn_range fail(vma_size=0x%08x)\n", (unsigned int)vma_size); - return -EAGAIN; - } - return 0; -} - - -static long dsp_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -{ - int ret = 0; - struct rk28dsp_req req; - struct rk28dsp_inf *inf; - - if(!g_inf) return -EAGAIN; - inf = g_inf; - - if(DSP_IOCTL_RES_REQUEST!=cmd && DSP_IOCTL_GET_TABLE_PHY!=cmd ) { - down(&sem); - if(inf->cur_pid!=current->tgid || inf->cur_file!=file) { - dspprintk("res is obtain by pid %d(cur_file=0x%08x), refuse this req(pid=%d file=0x%08x cmd=0x%08x) \n", - inf->cur_pid, (u32)inf->cur_file, current->tgid, (u32)file, cmd); - up(&sem); - return -EBUSY; - } - up(&sem); - } - - switch(cmd) - { - case DSP_IOCTL_RES_REQUEST: - if(copy_from_user(&req, (void *)arg, sizeof(struct rk28dsp_req))) - return -EFAULT; - dspprintk("DSP_IOCTL_RES_REQUEST reqno=%d(%d->%d) cur_req=%d(%d) \n", - req.reqno, current->tgid, current->pid, inf->cur_req, inf->cur_pid); - - if(0==req.reqno) return -EINVAL; - if(0==strcmp(req.fwname, "")) return -EINVAL; - - down(&sem); - if(0==inf->cur_req && !inf->req_waited) - { - inf->cur_req = req.reqno; - inf->cur_pid = current->tgid; - inf->cur_freq = req.freq; - inf->cur_file = file; - if(inf->cur_freq<24 || inf->cur_freq>600) inf->cur_freq = 500; - if(1==req.reqno) strcpy(inf->req1fwname, req.fwname); - } - else if(1==inf->cur_req && !inf->req_waited && inf->cur_req!=req.reqno) - { - inf->req_waited = 1; - wq_condition = 0; - up(&sem); - dspprintk("wait_event \n"); - wait_event(wq, wq_condition); - down(&sem); - inf->req_waited = 0; - inf->cur_req = req.reqno; - inf->cur_pid = current->tgid; - inf->cur_freq = req.freq; - inf->cur_file = file; - if(inf->cur_freq<24 || inf->cur_freq>600) inf->cur_freq = 500; - } else { - ret = -EBUSY; - } - - if(0==ret) { - del_timer(&inf->dsp_timer); - _down_firmware(req.fwname, inf); - queue_flush(inf->rcvmsg_q); - rcv_quit = 0; - wq2_condition = 0; - } - up(&sem); - break; - - case DSP_IOCTL_RES_RELEASE: - dspprintk("DSP_IOCTL_RES_RELEASE cur_req = %d \n",inf->cur_req); - down(&sem); - if(inf->cur_req) { - if(1==inf->cur_req) { - if(1==arg) strcpy(inf->req1fwname, ""); - wq_condition = 1; - wake_up(&wq); - } else { - if(strcmp(inf->req1fwname, "")) { - //_down_firmware(inf->req1fwname, inf); - } - } - - inf->cur_req = 0; - inf->cur_pid = 0; - inf->cur_file = NULL; - -#if ENTER_SLOW - /* dsp work mode :slow mode*/ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x0c) & (~0x03)) , SCU_BASE_ADDR_VA+0x0c); -#endif - -#if CLOSE_CLK_GATE - /* dsp clock disable */ - DSP_CLOCK_DISABLE(); - /* dsp ahb bus clock disable */ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x24) | (0x04)) , SCU_BASE_ADDR_VA+0x24); - /* sram dsp clock disable */ - __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x1c) | (0x10)) , SCU_BASE_ADDR_VA+0x1c); -#endif - - if(DS_SLEEP!=inf->dsp_status) { - mod_timer(&inf->dsp_timer, jiffies + 5*HZ); - inf->dsp_status = DS_TOSLEEP; - } - } - - /* force DSP_IOCTL_RECV_MSG return */ - rcv_quit = 1; - wq2_condition = 1; - wake_up(&wq2); - - up(&sem); - dspprintk("\n"); - break; - - case DSP_IOCTL_SEND_MSG: - //dspprintk("DSP_IOCTL_SEND_MSG \n"); - { - struct rk28dsp_msg msg; - if(copy_from_user(&msg, (void *)arg, sizeof(struct rk28dsp_msg))) - return -EFAULT; - - if(CODEC_MSG_ICU_CHANNEL==msg.channel) { - __raw_writel((__raw_readl(inf->pmu_base+0x043C) | 0x100), inf->pmu_base+0x043C); - } else { - PIU_SEND_CMD(msg.channel, msg.cmd); - } - } - break; - - case DSP_IOCTL_RECV_MSG: - { - struct rk28dsp_msg *pmsg = NULL; - struct rk28dsp_msg msg; - if(NULL==inf->rcvmsg_q) return -EFAULT; - - while(NULL==pmsg) - { - pmsg = queue_get(inf->rcvmsg_q); - if(pmsg) break; - - if(copy_from_user(&msg, (void *)arg, sizeof(struct rk28dsp_msg))) return -EFAULT; - if(0==msg.rcv_timeout) return -EAGAIN; - - if(-1==msg.rcv_timeout) { - if(rcv_quit) return -EAGAIN; - wait_event(wq2, wq2_condition); - wq2_condition = 0; - if(rcv_quit) return -EAGAIN; - } else { - if(rcv_quit) return -EAGAIN; - if(!wait_event_timeout(wq2, wq2_condition, msecs_to_jiffies(msg.rcv_timeout))) { wq2_condition = 0; return -EAGAIN; } - wq2_condition = 0; - if(rcv_quit) return -EAGAIN; - } - } - - if(pmsg) { - if(copy_to_user((void __user *)arg, pmsg, sizeof(struct rk28dsp_msg))) ret = -EFAULT; - kfree(pmsg); - } else { - ret = -EFAULT; - } - } - break; - - case DSP_IOCTL_SET_FREQ: - dspprintk("DSP_IOCTL_SET_FREQ: %dM!\n", (int)arg); - { - dsp_set_clk((int)arg); - inf->cur_freq = (int)arg; - if(inf->cur_freq<24 || inf->cur_freq>600) inf->cur_freq = 500; - } - break; - - case DSP_IOCTL_GET_TABLE_PHY: - { - unsigned int table_phy = __pa(inf->codetableaddress); - if(copy_to_user((void __user *)arg, (void*)&table_phy, 4)) ret = -EFAULT; - } - break; - - default: - break; - } - - return ret; -} - - -static int dsp_open(struct inode *inode, struct file *file) -{ - return 0; -} - - -static int dsp_release(struct inode *inode, struct file *file) -{ - dsp_ioctl(file, DSP_IOCTL_RES_RELEASE, 1); - return 0; -} - -static irqreturn_t rk28_dsp_irq(int irq, void *dev_id) -{ - struct platform_device *pdev = (struct platform_device*)dev_id; - struct rk28dsp_inf *inf = platform_get_drvdata(pdev); - struct rk28dsp_msg *pmsg = NULL; - unsigned int cmd = 0; - - if(NULL==inf || NULL==inf->rcvmsg_q) return IRQ_HANDLED; - - if(IRQ_NR_PIUCMD == irq) - { - if (PIU_GET_STATUS_REPX(CODEC_OUTPUT_PIU_CHANNEL)) { - cmd = PIU_READ_REPX_VAL(CODEC_OUTPUT_PIU_CHANNEL); - if(inf->cur_pid && !queue_is_full(inf->rcvmsg_q)) { - pmsg = kmalloc(sizeof(struct rk28dsp_msg), GFP_ATOMIC); - if(pmsg) { - pmsg->channel = CODEC_OUTPUT_PIU_CHANNEL; - pmsg->cmd = cmd; - pmsg->rcv_timeout = 0; - if(!queue_put(inf->rcvmsg_q, pmsg, sizeof(struct rk28dsp_msg))) { - wq2_condition = 1; - wake_up(&wq2); - } else { - printk("queue_put fail! \n"); - } - } else { - printk("kmalloc fail! \n"); - } - } - PIU_CLR_STATUS_REPX(CODEC_OUTPUT_PIU_CHANNEL); // clear status. - } - - if (PIU_GET_STATUS_REPX(CODEC_MSG_PIU_CHANNEL)) { - cmd = PIU_READ_REPX_VAL(CODEC_MSG_PIU_CHANNEL); - if(inf->cur_pid && !queue_is_full(inf->rcvmsg_q)) { - pmsg = kmalloc(sizeof(struct rk28dsp_msg), GFP_ATOMIC); - if(pmsg) { - pmsg->channel = CODEC_MSG_PIU_CHANNEL; - pmsg->cmd = cmd; - pmsg->rcv_timeout = 0; - if(!queue_put(inf->rcvmsg_q, pmsg, sizeof(struct rk28dsp_msg))) { - wq2_condition = 1; - wake_up(&wq2); - } else { - printk("queue_put fail! \n"); - } - } else { - printk("kmalloc fail! \n"); - } - } - PIU_CLR_STATUS_REPX(CODEC_MSG_PIU_CHANNEL); // clear status. - } - - if (PIU_GET_STATUS_REPX(CODEC_MSG_PIU_NEXT_CHANNEL)) { - cmd = PIU_READ_REPX_VAL(CODEC_MSG_PIU_NEXT_CHANNEL); - if(inf->cur_pid && !queue_is_full(inf->rcvmsg_q)) { - pmsg = kmalloc(sizeof(struct rk28dsp_msg), GFP_ATOMIC); - if(pmsg) { - pmsg->channel = CODEC_MSG_PIU_NEXT_CHANNEL; - pmsg->cmd = cmd; - pmsg->rcv_timeout = 0; - if(!queue_put(inf->rcvmsg_q, pmsg, sizeof(struct rk28dsp_msg))) { - wq2_condition = 1; - wake_up(&wq2); - } else { - printk("queue_put fail! \n"); - } - } else { - printk("kmalloc fail! \n"); - } - } - PIU_CLR_STATUS_REPX(CODEC_MSG_PIU_NEXT_CHANNEL); // clear status. - } - } - - - if(IRQ_NR_DSPSWI == irq) - { - __raw_writel((__raw_readl(inf->pmu_base+0x2c10) & (~0x40)), inf->pmu_base+0x2c10); // clear status. - if(inf->cur_pid && !queue_is_full(inf->rcvmsg_q)) { - pmsg = kmalloc(sizeof(struct rk28dsp_msg), GFP_ATOMIC); - if(pmsg) { - pmsg->channel = CODEC_MSG_ICU_CHANNEL; - pmsg->cmd = 0; - pmsg->rcv_timeout = 0; - if(!queue_put(inf->rcvmsg_q, pmsg, sizeof(struct rk28dsp_msg))) { - wq2_condition = 1; - wake_up(&wq2); - } else { - printk("queue_put fail! \n"); - } - } else { - printk("kmalloc fail! \n"); - } - } - } - - return IRQ_HANDLED; -} - - -struct file_operations dsp_fops = { - .open = dsp_open, - .release = dsp_release, - .mmap = dsp_mmap, - .unlocked_ioctl = dsp_ioctl, -}; - -static struct miscdevice dsp_dev ={ - .minor = DSP_MAJOR, - .name = "rk28-dsp", - .fops = &dsp_fops, -}; - -void destruct(void *param, void *elem) -{ - if(elem) kfree(elem); -} - - -static int __init dsp_drv_probe(struct platform_device *pdev) -{ - struct rk28dsp_inf *inf; - int ret = 0; - - inf = kmalloc(sizeof(struct rk28dsp_inf), GFP_KERNEL); - if(NULL==inf) { ret = -ENOMEM; goto alloc_fail; } - memset(inf, 0, sizeof(struct rk28dsp_inf)); - - inf->clk = clk_get(NULL, "dsp_pll"); - if(inf->clk) DSP_CLOCK_ENABLE(); - - inf->piu_base = (void*)ioremap(PIU_BASE_ADDR, 0x70); - inf->pmu_base = (void*)ioremap(PMU_BASE_ADDR, 0x3000); - inf->l1_dbase = (void*)ioremap(DSP_BASE_ADDR, 0x10000); - inf->l2_idbase = (void*)ioremap(DSP_L2_IMEM_BASE, 0x400000); - inf->scu_base = (void *)ioremap(APB_SCU_BASE, 0x60); - inf->regfile_base = (void *)ioremap(APB_REG_FILE_BASE, 0x60); - - inf->irq0 = pdev->resource[1].start; - inf->irq1 = pdev->resource[2].start; - - inf->bootaddress = (void*)__get_free_page(GFP_DMA); - inf->codeprogramaddress = (void*)__get_free_pages(GFP_DMA,4); - inf->codedataaddress = (void*)__get_free_pages(GFP_DMA,4); - inf->codetableaddress = (void*)__get_free_pages(GFP_DMA,6); - if(0==inf->bootaddress) { ret = -ENOMEM; printk("alloc bootaddress fail!\n"); goto alloc2_fail; } - if(0==inf->codeprogramaddress) { ret = -ENOMEM; printk("alloc codeprogramaddress fail!\n"); goto alloc2_fail; } - if(0==inf->codedataaddress) { ret = -ENOMEM; printk("alloc codedataaddress fail!\n"); goto alloc2_fail; } - if(0==inf->codetableaddress) { ret = -ENOMEM; printk("alloc codetableaddress fail!\n"); goto alloc2_fail; } - - platform_set_drvdata(pdev, inf); - inf->dev = pdev->dev; - - inf->rcvmsg_q = queue_init(256, destruct, NULL); - - ret = request_irq(inf->irq0, rk28_dsp_irq, IRQF_SHARED, "rk28-dsp", pdev); - if (ret < 0) { - goto irq0_fail; - } - - ret = request_irq(inf->irq1, rk28_dsp_irq, IRQF_SHARED, "rk28-dsp", pdev); - if (ret < 0) { - goto irq1_fail; - } - - init_MUTEX(&sem); - - init_timer(&inf->dsp_timer); - inf->dsp_timer.function = dsptimer_callback; - inf->dsp_timer.expires = jiffies + 5*HZ; - add_timer(&inf->dsp_timer); - - inf->miscdev = dsp_dev; - ret = misc_register(&(inf->miscdev)); - if(ret) { - goto reg_fail; - } - - g_inf = inf; - - dsp_powerctl(DPC_SLEEP, 0); - inf->dsp_status = DS_SLEEP; - - return 0; - -reg_fail: - if(inf->irq1) free_irq(inf->irq1, &inf->miscdev); -irq1_fail: - if(inf->irq0) free_irq(inf->irq0, &inf->miscdev); -irq0_fail: -alloc2_fail: - if(inf->bootaddress) free_page((unsigned int)inf->bootaddress); - if(inf->codeprogramaddress) free_pages((unsigned int)inf->codeprogramaddress,4); - if(inf->codedataaddress) free_pages((unsigned int)inf->codedataaddress,4); - if(inf->codetableaddress) free_pages((unsigned int)inf->codetableaddress,6); - if(inf) kfree(inf); -alloc_fail: - return ret; -} - -static int dsp_drv_remove(struct platform_device *pdev) -{ - struct rk28dsp_inf *inf = platform_get_drvdata(pdev); - dspprintk("%s [%d]\n",__FUNCTION__,__LINE__); - - misc_deregister(&(inf->miscdev)); - if(inf->irq0) free_irq(inf->irq0, &inf->miscdev); - if(inf->irq1) free_irq(inf->irq1, &inf->miscdev); - - if(inf->bootaddress) free_page((unsigned int)inf->bootaddress); - if(inf->codeprogramaddress) free_pages((unsigned int)inf->codeprogramaddress,4); - if(inf->codedataaddress) free_pages((unsigned int)inf->codedataaddress,4); - if(inf->codetableaddress) free_pages((unsigned int)inf->codetableaddress,6); - - iounmap((void __iomem *)(inf->piu_base)); - iounmap((void __iomem *)(inf->pmu_base)); - iounmap((void __iomem *)(inf->l1_dbase)); - iounmap((void __iomem *)(inf->l2_idbase)); - iounmap((void __iomem *)(inf->scu_base)); - iounmap((void __iomem *)(inf->regfile_base)); - - if(inf->clk) { - DSP_CLOCK_DISABLE(); - clk_put(inf->clk); - } - - kfree(inf); - return 0; -} - - -#if defined(CONFIG_PM) -static int dsp_drv_suspend(struct platform_device *pdev, pm_message_t state) -{ - struct rk28dsp_inf *inf = platform_get_drvdata(pdev); - - dspprintk(">>>>>> %s : %s\n", __FILE__, __FUNCTION__); - - if(!inf) { - printk("inf==0, dsp_drv_suspend fail! \n"); - return -EINVAL; - } - - if(DS_NORMAL==inf->dsp_status) return -EPERM; //DSPÕýÔÚʹÓÃÖÐ - - if(DS_SLEEP != inf->dsp_status ) { - inf->dsp_status = DS_SLEEP; - dsp_powerctl(DPC_SLEEP, 0); - dspprintk("dsp : normal -> sleep \n"); - } - - return 0; -} - -static int dsp_drv_resume(struct platform_device *pdev) -{ - struct rk28dsp_inf *inf = platform_get_drvdata(pdev); - - dspprintk(">>>>>> %s : %s\n", __FILE__, __FUNCTION__); - - if(!inf) { - printk("inf==0, dsp_drv_resume fail! \n"); - return -EINVAL; - } - - return 0; -} -#else -#define dsp_drv_suspend NULL -#define dsp_drv_resume NULL -#endif /* CONFIG_PM */ - -typedef struct android_early_suspend android_early_suspend_t; -struct android_early_suspend -{ - struct list_head link; - int level; - void (*suspend)(android_early_suspend_t *h); - void (*resume)(android_early_suspend_t *h); -}; - -static void dsp_early_suspend(android_early_suspend_t *h) -{ - dspprintk(">>>>>> %s : %s\n", __FILE__, __FUNCTION__); - if(g_inf) - { - down(&sem); - if(0==g_inf->cur_req) { - g_inf->in_suspend = 1; - up(&sem); - } else if(2==g_inf->cur_req){ //can not in early suspend - up(&sem); - return; - } else { - g_inf->in_suspend = 1; - wq3_condition = 0; - up(&sem); - wait_event(wq3, wq3_condition); - } - del_timer(&g_inf->dsp_timer); - if(DS_SLEEP != g_inf->dsp_status ) { - g_inf->dsp_status = DS_SLEEP; - dsp_powerctl(DPC_SLEEP, 0); - dspprintk("dsp : normal -> sleep \n"); - } - } -} - -static void dsp_drv_shutdown(struct platform_device *pdev) -{ - printk("%s:: shutdown dsp\n" , __func__ ); - dsp_early_suspend( NULL ); -} - -static struct platform_driver dsp_driver = { - .probe = dsp_drv_probe, - .remove = dsp_drv_remove, - .suspend = dsp_drv_suspend, - .resume = dsp_drv_resume, - .driver = { - .name = "rk28-dsp", - }, - .shutdown = dsp_drv_shutdown, -}; - -static int __init rk2818_dsp_init(void) -{ - return platform_driver_register(&dsp_driver); -} - -static void __exit rk2818_dsp_exit(void) -{ - platform_driver_unregister(&dsp_driver); -} - -subsys_initcall(rk2818_dsp_init); -module_exit(rk2818_dsp_exit); - - -/* Module information */ -MODULE_AUTHOR(" dukunming dkm@rock-chips.com"); -MODULE_DESCRIPTION("Driver for rk2818 dsp device"); -MODULE_LICENSE("GPL"); - diff --git a/drivers/staging/rk2818/rk2818_dsp/rk2818_dsp.h b/drivers/staging/rk2818/rk2818_dsp/rk2818_dsp.h deleted file mode 100755 index 421297a7f030..000000000000 --- a/drivers/staging/rk2818/rk2818_dsp/rk2818_dsp.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * drivers/staging/rk2818/rk2818_dsp/rk2818_dsp.h - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __DRIVERS_STAGING_RK2818_DSP_H -#define __DRIVERS_STAGING_RK2818_DSP_H - - -#define PIU_CMD0_OFFSET (0x30) -#define PIU_REPLY0_OFFSET (0x3c) -#define PIU_STATUS_OFFSET (0x4c) -#define PIU_IMASK_OFFSET (0x48) -#define PIU_STATUS_R0WRS 3 - - -#define CODEC_OUTPUT_PIU_CHANNEL 0 -#define CODEC_MSG_PIU_CHANNEL 1 -#define CODEC_MSG_PIU_NEXT_CHANNEL 2 -#define CODEC_MSG_ICU_CHANNEL 3 - - -#define DSP_IOCTL_RES_REQUEST (0x00800000) -#define DSP_IOCTL_RES_RELEASE (0x00800001) -#define DSP_IOCTL_SEND_MSG (0x00800002) -#define DSP_IOCTL_RECV_MSG (0x00800003) -#define DSP_IOCTL_SET_FREQ (0x00800004) -#define DSP_IOCTL_GET_TABLE_PHY (0x00800005) - -struct rk28dsp_req { - int reqno; - char fwname[20]; - int freq; -}; - -struct rk28dsp_msg { - int channel; - unsigned int cmd; - int rcv_timeout; // 0:no block -1:block >0:block with timeout(ms) -}; - -extern void rockchip_add_device_dsp(void); - -#endif /* __DRIVERS_STAGING_RK2818_DSP_H */ - diff --git a/drivers/staging/rk2818/rk2818_power/Kconfig b/drivers/staging/rk2818/rk2818_power/Kconfig deleted file mode 100644 index 2ed9f9fd83aa..000000000000 --- a/drivers/staging/rk2818/rk2818_power/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -menu "rk2818 POWER CONTROL" -config RK2818_POWER - tristate "ROCKCHIP RK2818 POWER CONTROL" - default y - help - rk2818 power operation. Here control chip power reset or power off. -endmenu diff --git a/drivers/staging/rk2818/rk2818_power/Makefile b/drivers/staging/rk2818/rk2818_power/Makefile deleted file mode 100644 index 6e957073db98..000000000000 --- a/drivers/staging/rk2818/rk2818_power/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# Makefile for the chip info core. -# - -obj-$(CONFIG_RK2818_POWER) += rk2818_power.o - diff --git a/drivers/staging/rk2818/rk2818_power/rk2818_power.c b/drivers/staging/rk2818/rk2818_power/rk2818_power.c deleted file mode 100644 index c9060f8f962e..000000000000 --- a/drivers/staging/rk2818/rk2818_power/rk2818_power.c +++ /dev/null @@ -1,101 +0,0 @@ -/* -* Copyright (C) 2010 ROCKCHIP, Inc. -* -* This software is licensed under the terms of the GNU General Public -* License version 2, as published by the Free Software Foundation, and -* may be copied, distributed, and modified under those terms. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -*/ - -#include -#include - -#include -#include -#include -#include -#include -//#include -#include -#include -#include -#include - -/*************** -* DEBUG -****************/ -#define RESTART_DEBUG -#ifdef RESTART_DEBUG -#define restart_dbg(format, arg...) \ - printk("RESTART_DEBUG : " format "\n" , ## arg) -#else -#define restart_dbg(format, arg...) do {} while (0) -#endif - -extern void(*rk2818_reboot)(void ); -extern void setup_mm_for_reboot(char mode); -//extern void cpu_proc_fin(void); - - -/* - * reset: 0 : normal reset 1: panic , 2: hard reset. - * boot : 0: normal , 1: loader , 2: maskrom , 3:recovery - * - */ -void rk2818_soft_restart( void ) -{ - scu_set_clk_for_reboot( ); // MUST slow down ddr freq - rk2818_reboot( ); // normal -} - - - -static void rk_reboot( void) -{ - local_irq_disable(); -// cpu_proc_fin(); - setup_mm_for_reboot('r'); - rk2818_soft_restart(); -} - - - - - - int rk2818_restart( int mode, const char *cmd) -{ - restart_dbg("%s->%s->%d",__FILE__,__FUNCTION__,__LINE__); - switch ( mode ) { - case 0: - rk_reboot( ); - break; - case 1: - //rk28_usb(); - //kld_reboot( 0 , type ); // loader usb - break; - case 2: - //rk28_usb(); - //kld_reboot( 0 , type ); // maksrom usb - break; - case 3: - //kld_reboot( 0 , type ); // normal and recover - break; - case 4: - *(int*)(0xfe04c0fa) = 0xe5e6e700; - break; - default: - { - void(*deader)(void) = (void(*)(void))0xc600c400; - deader(); - } - break; - } - return 0x24; -} -EXPORT_SYMBOL(rk2818_restart); - diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 2bf73ccd6c09..03016d17b9a0 100755 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -120,8 +120,7 @@ obj-$(CONFIG_FB_PNX4008_DUM) += pnx4008/ obj-$(CONFIG_FB_PNX4008_DUM_RGB) += pnx4008/ obj-$(CONFIG_FB_IBM_GXT4500) += gxt4500.o obj-$(CONFIG_FB_PS3) += ps3fb.o -obj-$(CONFIG_FB_RK2818) += rk2818_fb.o -obj-$(CONFIG_FB_RK29) += rk29_fb.o +obj-$(CONFIG_FB_RK29) += rk29_fb.o obj-$(CONFIG_FB_SM501) += sm501fb.o obj-$(CONFIG_FB_XILINX) += xilinxfb.o obj-$(CONFIG_FB_SH_MOBILE_LCDC) += sh_mobile_lcdcfb.o diff --git a/drivers/video/backlight/rk2818_backlight.c b/drivers/video/backlight/rk2818_backlight.c deleted file mode 100755 index c660d64916ce..000000000000 --- a/drivers/video/backlight/rk2818_backlight.c +++ /dev/null @@ -1,403 +0,0 @@ -/* arch/arm/mach-rockchip/rk28_backlight.c - * - * Copyright (C) 2009 Rockchip Corporation. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -//#include -#include -#include -#include -#include - -#include "rk2818_backlight.h" - -//#define RK28_PRINT -//#include - -/* - * Debug - */ -#if 0 -#define DBG(x...) printk(KERN_INFO x) -#else -#define DBG(x...) -#endif - - -#define write_pwm_reg(id, addr, val) __raw_writel(val, addr+(RK2818_PWM_BASE+id*0x10)) -#define read_pwm_reg(id, addr) __raw_readl(addr+(RK2818_PWM_BASE+id*0x10)) -#define mask_pwm_reg(id, addr, msk, val) write_dma_reg(id, addr, (val)|((~(msk))&read_dma_reg(id, addr))) - -static struct clk *pwm_clk; -static unsigned long pwm_clk_rate; -static struct backlight_device *rk2818_bl; -static int suspend_flag = 0; -#define BACKLIGHT_SEE_MINVALUE 52 - -static s32 rk2818_bl_update_status(struct backlight_device *bl) -{ - u32 divh,div_total; - struct rk2818_bl_info *rk2818_bl_info = bl->dev.parent->platform_data; - u32 id = rk2818_bl_info->pwm_id; - u32 ref = rk2818_bl_info->bl_ref; - - if (suspend_flag) - return 0; - - div_total = read_pwm_reg(id, PWM_REG_LRC); - if (ref) { - - divh = div_total*(bl->props.brightness)/BL_STEP; - DBG(">>>%s-->%d bl->props.brightness == %d, div_total == %d , divh == %d\n",__FUNCTION__,__LINE__,bl->props.brightness, div_total, divh); - } else { - DBG(">>>%s-->%d bl->props.brightness == %d\n",__FUNCTION__,__LINE__,bl->props.brightness); - if(bl->props.brightness < BACKLIGHT_SEE_MINVALUE) /*avoid can't view screen when close backlight*/ - bl->props.brightness = BACKLIGHT_SEE_MINVALUE; - divh = div_total*(BL_STEP-bl->props.brightness)/BL_STEP; - } - write_pwm_reg(id, PWM_REG_HRC, divh); - DBG("%s::========================================\n",__func__); - return 0; -} - -static s32 rk2818_bl_get_brightness(struct backlight_device *bl) -{ - u32 divh,div_total; - struct rk2818_bl_info *rk2818_bl_info = bl->dev.parent->platform_data; - u32 id = rk2818_bl_info->pwm_id; - u32 ref = rk2818_bl_info->bl_ref; - - div_total = read_pwm_reg(id, PWM_REG_LRC); - divh = read_pwm_reg(id, PWM_REG_HRC); - - DBG("%s::======================================== div_total: %d\n",__func__,div_total); - - if (ref) { - return BL_STEP*divh/div_total; - } else { - return BL_STEP-(BL_STEP*divh/div_total); - } -} - -static struct backlight_ops rk2818_bl_ops = { - .update_status = rk2818_bl_update_status, - .get_brightness = rk2818_bl_get_brightness, -}; - -#ifdef CONFIG_CPU_FREQ -static int rk2818_bl_change_clk(struct notifier_block *nb, unsigned long val, void *data) -{ - struct rk2818_bl_info *rk2818_bl_info; - u32 id; - u32 divl, divh, tmp; - u32 div_total; - int is_suspended = suspend_flag; - - if (!rk2818_bl) { - DBG(KERN_CRIT "%s: backlight device does not exist\n", __func__); - return -ENODEV; - } - - switch (val) { - case CPUFREQ_PRECHANGE: - break; - case CPUFREQ_POSTCHANGE: - if (clk_get_rate(pwm_clk) == pwm_clk_rate) - break; - pwm_clk_rate = clk_get_rate(pwm_clk); - rk2818_bl_info = rk2818_bl->dev.parent->platform_data; - id = rk2818_bl_info->pwm_id; - - - - divl = read_pwm_reg(id, PWM_REG_LRC); - divh = read_pwm_reg(id, PWM_REG_HRC); - - tmp = pwm_clk_rate / PWM_APB_PRE_DIV; - tmp >>= (1 + (PWM_DIV >> 9)); - - - div_total = (tmp) ? tmp : 1; - tmp = div_total*divh/divl; - - if (!is_suspended) - clk_disable(pwm_clk); - write_pwm_reg(id, PWM_REG_LRC, div_total); - write_pwm_reg(id, PWM_REG_HRC, tmp); - write_pwm_reg(id, PWM_REG_CNTR, 0); - if (!is_suspended) - clk_enable(pwm_clk); - break; - } - - return 0; -} -#endif -static void rk2818_delaybacklight_timer(unsigned long data) -{ - struct rk2818_bl_info *rk2818_bl_info = (struct rk2818_bl_info *)data; - u32 id, brightness; - u32 div_total, divh; - clk_enable(pwm_clk); - id = rk2818_bl_info->pwm_id; - brightness = rk2818_bl->props.brightness; - div_total = read_pwm_reg(id, PWM_REG_LRC); - if (rk2818_bl_info->bl_ref) { - divh = div_total*(brightness)/BL_STEP; - } else { - divh = div_total*(BL_STEP-brightness)/BL_STEP; - } - write_pwm_reg(id, PWM_REG_HRC, divh); - suspend_flag = 0; - DBG("%s: ======================== \n",__func__); -} - -#ifdef CONFIG_HAS_EARLYSUSPEND -static void rk2818_bl_suspend(struct early_suspend *h) -{ - struct rk2818_bl_info *rk2818_bl_info; - u32 id; - u32 div_total, divh; - - rk2818_bl_info = rk2818_bl->dev.parent->platform_data; - - id = rk2818_bl_info->pwm_id; - - div_total = read_pwm_reg(id, PWM_REG_LRC); - - if(rk2818_bl_info->bl_ref) { - divh = 0; - } else { - divh = div_total; - } - - DBG("%s: ========== suspend =============== \n",__func__); - - write_pwm_reg(id, PWM_REG_HRC, divh); - if (!suspend_flag) - clk_disable(pwm_clk); - - suspend_flag = 1; - - DBG("%s: ========================= \n",__func__); -} - - -static void rk2818_bl_resume(struct early_suspend *h) -{ - struct rk2818_bl_info *rk2818_bl_info; - // u32 id, brightness; - //u32 div_total, divh; - DBG(">>>>>> %s : %s\n", __FILE__, __FUNCTION__); - rk2818_bl_info = rk2818_bl->dev.parent->platform_data; - - rk2818_bl_info->timer.expires = jiffies + 30; - add_timer(&rk2818_bl_info->timer); - #if 0 - id = rk28_bl_info->pwm_id; - brightness = rk28_bl->props.brightness; - - div_total = read_pwm_reg(id, PWM_REG_LRC); - if (rk28_bl_info->bl_ref) { - divh = div_total*(brightness)/BL_STEP; - } else { - divh = div_total*(BL_STEP-brightness)/BL_STEP; - } - //mdelay(100); - write_pwm_reg(id, PWM_REG_HRC, divh); - - suspend_flag = 0; - - rk28printk("%s: ======================== \n",__func__); - #endif -} - -static struct early_suspend bl_early_suspend; -#endif - -static int rk2818_backlight_probe(struct platform_device *pdev) -{ - int ret = 0; - struct rk2818_bl_info *rk2818_bl_info = pdev->dev.platform_data; - u32 id = rk2818_bl_info->pwm_id; - u32 divh, div_total; - - DBG("%s::=======================================\n",__func__); - - if (rk2818_bl) { - DBG(KERN_CRIT "%s: backlight device register has existed \n", - __func__); - return -EEXIST; - } - - rk2818_bl = backlight_device_register("rk28_bl", &pdev->dev, NULL, &rk2818_bl_ops); - if (!rk2818_bl) { - DBG(KERN_CRIT "%s: backlight device register error\n", - __func__); - return -ENODEV; - } - - if (!pwm_clk) - pwm_clk = clk_get(NULL, "pwm"); - if (!pwm_clk || IS_ERR(pwm_clk)) { - printk(KERN_ERR "failed to get pwm clock source\n"); - return -ENODEV; - } - pwm_clk_rate = clk_get_rate(pwm_clk); - div_total = pwm_clk_rate / PWM_APB_PRE_DIV; - - - - div_total >>= (1 + (PWM_DIV >> 9)); - div_total = (div_total) ? div_total : 1; - - /// if(rk2818_bl_info->bl_ref) { - /// divh = 0; - /// } else { - divh = div_total / 2; - // } - - /*init timer to dispose workqueue */ - setup_timer(&rk2818_bl_info->timer, rk2818_delaybacklight_timer, (unsigned long)rk2818_bl_info); - -#ifdef CONFIG_CPU_FREQ - rk2818_bl_info->freq_transition.notifier_call = rk2818_bl_change_clk; - cpufreq_register_notifier(&rk2818_bl_info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER); -#endif - -// clk_disable(pwm_clk); - write_pwm_reg(id, PWM_REG_CTRL, PWM_DIV|PWM_RESET); - write_pwm_reg(id, PWM_REG_LRC, div_total); - write_pwm_reg(id, PWM_REG_HRC, divh); - write_pwm_reg(id, PWM_REG_CNTR, 0x0); - write_pwm_reg(id, PWM_REG_CTRL, PWM_DIV|PWM_ENABLE|PWM_TIME_EN); - clk_enable(pwm_clk); - - rk2818_bl->props.power = FB_BLANK_UNBLANK; - rk2818_bl->props.fb_blank = FB_BLANK_UNBLANK; - rk2818_bl->props.max_brightness = BL_STEP; - rk2818_bl->props.brightness = rk2818_bl_get_brightness(rk2818_bl); - -#ifdef CONFIG_HAS_EARLYSUSPEND - bl_early_suspend.suspend = rk2818_bl_suspend; - bl_early_suspend.resume = rk2818_bl_resume; - bl_early_suspend.level = ~0x0; - register_early_suspend(&bl_early_suspend); -#endif - - if (rk2818_bl_info && rk2818_bl_info->io_init) { - rk2818_bl_info->io_init(); - } - - return ret; -} - -static int rk2818_backlight_remove(struct platform_device *pdev) -{ - struct rk2818_bl_info *rk2818_bl_info = pdev->dev.platform_data; - - if (rk2818_bl) { - backlight_device_unregister(rk2818_bl); -#ifdef CONFIG_HAS_EARLYSUSPEND - unregister_early_suspend(&bl_early_suspend); -#endif -#ifdef CONFIG_CPU_FREQ - cpufreq_unregister_notifier(&rk2818_bl_info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER); -#endif - clk_disable(pwm_clk); - clk_put(pwm_clk); - if (rk2818_bl_info && rk2818_bl_info->io_deinit) { - rk2818_bl_info->io_deinit(); - } - return 0; - } else { - DBG(KERN_CRIT "%s: no backlight device has registered\n", - __func__); - return -ENODEV; - } -} -static void rk2818_backlight_shutdown(struct platform_device *pdev) -{ - - u32 divh,div_total; - struct rk2818_bl_info *rk2818_bl_info = pdev->dev.platform_data; - u32 id = rk2818_bl_info->pwm_id; - u32 brightness; - brightness = rk2818_bl->props.brightness; - brightness/=2; - div_total = read_pwm_reg(id, PWM_REG_LRC); - - if (rk2818_bl_info->bl_ref) { - divh = div_total*(brightness)/BL_STEP; - } else { - divh = div_total*(BL_STEP-brightness)/BL_STEP; - } - write_pwm_reg(id, PWM_REG_HRC, divh); - //printk("divh=%d\n",divh); - mdelay(100); - - brightness/=2; - if (rk2818_bl_info->bl_ref) { - divh = div_total*(brightness)/BL_STEP; - } else { - divh = div_total*(BL_STEP-brightness)/BL_STEP; - } - //printk("------------rk28_backlight_shutdown mdelay----------------------------\n"); - write_pwm_reg(id, PWM_REG_HRC, divh); - mdelay(100); - /*set PF1=1 PF2=1 for close backlight*/ - - if(rk2818_bl_info->bl_ref) { - divh = 0; - } else { - divh = div_total; - } - write_pwm_reg(id, PWM_REG_HRC, divh); - -} - -static struct platform_driver rk2818_backlight_driver = { - .probe = rk2818_backlight_probe, - .remove = rk2818_backlight_remove, - .driver = { - .name = "rk2818_backlight", - .owner = THIS_MODULE, - }, - .shutdown=rk2818_backlight_shutdown, -}; - - -static int __init rk2818_backlight_init(void) -{ - DBG("%s::========================================\n",__func__); - platform_driver_register(&rk2818_backlight_driver); - return 0; -} -//rootfs_initcall(rk2818_backlight_init); - -late_initcall(rk2818_backlight_init); -//module_init(rk28_backlight_init); diff --git a/drivers/video/rk2818_fb.c b/drivers/video/rk2818_fb.c deleted file mode 100755 index 41ab0a983baf..000000000000 --- a/drivers/video/rk2818_fb.c +++ /dev/null @@ -1,2585 +0,0 @@ -/* - * drivers/video/rk2818_fb.c - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -#include -#include -#include - -#include "rk2818_fb.h" - -#ifdef CONFIG_PM -#include -#endif - -#include -#include -#include -#include -//#include - -#include "./display/screen/screen.h" - - -#define WIN1_USE_DOUBLE_BUF 1 //win1 use double buf to accelerate display -#define CURSOR_BUF_SIZE 256 //RK2818 cursor need 256B buf - -#if 0 - #define fbprintk(msg...) printk(msg); -#else - #define fbprintk(msg...) -#endif - - -#if 0 - #define fbprintk2(msg...) printk(msg); -#else - #define fbprintk2(msg...) -#endif - -#define LcdReadBit(inf, addr, msk) ((inf->regbak.addr=inf->preg->addr)&(msk)) -#define LcdWrReg(inf, addr, val) inf->preg->addr=inf->regbak.addr=(val) -#define LcdRdReg(inf, addr) (inf->preg->addr) -#define LcdSetBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) |= (msk)) -#define LcdClrBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) &= ~(msk)) -#define LcdSetRegBit(inf, addr, msk) inf->preg->addr=((inf->preg->addr) |= (msk)) -#define LcdMskReg(inf, addr, msk, val) (inf->regbak.addr)&=~(msk); inf->preg->addr=(inf->regbak.addr|=(val)) - - -#define IsMcuLandscape() ((SCREEN_MCU==inf->cur_screen->type) && (0==inf->mcu_scandir)) -#define IsMcuUseFmk() ( (2==inf->cur_screen->mcu_usefmk) || (1==inf->cur_screen->mcu_usefmk)) - -#define CalScaleW1(x, y) (u32)( ((u32)x*0x1000)/y) -#define CalScaleDownW0(x, y) (u32)( (x>=y) ? ( ((u32)x*0x1000)/y) : (0x1000) ) -#define CalScaleUpW0(x, y) (u32)( (x<=y) ? ( ((u32)x*0x1000)/y) : (0x1000) ) - -struct rk28fb_rgb { - struct fb_bitfield red; - struct fb_bitfield green; - struct fb_bitfield blue; - struct fb_bitfield transp; -}; - -static struct rk28fb_rgb def_rgb_16 = { - red: { offset: 11, length: 5, }, - green: { offset: 5, length: 6, }, - blue: { offset: 0, length: 5, }, - transp: { offset: 0, length: 0, }, -}; - -struct win0_par { - u32 refcount; - u32 pseudo_pal[16]; - u32 y_offset; - u32 uv_offset; - - u32 odd_y_offset; - u32 odd_uv_offset; - u32 odd_nxt_y_offset; - u32 odd_nxt_uv_offset; - u32 even_y_offset; - u32 even_uv_offset; - u32 even_nxt_y_offset; - u32 even_nxt_uv_offset; - - u8 par_seted; - u8 addr_seted; -}; - -struct win1_par { - u32 refcount; - u32 pseudo_pal[16]; - int lstblank; -}; - -struct rk2818fb_inf { - struct fb_info *win0fb; - struct fb_info *win1fb; - - void __iomem *reg_vir_base; // virtual basic address of lcdc register - u32 reg_phy_base; // physical basic address of lcdc register - u32 len; // physical map length of lcdc register - - struct clk *clk; - struct clk *dclk; //lcdc dclk - struct clk *dclk_parent; //lcdc dclk divider frequency source - struct clk *dclk_divider; //lcdc demodulator divider frequency - struct clk *clk_share_mem; //lcdc share memory frequency - unsigned long dclk_rate; - - /* lcdc reg base address and backup reg */ - LCDC_REG *preg; - LCDC_REG regbak; - - int in_suspend; - - /* variable used in mcu panel */ - int mcu_needflush; - int mcu_isrcnt; - u16 mcu_scandir; - struct timer_list mcutimer; - int mcu_status; - u8 mcu_fmksync; - int mcu_usetimer; - int mcu_stopflush; - - /* external memery */ - char __iomem *screen_base2; - __u32 smem_len2; - unsigned long smem_start2; - - char __iomem *cursor_base; /* cursor Virtual address*/ - __u32 cursor_size; /* Amount of ioremapped VRAM or 0 */ - unsigned long cursor_start; - - struct rk28fb_screen lcd_info; - struct rk28fb_screen tv_info[5]; - struct rk28fb_screen hdmi_info[2]; - struct rk28fb_screen *cur_screen; -#ifdef CONFIG_CPU_FREQ - struct notifier_block freq_transition; -#endif - -}; - -typedef enum _TRSP_MODE -{ - TRSP_CLOSE = 0, - TRSP_FMREG, - TRSP_FMREGEX, - TRSP_FMRAM, - TRSP_FMRAMEX, - TRSP_MASK, - TRSP_INVAL -} TRSP_MODE; - - -struct platform_device *g_pdev = NULL; -static int win1fb_set_par(struct fb_info *info); - -#if 0 -#define CHK_SUSPEND(inf) \ - if(inf->in_suspend) { \ - fbprintk(">>>>>> fb is in suspend! return! \n"); \ - return -EPERM; \ - } -#else -#define CHK_SUSPEND(inf) -#endif - -static DECLARE_WAIT_QUEUE_HEAD(wq); -static int wq_condition = 0; - -void set_lcd_pin(struct platform_device *pdev, int enable) -{ - int ret =0; - struct rk2818fb_info *mach_info = pdev->dev.platform_data; - - unsigned display_on = mach_info->disp_on_pin; - unsigned lcd_standby = mach_info->standby_pin; - - int display_on_pol = mach_info->disp_on_value; - int lcd_standby_pol = mach_info->standby_value; - - fbprintk(">>>>>> %s : %s \n", __FILE__, __FUNCTION__); - fbprintk(">>>>>> display_on(%d) = %d \n", display_on, enable ? display_on_pol : !display_on_pol); - fbprintk(">>>>>> lcd_standby(%d) = %d \n", lcd_standby, enable ? lcd_standby_pol : !lcd_standby_pol); - - // set display_on - - if(display_on != INVALID_GPIO) - { - gpio_direction_output(display_on, 0); - gpio_set_value(display_on, enable ? display_on_pol : !display_on_pol); - } - if(lcd_standby != INVALID_GPIO) - { - gpio_direction_output(lcd_standby, 0); - gpio_set_value(lcd_standby, enable ? lcd_standby_pol : !lcd_standby_pol); - } - - return; -pin_err: - return; -} - -int mcu_do_refresh(struct rk2818fb_inf *inf) -{ - if(inf->mcu_stopflush) return 0; - - if(SCREEN_MCU!=inf->cur_screen->type) return 0; - - // use frame mark - if(IsMcuUseFmk()) - { - inf->mcu_needflush = 1; - return 0; - } - - // not use frame mark - if(LcdReadBit(inf, MCU_TIMING_CTRL, m_MCU_HOLDMODE_SELECT)) - { - if(!LcdReadBit(inf, MCU_TIMING_CTRL, m_MCU_HOLD_STATUS)) - { - inf->mcu_needflush = 1; - } - else - { - if(inf->cur_screen->refresh) inf->cur_screen->refresh(REFRESH_PRE); - inf->mcu_needflush = 0; - inf->mcu_isrcnt = 0; - LcdSetRegBit(inf, MCU_TIMING_CTRL, m_MCU_HOLDMODE_FRAME_ST); - } - } - return 0; -} - - -void mcutimer_callback(unsigned long arg) -{ - struct rk2818fb_inf *inf = platform_get_drvdata(g_pdev); - static int waitcnt = 0; - - mod_timer(&inf->mcutimer, jiffies + HZ/10); - - switch(inf->mcu_status) - { - case MS_IDLE: - inf->mcu_status = MS_MCU; - break; - case MS_MCU: - if(inf->mcu_usetimer) mcu_do_refresh(inf); - break; - case MS_EWAITSTART: - inf->mcu_status = MS_EWAITEND; - waitcnt = 0; - break; - case MS_EWAITEND: - if(0==waitcnt) { - mcu_do_refresh(inf); - } - if(waitcnt++>14) { - inf->mcu_status = MS_EEND; - } - break; - case MS_EEND: - inf->mcu_status = MS_MCU; - break; - default: - inf->mcu_status = MS_MCU; - break; - } -} - -int mcu_refresh(struct rk2818fb_inf *inf) -{ - static int mcutimer_inited = 0; - - if(SCREEN_MCU!=inf->cur_screen->type) return 0; - - if(!mcutimer_inited) - { - mcutimer_inited = 1; - init_timer(&inf->mcutimer); - inf->mcutimer.function = mcutimer_callback; - inf->mcutimer.expires = jiffies + HZ/5; - inf->mcu_status = MS_IDLE; - add_timer(&inf->mcutimer); - } - - if(MS_MCU==inf->mcu_status) mcu_do_refresh(inf); - - return 0; -} - -int mcu_ioctl(unsigned int cmd, unsigned long arg) -{ - struct rk2818fb_inf *inf = NULL; - if(!g_pdev) return -1; - - inf = dev_get_drvdata(&g_pdev->dev); - - switch(cmd) - { - case MCU_WRCMD: - LcdClrBit(inf, MCU_TIMING_CTRL, m_MCU_RS_SELECT); - LcdWrReg(inf, MCU_BYPASS_WPORT, arg); - LcdSetBit(inf, MCU_TIMING_CTRL, m_MCU_RS_SELECT); - break; - - case MCU_WRDATA: - LcdSetBit(inf, MCU_TIMING_CTRL, m_MCU_RS_SELECT); - LcdWrReg(inf, MCU_BYPASS_WPORT, arg); - break; - - case MCU_SETBYPASS: - LcdMskReg(inf, MCU_TIMING_CTRL, m_MCU_BYPASSMODE_SELECT, v_MCU_BYPASSMODE_SELECT(arg)); - LcdWrReg(inf, REG_CFG_DONE, 0x01); - break; - - default: - break; - } - - return 0; -} - -static irqreturn_t mcu_irqfmk(int irq, void *dev_id) -{ - struct platform_device *pdev = (struct platform_device*)dev_id; - struct rk2818fb_inf *inf = platform_get_drvdata(pdev); - struct rk28fb_screen *screen; - - if(!inf) return IRQ_HANDLED; - - screen = inf->cur_screen; - - if(0==screen->mcu_usefmk) { - return IRQ_HANDLED; - } - - if(inf->mcu_fmksync == 1) - return IRQ_HANDLED; - - inf->mcu_fmksync = 1; - if(inf->mcu_needflush) - { - inf->mcu_needflush = 0; - inf->mcu_isrcnt = 0; - if(inf->cur_screen->refresh) - inf->cur_screen->refresh(REFRESH_PRE); - LcdSetBit(inf, MCU_TIMING_CTRL, m_MCU_HOLDMODE_FRAME_ST); - } - inf->mcu_fmksync = 0; - - return IRQ_HANDLED; -} - -int init_lcdc(struct fb_info *info) -{ - struct rk2818fb_inf *inf = dev_get_drvdata(info->device); - u32 reg1=0, reg2=0, msk=0, clr=0; - - fbprintk(">>>>>> %s : %s \n", __FILE__, __FUNCTION__); - - // set AHB access rule and disable all windows - LcdMskReg(inf, SYS_CONFIG, - m_W1_ROLLER | m_W0_ROLLER | m_INTERIACE_EN | m_MPEG2_I2P_EN | m_W0_ROTATE | - m_W1_ENABLE |m_W0_ENABLE | m_HWC_ENABLE | m_HWC_RELOAD_EN |m_W1_INTERLACE_READ | - m_W0_INTERLACE_READ | m_STANDBY | m_W1_HWC_INCR| - m_W1_HWC_BURST | m_W0_INCR | m_W0_BURST , - v_W1_ROLLER(0) | v_W0_ROLLER(0) | v_INTERIACE_EN(0) | - v_MPEG2_I2P_EN(0) | v_W0_ROTATE(0) |v_W1_ENABLE(0) | - v_W0_ENABLE(0) | v_HWC_ENABLE(0) | v_HWC_RELOAD_EN(0) | v_W1_INTERLACE_READ(0) | - v_W0_INTERLACE_READ(0) | v_STANDBY(0) | v_W1_HWC_INCR(31) | v_W1_HWC_BURST(1) | - v_W0_INCR(31) | v_W0_BURST(1) - ); // use ahb burst32 - - // set all swap rule for every window and set water mark - reg1 = v_W0_565_RB_SWAP(0) | v_W0_YRGB_M8_SWAP(0) | - v_W0_YRGB_R_SHIFT_SWAP(0) | v_W0_CBR_R_SHIFT_SWAP(0) | v_W0_YRGB_16_SWAP(0) | - v_W0_YRGB_8_SWAP(0) | v_W0_CBR_16_SWAP(0) | v_W0_CBR_8_SWAP(0) | v_W0_YRGB_HL8_SWAP(0); - - reg2 = v_W1_565_RB_SWAP(0) | v_W1_16_SWAP(0) | v_W1_8_SWAP(0) | - v_W1_R_SHIFT_SWAP(0) | v_OUTPUT_BG_SWAP(0) | v_OUTPUT_RB_SWAP(0) | v_OUTPUT_RG_SWAP(0) | - v_DELTA_SWAP(0) | v_DUMMY_SWAP(0); - - LcdWrReg(inf, SWAP_CTRL, reg1 | reg2); - - // and mcu holdmode; and set win1 top. - LcdMskReg(inf, MCU_TIMING_CTRL, m_MCU_HOLDMODE_SELECT | m_MCU_HOLDMODE_FRAME_ST | m_MCU_BYPASSMODE_SELECT , - v_MCU_HOLDMODE_SELECT(0)| v_MCU_HOLDMODE_FRAME_ST(0) |v_MCU_BYPASSMODE_SELECT(0)); - - // disable blank out, black out, tristate out, yuv2rgb bypass - LcdMskReg(inf, BLEND_CTRL, m_W1_BLEND_EN | m_W0_BLEND_EN | m_HWC_BLEND_EN | m_W1_BLEND_FACTOR_SELECT | - m_W0_BLEND_FACTOR_SELECT | m_W0W1_OVERLAY | m_HWC_BLEND_FACTOR | m_W1_BLEND_FACTOR | m_W0_BLEND_FACTOR, - v_W1_BLEND_EN(0) | v_W0_BLEND_EN(0) | v_HWC_BLEND_EN(0) | v_W1_BLEND_FACTOR_SELECT(0) | - v_W0_BLEND_FACTOR_SELECT(0) | v_W0W1_OVERLAY(0) | v_HWC_BLEND_FACTOR(0) | v_W1_BLEND_FACTOR(0) | v_W0_BLEND_FACTOR(0) - ); - - LcdMskReg(inf, WIN0_COLOR_KEY_CTRL, m_COLORKEY_EN, v_COLORKEY_EN(0)); - LcdMskReg(inf, WIN1_COLOR_KEY_CTRL, m_COLORKEY_EN, v_COLORKEY_EN(0)); - - LcdMskReg(inf, DSP_CTRL0, m_HSYNC_POLARITY | m_VSYNC_POLARITY | m_DEN_POLARITY | m_DCLK_POLARITY | - m_COLOR_SPACE_CONVERSION | m_DITHERING_EN | m_INTERLACE_FIELD_POLARITY | - m_YUV_CLIP_MODE | m_I2P_FILTER_EN , - v_HSYNC_POLARITY(0) | v_VSYNC_POLARITY(0) | v_DEN_POLARITY(0) | v_DCLK_POLARITY(0) | v_COLOR_SPACE_CONVERSION(0) | - v_DITHERING_EN(0) | v_INTERLACE_FIELD_POLARITY(0) | v_YUV_CLIP_MODE(0) | v_I2P_FILTER_EN(0)); - - LcdMskReg(inf, DSP_CTRL1, m_BG_COLOR | m_BLANK_MODE | m_BLACK_MODE | m_W1_SD_DEFLICKER_EN | m_W1_SP_DEFLICKER_EN | - m_W0CR_SD_DEFLICKER_EN | m_W0CR_SP_DEFLICKER_EN | m_W0YRGB_SD_DEFLICKER_EN | m_W0YRGB_SP_DEFLICKER_EN, - v_BG_COLOR(0) | v_BLANK_MODE(0) | v_BLACK_MODE(0) | v_W1_SD_DEFLICKER_EN(0) | v_W1_SP_DEFLICKER_EN(0) | - v_W0CR_SD_DEFLICKER_EN(0) | v_W0CR_SP_DEFLICKER_EN(0) | v_W0YRGB_SD_DEFLICKER_EN(0) | v_W0YRGB_SP_DEFLICKER_EN(0)); - - // initialize all interrupt - clr = v_HOR_STARTCLEAR(1) | v_FRM_STARTCLEAR(1) | v_SCANNING_CLEAR(1); - - msk = v_HOR_STARTMASK(1) | v_FRM_STARTMASK(0) | v_SCANNING_MASK(1); - - LcdWrReg(inf, INT_STATUS, clr | msk); - - // let above to take effect - LcdWrReg(inf, REG_CFG_DONE, 0x01); - - return 0; -} - -void load_screen(struct fb_info *info, bool initscreen) -{ - int ret = -EINVAL; - struct rk2818fb_inf *inf = dev_get_drvdata(info->device); - struct rk28fb_screen *screen = inf->cur_screen; - u16 face = screen->face; - u16 mcu_total, mcu_rwstart, mcu_csstart, mcu_rwend, mcu_csend; - u16 right_margin = screen->right_margin, lower_margin = screen->lower_margin; - u16 x_res = screen->x_res, y_res = screen->y_res; - u32 clk_rate = 0; - u32 dclk_rate = 0; - - fbprintk(">>>>>> %s : %s \n", __FILE__, __FUNCTION__); - - // set the rgb or mcu - LcdMskReg(inf, MCU_TIMING_CTRL, m_MCU_OUTPUT_SELECT, v_MCU_OUTPUT_SELECT((SCREEN_MCU==screen->type)?(1):(0))); - - // set out format and mcu timing - mcu_total = (screen->mcu_wrperiod*150*1000)/1000000; - if(mcu_total>31) mcu_total = 31; - if(mcu_total<3) mcu_total = 3; - mcu_rwstart = (mcu_total+1)/4 - 1; - mcu_rwend = ((mcu_total+1)*3)/4 - 1; - mcu_csstart = (mcu_rwstart>2) ? (mcu_rwstart-3) : (0); - mcu_csend = (mcu_rwend>15) ? (mcu_rwend-1) : (mcu_rwend); - - fbprintk(">> mcu_total=%d, mcu_rwstart=%d, mcu_csstart=%d, mcu_rwend=%d, mcu_csend=%d \n", - mcu_total, mcu_rwstart, mcu_csstart, mcu_rwend, mcu_csend); - - LcdMskReg(inf, MCU_TIMING_CTRL, - m_MCU_CS_ST | m_MCU_CS_END| m_MCU_RW_ST | m_MCU_RW_END | - m_MCU_WRITE_PERIOD | m_MCU_HOLDMODE_SELECT | m_MCU_HOLDMODE_FRAME_ST, - v_MCU_CS_ST(mcu_csstart) | v_MCU_CS_END(mcu_csend) | v_MCU_RW_ST(mcu_rwstart) | - v_MCU_RW_END(mcu_rwend) | v_MCU_WRITE_PERIOD(mcu_total) | - v_MCU_HOLDMODE_SELECT((SCREEN_MCU==screen->type)?(1):(0)) | v_MCU_HOLDMODE_FRAME_ST(0) - ); - - // set synchronous pin polarity and data pin swap rule - LcdMskReg(inf, DSP_CTRL0, - m_DISPLAY_FORMAT | m_HSYNC_POLARITY | m_VSYNC_POLARITY | m_DEN_POLARITY | - m_DCLK_POLARITY | m_COLOR_SPACE_CONVERSION, - v_DISPLAY_FORMAT(face) | v_HSYNC_POLARITY(screen->pin_hsync) | v_VSYNC_POLARITY(screen->pin_vsync) | - v_DEN_POLARITY(screen->pin_den) | v_DCLK_POLARITY(screen->pin_dclk) | v_COLOR_SPACE_CONVERSION(0) - ); - - LcdMskReg(inf, DSP_CTRL1, m_BG_COLOR, v_BG_COLOR(0x000000) ); - - LcdMskReg(inf, SWAP_CTRL, m_OUTPUT_RB_SWAP | m_OUTPUT_RG_SWAP | m_DELTA_SWAP | m_DUMMY_SWAP, - v_OUTPUT_RB_SWAP(screen->swap_rb) | v_OUTPUT_RG_SWAP(screen->swap_rg) | v_DELTA_SWAP(screen->swap_delta) | v_DUMMY_SWAP(screen->swap_dumy)); - - // set horizontal & vertical out timing - if(SCREEN_MCU==inf->cur_screen->type) - { - right_margin = x_res/6; - } - - LcdMskReg(inf, DSP_HTOTAL_HS_END, m_BIT11LO | m_BIT11HI, v_BIT11LO(screen->hsync_len) | - v_BIT11HI(screen->hsync_len + screen->left_margin + x_res + right_margin)); - LcdMskReg(inf, DSP_HACT_ST_END, m_BIT11LO | m_BIT11HI, v_BIT11LO(screen->hsync_len + screen->left_margin + x_res) | - v_BIT11HI(screen->hsync_len + screen->left_margin)); - - - LcdMskReg(inf, DSP_VTOTAL_VS_END, m_BIT11LO | m_BIT11HI, v_BIT11LO(screen->vsync_len) | - v_BIT11HI(screen->vsync_len + screen->upper_margin + y_res + lower_margin)); - LcdMskReg(inf, DSP_VACT_ST_END, m_BIT11LO | m_BIT11HI, v_BIT11LO(screen->vsync_len + screen->upper_margin+y_res)| - v_BIT11HI(screen->vsync_len + screen->upper_margin)); - - LcdMskReg(inf, DSP_VS_ST_END_F1, m_BIT11LO | m_BIT11HI, v_BIT11LO(0) | v_BIT11HI(0)); - LcdMskReg(inf, DSP_VACT_ST_END_F1, m_BIT11LO | m_BIT11HI, v_BIT11LO(0) | v_BIT11HI(0)); - - // let above to take effect - LcdWrReg(inf, REG_CFG_DONE, 0x01); - - // set lcdc clk - if(SCREEN_MCU==screen->type) screen->pixclock = 150; //mcu fix to 150 MHz - - clk_set_parent(inf->dclk_divider, inf->dclk_parent); - clk_set_parent(inf->dclk, inf->dclk_divider); - - dclk_rate = screen->pixclock * 1000000; - - fbprintk(">>>>>> set lcdc dclk need %d HZ, clk_parent = %d hz \n ", screen->pixclock, clk_rate); - - ret = clk_set_rate(inf->dclk_divider, dclk_rate); - - if(ret) - { - printk(KERN_ERR ">>>>>> set lcdc dclk_divider faild \n "); - } - - clk_enable(inf->dclk); - clk_enable(inf->clk); - clk_enable(inf->clk_share_mem); - - // init screen panel - if(screen->init && initscreen) - { - screen->init(); - } -} -#ifdef CONFIG_CPU_FREQ -/* -* CPU clock speed change handler. We need to adjust the LCD timing -* parameters when the CPU clock is adjusted by the power management -* subsystem. -*/ -#define TO_INF(ptr,member) container_of(ptr,struct rk2818fb_inf,member) - -static int -rk2818fb_freq_transition(struct notifier_block *nb, unsigned long val, void *data) -{ - struct rk2818fb_inf *inf = TO_INF(nb, freq_transition); - struct rk28fb_screen *screen = inf->cur_screen; - u32 dclk_rate = 0; - - switch (val) - { - case CPUFREQ_PRECHANGE: - break; - case CPUFREQ_POSTCHANGE: - { - dclk_rate = screen->pixclock * 1000000; - - fbprintk(">>>>>> set lcdc dclk need %d HZ, clk_parent = %d hz \n ", screen->pixclock, dclk_rate); - - clk_set_rate(inf->dclk_divider, dclk_rate); - break; - } - } - return 0; -} -#endif - -static inline unsigned int chan_to_field(unsigned int chan, - struct fb_bitfield *bf) -{ - chan &= 0xffff; - chan >>= 16 - bf->length; - return chan << bf->offset; -} - -static int fb_setcolreg(unsigned regno, - unsigned red, unsigned green, unsigned blue, - unsigned transp, struct fb_info *info) -{ - unsigned int val; -// fbprintk(">>>>>> %s : %s \n", __FILE__, __FUNCTION__); - - switch (info->fix.visual) { - case FB_VISUAL_TRUECOLOR: - /* true-colour, use pseudo-palette */ - if (regno < 16) { - u32 *pal = info->pseudo_palette; - val = chan_to_field(red, &info->var.red); - val |= chan_to_field(green, &info->var.green); - val |= chan_to_field(blue, &info->var.blue); - pal[regno] = val; - } - break; - default: - return -1; /* unknown type */ - } - - return 0; -} - -int rk2818_set_cursor(struct fb_info *info, struct fb_cursor *cursor) -{ - struct rk2818fb_inf *inf = dev_get_drvdata(info->device); - - //fbprintk(">>>>>> %s : %s \n", __FILE__, __FUNCTION__); - - /* check not being asked to exceed capabilities */ - - if (cursor->image.width > 32) - return -EINVAL; - - if (cursor->image.height > 32) - return -EINVAL; - - if (cursor->image.depth > 1) - return -EINVAL; - - if (cursor->enable) - LcdSetBit(inf, SYS_CONFIG, m_HWC_ENABLE); - else - LcdClrBit(inf, SYS_CONFIG, m_HWC_ENABLE); - - /* set data */ - if (cursor->set & FB_CUR_SETPOS) - { - unsigned int x = cursor->image.dx; - unsigned int y = cursor->image.dy; - - if (x >= 0x800 || y >= 0x800 ) - return -EINVAL; - LcdWrReg(inf, HWC_DSP_ST, v_BIT11LO(x)|v_BIT11HI(y)); - } - - - if (cursor->set & FB_CUR_SETCMAP) - { - unsigned int bg_col = cursor->image.bg_color; - unsigned int fg_col = cursor->image.fg_color; - - fbprintk("%s: update cmap (%08x,%08x)\n", - __func__, bg_col, fg_col); - - LcdMskReg(inf, HWC_COLOR_LUT0, m_HWC_R|m_HWC_G|m_HWC_B, - v_HWC_R(info->cmap.red[bg_col]>>8) | v_HWC_G(info->cmap.green[bg_col]>>8) | v_HWC_B(info->cmap.blue[bg_col]>>8)); - - LcdMskReg(inf, HWC_COLOR_LUT2, m_HWC_R|m_HWC_G|m_HWC_B, - v_HWC_R(info->cmap.red[fg_col]>>8) | v_HWC_G(info->cmap.green[fg_col]>>8) | v_HWC_B(info->cmap.blue[fg_col]>>8)); - } - - if ((cursor->set & FB_CUR_SETSIZE || - cursor->set & (FB_CUR_SETIMAGE | FB_CUR_SETSHAPE)) - && info->screen_base && info->fix.smem_start && info->fix.smem_len) - { - /* rk2818 cursor is a 2 bpp 32x32 bitmap this routine - * clears it to transparent then combines the cursor - * shape plane with the colour plane to set the - * cursor */ - int x, y; - const unsigned char *pcol = cursor->image.data; - const unsigned char *pmsk = cursor->mask; - void __iomem *dst; - unsigned long cursor_mem_start; - unsigned char dcol = 0; - unsigned char dmsk = 0; - unsigned int op; - - dst = info->screen_base + info->fix.smem_len - CURSOR_BUF_SIZE; - cursor_mem_start = info->fix.smem_start + info->fix.smem_len - CURSOR_BUF_SIZE; - - fbprintk("%s: setting shape (%d,%d)\n", - __func__, cursor->image.width, cursor->image.height); - - memset(dst, 0, CURSOR_BUF_SIZE); - - for (y = 0; y < cursor->image.height; y++) - { - for (x = 0; x < cursor->image.width; x++) - { - if ((x % 8) == 0) { - dcol = *pcol++; - dmsk = *pmsk++; - } else { - dcol >>= 1; - dmsk >>= 1; - } - - if (dmsk & 1) { - op = (dcol & 1) ? 1 : 3; - op <<= ((x % 4) * 2); - *(u8*)(dst+(x/4)) |= op; - } - } - dst += (32*2)/8; - } - LcdSetBit(inf, SYS_CONFIG,m_HWC_RELOAD_EN); - LcdWrReg(inf, HWC_MST, cursor_mem_start); - // flush end when wq_condition=1 in mcu panel, but not in rgb panel - if(SCREEN_MCU == inf->cur_screen->type) { - wait_event_interruptible_timeout(wq, wq_condition, HZ/20); - wq_condition = 0; - } else { - wq_condition = 0; - wait_event_interruptible_timeout(wq, wq_condition, HZ/20); - } - LcdClrBit(inf, SYS_CONFIG, m_HWC_RELOAD_EN); - } - - return 0; -} - - -static int win0fb_blank(int blank_mode, struct fb_info *info) -{ - struct rk2818fb_inf *inf = dev_get_drvdata(info->device); - - fbprintk(">>>>>> %s : %s \n", __FILE__, __FUNCTION__); - - CHK_SUSPEND(inf); - - switch(blank_mode) - { - case FB_BLANK_UNBLANK: - LcdMskReg(inf, SYS_CONFIG, m_W0_ENABLE, v_W0_ENABLE(1)); - break; - default: - LcdMskReg(inf, SYS_CONFIG, m_W0_ENABLE, v_W0_ENABLE(0)); - break; - } - LcdWrReg(inf, REG_CFG_DONE, 0x01); - - mcu_refresh(inf); - return 0; -} - -static int win0fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) -{ - struct rk2818fb_inf *inf = dev_get_drvdata(info->device); - struct rk28fb_screen *screen = inf->cur_screen; - - u32 ScaleYUpY=0x1000, ScaleYDnY=0x1000; - u16 xpos = (var->nonstd>>8) & 0xfff; //offset in panel - u16 ypos = (var->nonstd>>20) & 0xfff; - u16 xsize = (var->grayscale>>8) & 0xfff; //visiable size in panel - u16 ysize = (var->grayscale>>20) & 0xfff; - u16 xlcd = screen->x_res; //size of panel - u16 ylcd = screen->y_res; - u16 yres = 0; - - if(inf->win0fb->var.rotate == 270) { - xlcd = screen->y_res; - ylcd = screen->x_res; - } - - fbprintk(">>>>>> %s : %s\n", __FILE__, __FUNCTION__); - - CHK_SUSPEND(inf); - - if( 0==var->xres_virtual || 0==var->yres_virtual || - 0==var->xres || 0==var->yres || var->xres<16 || - 0==xsize || 0==ysize || xsize<16 || - ((16!=var->bits_per_pixel)&&(32!=var->bits_per_pixel)) ) - { - printk(">>>>>> win0fb_check_var fail 1!!! \n"); - printk("0==%d || 0==%d || 0==%d || 0==%d || %d<16 \n ||0==%d || 0==%d || %d<16 ||((16!=%d)&&(32!=%d)) \n", - var->xres_virtual, var->yres_virtual, var->xres, var->yres, var->xres, xsize, ysize, xsize, - var->bits_per_pixel, var->bits_per_pixel); - return -EINVAL; - } - - if( (var->xoffset+var->xres)>var->xres_virtual || - (var->yoffset+var->yres)>var->yres_virtual || - (xpos+xsize)>xlcd || (ypos+ysize)>ylcd ) - { - printk(">>>>>> win0fb_check_var fail 2!!! \n"); - printk("(%d+%d)>%d || (%d+%d)>%d || (%d+%d)>%d || (%d+%d)>%d \n ", - var->xoffset, var->xres, var->xres_virtual, var->yoffset, var->yres, - var->yres_virtual, xpos, xsize, xlcd, ypos, ysize, ylcd); - return -EINVAL; - } - - switch(var->nonstd&0x0f) - { - case 0: // rgb - switch(var->bits_per_pixel) - { - case 16: // rgb565 - var->xres_virtual = (var->xres_virtual + 0x1) & (~0x1); - var->xres = (var->xres + 0x1) & (~0x1); - var->xoffset = (var->xoffset) & (~0x1); - break; - default: // rgb888 - var->bits_per_pixel = 32; - break; - } - var->nonstd &= ~0xc0; //not support I2P in this format - break; - case 1: // yuv422 - var->xres_virtual = (var->xres_virtual + 0x3) & (~0x3); - var->xres = (var->xres + 0x3) & (~0x3); - var->xoffset = (var->xoffset) & (~0x3); - break; - case 2: // yuv4200 - var->xres_virtual = (var->xres_virtual + 0x3) & (~0x3); - var->yres_virtual = (var->yres_virtual + 0x1) & (~0x1); - var->xres = (var->xres + 0x3) & (~0x3); - var->yres = (var->yres + 0x1) & (~0x1); - var->xoffset = (var->xoffset) & (~0x3); - var->yoffset = (var->yoffset) & (~0x1); - break; - case 3: // yuv4201 - var->xres_virtual = (var->xres_virtual + 0x3) & (~0x3); - var->yres_virtual = (var->yres_virtual + 0x1) & (~0x1); - var->xres = (var->xres + 0x3) & (~0x3); - var->yres = (var->yres + 0x1) & (~0x1); - var->xoffset = (var->xoffset) & (~0x3); - var->yoffset = (var->yoffset) & (~0x1); - var->nonstd &= ~0xc0; //not support I2P in this format - break; - case 4: // yuv420m - var->xres_virtual = (var->xres_virtual + 0x7) & (~0x7); - var->yres_virtual = (var->yres_virtual + 0x1) & (~0x1); - var->xres = (var->xres + 0x7) & (~0x7); - var->yres = (var->yres + 0x1) & (~0x1); - var->xoffset = (var->xoffset) & (~0x7); - var->yoffset = (var->yoffset) & (~0x1); - var->nonstd &= ~0xc0; //not support I2P in this format - break; - case 5: // yuv444 - var->xres_virtual = (var->xres_virtual + 0x3) & (~0x3); - var->xres = (var->xres + 0x3) & (~0x3); - var->xoffset = (var->xoffset) & (~0x3); - var->nonstd &= ~0xc0; //not support I2P in this format - break; - default: - printk(">>>>>> win0fb var->nonstd=%d is invalid! \n", var->nonstd); - return -EINVAL; - } - - if(var->rotate == 270) - { - yres = var->xres; - } - else - { - yres = var->yres; - } - ScaleYDnY = CalScaleDownW0(yres, ysize); - ScaleYUpY = CalScaleUpW0(yres, ysize); - - if((ScaleYDnY>0x8000) || (ScaleYUpY<0x200)) - { - return -EINVAL; // multiple of scale down or scale up can't exceed 8 - } - - return 0; -} - -static int win0fb_set_par(struct fb_info *info) -{ - struct rk2818fb_inf *inf = dev_get_drvdata(info->device); - struct rk28fb_screen *screen = inf->cur_screen; - struct fb_var_screeninfo *var = &info->var; - struct fb_fix_screeninfo *fix = &info->fix; - struct win0_par *par = info->par; - - u8 format = 0; - dma_addr_t map_dma; - u32 cblen=0, crlen=0, map_size=0, smem_len=0, i2p_len=0; - u32 pre_y_addr = 0, pre_uv_addr = 0, nxt_y_addr = 0, nxt_uv_addr = 0; - - u32 actWidth = 0; - u32 actHeight = 0; - - u32 xact = var->xres; /* visible resolution */ - u32 yact = var->yres; - u32 xvir = var->xres_virtual; /* virtual resolution */ - u32 yvir = var->yres_virtual; - u32 xact_st = var->xoffset; /* offset from virtual to visible */ - u32 yact_st = var->yoffset; /* resolution */ - - u16 xpos = (var->nonstd>>8) & 0xfff; //visiable pos in panel - u16 ypos = (var->nonstd>>20) & 0xfff; - u16 xsize = (var->grayscale>>8) & 0xfff; //visiable size in panel - u16 ysize = (var->grayscale>>20) & 0xfff; - - u32 ScaleYUpX=0x1000, ScaleYDnX=0x1000, ScaleYUpY=0x1000, ScaleYDnY=0x1000; - u32 ScaleCbrUpX=0x1000, ScaleCbrDnX=0x1000, ScaleCbrUpY=0x1000, ScaleCbrDnY=0x1000; - - u8 i2p_mode = (var->nonstd & 0x80)>>7; - u8 i2p_polarity = (var->nonstd & 0x40)>>6; - u8 data_format = var->nonstd&0x0f; - u32 win0_en = var->reserved[2]; - u32 y_addr = var->reserved[3]; //user alloc buf addr y - u32 uv_addr = var->reserved[4]; - - if(var->rotate == 270) - { - xpos = (var->nonstd>>20) & 0xfff; //visiable pos in panel - ypos = (var->nonstd>>8) & 0xfff; - xsize = (var->grayscale>>20) & 0xfff; //visiable size in panel - ysize = (var->grayscale>>8) & 0xfff; - } - fbprintk(">>>>>> %s : %s\n", __FILE__, __FUNCTION__); - - CHK_SUSPEND(inf); - - /* calculate y_offset,uv_offset,line_length,cblen and crlen */ - switch (data_format) - { - case 0: // rgb - switch(var->bits_per_pixel) - { - case 16: // rgb565 - format = 1; - fix->line_length = 2 * xvir; - par->y_offset = (yact_st*xvir + xact_st)*2; - break; - case 32: // rgb888 - format = 0; - fix->line_length = 4 * xvir; - par->y_offset = (yact_st*xvir + xact_st)*4; - break; - default: - return -EINVAL; - } - break; - case 1: // yuv422 - format = 2; - fix->line_length = xvir; - cblen = crlen = (xvir*yvir)/2; - - if(i2p_mode) - { - i2p_len = (xvir*yvir)*2; - if(var->rotate==0) //even - { - par->even_y_offset = (yact_st*xvir+xact_st) + xvir; - par->even_uv_offset = (yact_st*xvir+xact_st) + xvir; - par->even_nxt_y_offset = (yact_st*xvir+xact_st); - par->even_nxt_uv_offset = (yact_st*xvir+xact_st); - - par->odd_y_offset = (yact_st*xvir+xact_st); - par->odd_uv_offset = (yact_st*xvir+xact_st); - par->odd_nxt_y_offset = (yact_st*xvir+xact_st) + xvir; - par->odd_nxt_uv_offset = (yact_st*xvir+xact_st) + xvir; - } - else if(var->rotate==270) //even - { - par->even_y_offset = (yact_st*xvir+xact_st) + xvir*(yact-1); - par->even_uv_offset = (yact_st*xvir+xact_st) + xvir*(yact-1); - par->even_nxt_y_offset = (yact_st*xvir+xact_st) + xvir*(yact-2); - par->even_nxt_uv_offset = (yact_st*xvir+xact_st) + xvir*(yact-2); - - par->odd_y_offset = (yact_st*xvir+xact_st) + xvir*(yact-2); - par->odd_uv_offset = (yact_st*xvir+xact_st) + xvir*(yact-2); - par->odd_nxt_y_offset = (yact_st*xvir+xact_st) + xvir*(yact-1); - par->odd_nxt_uv_offset = (yact_st*xvir+xact_st) + xvir*(yact-1); - } - } - else - { - par->y_offset = yact_st*xvir + xact_st; - par->uv_offset = yact_st*xvir + xact_st; - if(var->rotate == 270) - { - par->y_offset += xvir*(yact- 1); - par->uv_offset += xvir*(yact - 1); - } - } - break; - case 2: // yuv4200 - format = 3; - fix->line_length = xvir; - cblen = crlen = (xvir*yvir)/4; - if(i2p_mode) - { - i2p_len = (xvir*yvir)*3/2; - - if(var->rotate==0) //even - { - par->even_y_offset = (yact_st*xvir+xact_st) + xvir; - par->even_uv_offset = (yact_st/2*xvir+xact_st) + xvir; - par->even_nxt_y_offset = (yact_st*xvir+xact_st); - par->even_nxt_uv_offset = (yact_st/2*xvir+xact_st); - - par->odd_y_offset = (yact_st*xvir+xact_st); - par->odd_uv_offset = (yact_st/2*xvir+xact_st); - par->odd_nxt_y_offset = (yact_st*xvir+xact_st) + xvir; - par->odd_nxt_uv_offset = (yact_st/2*xvir+xact_st) + xvir; - } - else if(var->rotate==270) //even - { - par->even_y_offset = (yact_st*xvir+xact_st) + xvir*(yact-1); - par->even_uv_offset = (yact_st/2*xvir+xact_st) + xvir*(yact/2-1); - par->even_nxt_y_offset = (yact_st*xvir+xact_st) + xvir*(yact-2); - par->even_nxt_uv_offset = (yact_st/2*xvir+xact_st) + xvir*(yact/2-2); - - par->odd_y_offset = (yact_st*xvir+xact_st) + xvir*(yact-2); - par->odd_uv_offset = (yact_st/2*xvir+xact_st) + xvir*(yact/2-2); - par->odd_nxt_y_offset = (yact_st*xvir+xact_st) + xvir*(yact-1); - par->odd_nxt_uv_offset = (yact_st/2*xvir+xact_st) + xvir*(yact/2-1); - } - } - else - { - par->y_offset = yact_st*xvir + xact_st; - par->uv_offset = (yact_st/2)*xvir + xact_st; - if(var->rotate == 270) - { - par->y_offset += xvir*(yact - 1); - par->uv_offset += xvir*(yact/2 - 1); - } - } - break; - case 3: // yuv4201 - format = 4; - fix->line_length = xvir; - par->y_offset = (yact_st/2)*2*xvir + (xact_st)*2; - par->uv_offset = (yact_st/2)*xvir + xact_st; - if(var->rotate == 270) - { - par->y_offset += xvir*2*(yact/2 - 1); - par->uv_offset += xvir*(yact/2 - 1); - } - cblen = crlen = (xvir*yvir)/4; - break; - case 4: // yuv420m - format = 5; - fix->line_length = xvir; - par->y_offset = (yact_st/2)*3*xvir + (xact_st)*3; - cblen = crlen = (xvir*yvir)/4; - break; - case 5: // yuv444 - format = 6; - fix->line_length = xvir; - par->y_offset = yact_st*xvir + xact_st; - par->uv_offset = yact_st*2*xvir + xact_st*2; - cblen = crlen = (xvir*yvir); - break; - default: - return -EINVAL; - } - - smem_len = fix->line_length * yvir + cblen + crlen + i2p_len; - map_size = PAGE_ALIGN(smem_len); - - if(y_addr && uv_addr ) // buffer alloced by user, it's default instance - { - if (info->screen_base) { - printk(">>>>>> win0fb unmap memory(%d)! \n", info->fix.smem_len); - dma_free_writecombine(NULL, PAGE_ALIGN(info->fix.smem_len),info->screen_base, info->fix.smem_start); - info->screen_base = 0; - } - fix->smem_start = y_addr; - fix->smem_len = smem_len; - fix->mmio_start = uv_addr; - - par->addr_seted = ((-1==(int)y_addr)&&(-1==(int)uv_addr)) ? 0 : 1; - fbprintk("buffer alloced by user fix->smem_start = %8x, fix->smem_len = %8x, fix->mmio_start = %8x \n", (u32)fix->smem_start, (u32)fix->smem_len, (u32)fix->mmio_start); - } - else // driver alloce buffer - { - if ( (smem_len != fix->smem_len) || !info->screen_base ) // buffer need realloc - { - fbprintk(">>>>>> win0 buffer size is change! remap memory!\n"); - fbprintk(">>>>>> smem_len %d = %d * %d + %d + %d + %d\n", smem_len, fix->line_length, yvir, cblen, crlen, i2p_len); - fbprintk(">>>>>> map_size = %d\n", map_size); - LcdMskReg(inf, SYS_CONFIG, m_W0_ENABLE, v_W0_ENABLE(0)); - LcdWrReg(inf, REG_CFG_DONE, 0x01); - msleep(50); - if (info->screen_base) { - fbprintk(">>>>>> win0fb unmap memory(%d)! \n", info->fix.smem_len); - dma_free_writecombine(NULL, PAGE_ALIGN(info->fix.smem_len),info->screen_base, info->fix.smem_start); - info->screen_base = 0; - fix->smem_start = 0; - fix->smem_len = 0; - fix->reserved[1] = 0; - fix->reserved[2] = 0; - } - - info->screen_base = dma_alloc_writecombine(NULL, map_size, &map_dma, GFP_KERNEL); - if(!info->screen_base) { - printk(">>>>>> win0fb dma_alloc_writecombine fail!\n"); - return -ENOMEM; - } - memset(info->screen_base, 0x00, map_size); - fix->smem_start = map_dma; - fix->smem_len = smem_len; - fix->mmio_start = fix->smem_start + fix->line_length * yvir; - if(i2p_len) - { - fix->reserved[1] = fix->mmio_start + cblen + crlen; //next frame buf Y address in i2p mode - fix->reserved[2] = fix->reserved[1] + fix->line_length * yvir; //next frame buf UV address in i2p mode - } - else - { - fix->reserved[1] = fix->reserved[2] = 0; - } - fbprintk(">>>>>> alloc succ, smem_start=%08x, smem_len=%d, mmio_start=%08x!\n", - (u32)fix->smem_start, fix->smem_len, (u32)fix->mmio_start); - } - } - - // calculate the display phy address - y_addr = fix->smem_start + par->y_offset; - uv_addr = fix->mmio_start + par->uv_offset; - - fbprintk("y_addr 0x%08x = 0x%08x + %d\n", y_addr, (u32)fix->smem_start, par->y_offset); - fbprintk("uv_addr 0x%08x = 0x%08x + %d\n", uv_addr, (u32)fix->mmio_start , par->uv_offset); - - if(i2p_mode && fix->reserved[1] && fix->reserved[2]) - { - if(i2p_polarity) - { - y_addr = fix->smem_start + par->even_y_offset; - uv_addr = fix->mmio_start + par->even_uv_offset; - pre_y_addr = fix->smem_start + par->even_nxt_y_offset; - pre_uv_addr = fix->mmio_start + par->even_nxt_uv_offset; - nxt_y_addr = fix->reserved[1] + par->even_nxt_y_offset; - nxt_uv_addr = fix->reserved[2] + par->even_nxt_uv_offset; - } - else - { - y_addr = fix->smem_start + par->odd_y_offset; - uv_addr = fix->mmio_start + par->odd_uv_offset; - pre_y_addr = fix->smem_start + par->odd_nxt_y_offset; - pre_uv_addr = fix->mmio_start + par->odd_nxt_uv_offset; - nxt_y_addr = fix->reserved[1] + par->odd_nxt_y_offset; - nxt_uv_addr = fix->reserved[2] + par->odd_nxt_uv_offset; - } - - fbprintk("pre_y_addr 0x%08x = 0x%08x + %d\n", pre_y_addr, (u32)fix->smem_start, par->even_nxt_y_offset); - fbprintk("pre_uv_addr 0x%08x = 0x%08x + %d\n", pre_uv_addr, (u32)fix->mmio_start , par->even_nxt_uv_offset); - fbprintk("nxt_y_addr 0x%08x = 0x%08x + %d\n", nxt_y_addr, (u32)fix->reserved[1], par->even_nxt_y_offset); - fbprintk("nxt_uv_addr 0x%08x = 0x%08x + %d\n", nxt_uv_addr, (u32)fix->reserved[2] , par->even_nxt_uv_offset); - } - - if(var->rotate == 270) - { - actWidth = yact; - actHeight = xact; - } - else - { - actWidth = xact; - actHeight = yact; - } - if((xact>1280) && (xsize>1280)) - { - ScaleYDnX = CalScaleDownW0(actWidth, 1280); - ScaleYUpX = CalScaleUpW0(1280, xsize); - } - else - { - ScaleYDnX = CalScaleDownW0(actWidth, xsize); - ScaleYUpX = CalScaleUpW0(actWidth, xsize); - } - - ScaleYDnY = CalScaleDownW0(actHeight, ysize); - ScaleYUpY = CalScaleUpW0(actHeight, ysize); - - switch (data_format) - { - case 1:// yuv422 - if((xact>1280) && (xsize>1280)) - { - ScaleCbrDnX= CalScaleDownW0((actWidth/2), 1280); - ScaleCbrUpX = CalScaleUpW0((640), xsize); - } - else - { - if(var->rotate == 270) - { - ScaleCbrDnX= CalScaleDownW0(actWidth, xsize); - ScaleCbrUpX = CalScaleUpW0(actWidth, xsize); - } - else - { - ScaleCbrDnX= CalScaleDownW0((actWidth/2), xsize); - ScaleCbrUpX = CalScaleUpW0((actWidth/2), xsize); - } - } - - ScaleCbrDnY = CalScaleDownW0(actHeight, ysize); - ScaleCbrUpY = CalScaleUpW0(actHeight, ysize); - break; - case 2: // yuv4200 - case 3: // yuv4201 - case 4: // yuv420m - if((xact>1280) && (xsize>1280)) - { - ScaleCbrDnX= CalScaleDownW0(actWidth/2, 1280); - ScaleCbrUpX = CalScaleUpW0(640, xsize); - } - else - { - ScaleCbrDnX= CalScaleDownW0(actWidth/2, xsize); - ScaleCbrUpX = CalScaleUpW0(actWidth/2, xsize); - } - - ScaleCbrDnY = CalScaleDownW0(actHeight/2, ysize); - ScaleCbrUpY = CalScaleUpW0(actHeight/2, ysize); - break; - case 5:// yuv444 - if((xact>1280) && (xsize>1280)) - { - ScaleCbrDnX= CalScaleDownW0(actWidth, 1280); - ScaleCbrUpX = CalScaleUpW0(1280, xsize); - } - else - { - ScaleCbrDnX= CalScaleDownW0(actWidth, xsize); - ScaleCbrUpX = CalScaleUpW0(actWidth, xsize); - } - ScaleCbrDnY = CalScaleDownW0(actHeight, ysize); - ScaleCbrUpY = CalScaleUpW0(actHeight, ysize); - break; - } - - xpos += (screen->left_margin + screen->hsync_len); - ypos += (screen->upper_margin + screen->vsync_len); - - LcdWrReg(inf, WIN0_YRGB_MST, y_addr); - LcdWrReg(inf, WIN0_CBR_MST, uv_addr); - LcdWrReg(inf, WIN0_YRGB_VIR_MST, fix->smem_start); - LcdWrReg(inf, WIN0_CBR_VIR_MST, fix->mmio_start); - - LcdMskReg(inf, SYS_CONFIG, m_W0_ENABLE | m_W0_FORMAT | m_W0_ROTATE | m_MPEG2_I2P_EN, - v_W0_ENABLE(win0_en) | v_W0_FORMAT(format) | v_W0_ROTATE(var->rotate==270) | v_MPEG2_I2P_EN(i2p_mode)); - - LcdMskReg(inf, WIN0_VIR, m_WORDLO | m_WORDHI, v_VIRWIDTH(xvir) | v_VIRHEIGHT((yvir)) ); - LcdMskReg(inf, WIN0_ACT_INFO, m_WORDLO | m_WORDHI, v_WORDLO(actWidth) | v_WORDHI(actHeight)); - LcdMskReg(inf, WIN0_DSP_ST, m_BIT11LO | m_BIT11HI, v_BIT11LO(xpos) | v_BIT11HI(ypos)); - LcdMskReg(inf, WIN0_DSP_INFO, m_BIT11LO | m_BIT11HI, v_BIT11LO(xsize) | v_BIT11HI(ysize)); - LcdMskReg(inf, WIN0_SD_FACTOR_Y, m_WORDLO | m_WORDHI, v_WORDLO(ScaleYDnX) | v_WORDHI(ScaleYDnY)); - LcdMskReg(inf, WIN0_SP_FACTOR_Y, m_WORDLO | m_WORDHI, v_WORDLO(ScaleYUpX) | v_WORDHI(ScaleYUpY)); - LcdMskReg(inf, WIN0_SD_FACTOR_CBR, m_WORDLO | m_WORDHI, v_WORDLO(ScaleCbrDnX) | v_WORDHI(ScaleCbrDnY)); - LcdMskReg(inf, WIN0_SP_FACTOR_CBR, m_WORDLO | m_WORDHI, v_WORDLO(ScaleCbrUpX) | v_WORDHI(ScaleCbrUpY)); - - LcdMskReg(inf, DSP_CTRL0, m_I2P_THRESHOLD_Y | m_I2P_THRESHOLD_CBR | m_I2P_CUR_POLARITY | m_DROP_LINE_W0, - v_I2P_THRESHOLD_Y(0) | v_I2P_THRESHOLD_CBR(0)| v_I2P_CUR_POLARITY(i2p_polarity) | v_DROP_LINE_W0(0)); - - LcdWrReg(inf, I2P_REF0_MST_Y, pre_y_addr); - LcdWrReg(inf, I2P_REF0_MST_CBR, pre_uv_addr); - LcdWrReg(inf, I2P_REF1_MST_Y, nxt_y_addr); - LcdWrReg(inf, I2P_REF1_MST_CBR, nxt_uv_addr); - - switch(format) - { - case 1: //rgb565 - LcdMskReg(inf, SWAP_CTRL, m_W0_YRGB_8_SWAP | m_W0_YRGB_16_SWAP | m_W0_YRGB_R_SHIFT_SWAP | m_W0_565_RB_SWAP | m_W0_YRGB_M8_SWAP | m_W0_CBR_8_SWAP | m_W0_YRGB_HL8_SWAP, - v_W0_YRGB_8_SWAP(0) | v_W0_YRGB_16_SWAP(0) | v_W0_YRGB_R_SHIFT_SWAP(0) | v_W0_565_RB_SWAP(1) | v_W0_YRGB_M8_SWAP(0) | v_W0_CBR_8_SWAP(0) | v_W0_YRGB_HL8_SWAP(0) ); - break; - case 4: //yuv4201 - LcdMskReg(inf, SWAP_CTRL, m_W0_YRGB_8_SWAP | m_W0_YRGB_16_SWAP | m_W0_YRGB_R_SHIFT_SWAP | m_W0_565_RB_SWAP | m_W0_YRGB_M8_SWAP | m_W0_CBR_8_SWAP | m_W0_YRGB_HL8_SWAP, - v_W0_YRGB_8_SWAP(0) | v_W0_YRGB_16_SWAP(0) | v_W0_YRGB_R_SHIFT_SWAP(0) | v_W0_565_RB_SWAP(0) | - v_W0_YRGB_M8_SWAP((var->rotate==0)) | v_W0_CBR_8_SWAP(0) | v_W0_YRGB_HL8_SWAP(var->rotate!=0)); - break; - default: - LcdMskReg(inf, SWAP_CTRL, m_W0_YRGB_8_SWAP | m_W0_YRGB_16_SWAP | m_W0_YRGB_R_SHIFT_SWAP | m_W0_565_RB_SWAP | m_W0_YRGB_M8_SWAP | m_W0_CBR_8_SWAP | m_W0_YRGB_HL8_SWAP, - v_W0_YRGB_8_SWAP(0) | v_W0_YRGB_16_SWAP(0) | v_W0_YRGB_R_SHIFT_SWAP(0) | v_W0_565_RB_SWAP(0) | v_W0_YRGB_M8_SWAP(0) | v_W0_CBR_8_SWAP(0)| v_W0_YRGB_HL8_SWAP(0) ); - } - - LcdWrReg(inf, REG_CFG_DONE, 0x01); - - return 0; -} - -static int win0fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) -{ - struct rk2818fb_inf *inf = dev_get_drvdata(info->device); - struct fb_var_screeninfo *var0 = &info->var; - struct fb_fix_screeninfo *fix0 = &info->fix; - struct win0_par *par = info->par; - u32 y_offset=0, uv_offset=0, y_addr=0, uv_addr=0; - - fbprintk(">>>>>> %s : %s\n", __FILE__, __FUNCTION__); - - CHK_SUSPEND(inf); -#if 0 - switch(var0->nonstd&0x0f) - { - case 0: // rgb - switch(var0->bits_per_pixel) - { - case 16: // rgb565 - var->xoffset = (var->xoffset) & (~0x1); - y_offset = (var->yoffset*var0->xres_virtual + var->xoffset)*2; - break; - default: // rgb888 - y_offset = (var->yoffset*var0->xres_virtual + var->xoffset)*4; - break; - } - break; - case 1: // yuv422 - var->xoffset = (var->xoffset) & (~0x3); - y_offset = var->yoffset*var0->xres_virtual + var->xoffset; - uv_offset = var->yoffset*var0->xres_virtual + var->xoffset; - break; - case 2: // yuv4200 - var->xoffset = (var->xoffset) & (~0x3); - var->yoffset = (var->yoffset) & (~0x1); - y_offset = var->yoffset*var0->xres_virtual + var->xoffset; - uv_offset = (var->yoffset/2)*var0->xres_virtual + var->xoffset; - break; - case 3: // yuv4201 - var->xoffset = (var->xoffset) & (~0x3); - var->yoffset = (var->yoffset) & (~0x1); - y_offset = (var->yoffset/2)*2*var0->xres_virtual + (var->xoffset)*2; - uv_offset = (var->yoffset/2)*var0->xres_virtual + var->xoffset; - break; - case 4: // yuv420m - var->xoffset = (var->xoffset) & (~0x7); - var->yoffset = (var->yoffset) & (~0x1); - y_offset = (var->yoffset/2)*3*var0->xres_virtual + (var->xoffset)*3; - break; - case 5: // yuv444 - var->xoffset = (var->xoffset) & (~0x3); - y_offset = var->yoffset*var0->xres_virtual + var->xoffset; - uv_offset = var->yoffset*2*var0->xres_virtual + var->xoffset*2; - break; - default: - return -EINVAL; - } - - par->y_offset = y_offset; - par->uv_offset = uv_offset; -#endif - y_addr = fix0->smem_start + par->y_offset;//y_offset; - uv_addr = fix0->mmio_start + par->uv_offset ;//uv_offset; - - LcdWrReg(inf, WIN0_YRGB_MST, y_addr); - LcdWrReg(inf, WIN0_CBR_MST, uv_addr); - LcdWrReg(inf, REG_CFG_DONE, 0x01); - - // enable win0 after the win0 addr is seted - par->par_seted = 1; - LcdMskReg(inf, SYS_CONFIG, m_W0_ENABLE, v_W0_ENABLE((1==par->addr_seted)?(1):(0))); - mcu_refresh(inf); - - return 0; -} - -/* Set rotation (0, 90, 180, 270 degree), and switch to the new mode. */ -int win0fb_rotate(struct fb_info *fbi, int rotate) -{ - struct fb_var_screeninfo *var = &fbi->var; - // u32 SrcFmt = var->nonstd&0x0f; - - fbprintk(">>>>>> %s : %s \n", __FILE__, __FUNCTION__); - - if(rotate == 0) - { - if(var->rotate) - { - var->rotate = 0; - // if(!win0fb_check_var(var, fbi)) - // win0fb_set_par(fbi); - } - } - else - { - // if((var->xres >1280) || (var->yres >720)||((SrcFmt!= 1) && (SrcFmt!= 2) && (SrcFmt!= 3))) - // { - // printk(">>>>>> %s par err SrcFmt = %d\n", __FUNCTION__ ,SrcFmt); - // return -EPERM; - // } - if(var->rotate != 270) - { - var->rotate = 270; - // if(!win0fb_check_var(var, fbi)) - // win0fb_set_par(fbi); - } - } - - return 0; -} -int win0fb_open(struct fb_info *info, int user) -{ - struct win0_par *par = info->par; - - fbprintk(">>>>>> %s : %s \n", __FILE__, __FUNCTION__); - - par->par_seted = 0; - par->addr_seted = 0; - - if(par->refcount) { - printk(">>>>>> win0fb has opened! \n"); - return -EACCES; - } else { - par->refcount++; - return 0; - } -} - -int win0fb_release(struct fb_info *info, int user) -{ - struct win0_par *par = info->par; - struct fb_var_screeninfo *var0 = &info->var; - - fbprintk(">>>>>> %s : %s \n", __FILE__, __FUNCTION__); - - if(par->refcount) { - par->refcount--; - - win0fb_blank(FB_BLANK_POWERDOWN, info); - // wait for lcdc stop access memory - msleep(50); - - // unmap memory - if (info->screen_base) { - printk(">>>>>> win0fb unmap memory(%d)! \n", info->fix.smem_len); - dma_free_writecombine(NULL, PAGE_ALIGN(info->fix.smem_len),info->screen_base, info->fix.smem_start); - info->screen_base = 0; - info->fix.smem_start = 0; - info->fix.smem_len = 0; - } - - // clean the var param - memset(var0, 0, sizeof(struct fb_var_screeninfo)); - } - - return 0; -} - -static int win0fb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) -{ - struct rk2818fb_inf *inf = dev_get_drvdata(info->device); - struct win0_par *par = info->par; - void __user *argp = (void __user *)arg; - - fbprintk(">>>>>> %s : %s \n", __FILE__, __FUNCTION__); - fbprintk("win0fb_ioctl cmd = %8x, arg = %8x \n", (u32)cmd, (u32)arg); - - CHK_SUSPEND(inf); - - switch(cmd) - { - case FB1_IOCTL_GET_PANEL_SIZE: //get panel size - { - u32 panel_size[2]; - if(inf->win0fb->var.rotate == 270) { - panel_size[0] = inf->cur_screen->y_res; - panel_size[1] = inf->cur_screen->x_res; - } else { - panel_size[0] = inf->cur_screen->x_res; - panel_size[1] = inf->cur_screen->y_res; - } - - if(copy_to_user(argp, panel_size, 8)) return -EFAULT; - } - break; - - case FB1_IOCTL_SET_YUV_ADDR: //set y&uv address to register direct - { - u32 yuv_phy[2]; - if (copy_from_user(yuv_phy, argp, 8)) - return -EFAULT; - LcdWrReg(inf, WIN0_YRGB_VIR_MST,yuv_phy[0]); - LcdWrReg(inf, WIN0_CBR_VIR_MST,yuv_phy[1]); - - yuv_phy[0] += par->y_offset; - yuv_phy[1] += par->uv_offset; - - LcdWrReg(inf, WIN0_YRGB_MST, yuv_phy[0]); - LcdWrReg(inf, WIN0_CBR_MST, yuv_phy[1]); - LcdWrReg(inf, REG_CFG_DONE, 0x01); - // enable win0 after the win0 par is seted - par->addr_seted = 1; - if(par->par_seted) { - LcdMskReg(inf, SYS_CONFIG, m_W0_ENABLE, v_W0_ENABLE(1)); - mcu_refresh(inf); - } - } - break; - - case FB1_IOCTL_SET_ROTATE: //change MCU panel scan direction - fbprintk(">>>>>> change lcdc direction(%d) \n", (int)arg); - switch(arg) - { - case 0: - win0fb_rotate(info, 0); - break; - case 90: - case 270: - win0fb_rotate(info, 270); - break; - default: - return -1; - } - break; - case FB1_IOCTL_SET_I2P_ODD_ADDR: - { - u32 yuv_phy[4]; - u32 y_addr=0, uv_addr=0; - u32 pre_y_addr=0, pre_uv_addr=0; - u32 nxt_y_addr=0,nxt_uv_addr=0; - if (copy_from_user(yuv_phy, argp, 16)) - return -EFAULT; - - y_addr = yuv_phy[0] + par->odd_y_offset; - uv_addr = yuv_phy[1] + par->odd_uv_offset; - pre_y_addr = yuv_phy[0] + par->odd_nxt_y_offset; - pre_uv_addr = yuv_phy[1] + par->odd_nxt_uv_offset; - nxt_y_addr = yuv_phy[2] + par->odd_nxt_y_offset; - nxt_uv_addr = yuv_phy[3] + par->odd_nxt_uv_offset; - - //printk("new y_addr=%08x, new uv_addr=%08x \n", yuv_phy[0], yuv_phy[1]); - LcdWrReg(inf, WIN0_YRGB_MST, y_addr); - LcdWrReg(inf, WIN0_CBR_MST, uv_addr); - LcdWrReg(inf, I2P_REF0_MST_Y, pre_y_addr); - LcdWrReg(inf, I2P_REF0_MST_CBR, pre_uv_addr); - LcdWrReg(inf, I2P_REF1_MST_Y, nxt_y_addr); - LcdWrReg(inf, I2P_REF1_MST_CBR, nxt_uv_addr); - LcdMskReg(inf, DSP_CTRL0, m_I2P_CUR_POLARITY, v_I2P_CUR_POLARITY(0)); - LcdWrReg(inf, REG_CFG_DONE, 0x01); - - // enable win0 after the win0 par is seted - par->addr_seted = 1; - if(par->par_seted) { - LcdMskReg(inf, SYS_CONFIG, m_W0_ENABLE, v_W0_ENABLE(1)); - mcu_refresh(inf); - } - } - break; - case FB1_IOCTL_SET_I2P_EVEN_ADDR: - { - u32 yuv_phy[4]; - u32 y_addr=0, uv_addr=0; - u32 pre_y_addr=0, pre_uv_addr=0; - u32 nxt_y_addr=0,nxt_uv_addr=0; - if (copy_from_user(yuv_phy, argp, 16)) - return -EFAULT; - - y_addr = yuv_phy[0] + par->even_y_offset; - uv_addr = yuv_phy[1] + par->even_uv_offset; - pre_y_addr = yuv_phy[0] + par->even_nxt_y_offset; - pre_uv_addr = yuv_phy[1] + par->even_nxt_uv_offset; - nxt_y_addr = yuv_phy[2] + par->even_nxt_y_offset; - nxt_uv_addr = yuv_phy[3] + par->even_nxt_uv_offset; - - //printk("new y_addr=%08x, new uv_addr=%08x \n", yuv_phy[0], yuv_phy[1]); - LcdWrReg(inf, WIN0_YRGB_MST, y_addr); - LcdWrReg(inf, WIN0_CBR_MST, uv_addr); - LcdWrReg(inf, I2P_REF0_MST_Y, pre_y_addr); - LcdWrReg(inf, I2P_REF0_MST_CBR, pre_uv_addr); - LcdWrReg(inf, I2P_REF1_MST_Y, nxt_y_addr); - LcdWrReg(inf, I2P_REF1_MST_CBR, nxt_uv_addr); - LcdMskReg(inf, DSP_CTRL0, m_I2P_CUR_POLARITY, v_I2P_CUR_POLARITY(1)); - LcdWrReg(inf, REG_CFG_DONE, 0x01); - - // enable win0 after the win0 par is seted - par->addr_seted = 1; - if(par->par_seted) { - LcdMskReg(inf, SYS_CONFIG, m_W0_ENABLE, v_W0_ENABLE(1)); - mcu_refresh(inf); - } - } - break; - default: - break; - } - return 0; -} - -static struct fb_ops win0fb_ops = { - .owner = THIS_MODULE, - .fb_open = win0fb_open, - .fb_release = win0fb_release, - .fb_check_var = win0fb_check_var, - .fb_set_par = win0fb_set_par, - .fb_blank = win0fb_blank, - .fb_pan_display = win0fb_pan_display, - .fb_ioctl = win0fb_ioctl, - .fb_setcolreg = fb_setcolreg, - .fb_fillrect = cfb_fillrect, - .fb_copyarea = cfb_copyarea, - .fb_imageblit = cfb_imageblit, -}; - -static int win1fb_blank(int blank_mode, struct fb_info *info) -{ - struct rk2818fb_inf *inf = dev_get_drvdata(info->device); - - fbprintk(">>>>>> %s : %s \n", __FILE__, __FUNCTION__); - - CHK_SUSPEND(inf); - - switch(blank_mode) - { - case FB_BLANK_UNBLANK: - LcdMskReg(inf, SYS_CONFIG, m_W1_ENABLE, v_W1_ENABLE(1)); - break; - default: - LcdMskReg(inf, SYS_CONFIG, m_W1_ENABLE, v_W1_ENABLE(0)); - break; - } - LcdWrReg(inf, REG_CFG_DONE, 0x01); - - mcu_refresh(inf); - return 0; -} - -static int win1fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) -{ - struct rk2818fb_inf *inf = dev_get_drvdata(info->device); - struct rk28fb_screen *screen = inf->cur_screen; - u32 ScaleY = 0x1000; - u16 xpos = (var->nonstd>>8) & 0xfff; - u16 ypos = (var->nonstd>>20) & 0xfff; - u16 xlcd = screen->x_res; - u16 ylcd = screen->y_res; - u8 trspmode = (var->grayscale>>8) & 0xff; - u8 trspval = (var->grayscale) & 0xff; - //u16 xsize = screen->x_res; //visiable size in panel - u16 ysize = screen->y_res; - - fbprintk(">>>>>> %s : %s\n", __FILE__, __FUNCTION__); - - CHK_SUSPEND(inf); - -#if (0==WIN1_USE_DOUBLE_BUF) - if(var->yres_virtual>ylcd) - var->yres_virtual = ylcd; -#endif - - if( 0==var->xres_virtual || 0==var->yres_virtual || - 0==var->xres || 0==var->yres || var->xres<16 || - trspmode>5 || trspval>16 || - ((16!=var->bits_per_pixel)&&(32!=var->bits_per_pixel)) ) - { - printk(">>>>>> win1fb_check_var fail 1!!! \n"); - printk(">>>>>> 0==%d || 0==%d ", var->xres_virtual,var->yres_virtual); - printk("0==%d || 0==%d || %d<16 || ", var->xres,var->yres,var->xres<16); - printk("%d>5 || %d>16 \n", trspmode,trspval); - printk("bits_per_pixel=%d \n", var->bits_per_pixel); - return -EINVAL; - } - - if( (var->xoffset+var->xres)>var->xres_virtual || - (var->yoffset+var->yres)>var->yres_virtual || - (xpos+var->xres)>xlcd || (ypos+var->yres)>ylcd ) - { - printk(">>>>>> win1fb_check_var fail 2!!! \n"); - printk(">>>>>> (%d+%d)>%d || ", var->xoffset,var->xres,var->xres_virtual); - printk("(%d+%d)>%d || ", var->yoffset,var->yres,var->yres_virtual); - printk("(%d+%d)>%d || (%d+%d)>%d \n", xpos,var->xres,xlcd,ypos,var->yres,ylcd); - return -EINVAL; - } - - switch(var->bits_per_pixel) - { - case 16: // rgb565 - var->xres_virtual = (var->xres_virtual + 0x1) & (~0x1); - var->xres = (var->xres + 0x1) & (~0x1); - var->xoffset = (var->xoffset) & (~0x1); - break; - default: // rgb888 - var->bits_per_pixel = 32; - break; - } - - ScaleY = CalScaleW1(var->yres, ysize); - - if((ScaleY>0x8000) ||(ScaleY<0x200)) - { - return (-EINVAL); // multiple of scale down or scale up can't exceed 8 - } - - return 0; -} - -static int win1fb_set_par(struct fb_info *info) -{ - struct rk2818fb_inf *inf = dev_get_drvdata(info->device); - struct fb_var_screeninfo *var = &info->var; - struct fb_fix_screeninfo *fix = &info->fix; - struct rk28fb_screen *screen = inf->cur_screen; - - - u8 format = 0; - dma_addr_t map_dma; - u32 offset=0, addr=0, map_size=0, smem_len=0; - u32 ScaleX = 0x1000; - u32 ScaleY = 0x1000; - - u16 xres_virtual = var->xres_virtual; //virtual screen size - //u16 yres_virtual = var->yres_virtual; - u16 xsize_virtual = var->xres; //visiable size in virtual screen - u16 ysize_virtual = var->yres; - u16 xpos_virtual = var->xoffset; //visiable offset in virtual screen - u16 ypos_virtual = var->yoffset; - - u16 xpos = 0; //visiable offset in panel - u16 ypos = 0; - u16 xsize = screen->x_res; //visiable size in panel - u16 ysize = screen->y_res; - u8 trspmode = TRSP_CLOSE; - u8 trspval = 0; - - fbprintk(">>>>>> %s : %s\n", __FILE__, __FUNCTION__); - - CHK_SUSPEND(inf); - - switch(var->bits_per_pixel) - { - case 16: // rgb565 - format = 1; - fix->line_length = 2 * xres_virtual; - offset = (ypos_virtual*xres_virtual + xpos_virtual)*2; - break; - case 32: // rgb888 - default: - format = 0; - fix->line_length = 4 * xres_virtual; - offset = (ypos_virtual*xres_virtual + xpos_virtual)*4; - break; - } - - smem_len = fix->line_length * var->yres_virtual + CURSOR_BUF_SIZE; //cursor buf also alloc here - map_size = PAGE_ALIGN(smem_len); - -#if WIN1_USE_DOUBLE_BUF - if( var->yres_virtual == 2*screen->y_res ) { - inf->mcu_usetimer = 0; - } - if(0==fix->smem_len) { - smem_len = smem_len*2; - map_size = PAGE_ALIGN(smem_len); - fbprintk(">>>>>> first alloc, alloc double!!! \n "); - } -#endif - -#if WIN1_USE_DOUBLE_BUF - if (smem_len > fix->smem_len) // buffer need realloc -#else - if (smem_len != fix->smem_len) // buffer need realloc -#endif - { - fbprintk(">>>>>> win1 buffer size is change(%d->%d)! remap memory!\n",fix->smem_len, smem_len); - fbprintk(">>>>>> smem_len %d = %d * %d \n", smem_len, fix->line_length, var->yres_virtual); - fbprintk(">>>>>> map_size = %d\n", map_size); - LcdMskReg(inf, SYS_CONFIG, m_W1_ENABLE, v_W1_ENABLE(0)); - LcdWrReg(inf, REG_CFG_DONE, 0x01); - msleep(50); - if (info->screen_base) { - printk(">>>>>> win1fb unmap memory(%d)! \n", info->fix.smem_len); - dma_free_writecombine(NULL, PAGE_ALIGN(info->fix.smem_len), info->screen_base, info->fix.smem_start); - info->screen_base = 0; - fix->smem_start = 0; - fix->smem_len = 0; - } - - info->screen_base = dma_alloc_writecombine(NULL, map_size, &map_dma, GFP_KERNEL); - if(!info->screen_base) { - printk(">>>>>> win1fb dma_alloc_writecombine fail!\n"); - return -ENOMEM; - } - memset(info->screen_base, 0, map_size); - fix->smem_start = map_dma; - fix->smem_len = smem_len; - fbprintk(">>>>>> alloc succ, mem=%08x, len=%d!\n", (u32)fix->smem_start, fix->smem_len); - } - - addr = fix->smem_start + offset; - - ScaleX = CalScaleW1(xsize_virtual, xsize); - ScaleY = CalScaleW1(ysize_virtual, ysize); - - LcdMskReg(inf, SYS_CONFIG, m_W1_ENABLE|m_W1_FORMAT, v_W1_ENABLE(1)|v_W1_FORMAT(format)); - - xpos += (screen->left_margin + screen->hsync_len); - ypos += (screen->upper_margin + screen->vsync_len); - - LcdWrReg(inf, WIN1_YRGB_MST, addr); - LcdWrReg(inf, WIN1_VIR_MST, fix->smem_start); - - LcdMskReg(inf, WIN1_DSP_ST, m_BIT11LO|m_BIT11HI, v_BIT11LO(xpos) | v_BIT11HI(ypos)); - LcdMskReg(inf, WIN1_DSP_INFO, m_BIT11LO|m_BIT11HI, v_BIT11LO(xsize) | v_BIT11HI(ysize)); - - LcdMskReg(inf, WIN1_VIR, m_WORDLO | m_WORDHI , v_WORDLO(xres_virtual) | v_WORDHI(var->yres_virtual)); - LcdMskReg(inf, WIN1_ACT_INFO, m_WORDLO | m_WORDHI, v_WORDLO(xsize_virtual) | v_WORDHI(ysize_virtual)); - - LcdMskReg(inf, WIN1_SCL_FACTOR, m_HSCALE_FACTOR | m_VSCALE_FACTOR, v_HSCALE_FACTOR(ScaleX) | v_VSCALE_FACTOR(ScaleY)); - - LcdMskReg(inf, BLEND_CTRL, m_W1_BLEND_EN | m_W1_BLEND_FACTOR_SELECT | m_W1_BLEND_FACTOR, - v_W1_BLEND_EN((TRSP_FMREG==trspmode) || (TRSP_MASK==trspmode)) | - v_W1_BLEND_FACTOR_SELECT(TRSP_FMRAM==trspmode) | v_W1_BLEND_FACTOR(trspval)); - - // enable win1 color key and set the color to black(rgb=0) - LcdMskReg(inf, WIN1_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR, v_COLORKEY_EN(1) | v_KEYCOLOR(0)); - - if(1==format) //rgb565 - { - LcdMskReg(inf, SWAP_CTRL, m_W1_8_SWAP | m_W1_16_SWAP | m_W1_R_SHIFT_SWAP | m_W1_565_RB_SWAP, - v_W1_8_SWAP(0) | v_W1_16_SWAP(0) | v_W1_R_SHIFT_SWAP(0) | v_W1_565_RB_SWAP(0) ); - } - else - { - LcdMskReg(inf, SWAP_CTRL, m_W1_8_SWAP | m_W1_16_SWAP | m_W1_R_SHIFT_SWAP | m_W1_565_RB_SWAP, - v_W1_8_SWAP(0) | v_W1_16_SWAP(0) | v_W1_R_SHIFT_SWAP(0) | v_W1_565_RB_SWAP(0) ); - } - - LcdWrReg(inf, REG_CFG_DONE, 0x01); - - return 0; -} - -static int win1fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) -{ - struct rk2818fb_inf *inf = dev_get_drvdata(info->device); - struct fb_var_screeninfo *var1 = &info->var; - struct fb_fix_screeninfo *fix1 = &info->fix; - - u32 offset = 0, addr = 0; - - fbprintk(">>>>>> %s : %s \n", __FILE__, __FUNCTION__); - - CHK_SUSPEND(inf); - - switch(var1->bits_per_pixel) - { - case 16: // rgb565 - var->xoffset = (var->xoffset) & (~0x1); - offset = (var->yoffset*var1->xres_virtual + var->xoffset)*2; - break; - case 32: // rgb888 - offset = (var->yoffset*var1->xres_virtual + var->xoffset)*4; - break; - default: - return -EINVAL; - } - - addr = fix1->smem_start + offset; - - fbprintk("info->screen_base = %8x ; fix1->smem_len = %d , addr = %8x\n",(u32)info->screen_base, fix1->smem_len, addr); - - LcdWrReg(inf, WIN1_YRGB_MST, addr); - LcdWrReg(inf, REG_CFG_DONE, 0x01); - - mcu_refresh(inf); - - // flush end when wq_condition=1 in mcu panel, but not in rgb panel - if(SCREEN_MCU == inf->cur_screen->type) { - wait_event_interruptible_timeout(wq, wq_condition, HZ/20); - wq_condition = 0; - } else { - wq_condition = 0; - wait_event_interruptible_timeout(wq, wq_condition, HZ/20); - } - - return 0; -} - - -static int win1fb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) -{ - struct rk2818fb_inf *inf = dev_get_drvdata(info->device); - struct rk2818fb_info *mach_info = info->device->platform_data; - unsigned display_on; - int display_on_pol; - - fbprintk(">>>>>> %s : %s \n", __FILE__, __FUNCTION__); - - CHK_SUSPEND(inf); - - switch(cmd) - { - case FB0_IOCTL_STOP_TIMER_FLUSH: //stop timer flush mcu panel after android is runing - if(1==arg) - { - inf->mcu_usetimer = 0; - } - break; - - case FB0_IOCTL_SET_PANEL: - if(arg>7) return -1; - - /* Black out, because some display device need clock to standby */ - //LcdMskReg(inf, DSP_CTRL_REG1, m_BLACK_OUT, v_BLACK_OUT(1)); - LcdMskReg(inf, SYS_CONFIG, m_W0_ENABLE, v_W0_ENABLE(0)); - LcdMskReg(inf, SYS_CONFIG, m_W1_ENABLE, v_W1_ENABLE(0)); - LcdMskReg(inf, DSP_CTRL1, m_BLACK_MODE, v_BLACK_MODE(1)); - LcdWrReg(inf, REG_CFG_DONE, 0x01); - if(inf->cur_screen) - { - if(inf->cur_screen->standby) inf->cur_screen->standby(1); - // operate the display_on pin to power down the lcd - if(SCREEN_RGB==inf->cur_screen->type || SCREEN_MCU==inf->cur_screen->type) - { - if(mach_info && mach_info->disp_on_pin) - { - display_on = mach_info->disp_on_pin; - display_on_pol = mach_info->disp_on_value; - gpio_direction_output(display_on, 0); - gpio_set_value(display_on, !display_on_pol); - } - } - } - - /* Load the new device's param */ - switch(arg) - { - case 0: inf->cur_screen = &inf->lcd_info; break; //lcd - case 1: inf->cur_screen = &inf->tv_info[0]; break; //tv ntsc cvbs - case 2: inf->cur_screen = &inf->tv_info[1]; break; //tv pal cvbs - case 3: inf->cur_screen = &inf->tv_info[2]; break; //tv 480 ypbpr - case 4: inf->cur_screen = &inf->tv_info[3]; break; //tv 576 ypbpr - case 5: inf->cur_screen = &inf->tv_info[4]; break; //tv 720 ypbpr - case 6: inf->cur_screen = &inf->hdmi_info[0]; break; //hdmi 576 - case 7: inf->cur_screen = &inf->hdmi_info[1]; break; //hdmi 720 - default: break; - } - load_screen(info, 1); - mcu_refresh(inf); - break; - default: - break; - } - return 0; -} - - -static struct fb_ops win1fb_ops = { - .owner = THIS_MODULE, - .fb_check_var = win1fb_check_var, - .fb_set_par = win1fb_set_par, - .fb_blank = win1fb_blank, - .fb_pan_display = win1fb_pan_display, - .fb_ioctl = win1fb_ioctl, - .fb_setcolreg = fb_setcolreg, - .fb_fillrect = cfb_fillrect, - .fb_copyarea = cfb_copyarea, - .fb_imageblit = cfb_imageblit, - .fb_cursor = rk2818_set_cursor, -}; - - -static irqreturn_t rk2818fb_irq(int irq, void *dev_id) -{ - struct platform_device *pdev = (struct platform_device*)dev_id; - struct rk2818fb_inf *inf = platform_get_drvdata(pdev); - if(!inf) - return IRQ_HANDLED; - - //fbprintk(">>>>>> %s : %s \n", __FILE__, __FUNCTION__); - - LcdMskReg(inf, INT_STATUS, m_FRM_STARTCLEAR, v_FRM_STARTCLEAR(1)); - - if(SCREEN_MCU == inf->cur_screen->type) - { - inf->mcu_isrcnt = !inf->mcu_isrcnt; - if(inf->mcu_isrcnt) - return IRQ_HANDLED; - - if(IsMcuUseFmk()) - { - if(LcdReadBit(inf, MCU_TIMING_CTRL, m_MCU_HOLD_STATUS) && (inf->mcu_fmksync == 0)) - { - inf->mcu_fmksync = 1; - if(inf->cur_screen->refresh) - inf->cur_screen->refresh(REFRESH_END); - inf->mcu_fmksync = 0; - } - else - { - return IRQ_HANDLED; - } - } - else - { - if(inf->mcu_needflush) { - if(inf->cur_screen->refresh) - inf->cur_screen->refresh(REFRESH_PRE); - inf->mcu_needflush = 0; - inf->mcu_isrcnt = 0; - LcdSetRegBit(inf, MCU_TIMING_CTRL, m_MCU_HOLDMODE_FRAME_ST); - } else { - if(inf->cur_screen->refresh) - inf->cur_screen->refresh(REFRESH_END); - } - } - } - - wq_condition = 1; - wake_up_interruptible(&wq); - - return IRQ_HANDLED; -} - -#ifdef CONFIG_HAS_EARLYSUSPEND - -struct suspend_info { - struct early_suspend early_suspend; - struct rk2818fb_inf *inf; -}; - -void suspend(struct early_suspend *h) -{ - struct suspend_info *info = container_of(h, struct suspend_info, - early_suspend); - - struct rk2818fb_inf *inf = info->inf; - - fbprintk(">>>>>> %s : %s\n", __FILE__, __FUNCTION__); - - if(!inf) { - printk("inf==0, rk2818fb_suspend fail! \n"); - return; - } - - set_lcd_pin(g_pdev, 0); - - if(inf->cur_screen->standby) - { - fbprintk(">>>>>> power down the screen! \n"); - inf->cur_screen->standby(1); - } - - LcdMskReg(inf, DSP_CTRL1, m_BLANK_MODE , v_BLANK_MODE(1)); - LcdMskReg(inf, SYS_CONFIG, m_STANDBY, v_STANDBY(1)); - LcdWrReg(inf, REG_CFG_DONE, 0x01); - - if(!inf->in_suspend) - { - fbprintk(">>>>>> diable the lcdc clk! \n"); - msleep(100); - if (inf->dclk){ - clk_disable(inf->dclk); - } - if(inf->clk){ - clk_disable(inf->clk); - } - - inf->in_suspend = 1; - } - -} - -void resume(struct early_suspend *h) -{ - struct suspend_info *info = container_of(h, struct suspend_info, - early_suspend); - - struct rk2818fb_inf *inf = info->inf; - - fbprintk(">>>>>> %s : %s\n", __FILE__, __FUNCTION__); - if(!inf) { - printk("inf==0, rk2818fb_resume fail! \n"); - return ; - } - - if(inf->in_suspend) - { - inf->in_suspend = 0; - fbprintk(">>>>>> enable the lcdc clk! \n"); - if (inf->dclk){ - clk_enable(inf->dclk); - } - if(inf->clk){ - clk_enable(inf->clk); - } - msleep(100); - } - LcdMskReg(inf, DSP_CTRL1, m_BLANK_MODE , v_BLANK_MODE(0)); - LcdMskReg(inf, SYS_CONFIG, m_STANDBY, v_STANDBY(0)); - LcdWrReg(inf, REG_CFG_DONE, 0x01); - - if(inf->cur_screen->standby) - { - fbprintk(">>>>>> power on the screen! \n"); - inf->cur_screen->standby(0); - } - msleep(100); - set_lcd_pin(g_pdev, 1); - memcpy(inf->preg, &inf->regbak, 47*4); //resume reg -} - -struct suspend_info suspend_info = { - .early_suspend.suspend = suspend, - .early_suspend.resume = resume, - .early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB, -}; -#endif - -static int __init rk2818fb_probe (struct platform_device *pdev) -{ - struct rk2818fb_inf *inf = NULL; - struct resource *res = NULL; - struct resource *mem = NULL; - struct rk2818fb_info *mach_info = NULL; - struct rk28fb_screen *screen = NULL; - int irq = 0; - int ret = 0; - - fbprintk(">>>>>> %s : %s\n", __FILE__, __FUNCTION__); - - /* Malloc rk2818fb_inf and set it to pdev for drvdata */ - fbprintk(">> Malloc rk2818fb_inf and set it to pdev for drvdata \n"); - inf = kmalloc(sizeof(struct rk2818fb_inf), GFP_KERNEL); - if(!inf) - { - dev_err(&pdev->dev, ">> inf kmalloc fail!"); - ret = -ENOMEM; - goto release_drvdata; - } - memset(inf, 0, sizeof(struct rk2818fb_inf)); - platform_set_drvdata(pdev, inf); - - mach_info = pdev->dev.platform_data; - /* Fill screen info and set current screen */ - fbprintk(">> Fill screen info and set current screen \n"); - set_lcd_info(&inf->lcd_info, mach_info->lcd_info); - set_tv_info(&inf->tv_info[0]); - set_hdmi_info(&inf->hdmi_info[0]); - inf->cur_screen = &inf->lcd_info; - screen = inf->cur_screen; - if(SCREEN_NULL==screen->type) - { - dev_err(&pdev->dev, ">> Please select a display device! \n"); - ret = -EINVAL; - goto release_drvdata; - } - - /* get virtual basic address of lcdc register */ - fbprintk(">> get virtual basic address of lcdc register \n"); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (res == NULL) - { - dev_err(&pdev->dev, "failed to get memory registers\n"); - ret = -ENOENT; - goto release_drvdata; - } - inf->reg_phy_base = res->start; - inf->len = (res->end - res->start) + 1; - mem = request_mem_region(inf->reg_phy_base, inf->len, pdev->name); - if (mem == NULL) - { - dev_err(&pdev->dev, "failed to get memory region\n"); - ret = -ENOENT; - goto release_drvdata; - } - fbprintk("inf->reg_phy_base = 0x%08x, inf->len = %d \n", inf->reg_phy_base, inf->len); - inf->reg_vir_base = ioremap(inf->reg_phy_base, inf->len); - if (inf->reg_vir_base == NULL) - { - dev_err(&pdev->dev, "ioremap() of registers failed\n"); - ret = -ENXIO; - goto release_drvdata; - } - inf->preg = (LCDC_REG*)inf->reg_vir_base; - - /* Prepare win1 info */ - fbprintk(">> Prepare win1 info \n"); - inf->win1fb = framebuffer_alloc(sizeof(struct win1_par), &pdev->dev); - if(!inf->win1fb) - { - dev_err(&pdev->dev, ">> win1fb framebuffer_alloc fail!"); - inf->win1fb = NULL; - ret = -ENOMEM; - goto release_win1fb; - } - - strcpy(inf->win1fb->fix.id, "win1fb"); - inf->win1fb->fix.type = FB_TYPE_PACKED_PIXELS; - inf->win1fb->fix.type_aux = 0; - inf->win1fb->fix.xpanstep = 1; - inf->win1fb->fix.ypanstep = 1; - inf->win1fb->fix.ywrapstep = 0; - inf->win1fb->fix.accel = FB_ACCEL_NONE; - inf->win1fb->fix.visual = FB_VISUAL_TRUECOLOR; - inf->win1fb->fix.smem_len = 0; - inf->win1fb->fix.line_length = 0; - inf->win1fb->fix.smem_start = 0; - - inf->win1fb->var.xres = screen->x_res; - inf->win1fb->var.yres = screen->y_res; - inf->win1fb->var.bits_per_pixel = 16; - inf->win1fb->var.xres_virtual = screen->x_res; - inf->win1fb->var.yres_virtual = screen->y_res; - inf->win1fb->var.width = screen->x_res; - inf->win1fb->var.height = screen->y_res; - inf->win1fb->var.pixclock = screen->pixclock; - inf->win1fb->var.left_margin = screen->left_margin; - inf->win1fb->var.right_margin = screen->right_margin; - inf->win1fb->var.upper_margin = screen->upper_margin; - inf->win1fb->var.lower_margin = screen->lower_margin; - inf->win1fb->var.vsync_len = screen->vsync_len; - inf->win1fb->var.hsync_len = screen->hsync_len; - inf->win1fb->var.red = def_rgb_16.red; - inf->win1fb->var.green = def_rgb_16.green; - inf->win1fb->var.blue = def_rgb_16.blue; - inf->win1fb->var.transp = def_rgb_16.transp; - - inf->win1fb->var.nonstd = 0; //win1 format & ypos & xpos (ypos<<20 + xpos<<8 + format) - inf->win1fb->var.grayscale = 0; //win1 transprent mode & value(mode<<8 + value) - inf->win1fb->var.activate = FB_ACTIVATE_NOW; - inf->win1fb->var.accel_flags = 0; - inf->win1fb->var.vmode = FB_VMODE_NONINTERLACED; - - inf->win1fb->fbops = &win1fb_ops; - inf->win1fb->flags = FBINFO_FLAG_DEFAULT; - inf->win1fb->pseudo_palette = ((struct win1_par*)inf->win1fb->par)->pseudo_pal; - inf->win1fb->screen_base = 0; - - memset(inf->win1fb->par, 0, sizeof(struct win1_par)); - ret = fb_alloc_cmap(&inf->win1fb->cmap, 256, 0); - if (ret < 0) - goto release_cmap; - - /* Prepare win0 info */ - fbprintk(">> Prepare win0 info \n"); - inf->win0fb = framebuffer_alloc(sizeof(struct win0_par), &pdev->dev); - if(!inf->win0fb) - { - dev_err(&pdev->dev, ">> win0fb framebuffer_alloc fail!"); - inf->win0fb = NULL; - ret = -ENOMEM; - goto release_win0fb; - } - - strcpy(inf->win0fb->fix.id, "win0fb"); - inf->win0fb->fix.type = FB_TYPE_PACKED_PIXELS; - inf->win0fb->fix.type_aux = 0; - inf->win0fb->fix.xpanstep = 1; - inf->win0fb->fix.ypanstep = 1; - inf->win0fb->fix.ywrapstep = 0; - inf->win0fb->fix.accel = FB_ACCEL_NONE; - inf->win0fb->fix.visual = FB_VISUAL_TRUECOLOR; - inf->win0fb->fix.smem_len = 0; - inf->win0fb->fix.line_length = 0; - inf->win0fb->fix.smem_start = 0; - - inf->win0fb->var.xres = screen->x_res; - inf->win0fb->var.yres = screen->y_res; - inf->win0fb->var.bits_per_pixel = 16; - inf->win0fb->var.xres_virtual = screen->x_res; - inf->win0fb->var.yres_virtual = screen->y_res; - inf->win0fb->var.width = screen->x_res; - inf->win0fb->var.height = screen->y_res; - inf->win0fb->var.pixclock = screen->pixclock; - inf->win0fb->var.left_margin = screen->left_margin; - inf->win0fb->var.right_margin = screen->right_margin; - inf->win0fb->var.upper_margin = screen->upper_margin; - inf->win0fb->var.lower_margin = screen->lower_margin; - inf->win0fb->var.vsync_len = screen->vsync_len; - inf->win0fb->var.hsync_len = screen->hsync_len; - inf->win0fb->var.red = def_rgb_16.red; - inf->win0fb->var.green = def_rgb_16.green; - inf->win0fb->var.blue = def_rgb_16.blue; - inf->win0fb->var.transp = def_rgb_16.transp; - - inf->win0fb->var.nonstd = 0; //win0 format & ypos & xpos (ypos<<20 + xpos<<8 + format) - inf->win0fb->var.grayscale = ((inf->win0fb->var.yres<<20)&0xfff00000) + ((inf->win0fb->var.xres<<8)&0xfff00);//win0 xsize & ysize - inf->win0fb->var.activate = FB_ACTIVATE_NOW; - inf->win0fb->var.accel_flags = 0; - inf->win0fb->var.vmode = FB_VMODE_NONINTERLACED; - - inf->win0fb->fbops = &win0fb_ops; - inf->win0fb->flags = FBINFO_FLAG_DEFAULT; - inf->win0fb->pseudo_palette = ((struct win0_par*)inf->win0fb->par)->pseudo_pal; - inf->win0fb->screen_base = 0; - - memset(inf->win0fb->par, 0, sizeof(struct win0_par)); - - /* Init all lcdc and lcd before register_framebuffer. */ - /* because after register_framebuffer, the win1fb_check_par and winfb_set_par execute immediately */ - fbprintk(">> Init all lcdc and lcd before register_framebuffer \n"); - init_lcdc(inf->win1fb); - inf->clk = clk_get(&pdev->dev, "lcdc_hclk"); - if (!inf->clk || IS_ERR(inf->clk)) - { - printk(KERN_ERR "failed to get lcdc_hclk source\n"); - ret = -ENOENT; - goto unregister_win1fb; - } - - inf->dclk = clk_get(&pdev->dev, "lcdc"); - if (!inf->dclk || IS_ERR(inf->dclk)) - { - printk(KERN_ERR "failed to get lcd dclock source\n"); - ret = -ENOENT; - goto unregister_win1fb; - } - inf->dclk_parent = clk_get(&pdev->dev, "arm_pll"); - if (!inf->dclk_parent || IS_ERR(inf->dclk_parent)) - { - printk(KERN_ERR "failed to get lcd dclock parent source\n"); - ret = -ENOENT; - goto unregister_win1fb; - } - inf->dclk_divider= clk_get(&pdev->dev, "lcdc_divider"); - if (!inf->dclk_divider || IS_ERR(inf->dclk_divider)) - { - printk(KERN_ERR "failed to get lcd clock lcdc_divider source \n"); - ret = -ENOENT; - goto unregister_win1fb; - } - - inf->clk_share_mem = clk_get(&pdev->dev, "lcdc_share_memory"); - if (!inf->clk_share_mem || IS_ERR(inf->clk_share_mem)) - { - dev_err(&pdev->dev, "failed to get lcd clock clk_share_mem source \n"); - ret = -ENOENT; - goto unregister_win1fb; - } - #ifdef CONFIG_CPU_FREQ - inf->freq_transition.notifier_call = rk2818fb_freq_transition; - cpufreq_register_notifier(&inf->freq_transition, CPUFREQ_TRANSITION_NOTIFIER); - #endif - fbprintk("got clock\n"); - - if(mach_info) - { - struct rk2818_fb_setting_info fb_setting; - if( OUT_P888==inf->lcd_info.face || - OUT_P888==inf->tv_info[0].face || - OUT_P888==inf->hdmi_info[0].face ) // set lcdc iomux - { - fb_setting.data_num = 24; - } - else if(OUT_P666 == inf->lcd_info.face ) - { - fb_setting.data_num = 18; - } - else - { - fb_setting.data_num = 16; - } - fb_setting.den_en = 1; - fb_setting.vsync_en = 1; - fb_setting.disp_on_en = 1; - fb_setting.standby_en = 1; - if( inf->lcd_info.mcu_usefmk ) - fb_setting.mcu_fmk_en =1; - mach_info->io_init(&fb_setting); - } - - set_lcd_pin(pdev, 1); - mdelay(10); - g_pdev = pdev; - inf->mcu_usetimer = 1; - inf->mcu_fmksync = 0; - load_screen(inf->win1fb, 1); - - /* Register framebuffer(win1fb & win0fb) */ - fbprintk(">> Register framebuffer(win1fb) \n"); - ret = register_framebuffer(inf->win1fb); - if(ret<0) - { - printk(">> win1fb register_framebuffer fail!\n"); - ret = -EINVAL; - goto release_win0fb; - } - - fbprintk(">> Register framebuffer(win0fb) \n"); - - ret = register_framebuffer(inf->win0fb); - if(ret<0) - { - printk(">> win0fb register_framebuffer fail!\n"); - ret = -EINVAL; - goto unregister_win1fb; - } - -#ifdef CONFIG_HAS_EARLYSUSPEND - suspend_info.inf = inf; - register_early_suspend(&suspend_info.early_suspend); -#endif - - /* get and request irq */ - fbprintk(">> get and request irq \n"); - irq = platform_get_irq(pdev, 0); - if (irq < 0) { - dev_err(&pdev->dev, "no irq for device\n"); - ret = -ENOENT; - goto unregister_win1fb; - } - ret = request_irq(irq, rk2818fb_irq, IRQF_DISABLED, pdev->name, pdev); - if (ret) { - dev_err(&pdev->dev, "cannot get irq %d - err %d\n", irq, ret); - ret = -EBUSY; - goto release_irq; - } - - if( inf->lcd_info.mcu_usefmk && (mach_info->mcu_fmk_pin != -1) ) - { - ret = request_irq(gpio_to_irq(mach_info->mcu_fmk_pin), mcu_irqfmk, GPIOEdgelFalling, pdev->name, pdev); - if (ret) - { - dev_err(&pdev->dev, "cannot get fmk irq %d - err %d\n", irq, ret); - ret = -EBUSY; - goto release_irq; - } - } - - printk(" %s ok\n", __FUNCTION__); - return ret; - -release_irq: - if(irq>=0) - free_irq(irq, pdev); -unregister_win1fb: - unregister_framebuffer(inf->win1fb); -release_win0fb: - if(inf->win0fb) - framebuffer_release(inf->win0fb); - inf->win0fb = NULL; -release_cmap: - if(&inf->win1fb->cmap) - fb_dealloc_cmap(&inf->win1fb->cmap); -release_win1fb: - if(inf->win1fb) - framebuffer_release(inf->win1fb); - inf->win1fb = NULL; -release_drvdata: - if(inf && inf->reg_vir_base) - iounmap(inf->reg_vir_base); - if(inf && mem) - release_mem_region(inf->reg_phy_base, inf->len); - if(inf) - kfree(inf); - platform_set_drvdata(pdev, NULL); - return ret; -} - -static int rk2818fb_remove(struct platform_device *pdev) -{ - struct rk2818fb_inf *inf = platform_get_drvdata(pdev); - struct fb_info *info = NULL; - //pm_message_t msg; - struct rk2818fb_info *mach_info = NULL; - int irq = 0; - - fbprintk(">>>>>> %s : %s\n", __FILE__, __FUNCTION__); - - if(!inf) { - printk("inf==0, rk2818_fb_remove fail! \n"); - return -EINVAL; - } - - irq = platform_get_irq(pdev, 0); - if (irq >0) - { - free_irq(irq, pdev); - } - - mach_info = pdev->dev.platform_data; - if(mach_info->mcu_fmk_pin) - { - free_irq(gpio_to_irq(mach_info->mcu_fmk_pin), pdev); - } - - set_lcd_pin(pdev, 0); - - // blank the lcdc - if(inf->win0fb) - win0fb_blank(FB_BLANK_POWERDOWN, inf->win0fb); - if(inf->win1fb) - win1fb_blank(FB_BLANK_POWERDOWN, inf->win1fb); - - // suspend the lcdc - //rk2818fb_suspend(pdev, msg); - - // unmap memory and release framebuffer - if(inf->win0fb) { - info = inf->win0fb; - if (info->screen_base) { - dma_free_writecombine(NULL, PAGE_ALIGN(info->fix.smem_len),info->screen_base, info->fix.smem_start); - info->screen_base = 0; - info->fix.smem_start = 0; - info->fix.smem_len = 0; - } - unregister_framebuffer(inf->win0fb); - framebuffer_release(inf->win0fb); - inf->win0fb = NULL; - } - if(inf->win1fb) { - info = inf->win1fb; - if (info->screen_base) { - dma_free_writecombine(NULL, PAGE_ALIGN(info->fix.smem_len),info->screen_base, info->fix.smem_start); - info->screen_base = 0; - info->fix.smem_start = 0; - info->fix.smem_len = 0; - } - unregister_framebuffer(inf->win1fb); - framebuffer_release(inf->win1fb); - inf->win1fb = NULL; - } - - #ifdef CONFIG_CPU_FREQ - cpufreq_unregister_notifier(&inf->freq_transition, CPUFREQ_TRANSITION_NOTIFIER); - #endif - - if (inf->clk) - { - clk_disable(inf->clk); - clk_put(inf->clk); - inf->clk = NULL; - } - if (inf->dclk) - { - clk_disable(inf->dclk); - clk_put(inf->dclk); - inf->dclk = NULL; - } - - kfree(inf); - platform_set_drvdata(pdev, NULL); - - return 0; -} - -static void rk2818fb_shutdown(struct platform_device *pdev) -{ - struct rk2818fb_inf *inf = platform_get_drvdata(pdev); - mdelay(300); - //printk("----------------------------rk2818fb_shutdown----------------------------\n"); - set_lcd_pin(pdev, 0); - if (inf->dclk) - { - clk_disable(inf->dclk); - } - if (inf->clk) - { - clk_disable(inf->clk); - } -} - -static struct platform_driver rk2818fb_driver = { - .probe = rk2818fb_probe, - .remove = rk2818fb_remove, - .driver = { - .name = "rk2818-fb", - .owner = THIS_MODULE, - }, - .shutdown = rk2818fb_shutdown, -}; - -static int __init rk2818fb_init(void) -{ - return platform_driver_register(&rk2818fb_driver); -} - -static void __exit rk2818fb_exit(void) -{ - platform_driver_unregister(&rk2818fb_driver); -} - -//subsys_initcall(rk2818fb_init); - -module_init(rk2818fb_init); -module_exit(rk2818fb_exit); - - -MODULE_AUTHOR(" zyw@rock-chips.com"); -MODULE_DESCRIPTION("Driver for rk2818 fb device"); -MODULE_LICENSE("GPL"); - - diff --git a/drivers/video/rk2818_fb.h b/drivers/video/rk2818_fb.h deleted file mode 100755 index ad4d1ed8404f..000000000000 --- a/drivers/video/rk2818_fb.h +++ /dev/null @@ -1,416 +0,0 @@ -/* drivers/video/rk2818_fb.h - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __ARCH_ARM_MACH_RK2818_FB_H -#define __ARCH_ARM_MACH_RK2818_FB_H - -/******************************************************************** -** ºê¶¨Òå * -********************************************************************/ -/* ÊäÍùÆÁµÄÊý¾Ý¸ñʽ */ -#define OUT_P888 0 -#define OUT_P666 1 -#define OUT_P565 2 -#define OUT_S888x 4 -#define OUT_CCIR656 6 -#define OUT_S888 8 -#define OUT_S888DUMY 12 -#define OUT_P16BPP4 24 //Ä£Äⷽʽ,¿ØÖÆÆ÷²¢²»Ö§³Ö - -/* Low Bits Mask */ -#define m_WORDLO (0xffff<<0) -#define m_WORDHI (0xffff<<16) -#define v_WORDLO(x) (((x)&0xffff)<<0) -#define v_WORDHI(x) (((x)&0xffff)<<16) - -#define m_BIT11LO (0x7ff<<0) -#define m_BIT11HI (0x7ff<<16) -#define v_BIT11LO(x) (((x)&0x7ff)<<0) -#define v_BIT11HI(x) (((x)&0x7ff)<<16) - - -/* SYS_CONFIG */ -#define m_W1_FORMAT (1<<0) -#define m_W0_FORMAT (7<<1) -#define m_W1_ROLLER (1<<4) -#define m_W0_ROLLER (1<<5) -#define m_INTERIACE_EN (1<<6) -#define m_MPEG2_I2P_EN (1<<7) -#define m_W0_ROTATE (1<<8) -#define m_W1_ENABLE (1<<9) -#define m_W0_ENABLE (1<<10) -#define m_HWC_ENABLE (1<<11) -#define m_HWC_RELOAD_EN (1<<12) -#define m_W1_INTERLACE_READ (1<<13) -#define m_W0_INTERLACE_READ (1<<14) -#define m_STANDBY (1<<15) -#define m_W1_HWC_INCR (31<<16) -#define m_W1_HWC_BURST (7<<21) -#define m_W0_INCR (31<<24) -#define m_W0_BURST (7<<29) -#define v_W1_FORMAT(x) (((x)&1)<<0) -#define v_W0_FORMAT(x) (((x)&7)<<1) -#define v_W1_ROLLER(x) (((x)&1)<<4) -#define v_W0_ROLLER(x) (((x)&1)<<5) -#define v_INTERIACE_EN(x) (((x)&1)<<6) -#define v_MPEG2_I2P_EN(x) (((x)&1)<<7) -#define v_W0_ROTATE(x) (((x)&1)<<8) -#define v_W1_ENABLE(x) (((x)&1)<<9) -#define v_W0_ENABLE(x) (((x)&1)<<10) -#define v_HWC_ENABLE(x) (((x)&1)<<11) -#define v_HWC_RELOAD_EN(x) (((x)&1)<<12) -#define v_W1_INTERLACE_READ(x) (((x)&1)<<13) -#define v_W0_INTERLACE_READ(x) (((x)&1)<<14) -#define v_STANDBY(x) (((x)&1)<<15) -#define v_W1_HWC_INCR(x) (((x)&31)<<16) -#define v_W1_HWC_BURST(x) (((x)&7)<<21) -#define v_W0_INCR(x) (((x)&31)<<24) -#define v_W0_BURST(x) (((x)&7)<<29) - -//LCDC_SWAP_CTRL -#define m_W1_565_RB_SWAP (1<<0) -#define m_W0_565_RB_SWAP (1<<1) -#define m_W0_YRGB_M8_SWAP (1<<2) -#define m_W0_YRGB_R_SHIFT_SWAP (1<<3) -#define m_W0_CBR_R_SHIFT_SWAP (1<<4) -#define m_W0_YRGB_16_SWAP (1<<5) -#define m_W0_YRGB_8_SWAP (1<<6) -#define m_W0_CBR_16_SWAP (1<<7) -#define m_W0_CBR_8_SWAP (1<<8) -#define m_W1_16_SWAP (1<<9) -#define m_W1_8_SWAP (1<<10) -#define m_W1_R_SHIFT_SWAP (1<<11) -#define m_OUTPUT_BG_SWAP (1<<12) -#define m_OUTPUT_RB_SWAP (1<<13) -#define m_OUTPUT_RG_SWAP (1<<14) -#define m_DELTA_SWAP (1<<15) -#define m_DUMMY_SWAP (1<<16) -#define m_W0_YRGB_HL8_SWAP (1<<17) -#define v_W1_565_RB_SWAP(x) (((x)&1)<<0) -#define v_W0_565_RB_SWAP(x) (((x)&1)<<1) -#define v_W0_YRGB_M8_SWAP(x) (((x)&1)<<2) -#define v_W0_YRGB_R_SHIFT_SWAP(x) (((x)&1)<<3) -#define v_W0_CBR_R_SHIFT_SWAP(x) (((x)&1)<<4) -#define v_W0_YRGB_16_SWAP(x) (((x)&1)<<5) -#define v_W0_YRGB_8_SWAP(x) (((x)&1)<<6) -#define v_W0_CBR_16_SWAP(x) (((x)&1)<<7) -#define v_W0_CBR_8_SWAP(x) (((x)&1)<<8) -#define v_W1_16_SWAP(x) (((x)&1)<<9) -#define v_W1_8_SWAP(x) (((x)&1)<<10) -#define v_W1_R_SHIFT_SWAP(x) (((x)&1)<<11) -#define v_OUTPUT_BG_SWAP(x) (((x)&1)<<12) -#define v_OUTPUT_RB_SWAP(x) (((x)&1)<<13) -#define v_OUTPUT_RG_SWAP(x) (((x)&1)<<14) -#define v_DELTA_SWAP(x) (((x)&1)<<15) -#define v_DUMMY_SWAP(x) (((x)&1)<<16) -#define v_W0_YRGB_HL8_SWAP(x) (((x)&1)<<17) - -//LCDC_MCU_TIMING_CTRL -#define m_MCU_WRITE_PERIOD (31<<0) -#define m_MCU_CS_ST (31<<5) -#define m_MCU_CS_END (31<<10) -#define m_MCU_RW_ST (31<<15) -#define m_MCU_RW_END (31<<20) -#define m_MCU_HOLD_STATUS (1<<26) -#define m_MCU_HOLDMODE_SELECT (1<<27) -#define m_MCU_HOLDMODE_FRAME_ST (1<<28) -#define m_MCU_RS_SELECT (1<<29) -#define m_MCU_BYPASSMODE_SELECT (1<<30) -#define m_MCU_OUTPUT_SELECT (1<<31) -#define v_MCU_WRITE_PERIOD(x) (((x)&31)<<0) -#define v_MCU_CS_ST(x) (((x)&31)<<5) -#define v_MCU_CS_END(x) (((x)&31)<<10) -#define v_MCU_RW_ST(x) (((x)&31)<<15) -#define v_MCU_RW_END(x) (((x)&31)<<20) -#define v_MCU_HOLD_STATUS(x) (((x)&1)<<26) -#define v_MCU_HOLDMODE_SELECT(x) (((x)&1)<<27) -#define v_MCU_HOLDMODE_FRAME_ST(x) (((x)&1)<<28) -#define v_MCU_RS_SELECT(x) (((x)&1)<<29) -#define v_MCU_BYPASSMODE_SELECT(x) (((x)&1)<<30) -#define v_MCU_OUTPUT_SELECT(x) (((x)&1)<<31) - -//LCDC_ BLEND_CTRL -#define m_W1_BLEND_EN (1<<0) -#define m_W0_BLEND_EN (1<<1) -#define m_HWC_BLEND_EN (1<<2) -#define m_W1_BLEND_FACTOR_SELECT (1<<3) -#define m_W0_BLEND_FACTOR_SELECT (1<<4) -#define m_W0W1_OVERLAY (1<<5) -#define m_HWC_BLEND_FACTOR (15<<12) -#define m_W1_BLEND_FACTOR (0xff<<16) -#define m_W0_BLEND_FACTOR (0xff<<24) -#define v_W1_BLEND_EN(x) (((x)&1)<<0) -#define v_W0_BLEND_EN(x) (((x)&1)<<1) -#define v_HWC_BLEND_EN(x) (((x)&1)<<2) -#define v_W1_BLEND_FACTOR_SELECT(x) (((x)&1)<<3) -#define v_W0_BLEND_FACTOR_SELECT(x) (((x)&1)<<4) -#define v_W0W1_OVERLAY(x) (((x)&1)<<5) -#define v_HWC_BLEND_FACTOR(x) (((x)&15)<<12) -#define v_W1_BLEND_FACTOR(x) (((x)&0xff)<<16) -#define v_W0_BLEND_FACTOR(x) (((x)&0xff)<<24) - -//LCDC_WIN0_COLOR_KEY_CTRL / LCDC_WIN1_COLOR_KEY_CTRL -#define m_KEYCOLOR (0xffffff<<0) -#define m_KEYCOLOR_B (0xff<<0) -#define m_KEYCOLOR_G (0xff<<8) -#define m_KEYCOLOR_R (0xff<<16) -#define m_COLORKEY_EN (1<<24) -#define v_KEYCOLOR(x) (((x)&0xffffff)<<0) -#define v_KEYCOLOR_B(x) (((x)&0xff)<<0) -#define v_KEYCOLOR_G(x) (((x)&0xff)<<8) -#define v_KEYCOLOR_R(x) (((x)&0xff)<<16) -#define v_COLORKEY_EN(x) (((x)&1)<<24) - -//LCDC_DEFLICKER_SCL_OFFSET -#define m_W0_YRGB_VSD_OFFSET (0xff<<0) -#define m_W0_YRGB_VSP_OFFSET (0xff<<8) -#define m_W1_VSD_OFFSET (0xff<<16) -#define m_W1_VSP_OFFSET (0xff<<24) -#define v_W0_YRGB_VSD_OFFSET(x) (((x)&0xff)<<0) -#define v_W0_YRGB_VSP_OFFSET(x) (((x)&0xff)<<8) -#define v_W1_VSD_OFFSET(x) (((x)&0xff)<<16) -#define v_W1_VSP_OFFSET(x) (((x)&0xff)<<24) - -//LCDC_DSP_CTRL_REG0 -#define m_DISPLAY_FORMAT (0xf<<0) -#define m_HSYNC_POLARITY (1<<4) -#define m_VSYNC_POLARITY (1<<5) -#define m_DEN_POLARITY (1<<6) -#define m_DCLK_POLARITY (1<<7) -#define m_COLOR_SPACE_CONVERSION (3<<8) -#define m_I2P_THRESHOLD_Y (0x3f<<10) -#define m_I2P_THRESHOLD_CBR (0x3f<<16) -#define m_565_TO_888_REPLICATION_EN (1<<22) -#define m_DITHERING_MODE (1<<23) -#define m_DITHERING_EN (1<<24) -#define m_DROP_LINE_W1 (1<<25) -#define m_DROP_LINE_W0 (1<<26) -#define m_I2P_CUR_POLARITY (1<<27) -#define m_INTERLACE_FIELD_POLARITY (1<<28) -#define m_YUV_CLIP_MODE (1<<29) -#define m_I2P_FILTER_EN (1<<30) -#define m_I2P_FILTER_PARAM (1<<31) -#define v_DISPLAY_FORMAT(x) (((x)&0xf)<<0) -#define v_HSYNC_POLARITY(x) (((x)&1)<<4) -#define v_VSYNC_POLARITY(x) (((x)&1)<<5) -#define v_DEN_POLARITY(x) (((x)&1)<<6) -#define v_DCLK_POLARITY(x) (((x)&1)<<7) -#define v_COLOR_SPACE_CONVERSION(x) (((x)&3)<<8) -#define v_I2P_THRESHOLD_Y(x) (((x)&0x3f)<<10) -#define v_I2P_THRESHOLD_CBR(x) (((x)&0x3f)<<16) -#define v_565_TO_888_REPLICATION_EN(x) (((x)&1)<<22) -#define v_DITHERING_MODE(x) (((x)&1)<<23) -#define v_DITHERING_EN(x) (((x)&1)<<24) -#define v_DROP_LINE_W1(x) (((x)&1)<<25) -#define v_DROP_LINE_W0(x) (((x)&1)<<26) -#define v_I2P_CUR_POLARITY(x) (((x)&1)<<27) -#define v_INTERLACE_FIELD_POLARITY(x) (((x)&1)<<28) -#define v_YUV_CLIP_MODE(x) (((x)&1)<<29) -#define v_I2P_FILTER_EN(x) (((x)&1)<<30) -#define v_I2P_FILTER_PARAM(x) (((x)&1)<<31) - -//LCDC_DSP_CTRL_REG1 -#define m_BG_COLOR (0xffffff<<0) -#define m_BG_B (0xff<<0) -#define m_BG_G (0xff<<8) -#define m_BG_R (0xff<<16) -#define m_BLANK_MODE (1<<24) -#define m_BLACK_MODE (1<<25) -#define m_W1_SD_DEFLICKER_EN (1<<26) -#define m_W1_SP_DEFLICKER_EN (1<<27) -#define m_W0CR_SD_DEFLICKER_EN (1<<28) -#define m_W0CR_SP_DEFLICKER_EN (1<<29) -#define m_W0YRGB_SD_DEFLICKER_EN (1<<30) -#define m_W0YRGB_SP_DEFLICKER_EN (1<<31) -#define v_BG_COLOR(x) (((x)&0xffffff)<<0) -#define v_BG_B(x) (((x)&0xff)<<0) -#define v_BG_G(x) (((x)&0xff)<<8) -#define v_BG_R(x) (((x)&0xff)<<16) -#define v_BLANK_MODE(x) (((x)&1)<<24) -#define v_BLACK_MODE(x) (((x)&1)<<25) -#define v_W1_SD_DEFLICKER_EN(x) (((x)&1)<<26) -#define v_W1_SP_DEFLICKER_EN(x) (((x)&1)<<27) -#define v_W0CR_SD_DEFLICKER_EN(x) (((x)&1)<<28) -#define v_W0CR_SP_DEFLICKER_EN(x) (((x)&1)<<29) -#define v_W0YRGB_SD_DEFLICKER_EN(x) (((x)&1)<<30) -#define v_W0YRGB_SP_DEFLICKER_EN(x) (((x)&1)<<31) - -//LCDC_INT_STATUS -#define m_HOR_START (1<<0) -#define m_FRM_START (1<<1) -#define m_SCANNING_FLAG (1<<2) -#define m_HOR_STARTMASK (1<<3) -#define m_FRM_STARTMASK (1<<4) -#define m_SCANNING_MASK (1<<5) -#define m_HOR_STARTCLEAR (1<<6) -#define m_FRM_STARTCLEAR (1<<7) -#define m_SCANNING_CLEAR (1<<8) -#define m_SCAN_LINE_NUM (0x7ff<<9) -#define v_HOR_START(x) (((x)&1)<<0) -#define v_FRM_START(x) (((x)&1)<<1) -#define v_SCANNING_FLAG(x) (((x)&1)<<2) -#define v_HOR_STARTMASK(x) (((x)&1)<<3) -#define v_FRM_STARTMASK(x) (((x)&1)<<4) -#define v_SCANNING_MASK(x) (((x)&1)<<5) -#define v_HOR_STARTCLEAR(x) (((x)&1)<<6) -#define v_FRM_STARTCLEAR(x) (((x)&1)<<7) -#define v_SCANNING_CLEAR(x) (((x)&1)<<8) -#define v_SCAN_LINE_NUM(x) (((x)&0x7ff)<<9) - -#define m_VIRWIDTH (0xffff<<0) -#define m_VIRHEIGHT (0xffff<<16) -#define v_VIRWIDTH(x) (((x)&0xffff)<<0) -#define v_VIRHEIGHT(x) (((x)&0xffff)<<16) - -#define m_ACTWIDTH (0xffff<<0) -#define m_ACTHEIGHT (0xffff<<16) -#define v_ACTWIDTH(x) (((x)&0xffff)<<0) -#define v_ACTHEIGHT(x) (((x)&0xffff)<<16) - -#define m_VIRST_X (0xffff<<0) -#define m_VIRST_Y (0xffff<<16) -#define v_VIRST_X(x) (((x)&0xffff)<<0) -#define v_VIRST_Y(x) (((x)&0xffff)<<16) - -#define m_PANELST_X (0x3ff<<0) -#define m_PANELST_Y (0x3ff<<16) -#define v_PANELST_X(x) (((x)&0x3ff)<<0) -#define v_PANELST_Y(x) (((x)&0x3ff)<<16) - -#define m_PANELWIDTH (0x3ff<<0) -#define m_PANELHEIGHT (0x3ff<<16) -#define v_PANELWIDTH(x) (((x)&0x3ff)<<0) -#define v_PANELHEIGHT(x) (((x)&0x3ff)<<16) - -#define m_HWC_B (0xff<<0) -#define m_HWC_G (0xff<<8) -#define m_HWC_R (0xff<<16) -#define m_W0_YRGB_HSP_OFFSET (0xff<<24) -#define m_W0_YRGB_HSD_OFFSET (0xff<<24) -#define v_HWC_B(x) (((x)&0xff)<<0) -#define v_HWC_G(x) (((x)&0xff)<<8) -#define v_HWC_R(x) (((x)&0xff)<<16) -#define v_W0_YRGB_HSP_OFFSET(x) (((x)&0xff)<<24) -#define v_W0_YRGB_HSD_OFFSET(x) (((x)&0xff)<<24) - - -//Panel display scanning -#define m_PANEL_HSYNC_WIDTH (0x3ff<<0) -#define m_PANEL_HORIZONTAL_PERIOD (0x3ff<<16) -#define v_PANEL_HSYNC_WIDTH(x) (((x)&0x3ff)<<0) -#define v_PANEL_HORIZONTAL_PERIOD(x) (((x)&0x3ff)<<16) - -#define m_PANEL_END (0x3ff<<0) -#define m_PANEL_START (0x3ff<<16) -#define v_PANEL_END(x) (((x)&0x3ff)<<0) -#define v_PANEL_START(x) (((x)&0x3ff)<<16) - -#define m_PANEL_VSYNC_WIDTH (0x3ff<<0) -#define m_PANEL_VERTICAL_PERIOD (0x3ff<<16) -#define v_PANEL_VSYNC_WIDTH(x) (((x)&0x3ff)<<0) -#define v_PANEL_VERTICAL_PERIOD(x) (((x)&0x3ff)<<16) -//----------- - -#define m_HSCALE_FACTOR (0xffff<<0) -#define m_VSCALE_FACTOR (0xffff<<16) -#define v_HSCALE_FACTOR(x) (((x)&0xffff)<<0) -#define v_VSCALE_FACTOR(x) (((x)&0xffff)<<16) - -#define m_W0_CBR_HSD_OFFSET (0xff<<0) -#define m_W0_CBR_HSP_OFFSET (0xff<<8) -#define m_W0_CBR_VSD_OFFSET (0xff<<16) -#define m_W0_CBR_VSP_OFFSET (0xff<<24) -#define v_W0_CBR_HSD_OFFSET(x) (((x)&0xff)<<0) -#define v_W0_CBR_HSP_OFFSET(x) (((x)&0xff)<<8) -#define v_W0_CBR_VSD_OFFSET(x) (((x)&0xff)<<16) -#define v_W0_CBR_VSP_OFFSET(x) (((x)&0xff)<<24) - - -#define FB0_IOCTL_STOP_TIMER_FLUSH 0x6001 -#define FB0_IOCTL_SET_PANEL 0x6002 - -#define FB1_IOCTL_GET_PANEL_SIZE 0x5001 -#define FB1_IOCTL_SET_YUV_ADDR 0x5002 -//#define FB1_TOCTL_SET_MCU_DIR 0x5003 -#define FB1_IOCTL_SET_ROTATE 0x5003 -#define FB1_IOCTL_SET_I2P_ODD_ADDR 0x5005 -#define FB1_IOCTL_SET_I2P_EVEN_ADDR 0x5006 - - -/******************************************************************** -** ½á¹¹¶¨Òå * -********************************************************************/ -/* LCDCµÄ¼Ä´æÆ÷½á¹¹ */ -typedef volatile struct tagLCDC_REG -{ - /* offset 0x00~0xc0 */ - unsigned int SYS_CONFIG; //SYSTEM configure register - unsigned int SWAP_CTRL; //Data SWAP control - unsigned int MCU_TIMING_CTRL; //MCU TIMING control register - unsigned int BLEND_CTRL; //Blending control register - unsigned int WIN0_COLOR_KEY_CTRL; //Win0 blending control register - unsigned int WIN1_COLOR_KEY_CTRL; //Win1 blending control register - unsigned int DEFLICKER_SCL_OFFSET; //Deflick scaling start point offset - unsigned int DSP_CTRL0; //Display control register0 - unsigned int DSP_CTRL1; //Display control register1 - unsigned int INT_STATUS; //Interrupt status register - unsigned int WIN0_VIR; //WIN0 virtual display width/height - unsigned int WIN0_YRGB_MST; //Win0 active YRGB memory start address - unsigned int WIN0_CBR_MST; //Win0 active Cbr memory start address - unsigned int WIN0_ACT_INFO; //Win0 active window width/height - unsigned int WIN0_ROLLER_INFO; //Win0 x and y value of start point in roller mode - unsigned int WIN0_DSP_ST; //Win0 display start point on panel - unsigned int WIN0_DSP_INFO; //Win0 display width/height on panel - unsigned int WIN1_VIR; //Win1 virtual display width/height - unsigned int WIN1_YRGB_MST; //Win1 active memory start address - unsigned int WIN1_ACT_INFO; //Win1 active width /height - unsigned int WIN1_ROLLER_INFO; //Win1 x and y value of start point in roller mode - unsigned int WIN1_DSP_ST; //Win1 display start point on panel - unsigned int WIN1_DSP_INFO; //Win1 display width/height on panel - unsigned int HWC_MST; //HWC memory start address - unsigned int HWC_DSP_ST; //HWC display start point on panel - unsigned int HWC_COLOR_LUT0; //Hardware cursor color 2¡¯b01 look up table 0 - unsigned int HWC_COLOR_LUT1; //Hardware cursor color 2¡¯b10 look up table 1 - unsigned int HWC_COLOR_LUT2; //Hardware cursor color 2¡¯b11 look up table 2 - unsigned int DSP_HTOTAL_HS_END; //Panel scanning horizontal width and hsync pulse end point - unsigned int DSP_HACT_ST_END; //Panel active horizontal scanning start/end point - unsigned int DSP_VTOTAL_VS_END; //Panel scanning vertical height and vsync pulse end point - unsigned int DSP_VACT_ST_END; //Panel active vertical scanning start/end point - unsigned int DSP_VS_ST_END_F1; //Vertical scanning start point and vsync pulse end point of even filed in interlace mode - unsigned int DSP_VACT_ST_END_F1; //Vertical scanning active start/end point of even filed in interlace mode - unsigned int WIN0_SD_FACTOR_Y; //Win0 YRGB scaling down factor setting - unsigned int WIN0_SP_FACTOR_Y; //Win0 YRGB scaling up factor setting - unsigned int WIN0_CBR_SCL_OFFSET; //Win0 Cbr scaling start point offset - unsigned int WIN1_SCL_FACTOR; //Win1 scaling factor setting - unsigned int I2P_REF0_MST_Y; //I2P field 0 memory start address - unsigned int I2P_REF0_MST_CBR; //I2P field 0 memory start address - unsigned int I2P_REF1_MST_Y; //I2P field 2 memory start address - unsigned int I2P_REF1_MST_CBR; //I2P field 2 memory start address - unsigned int WIN0_YRGB_VIR_MST; //Win0 virtual memory start address - unsigned int WIN0_CBR_VIR_MST; //Win0 virtual memory start address - unsigned int WIN1_VIR_MST; //Win1 virtual memory start address - unsigned int WIN0_SD_FACTOR_CBR; //Win0 CBR scaling down factor setting - unsigned int WIN0_SP_FACTOR_CBR; //Win0 CBR scaling up factor setting - unsigned int reserved0; - unsigned int REG_CFG_DONE; //REGISTER CONFIG FINISH - unsigned int reserved1[(0x500-0xc4)/4]; - unsigned int MCU_BYPASS_WPORT; //MCU BYPASS MODE, DATA Write Port -} LCDC_REG, *pLCDC_REG; - - -extern void __init rk2818_add_device_lcdc(void); -extern int mcu_ioctl(unsigned int cmd, unsigned long arg); - -#endif diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig index 40b0f7beab08..88ea5eb97c19 100644 --- a/sound/soc/Kconfig +++ b/sound/soc/Kconfig @@ -36,7 +36,6 @@ source "sound/soc/s3c24xx/Kconfig" source "sound/soc/s6000/Kconfig" source "sound/soc/sh/Kconfig" source "sound/soc/txx9/Kconfig" -source "sound/soc/rk2818/Kconfig" source "sound/soc/rk29/Kconfig" # Supported codecs source "sound/soc/codecs/Kconfig" diff --git a/sound/soc/Makefile b/sound/soc/Makefile index ffa30c5832ae..096b7a6aaee1 100644 --- a/sound/soc/Makefile +++ b/sound/soc/Makefile @@ -14,5 +14,4 @@ obj-$(CONFIG_SND_SOC) += s3c24xx/ obj-$(CONFIG_SND_SOC) += s6000/ obj-$(CONFIG_SND_SOC) += sh/ obj-$(CONFIG_SND_SOC) += txx9/ -obj-$(CONFIG_SND_SOC) += rk2818/ -obj-$(CONFIG_SND_SOC) += rk29/ +obj-$(CONFIG_SND_SOC) += rk29/ diff --git a/sound/soc/rk2818/Kconfig b/sound/soc/rk2818/Kconfig deleted file mode 100755 index 304ac0a3ba51..000000000000 --- a/sound/soc/rk2818/Kconfig +++ /dev/null @@ -1,139 +0,0 @@ -config SND_ROCKCHIP_SOC - tristate "SoC Audio for the rockchip RK2818 System-on-Chip" - depends on ARCH_RK2818 && SND_SOC - help - Say Y or M if you want to add support for codecs attached to - the ROCKCHIP IIS interface. You will also need - to select the audio interfaces to support below. - -config SND_ROCKCHIP_SOC_I2S - tristate - -config SND_ROCKCHIP_SOC_WM8988 - tristate "SoC I2S Audio support for rockchip - WM8988" - depends on SND_ROCKCHIP_SOC - select SND_ROCKCHIP_SOC_I2S - select SND_SOC_WM8988 - help - Say Y if you want to add support for SoC audio on rockchip - with the WM8988. - -config SND_ROCKCHIP_SOC_WM8994 - tristate "SoC I2S Audio support for rockchip - WM8994" - depends on SND_ROCKCHIP_SOC - select SND_ROCKCHIP_SOC_I2S - select SND_SOC_WM8994 - help - Say Y if you want to add support for SoC audio on rockchip - with the WM8994. - -if SND_ROCKCHIP_SOC_WM8994 -choice - prompt "Chose earpiece type" - - config SND_INSIDE_EARPIECE - tristate "Inside earpiece" - - config SND_OUTSIDE_EARPIECE - tristate "Outside earpiece" - - config SND_NO_EARPIECE - tristate "No earpiece" -endchoice - -choice - prompt "Chose BB input signal type" - - config SND_BB_NORMAL_INPUT - tristate "BB normal singnal input" - - config SND_BB_DIFFERENTIAL_INPUT - tristate "BB differential singnal input" - -endchoice - -config WM8994_SPEAKER_INCALL_VOL - default 0 - int "Setting the wm8994 speaker incall vol" - help - -21dB to 12dB - -config WM8994_SPEAKER_INCALL_MIC_VOL - default -9 - int "Setting the wm8994 speaker incall mic vol" - help - -22dB to 30dB - -config WM8994_SPEAKER_NORMAL_VOL - default 6 - int "Setting the wm8994 speaker normal vol" - help - -57dB to 18dB - -if SND_INSIDE_EARPIECE||SND_OUTSIDE_EARPIECE -config WM8994_EARPIECE_INCALL_VOL - default 0 - int "Setting the wm8994 earpiece incall vol(normal)" - help - -27dB to 30dB -endif - -if SND_BB_DIFFERENTIAL_INPUT -config WM8994_HEADSET_INCALL_VOL - default 6 - int "Setting the wm8994 headset incall vol" - help - -12dB to 6dB -endif - -config WM8994_HEADSET_INCALL_MIC_VOL - default -6 - int "Setting the wm8994 headset incall mic vol" - help - -22dB to 30dB - -config WM8994_HEADSET_NORMAL_VOL - default 6 - int "Setting the wm8994 headset normal vol" - help - -57dB to 6dB - -config WM8994_BT_INCALL_VOL - default 0 - int "Setting the wm8994 BT incall vol" - help - 0dB or 30dB - -config WM8994_BT_INCALL_MIC_VOL - default 0 - int "Setting the wm8994 BT incall mic vol" - help - -57dB to 6dB - -config WM8994_RECORDER_VOL - default 50 - int "Setting the wm8994 recorder vol" - help - -16dB to 60dB -endif - -config SND_ROCKCHIP_SOC_RK1000 - tristate "SoC I2S Audio support for rockchip - RK1000" - depends on SND_ROCKCHIP_SOC && RK1000_CONTROL - select SND_ROCKCHIP_SOC_I2S - select SND_SOC_RK1000 - help - Say Y if you want to add support for SoC audio on rockchip - with the RK1000. - -if SND_ROCKCHIP_SOC_WM8988 || SND_ROCKCHIP_SOC_RK1000 || SND_ROCKCHIP_SOC_WM8994 -choice - prompt "Set i2s type" - - config SND_CODEC_SOC_MASTER - tristate "Codec run in Master" - - config SND_CODEC_SOC_SLAVE - tristate "Codec run in Slave" -endchoice -endif diff --git a/sound/soc/rk2818/Makefile b/sound/soc/rk2818/Makefile deleted file mode 100755 index 5aa86f729b5e..000000000000 --- a/sound/soc/rk2818/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# ROCKCHIP Platform Support -snd-soc-rockchip-objs := rk2818_pcm.o -snd-soc-rockchip-i2s-objs := rk2818_i2s.o - -obj-$(CONFIG_SND_ROCKCHIP_SOC) += snd-soc-rockchip.o -obj-$(CONFIG_SND_ROCKCHIP_SOC_I2S) += snd-soc-rockchip-i2s.o - -# ROCKCHIP Machine Support -snd-soc-wm8988-objs := rk2818_wm8988.o -snd-soc-rk1000-objs := rk2818_rk1000codec.o -snd-soc-wm8994-objs := rk2818_wm8994.o - -obj-$(CONFIG_SND_ROCKCHIP_SOC_WM8994) += snd-soc-wm8994.o -obj-$(CONFIG_SND_ROCKCHIP_SOC_WM8988) += snd-soc-wm8988.o -obj-$(CONFIG_SND_ROCKCHIP_SOC_RK1000) += snd-soc-rk1000.o \ No newline at end of file diff --git a/sound/soc/rk2818/rk2818_i2s.c b/sound/soc/rk2818/rk2818_i2s.c deleted file mode 100755 index 05804af27657..000000000000 --- a/sound/soc/rk2818/rk2818_i2s.c +++ /dev/null @@ -1,435 +0,0 @@ -/* - * rk2818_i2s.c -- ALSA SoC ROCKCHIP IIS Audio Layer Platform driver - * - * Driver for rockchip iis audio - * Copyright (C) 2009 lhh - * - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "rk2818_pcm.h" -#include "rk2818_i2s.h" - - -#if 0 -#define DBG(x...) printk(KERN_INFO x) -#else -#define DBG(x...) do { } while (0) -#endif - -#define pheadi2s ((pI2S_REG)(i2s->regs)) - -struct rockchip_i2s_info { - struct device *dev; - void __iomem *regs; - struct clk *iis_clk; - struct clk *iis_pclk; - - u32 suspend_iismod; - u32 suspend_iiscon; - u32 suspend_iispsr; -}; - -static struct rockchip_i2s_info rockchip_i2s; - -static struct rockchip_dma_client rockchip_dma_client_out = { - //.name = "I2S PCM Stereo out" - .name = "i2s" -}; - -static struct rockchip_dma_client rockchip_dma_client_in = { - //.name = "I2S PCM Stereo in" - .name = "i2s" -}; - -static struct rockchip_pcm_dma_params rockchip_i2s_pcm_stereo_out = { - .client = &rockchip_dma_client_out, - .channel = RK28_DMA_CH4, ///0, //DMACH_I2S_OUT, - .dma_addr = RK2818_I2S_PHYS + I2S_TXR_BUFF, - .dma_size = 4, -}; - -static struct rockchip_pcm_dma_params rockchip_i2s_pcm_stereo_in = { - .client = &rockchip_dma_client_in, - .channel = RK28_DMA_CH5, ///1, //DMACH_I2S_IN, - .dma_addr = RK2818_I2S_PHYS + I2S_RXR_BUFF, - .dma_size = 4, -}; - - - - -/* - *Turn on or off the transmission path. - */ -static void rockchip_snd_txctrl(int on) -{ - struct rockchip_i2s_info *i2s = &rockchip_i2s; - u32 opr,fifosts; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - - opr = readl(&(pheadi2s->I2S_OPR)); - fifosts = readl(&(pheadi2s->I2S_FIFOSTS)); - fifosts = (fifosts & (~(0x0f<<16))) | TX_HALF_FULL | RX_HALF_FULL; - writel(fifosts, &(pheadi2s->I2S_FIFOSTS)); - if (on) - { - opr = (opr & (~(RESET_RX | I2S_DMA_REQ2_DISABLE | TX_START | RX_START))) | (RESET_TX | I2S_DMA_REQ1_DISABLE); - writel(opr, &(pheadi2s->I2S_OPR)); - udelay(5); - opr = (opr & (~(I2S_DMA_REQ1_DISABLE | I2S_DMA_REQ1_RX_ENABLE | RX_START))) | I2S_DMA_REQ1_ENABLE | I2S_DMA_REQ1_TX_ENABLE | TX_START; - writel(opr, &(pheadi2s->I2S_OPR)); - } - else - { - opr = (opr & (~TX_START)) | I2S_DMA_REQ1_DISABLE; - writel(opr, &(pheadi2s->I2S_OPR)); - } -} -static void rockchip_snd_rxctrl(int on) -{ - struct rockchip_i2s_info *i2s = &rockchip_i2s; - u32 opr,fifosts; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - opr = readl(&(pheadi2s->I2S_OPR)); - fifosts = readl(&(pheadi2s->I2S_FIFOSTS)); - fifosts = (fifosts & (~(0x0f<<16))) | TX_HALF_FULL | RX_HALF_FULL; - writel(fifosts, &(pheadi2s->I2S_FIFOSTS)); - if (on) - { - opr = (opr & (~(RESET_TX | I2S_DMA_REQ1_DISABLE| TX_START | RX_START))) | (RESET_RX | I2S_DMA_REQ2_DISABLE); - writel(opr, &(pheadi2s->I2S_OPR)); - udelay(5); - opr = (opr & (~(I2S_DMA_REQ2_DISABLE | I2S_DMA_REQ2_TX_ENABLE | TX_START))) | I2S_DMA_REQ2_ENABLE | I2S_DMA_REQ2_RX_ENABLE | RX_START; - writel(opr, &(pheadi2s->I2S_OPR)); - } - else - { - opr = (opr & (~RX_START)) | I2S_DMA_REQ2_DISABLE; - writel(opr, &(pheadi2s->I2S_OPR)); - } -} - -/* - * Set Rockchip I2S DAI format - */ -static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai, - unsigned int fmt) -{ - struct rockchip_i2s_info *i2s = &rockchip_i2s; - u32 tx_ctl,rx_ctl; - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - - tx_ctl = readl(&(pheadi2s->I2S_TXCTL)); - tx_ctl &= (~MASTER_MODE); - - switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { - case SND_SOC_DAIFMT_CBM_CFM: - tx_ctl |= MASTER_MODE; - break; - case SND_SOC_DAIFMT_CBS_CFS: - tx_ctl |= SLAVE_MODE; - break; - default: - DBG("unknwon master/slave format\n"); - return -EINVAL; - } - tx_ctl &= ~IISMOD_SDF_MASK; - - switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { - case SND_SOC_DAIFMT_RIGHT_J: - tx_ctl |= RIGHT_JUSTIFIED; - break; - case SND_SOC_DAIFMT_LEFT_J: - tx_ctl |= LEFT_JUSTIFIED; - break; - case SND_SOC_DAIFMT_I2S: - tx_ctl |= I2S_MODE; - break; - default: - DBG("Unknown data format\n"); - return -EINVAL; - } - tx_ctl = tx_ctl & (~(0xff<<8)) & (~(0x03<<16)) & (~(1<<3)); - tx_ctl = tx_ctl | OVERSAMPLING_RATE_64FS | SCK_RATE4 | STEREO_MODE; - writel(tx_ctl, &(pheadi2s->I2S_TXCTL)); - rx_ctl = tx_ctl | CLEAR_RXFIFO; - writel(rx_ctl, &(pheadi2s->I2S_RXCTL)); - return 0; -} - -static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) -{ - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct rockchip_i2s_info *i2s = &rockchip_i2s; - u32 iismod; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - /*by Vincent Hsiung for EQ Vol Change*/ - #define HW_PARAMS_FLAG_EQVOL_ON 0x21 - #define HW_PARAMS_FLAG_EQVOL_OFF 0x22 - if ((params->flags == HW_PARAMS_FLAG_EQVOL_ON)||(params->flags == HW_PARAMS_FLAG_EQVOL_OFF)) - { - return 0; - } - - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) - rtd->dai->cpu_dai->dma_data = &rockchip_i2s_pcm_stereo_out; - else - rtd->dai->cpu_dai->dma_data = &rockchip_i2s_pcm_stereo_in; - - /* Working copies of register */ - iismod = readl(&(pheadi2s->I2S_TXCTL)); - iismod &= (~SAMPLE_DATA_MASK); - switch (params_format(params)) { - case SNDRV_PCM_FORMAT_S8: - iismod |= SAMPLE_DATA_8bit; - break; - case SNDRV_PCM_FORMAT_S16_LE: - iismod |= SAMPLE_DATA_16bit; - break; - } - /*stereo mode MCLK/SCK=4*/ - iismod = iismod & (~(0xff<<8)) & (~(0x03<<16)) & (~(1<<3)); - iismod = iismod | OVERSAMPLING_RATE_64FS | SCK_RATE4 | STEREO_MODE; - - writel(iismod, &(pheadi2s->I2S_TXCTL)); - iismod = iismod | CLEAR_RXFIFO; - writel(iismod, &(pheadi2s->I2S_RXCTL)); - return 0; -} - - -static int rockchip_i2s_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) -{ - int ret = 0; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - - switch (cmd) { - case SNDRV_PCM_TRIGGER_START: - case SNDRV_PCM_TRIGGER_RESUME: - case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: - if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) - rockchip_snd_rxctrl(1); - else - rockchip_snd_txctrl(1); - break; - case SNDRV_PCM_TRIGGER_STOP: - case SNDRV_PCM_TRIGGER_SUSPEND: - case SNDRV_PCM_TRIGGER_PAUSE_PUSH: - if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) - rockchip_snd_rxctrl(0); - else - rockchip_snd_txctrl(0); - break; - default: - ret = -EINVAL; - break; - } - - return ret; -} -/* - * Set Rockchip Clock source - */ -static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, - int clk_id, unsigned int freq, int dir) -{ - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - /*add scu clk source and enable clk*/ - - return 0; -} - -/* - * Set Rockchip Clock dividers - */ -static int rockchip_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai, - int div_id, int div) -{ - //u32 reg; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - /*when i2s in master mode ,must set codec pll div*/ - switch (div_id) { - case ROCKCHIP_DIV_BCLK: - //reg = readl(&(pheadi2s->I2S_TXCTL)) & ~S3C2410_IISMOD_FS_MASK; - //writel(reg | div, &(pheadi2s->I2S_TXCTL)); - break; - case ROCKCHIP_DIV_MCLK: - //reg = readl(rockchip_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS); - //writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD); - break; - case ROCKCHIP_DIV_PRESCALER: - //writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR); - //reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON); - //writel(reg | S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON); - break; - default: - return -EINVAL; - } - return 0; -} -/* - * To avoid duplicating clock code, allow machine driver to - * get the clockrate from here. - */ -u32 rockchip_i2s_get_clockrate(void) -{ - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - return 0; ///clk_get_rate(s3c24xx_i2s.iis_clk); -} -EXPORT_SYMBOL_GPL(rockchip_i2s_get_clockrate); - -static int rockchip_i2s_dai_probe(struct platform_device *pdev, struct snd_soc_dai *dai) -{ - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - - rockchip_snd_txctrl(0); - rockchip_snd_rxctrl(0); - - return 0; -} - -#ifdef CONFIG_PM -int rockchip_i2s_suspend(struct snd_soc_dai *cpu_dai) -{ - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - //clk_disable(clk); - return 0; -} - -int rockchip_i2s_resume(struct snd_soc_dai *cpu_dai) -{ - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - //clk_enable(clk); - return 0; -} -#else -#define rockchip_i2s_suspend NULL -#define rockchip_i2s_resume NULL -#endif - -#define ROCKCHIP_I2S_RATES SNDRV_PCM_RATE_48000 - -static struct snd_soc_dai_ops rockchip_i2s_dai_ops = { - .trigger = rockchip_i2s_trigger, - .hw_params = rockchip_i2s_hw_params, - .set_fmt = rockchip_i2s_set_fmt, - .set_clkdiv = rockchip_i2s_set_clkdiv, - .set_sysclk = rockchip_i2s_set_sysclk, -}; - -struct snd_soc_dai rk2818_i2s_dai = { - .name = "rk2818_i2s", - .id = -1, - .probe = rockchip_i2s_dai_probe, - .suspend = rockchip_i2s_suspend, - .resume = rockchip_i2s_resume, - .playback = { - .channels_min = 1, - .channels_max = 2, - .rates = ROCKCHIP_I2S_RATES, - .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,}, - .capture = { - .channels_min = 2, - .channels_max = 2, - .rates = ROCKCHIP_I2S_RATES, - .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,}, - .ops = &rockchip_i2s_dai_ops, -}; - - -EXPORT_SYMBOL_GPL(rk2818_i2s_dai); - -static int __devinit rockchip_i2s_probe(struct platform_device *pdev) -{ - struct resource *regs; - struct rk2818_i2s_platform_data *pdata = pdev->dev.platform_data; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - - if (pdata && pdata->io_init) - pdata->io_init(); - - rk2818_i2s_dai.dev = &pdev->dev; - rockchip_i2s.iis_clk = clk_get(&pdev->dev, "i2s"); - clk_enable(rockchip_i2s.iis_clk); - regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!regs) { - DBG("platform get resource fail\n"); - return -ENXIO; - } - rockchip_i2s.regs = ioremap(regs->start, (regs->end - regs->start) + 1); - if (rockchip_i2s.regs == NULL) { - DBG("rk2818 i2s ioremap err\n"); - release_mem_region(regs->start, (regs->end - regs->start) + 1); - return -EBUSY; - } - - return snd_soc_register_dai(&rk2818_i2s_dai); -} - - -static int __devexit rockchip_i2s_remove(struct platform_device *pdev) -{ - snd_soc_unregister_dai(&rk2818_i2s_dai); - - return 0; -} - -static struct platform_driver rockchip_i2s_driver = { - .probe = rockchip_i2s_probe, - .remove = __devexit_p(rockchip_i2s_remove), - .driver = { - .name = "rk2818_i2s", - .owner = THIS_MODULE, - }, -}; - -static int __init rockchip_i2s_init(void) -{ - return platform_driver_register(&rockchip_i2s_driver); -} -module_init(rockchip_i2s_init); - -static void __exit rockchip_i2s_exit(void) -{ - platform_driver_unregister(&rockchip_i2s_driver); -} -module_exit(rockchip_i2s_exit); - -/* Module information */ -MODULE_AUTHOR("lhh lhh@rock-chips.com"); -MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface"); -MODULE_LICENSE("GPL"); diff --git a/sound/soc/rk2818/rk2818_i2s.h b/sound/soc/rk2818/rk2818_i2s.h deleted file mode 100755 index 619bfda244d7..000000000000 --- a/sound/soc/rk2818/rk2818_i2s.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * rockchip-iis.h - ALSA IIS interface for the Rockchip rk28 SoC - * - * Driver for rockchip iis audio - * Copyright (C) 2009 lhh - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _ROCKCHIP_IIS_H -#define _ROCKCHIP_IIS_H - -//I2S_OPR -#define RESET_TX (1<<17) -#define RESET_RX (1<<16) -#define I2S_DMA_REQ1_DISABLE (1<<6) -#define I2S_DMA_REQ1_ENABLE (0) -#define I2S_DMA_REQ2_DISABLE (1<<5) -#define I2S_DMA_REQ2_ENABLE (0) -#define I2S_DMA_REQ1_TX_ENABLE (0) -#define I2S_DMA_REQ1_RX_ENABLE (1<<4) -#define I2S_DMA_REQ2_TX_ENABLE (0) -#define I2S_DMA_REQ2_RX_ENABLE (1<<3) -#define TX_START (1<<1) -#define RX_START (1) - - - -//I2S_TXCTL I2S_RXCTL -#define CLEAR_RXFIFO (1<<24) -#define TRAN_DEVICES0 (0) -#define TRAN_DEVICES1 (1<<18) -#define TRAN_DEVICES2 (2<<18) -#define TRAN_DEVICES3 (3<<18) -#define OVERSAMPLING_RATE_32FS (0) -#define OVERSAMPLING_RATE_64FS (1<<16) -#define OVERSAMPLING_RATE_128FS (2<<16) -#define SCK_RATE2 (0x02<<8) -#define SCK_RATE4 (0x04<<8) -#define SCK_RATE8 (0x08<<8) -#define SAMPLE_DATA_8bit (0) -#define SAMPLE_DATA_16bit (1<<4) -#define SAMPLE_DATA_MASK (3<<4) -#define MONO_MODE (1<<3) -#define STEREO_MODE (0) -#define I2S_MODE (0) -#define LEFT_JUSTIFIED (1<<1) -#define RIGHT_JUSTIFIED (2<<1) -#define IISMOD_SDF_MASK (3<<1) -#define MASTER_MODE (1) -#define SLAVE_MODE (0) - -//I2S_FIFOSTS -#define TX_HALF_FULL (1<<18) -#define RX_HALF_FULL (1<<16) - -#define I2S_TXR_BUFF 0x04 -#define I2S_RXR_BUFF 0x08 - -/* Clock dividers */ -#define ROCKCHIP_DIV_MCLK 0 -#define ROCKCHIP_DIV_BCLK 1 -#define ROCKCHIP_DIV_PRESCALER 2 - -//I2S Registers -typedef volatile struct tagIIS_STRUCT -{ - unsigned int I2S_OPR; - unsigned int I2S_TXR; - unsigned int I2S_RXR; - unsigned int I2S_TXCTL; - unsigned int I2S_RXCTL; - unsigned int I2S_FIFOSTS; - unsigned int I2S_IER; - unsigned int I2S_ISR; -}I2S_REG,*pI2S_REG; - -extern struct snd_soc_dai rk2818_i2s_dai; -//extern void rockchip_add_device_i2s(void); -#endif /* _ROCKCHIP_IIS_H */ - diff --git a/sound/soc/rk2818/rk2818_pcm.c b/sound/soc/rk2818/rk2818_pcm.c deleted file mode 100755 index bbfe586268bb..000000000000 --- a/sound/soc/rk2818/rk2818_pcm.c +++ /dev/null @@ -1,630 +0,0 @@ -/* - * rk2818_pcm.c -- ALSA SoC ROCKCHIP PCM Audio Layer Platform driver - * - * Driver for rockchip pcm audio - * Copyright (C) 2009 lhh - * - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include "rk2818_pcm.h" - -#ifdef CONFIG_ANDROID_POWER -#include -static android_suspend_lock_t audio_lock; -#endif - -#if 0 -#define DBG(x...) printk(KERN_INFO x) -#else -#define DBG(x...) do { } while (0) -#endif - - -static const struct snd_pcm_hardware rockchip_pcm_hardware = { - .info = SNDRV_PCM_INFO_INTERLEAVED | - SNDRV_PCM_INFO_BLOCK_TRANSFER | - SNDRV_PCM_INFO_MMAP | - SNDRV_PCM_INFO_MMAP_VALID | - SNDRV_PCM_INFO_PAUSE | - SNDRV_PCM_INFO_RESUME, - .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_U16_LE | - SNDRV_PCM_FMTBIT_U8 | - SNDRV_PCM_FMTBIT_S8, - .channels_min = 2, - .channels_max = 2, - .buffer_bytes_max = 128*1024, - .period_bytes_min = 64, ///PAGE_SIZE, - .period_bytes_max = 2047*4,///PAGE_SIZE*2, - .periods_min = 3,///2, - .periods_max = 128, - .fifo_size = 16, -}; - - -struct rockchip_dma_buf_set { - struct rockchip_dma_buf_set *next; - struct scatterlist sg; -}; - -struct rockchip_runtime_data { - spinlock_t lock; - int state; - int transfer_first; - unsigned int dma_loaded; - unsigned int dma_limit; - unsigned int dma_period; - dma_addr_t dma_start; - dma_addr_t dma_pos; - dma_addr_t dma_end; - struct rockchip_pcm_dma_params *params; - struct rockchip_dma_buf_set *curr; /* current dma buffer set */ - struct rockchip_dma_buf_set *next; /* next buffer set to load */ - struct rockchip_dma_buf_set *end; /* end of queue set*/ -}; - - -/* rockchip__dma_buf_enqueue - * - *queue an given buffer for dma transfer set. - *data the physical address of the buffer data - *size the size of the buffer in bytes -*/ -static int rockchip_dma_buffer_set_enqueue(struct rockchip_runtime_data *prtd, dma_addr_t data, int size) -{ - struct rockchip_dma_buf_set *sg_buf; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - sg_buf = kzalloc(sizeof(struct rockchip_dma_buf_set), GFP_ATOMIC);/* ddl@rock-chips.com:GFP_KERNEL->GFP_ATOMIC */ - - if (sg_buf == NULL) { - DBG("scatter sg buffer allocate failed,no memory!\n"); - return -ENOMEM; - } - sg_buf->next = NULL; - sg_buf->sg.dma_address = data; - sg_buf->sg.length = size/4; ////4; - if( prtd->curr == NULL) { - prtd->curr = sg_buf; - prtd->end = sg_buf; - prtd->next = NULL; - } else { - if (prtd->end == NULL) - DBG("prtd->end is NULL\n"); - prtd->end->next = sg_buf; - prtd->end = sg_buf; - } - /* if necessary, update the next buffer field */ - if (prtd->next == NULL) - prtd->next = sg_buf; - return 0; -} - -void rockchip_pcm_dma_irq(s32 ch, void *data); - -void audio_start_dma(struct snd_pcm_substream *substream, int mode) -{ - struct rockchip_runtime_data *prtd; - unsigned long flags; - struct rockchip_dma_buf_set *sg_buf; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - - prtd = substream->runtime->private_data; - - switch (mode) { - case DMA_MODE_WRITE: - if (prtd->transfer_first == 1) { - prtd->transfer_first = 0; - } else { - sg_buf = prtd->curr; - if (sg_buf != NULL) { - prtd->curr = sg_buf->next; - prtd->next = sg_buf->next; - sg_buf->next = NULL; - kfree(sg_buf); - sg_buf = NULL; - } - } - - sg_buf = prtd->next; - DBG("Enter::%s----%d---length=%x---dma_address=%x\n",__FUNCTION__,__LINE__,sg_buf->sg.length,sg_buf->sg.dma_address); - if (sg_buf) { - spin_lock_irqsave(&prtd->lock, flags); - disable_dma(prtd->params->channel); - //set_dma_sg(prtd->params->channel, &(sg_buf->sg), 1); - set_dma_mode(prtd->params->channel, DMA_MODE_WRITE); - set_dma_handler(prtd->params->channel, rockchip_pcm_dma_irq, substream, DMA_IRQ_RIGHTNOW_MODE); - __set_dma_addr(prtd->params->channel, (void *)(sg_buf->sg.dma_address)); - set_dma_count(prtd->params->channel, sg_buf->sg.length); - enable_dma(prtd->params->channel); - spin_unlock_irqrestore(&prtd->lock, flags); - } else { - DBG("next buffer is NULL for playback\n"); - return; - } - break; - case DMA_MODE_READ: - if (prtd->transfer_first == 1) { - prtd->transfer_first = 0; - } else { - sg_buf = prtd->curr; - if (sg_buf != NULL) { - prtd->curr = sg_buf->next; - prtd->next = sg_buf->next; - sg_buf->next = NULL; - kfree(sg_buf); - sg_buf = NULL; - } - } - - sg_buf = prtd->next; - if (sg_buf) { - spin_lock_irqsave(&prtd->lock, flags); - disable_dma(prtd->params->channel); - //set_dma_sg(prtd->params->channel, &(sg_buf->sg), 1); - set_dma_mode(prtd->params->channel, DMA_MODE_READ); - set_dma_handler(prtd->params->channel, rockchip_pcm_dma_irq, substream, DMA_IRQ_RIGHTNOW_MODE); - __set_dma_addr(prtd->params->channel, (void *)(sg_buf->sg.dma_address)); - set_dma_count(prtd->params->channel, sg_buf->sg.length); - enable_dma(prtd->params->channel); - spin_unlock_irqrestore(&prtd->lock, flags); - } else { - DBG("next buffer is NULL for capture\n"); - return; - } - break; - } -} - -/* rockchip_pcm_enqueue - * - * place a dma buffer onto the queue for the dma system - * to handle. -*/ -static void rockchip_pcm_enqueue(struct snd_pcm_substream *substream) -{ - struct rockchip_runtime_data *prtd = substream->runtime->private_data; - dma_addr_t pos = prtd->dma_pos; - int ret; - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - - while (prtd->dma_loaded < prtd->dma_limit) { - unsigned long len = prtd->dma_period; - - DBG("dma_loaded: %d\n", prtd->dma_loaded); - if ((pos + len) > prtd->dma_end) { - len = prtd->dma_end - pos; - } - ret = rockchip_dma_buffer_set_enqueue(prtd, pos, len); - if (ret == 0) { - prtd->dma_loaded++; - pos += prtd->dma_period; - if (pos >= prtd->dma_end) - pos = prtd->dma_start; - } else - break; - } - - prtd->dma_pos = pos; -} - -void rockchip_pcm_dma_irq(s32 ch, void *data) -{ - struct snd_pcm_substream *substream = data; - struct rockchip_runtime_data *prtd; - unsigned long flags; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - - prtd = substream->runtime->private_data; - if (substream) - snd_pcm_period_elapsed(substream); - spin_lock(&prtd->lock); - prtd->dma_loaded--; - if (prtd->state & ST_RUNNING) { - rockchip_pcm_enqueue(substream); - } - spin_unlock(&prtd->lock); - local_irq_save(flags); - if (prtd->state & ST_RUNNING) { - if (prtd->dma_loaded) { - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) - audio_start_dma(substream, DMA_MODE_WRITE); - else - audio_start_dma(substream, DMA_MODE_READ); - } - } - local_irq_restore(flags); -} - - -static int rockchip_pcm_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) -{ - struct snd_pcm_runtime *runtime = substream->runtime; - struct rockchip_runtime_data *prtd = runtime->private_data; - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct rockchip_pcm_dma_params *dma = rtd->dai->cpu_dai->dma_data; - unsigned long totbytes = params_buffer_bytes(params); - int ret = 0; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - /*by Vincent Hsiung for EQ Vol Change*/ - #define HW_PARAMS_FLAG_EQVOL_ON 0x21 - #define HW_PARAMS_FLAG_EQVOL_OFF 0x22 - if ((params->flags == HW_PARAMS_FLAG_EQVOL_ON)||(params->flags == HW_PARAMS_FLAG_EQVOL_OFF)) - { - return 0; - } - - /* return if this is a bufferless transfer e.g. - * codec <--> BT codec or GSM modem -- lg FIXME */ - if (!dma) - return 0; - - /* this may get called several times by oss emulation - * with different params -HW */ - if (prtd->params == NULL) { - /* prepare DMA */ - prtd->params = dma; - - DBG("params %p, client %p, channel %d\n", prtd->params, - prtd->params->client, prtd->params->channel); - - ret = request_dma(prtd->params->channel, "i2s"); ///prtd->params->client->name); - if(ret){ - for(prtd->params->channel=5;prtd->params->channel>0;prtd->params->channel--){ - ret = request_dma(prtd->params->channel, "i2s"); - if(!ret)break; - } - } - if (ret) { - DBG(KERN_ERR "failed to get dma channel\n"); - return ret; - } - } - - - snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); - - runtime->dma_bytes = totbytes; - - spin_lock_irq(&prtd->lock); - prtd->dma_loaded = 0; - prtd->dma_limit = runtime->hw.periods_min; - prtd->dma_period = params_period_bytes(params); - prtd->dma_start = runtime->dma_addr; - prtd->dma_pos = prtd->dma_start; - prtd->dma_end = prtd->dma_start + totbytes; - prtd->transfer_first = 1; - prtd->curr = NULL; - prtd->next = NULL; - prtd->end = NULL; - spin_unlock_irq(&prtd->lock); - return 0; -} - -static int rockchip_pcm_hw_free(struct snd_pcm_substream *substream) -{ - struct rockchip_runtime_data *prtd = substream->runtime->private_data; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - /* TODO - do we need to ensure DMA flushed */ - snd_pcm_set_runtime_buffer(substream, NULL); - - if (prtd->params) { - free_dma(prtd->params->channel); - prtd->params = NULL; - } - - return 0; -} - -static int rockchip_pcm_prepare(struct snd_pcm_substream *substream) -{ - struct rockchip_runtime_data *prtd = substream->runtime->private_data; - int ret = 0; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - - /* return if this is a bufferless transfer e.g. - * codec <--> BT codec or GSM modem -- lg FIXME */ - if (!prtd->params) - return 0; - prtd->dma_loaded = 0; - prtd->dma_pos = prtd->dma_start; - - /* enqueue dma buffers */ - rockchip_pcm_enqueue(substream); - return ret; -} - -static int rockchip_pcm_trigger(struct snd_pcm_substream *substream, int cmd) -{ - struct rockchip_runtime_data *prtd = substream->runtime->private_data; - int ret = 0; - /**************add by qiuen for volume*****/ - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_dai *pCodec_dai = rtd->dai->codec_dai; - int vol = 0; - int streamType = 0; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - - if(cmd==SNDRV_PCM_TRIGGER_VOLUME){ - vol = substream->number % 100; - streamType = (substream->number / 100) % 100; - DBG("enter:vol=%d,streamType=%d\n",vol,streamType); - pCodec_dai->ops->set_volume(streamType, vol); - } - /****************************************************/ - spin_lock(&prtd->lock); - - switch (cmd) { - case SNDRV_PCM_TRIGGER_START: - DBG(" START \n"); - prtd->state |= ST_RUNNING; - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - audio_start_dma(substream, DMA_MODE_WRITE); - } else { - audio_start_dma(substream, DMA_MODE_READ); - } -#ifdef CONFIG_ANDROID_POWER - android_lock_suspend(&audio_lock); - DBG("%s::start audio , lock system suspend\n" , __func__ ); -#endif - break; - case SNDRV_PCM_TRIGGER_RESUME: - DBG(" RESUME \n"); - break; - case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: - DBG(" RESTART \n"); - break; - - case SNDRV_PCM_TRIGGER_STOP: - case SNDRV_PCM_TRIGGER_SUSPEND: - case SNDRV_PCM_TRIGGER_PAUSE_PUSH: - DBG(" STOPS \n"); - prtd->state &= ~ST_RUNNING; - disable_dma(prtd->params->channel); -#ifdef CONFIG_ANDROID_POWER - android_unlock_suspend(&audio_lock ); - DBG("%s::stop audio , unlock system suspend\n" , __func__ ); -#endif - - break; - default: - ret = -EINVAL; - break; - } - - spin_unlock(&prtd->lock); - return ret; -} - - -static snd_pcm_uframes_t -rockchip_pcm_pointer(struct snd_pcm_substream *substream) -{ - struct snd_pcm_runtime *runtime = substream->runtime; - struct rockchip_runtime_data *prtd = runtime->private_data; - unsigned long res; - dma_addr_t src, dst; - snd_pcm_uframes_t ret; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - spin_lock(&prtd->lock); - - get_dma_position(prtd->params->channel, &src, &dst); - //dma_getposition(prtd->params->channel, &src, &dst); - - if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) - res = dst - prtd->dma_start; - else - res = src - prtd->dma_start; - - spin_unlock(&prtd->lock); - - DBG("Pointer %x %x\n",src,dst); - - ret = bytes_to_frames(runtime, res); - if (ret == runtime->buffer_size) - ret = 0; - return ret; -} - - -static int rockchip_pcm_open(struct snd_pcm_substream *substream) -{ - struct snd_pcm_runtime *runtime = substream->runtime; - struct rockchip_runtime_data *prtd; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - - snd_soc_set_runtime_hwparams(substream, &rockchip_pcm_hardware); - - prtd = kzalloc(sizeof(struct rockchip_runtime_data), GFP_KERNEL); - if (prtd == NULL) - return -ENOMEM; - - spin_lock_init(&prtd->lock); - - runtime->private_data = prtd; - return 0; -} - -static int rockchip_pcm_close(struct snd_pcm_substream *substream) -{ - struct snd_pcm_runtime *runtime = substream->runtime; - struct rockchip_runtime_data *prtd = runtime->private_data; - struct rockchip_dma_buf_set *sg_buf = NULL; - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - - if (!prtd) - DBG("rockchip_pcm_close called with prtd == NULL\n"); - if (prtd) - sg_buf = prtd->curr; - - while (sg_buf != NULL) { - prtd->curr = sg_buf->next; - prtd->next = sg_buf->next; - sg_buf->next = NULL; - kfree(sg_buf); - sg_buf = NULL; - sg_buf = prtd->curr; - } - kfree(prtd); - - return 0; -} - -static int rockchip_pcm_mmap(struct snd_pcm_substream *substream, - struct vm_area_struct *vma) -{ - struct snd_pcm_runtime *runtime = substream->runtime; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - - return dma_mmap_writecombine(substream->pcm->card->dev, vma, - runtime->dma_area, - runtime->dma_addr, - runtime->dma_bytes); -} - -static struct snd_pcm_ops rockchip_pcm_ops = { - .open = rockchip_pcm_open, - .close = rockchip_pcm_close, - .ioctl = snd_pcm_lib_ioctl, - .hw_params = rockchip_pcm_hw_params, - .hw_free = rockchip_pcm_hw_free, - .prepare = rockchip_pcm_prepare, - .trigger = rockchip_pcm_trigger, - .pointer = rockchip_pcm_pointer, - .mmap = rockchip_pcm_mmap, -}; - -static int rockchip_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream) -{ - struct snd_pcm_substream *substream = pcm->streams[stream].substream; - struct snd_dma_buffer *buf = &substream->dma_buffer; - size_t size = rockchip_pcm_hardware.buffer_bytes_max; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - - buf->dev.type = SNDRV_DMA_TYPE_DEV; - buf->dev.dev = pcm->card->dev; - buf->private_data = NULL; - buf->area = dma_alloc_writecombine(pcm->card->dev, size, - &buf->addr, GFP_KERNEL); - if (!buf->area) - return -ENOMEM; - buf->bytes = size; - return 0; -} - -static void rockchip_pcm_free_dma_buffers(struct snd_pcm *pcm) -{ - struct snd_pcm_substream *substream; - struct snd_dma_buffer *buf; - int stream; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - - for (stream = 0; stream < 2; stream++) { - substream = pcm->streams[stream].substream; - if (!substream) - continue; - - buf = &substream->dma_buffer; - if (!buf->area) - continue; - - dma_free_writecombine(pcm->card->dev, buf->bytes, - buf->area, buf->addr); - buf->area = NULL; - } -} - -static u64 rockchip_pcm_dmamask = DMA_BIT_MASK(32); - -static int rockchip_pcm_new(struct snd_card *card, - struct snd_soc_dai *dai, struct snd_pcm *pcm) -{ - int ret = 0; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - -#ifdef CONFIG_ANDROID_POWER - audio_lock.name = "rk-audio"; - android_init_suspend_lock(&audio_lock); -#endif - - if (!card->dev->dma_mask) - card->dev->dma_mask = &rockchip_pcm_dmamask; - if (!card->dev->coherent_dma_mask) - card->dev->coherent_dma_mask = 0xffffffff; - - if (dai->playback.channels_min) { - ret = rockchip_pcm_preallocate_dma_buffer(pcm, - SNDRV_PCM_STREAM_PLAYBACK); - if (ret) - goto out; - } - - if (dai->capture.channels_min) { - ret = rockchip_pcm_preallocate_dma_buffer(pcm, - SNDRV_PCM_STREAM_CAPTURE); - if (ret) - goto out; - } - out: - return ret; -} - -struct snd_soc_platform rk2818_soc_platform = { - .name = "rockchip-audio", - .pcm_ops = &rockchip_pcm_ops, - .pcm_new = rockchip_pcm_new, - .pcm_free = rockchip_pcm_free_dma_buffers, -}; -EXPORT_SYMBOL_GPL(rk2818_soc_platform); - -static int __init rockchip_soc_platform_init(void) -{ - return snd_soc_register_platform(&rk2818_soc_platform); -} -module_init(rockchip_soc_platform_init); - -static void __exit rockchip_soc_platform_exit(void) -{ - snd_soc_unregister_platform(&rk2818_soc_platform); -} -module_exit(rockchip_soc_platform_exit); - -/* Module information */ -MODULE_AUTHOR("lhh lhh@rock-chips.com"); -MODULE_DESCRIPTION("ROCKCHIP PCM ASoC Interface"); -MODULE_LICENSE("GPL"); - diff --git a/sound/soc/rk2818/rk2818_pcm.h b/sound/soc/rk2818/rk2818_pcm.h deleted file mode 100755 index ad4ac2b50ee5..000000000000 --- a/sound/soc/rk2818/rk2818_pcm.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * rockchip-pcm.h - ALSA PCM interface for the Rockchip rk28 SoC - * - * Driver for rockchip iis audio - * Copyright (C) 2009 lhh - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _ROCKCHIP_PCM_H -#define _ROCKCHIP_PCM_H - -#include - -#define ST_RUNNING (1<<0) -#define ST_OPENED (1<<1) - -/* dma buffer */ -struct rockchip_dma_client { - char *name; -}; - -struct rockchip_pcm_dma_params { - struct rockchip_dma_client *client; /* stream identifier */ - int channel; /* Channel ID */ - dma_addr_t dma_addr; - int dma_size; /* Size of the DMA transfer */ -}; - -extern struct snd_soc_platform rk2818_soc_platform; - -#endif /* _ROCKCHIP_PCM_H */ diff --git a/sound/soc/rk2818/rk2818_rk1000codec.c b/sound/soc/rk2818/rk2818_rk1000codec.c deleted file mode 100644 index 4474e88554f8..000000000000 --- a/sound/soc/rk2818/rk2818_rk1000codec.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * rk2818_wm8988.c -- SoC audio for rockchip - * - * Driver for rockchip wm8988 audio - * Copyright (C) 2009 lhh - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../codecs/rk1000_codec.h" -#include "rk2818_pcm.h" -#include "rk2818_i2s.h" - -#if 0 -#define DBG(x...) printk(KERN_INFO x) -#else -#define DBG(x...) -#endif - -static int rk2818_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) -{ - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_dai *codec_dai = rtd->dai->codec_dai; - struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; - int ret; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - /*by Vincent Hsiung for EQ Vol Change*/ - #define HW_PARAMS_FLAG_EQVOL_ON 0x21 - #define HW_PARAMS_FLAG_EQVOL_OFF 0x22 - if ((params->flags == HW_PARAMS_FLAG_EQVOL_ON)||(params->flags == HW_PARAMS_FLAG_EQVOL_OFF)) - { - ret = codec_dai->ops->hw_params(substream, params, codec_dai); //by Vincent - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - } - else - { - /* set codec DAI configuration */ - #if defined (CONFIG_SND_ROCKCHIP_SOC_MASTER) - ret = codec_dai->ops->set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | - SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); - #endif - #if defined (CONFIG_SND_ROCKCHIP_SOC_SLAVE) - ret = codec_dai->ops->set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | - SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM ); - #endif - if (ret < 0) - return ret; - /* set cpu DAI configuration */ - #if defined (CONFIG_SND_ROCKCHIP_SOC_MASTER) - ret = cpu_dai->ops->set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | - SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); - #endif - #if defined (CONFIG_SND_ROCKCHIP_SOC_SLAVE) - ret = cpu_dai->ops->set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | - SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); - #endif - if (ret < 0) - return ret; - } - - return 0; -} - -static const struct snd_soc_dapm_widget rk2818_dapm_widgets[] = { - SND_SOC_DAPM_LINE("Audio Out", NULL), - SND_SOC_DAPM_LINE("Line in", NULL), - SND_SOC_DAPM_MIC("Micn", NULL), - SND_SOC_DAPM_MIC("Micp", NULL), -}; - -static const struct snd_soc_dapm_route audio_map[]= { - - {"Audio Out", NULL, "LOUT1"}, - {"Audio Out", NULL, "ROUT1"}, - {"Line in", NULL, "RINPUT1"}, - {"Line in", NULL, "LINPUT1"}, - {"Micn", NULL, "RINPUT2"}, - {"Micp", NULL, "LINPUT2"}, -}; - -/* - * Logic for a rk1000 codec as connected on a rockchip board. - */ -static int rk2818_rk1000_codec_init(struct snd_soc_codec *codec) -{ - struct snd_soc_dai *codec_dai = &codec->dai[0]; - int ret; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - - ret = snd_soc_dai_set_sysclk(codec_dai, 0, - 12000000, SND_SOC_CLOCK_IN); - if (ret < 0) { - printk(KERN_ERR "Failed to set WM8988 SYSCLK: %d\n", ret); - return ret; - } - - /* Add specific widgets */ - snd_soc_dapm_new_controls(codec, rk2818_dapm_widgets, - ARRAY_SIZE(rk2818_dapm_widgets)); - - /* Set up specific audio path audio_mapnects */ - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); - - snd_soc_dapm_sync(codec); - - return 0; -} - -static struct snd_soc_ops rk2818_ops = { - .hw_params = rk2818_hw_params, -}; - -static struct snd_soc_dai_link rk2818_dai = { - .name = "RK1000_CODEC", - .stream_name = "RK1000 CODEC PCM", - .cpu_dai = &rk2818_i2s_dai, - .codec_dai = &rk1000_codec_dai, - .init = rk2818_rk1000_codec_init, - .ops = &rk2818_ops, -}; - -static struct snd_soc_card snd_soc_card_rk2818 = { - .name = "RK1000_CODEC", - .platform = &rk2818_soc_platform, - .dai_link = &rk2818_dai, - .num_links = 1, -}; - - -static struct snd_soc_device rk2818_snd_devdata = { - .card = &snd_soc_card_rk2818, - .codec_dev = &soc_codec_dev_rk1000_codec, -}; - -static struct platform_device *rk2818_snd_device; - -static int __init audio_card_init(void) -{ - int ret =0; - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - rk2818_snd_device = platform_device_alloc("soc-audio", -1); - if (!rk2818_snd_device) { - DBG("platform device allocation failed\n"); - ret = -ENOMEM; - return ret; - } - platform_set_drvdata(rk2818_snd_device, &rk2818_snd_devdata); - rk2818_snd_devdata.dev = &rk2818_snd_device->dev; - ret = platform_device_add(rk2818_snd_device); - if (ret) { - DBG("platform device add failed\n"); - platform_device_put(rk2818_snd_device); - } - return ret; -} -static void __exit audio_card_exit(void) -{ - platform_device_unregister(rk2818_snd_device); -} - -module_init(audio_card_init); -module_exit(audio_card_exit); -/* Module information */ -MODULE_AUTHOR("lhh lhh@rock-chips.com"); -MODULE_DESCRIPTION("ROCKCHIP i2s ASoC Interface"); -MODULE_LICENSE("GPL"); diff --git a/sound/soc/rk2818/rk2818_wm8988.c b/sound/soc/rk2818/rk2818_wm8988.c deleted file mode 100755 index 5dfeb3331f0f..000000000000 --- a/sound/soc/rk2818/rk2818_wm8988.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * rk2818_wm8988.c -- SoC audio for rockchip - * - * Driver for rockchip wm8988 audio - * Copyright (C) 2009 lhh - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../codecs/wm8988.h" -#include "rk2818_pcm.h" -#include "rk2818_i2s.h" - -#if 0 -#define DBG(x...) printk(KERN_INFO x) -#else -#define DBG(x...) -#endif - -static int rk2818_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) -{ - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_dai *codec_dai = rtd->dai->codec_dai; - struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; - int ret; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - /*by Vincent Hsiung for EQ Vol Change*/ - #define HW_PARAMS_FLAG_EQVOL_ON 0x21 - #define HW_PARAMS_FLAG_EQVOL_OFF 0x22 - if ((params->flags == HW_PARAMS_FLAG_EQVOL_ON)||(params->flags == HW_PARAMS_FLAG_EQVOL_OFF)) - { - ret = codec_dai->ops->hw_params(substream, params, codec_dai); //by Vincent - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - } - else - { - /* set codec DAI configuration */ - #if defined (CONFIG_SND_ROCKCHIP_SOC_MASTER) - ret = codec_dai->ops->set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | - SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); - #endif - #if defined (CONFIG_SND_ROCKCHIP_SOC_SLAVE) - ret = codec_dai->ops->set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | - SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM ); - #endif - if (ret < 0) - return ret; - /* set cpu DAI configuration */ - #if defined (CONFIG_SND_ROCKCHIP_SOC_MASTER) - ret = cpu_dai->ops->set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | - SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); - #endif - #if defined (CONFIG_SND_ROCKCHIP_SOC_SLAVE) - ret = cpu_dai->ops->set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | - SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); - #endif - if (ret < 0) - return ret; - } - - return 0; -} - -static const struct snd_soc_dapm_widget rk2818_dapm_widgets[] = { - SND_SOC_DAPM_LINE("Audio Out", NULL), - SND_SOC_DAPM_LINE("Line in", NULL), - SND_SOC_DAPM_MIC("Micn", NULL), - SND_SOC_DAPM_MIC("Micp", NULL), -}; - -static const struct snd_soc_dapm_route audio_map[]= { - - {"Audio Out", NULL, "LOUT1"}, - {"Audio Out", NULL, "ROUT1"}, - {"Line in", NULL, "RINPUT1"}, - {"Line in", NULL, "LINPUT1"}, - {"Micn", NULL, "RINPUT2"}, - {"Micp", NULL, "LINPUT2"}, -}; - -/* - * Logic for a wm8988 as connected on a rockchip board. - */ -static int rk2818_wm8988_init(struct snd_soc_codec *codec) -{ - struct snd_soc_dai *codec_dai = &codec->dai[0]; - int ret; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - - ret = snd_soc_dai_set_sysclk(codec_dai, 0, - 12000000, SND_SOC_CLOCK_IN); - if (ret < 0) { - printk(KERN_ERR "Failed to set WM8988 SYSCLK: %d\n", ret); - return ret; - } - - /* Add specific widgets */ - snd_soc_dapm_new_controls(codec, rk2818_dapm_widgets, - ARRAY_SIZE(rk2818_dapm_widgets)); - snd_soc_dapm_nc_pin(codec, "LOUT2"); - snd_soc_dapm_nc_pin(codec, "ROUT2"); - - /* Set up specific audio path audio_mapnects */ - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); - - snd_soc_dapm_sync(codec); - - return 0; -} - -static struct snd_soc_ops rk2818_ops = { - .hw_params = rk2818_hw_params, -}; - -static struct snd_soc_dai_link rk2818_dai = { - .name = "WM8988", - .stream_name = "WM8988 PCM", - .cpu_dai = &rk2818_i2s_dai, - .codec_dai = &wm8988_dai, - .init = rk2818_wm8988_init, - .ops = &rk2818_ops, -}; - -static struct snd_soc_card snd_soc_card_rk2818 = { - .name = "RK2818_WM8988", - .platform = &rk2818_soc_platform, - .dai_link = &rk2818_dai, - .num_links = 1, -}; - - -static struct snd_soc_device rk2818_snd_devdata = { - .card = &snd_soc_card_rk2818, - .codec_dev = &soc_codec_dev_wm8988, -}; - -static struct platform_device *rk2818_snd_device; - -static int __init audio_card_init(void) -{ - int ret =0; - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - rk2818_snd_device = platform_device_alloc("soc-audio", -1); - if (!rk2818_snd_device) { - DBG("platform device allocation failed\n"); - ret = -ENOMEM; - return ret; - } - platform_set_drvdata(rk2818_snd_device, &rk2818_snd_devdata); - rk2818_snd_devdata.dev = &rk2818_snd_device->dev; - ret = platform_device_add(rk2818_snd_device); - if (ret) { - DBG("platform device add failed\n"); - platform_device_put(rk2818_snd_device); - } - return ret; -} -static void __exit audio_card_exit(void) -{ - platform_device_unregister(rk2818_snd_device); -} - -module_init(audio_card_init); -module_exit(audio_card_exit); -/* Module information */ -MODULE_AUTHOR("lhh lhh@rock-chips.com"); -MODULE_DESCRIPTION("ROCKCHIP i2s ASoC Interface"); -MODULE_LICENSE("GPL"); diff --git a/sound/soc/rk2818/rk2818_wm8994.c b/sound/soc/rk2818/rk2818_wm8994.c deleted file mode 100755 index 22c12481f443..000000000000 --- a/sound/soc/rk2818/rk2818_wm8994.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * rk2818_wm8988.c -- SoC audio for rockchip - * - * Driver for rockchip wm8988 audio - * Copyright (C) 2009 lhh - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../codecs/wm8994.h" -#include "rk2818_pcm.h" -#include "rk2818_i2s.h" - -#if 0 -#define DBG(x...) printk(KERN_INFO x) -#else -#define DBG(x...) -#endif - -static int rk2818_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) -{ - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_dai *codec_dai = rtd->dai->codec_dai; - struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; - int ret; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - /*by Vincent Hsiung for EQ Vol Change*/ - #define HW_PARAMS_FLAG_EQVOL_ON 0x21 - #define HW_PARAMS_FLAG_EQVOL_OFF 0x22 - if ((params->flags == HW_PARAMS_FLAG_EQVOL_ON)||(params->flags == HW_PARAMS_FLAG_EQVOL_OFF)) - { - ret = codec_dai->ops->hw_params(substream, params, codec_dai); //by Vincent - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - } - else - { - /* set codec DAI configuration */ - #if defined (CONFIG_SND_CODEC_SOC_SLAVE) - ret = codec_dai->ops->set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | - SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); - #endif - #if defined (CONFIG_SND_CODEC_SOC_MASTER) - ret = codec_dai->ops->set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | - SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM ); - #endif - if (ret < 0) - return ret; - /* set cpu DAI configuration */ - #if defined (CONFIG_SND_CODEC_SOC_SLAVE) - ret = cpu_dai->ops->set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | - SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); - #endif - #if defined (CONFIG_SND_CODEC_SOC_MASTER) - ret = cpu_dai->ops->set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | - SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); - #endif - if (ret < 0) - return ret; - } - - return 0; -} - -static const struct snd_soc_dapm_widget rk2818_dapm_widgets[] = { - SND_SOC_DAPM_LINE("Audio Out", NULL), - SND_SOC_DAPM_LINE("Line in", NULL), - SND_SOC_DAPM_MIC("Micn", NULL), - SND_SOC_DAPM_MIC("Micp", NULL), -}; - -static const struct snd_soc_dapm_route audio_map[]= { - - {"Audio Out", NULL, "LOUT1"}, - {"Audio Out", NULL, "ROUT1"}, - {"Line in", NULL, "RINPUT1"}, - {"Line in", NULL, "LINPUT1"}, - {"Micn", NULL, "RINPUT2"}, - {"Micp", NULL, "LINPUT2"}, -}; - -/* - * Logic for a wm8994 as connected on a rockchip board. - */ -static int rk2818_wm8994_init(struct snd_soc_codec *codec) -{ - struct snd_soc_dai *codec_dai = &codec->dai[0]; - int ret; - - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - - ret = snd_soc_dai_set_sysclk(codec_dai, 0, - 12000000, SND_SOC_CLOCK_IN); - if (ret < 0) { - printk(KERN_ERR "Failed to set WM8994 SYSCLK: %d\n", ret); - return ret; - } - - /* Add specific widgets */ - snd_soc_dapm_new_controls(codec, rk2818_dapm_widgets, - ARRAY_SIZE(rk2818_dapm_widgets)); - snd_soc_dapm_nc_pin(codec, "LOUT2"); - snd_soc_dapm_nc_pin(codec, "ROUT2"); - - /* Set up specific audio path audio_mapnects */ - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); - - snd_soc_dapm_sync(codec); - - return 0; -} - -static struct snd_soc_ops rk2818_ops = { - .hw_params = rk2818_hw_params, -}; - -static struct snd_soc_dai_link rk2818_dai = { - .name = "WM8994", - .stream_name = "WM8994 PCM", - .cpu_dai = &rk2818_i2s_dai, - .codec_dai = &wm8994_dai, - .init = rk2818_wm8994_init, - .ops = &rk2818_ops, -}; - -static struct snd_soc_card snd_soc_card_rk2818 = { - .name = "RK2818_WM8994", - .platform = &rk2818_soc_platform, - .dai_link = &rk2818_dai, - .num_links = 1, -}; - - -static struct snd_soc_device rk2818_snd_devdata = { - .card = &snd_soc_card_rk2818, - .codec_dev = &soc_codec_dev_wm8994, -}; - -static struct platform_device *rk2818_snd_device; - -static int __init audio_card_init(void) -{ - int ret =0; - DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); - - rk2818_snd_device = platform_device_alloc("soc-audio", -1); - if (!rk2818_snd_device) { - DBG("platform device allocation failed\n"); - ret = -ENOMEM; - return ret; - } - platform_set_drvdata(rk2818_snd_device, &rk2818_snd_devdata); - rk2818_snd_devdata.dev = &rk2818_snd_device->dev; - ret = platform_device_add(rk2818_snd_device); - if (ret) { - DBG("platform device add failed\n"); - platform_device_put(rk2818_snd_device); - } - return ret; -} -static void __exit audio_card_exit(void) -{ - platform_device_unregister(rk2818_snd_device); -} - -module_init(audio_card_init); -module_exit(audio_card_exit); -/* Module information */ -MODULE_AUTHOR("lhh lhh@rock-chips.com"); -MODULE_DESCRIPTION("ROCKCHIP i2s ASoC Interface"); -MODULE_LICENSE("GPL");