From: Vinod Koul <vinod.koul@intel.com>
Date: Wed, 30 Oct 2013 07:37:18 +0000 (+0530)
Subject: Merge branch 'for-linus' into next
X-Git-Tag: firefly_0821_release~176^2~4916^2~23
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=b967aecf1714c10d1e6c045e43b6385884f1ca77;p=firefly-linux-kernel-4.4.55.git

Merge branch 'for-linus' into next

Conflicts:
	drivers/dma/edma.c
Moved the memory leak fix post merge

Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---

b967aecf1714c10d1e6c045e43b6385884f1ca77
diff --cc drivers/dma/edma.c
index 10b577fcf48d,79b046b3e2f0..8c612415867e
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@@ -315,64 -428,19 +430,21 @@@ static struct dma_async_tx_descriptor *
  
  	/* Configure PaRAM sets for each SG */
  	for_each_sg(sgl, sg, sg_len, i) {
- 
- 		acnt = dev_width;
- 
- 		/*
- 		 * If the maxburst is equal to the fifo width, use
- 		 * A-synced transfers. This allows for large contiguous
- 		 * buffer transfers using only one PaRAM set.
- 		 */
- 		if (burst == 1) {
- 			edesc->absync = false;
- 			ccnt = sg_dma_len(sg) / acnt / (SZ_64K - 1);
- 			bcnt = sg_dma_len(sg) / acnt - ccnt * (SZ_64K - 1);
- 			if (bcnt)
- 				ccnt++;
- 			else
- 				bcnt = SZ_64K - 1;
- 			cidx = acnt;
- 		/*
- 		 * If maxburst is greater than the fifo address_width,
- 		 * use AB-synced transfers where A count is the fifo
- 		 * address_width and B count is the maxburst. In this
- 		 * case, we are limited to transfers of C count frames
- 		 * of (address_width * maxburst) where C count is limited
- 		 * to SZ_64K-1. This places an upper bound on the length
- 		 * of an SG segment that can be handled.
- 		 */
- 		} else {
- 			edesc->absync = true;
- 			bcnt = burst;
- 			ccnt = sg_dma_len(sg) / (acnt * bcnt);
- 			if (ccnt > (SZ_64K - 1)) {
- 				dev_err(dev, "Exceeded max SG segment size\n");
- 				kfree(edesc);
- 				return NULL;
- 			}
- 			cidx = acnt * bcnt;
- 		}
- 
- 		if (direction == DMA_MEM_TO_DEV) {
- 			src = sg_dma_address(sg);
- 			dst = dev_addr;
- 			src_bidx = acnt;
- 			src_cidx = cidx;
- 			dst_bidx = 0;
- 			dst_cidx = 0;
- 		} else {
- 			src = dev_addr;
- 			dst = sg_dma_address(sg);
- 			src_bidx = 0;
- 			src_cidx = 0;
- 			dst_bidx = acnt;
- 			dst_cidx = cidx;
+ 		/* Get address for each SG */
+ 		if (direction == DMA_DEV_TO_MEM)
+ 			dst_addr = sg_dma_address(sg);
+ 		else
+ 			src_addr = sg_dma_address(sg);
+ 
+ 		ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
+ 				       dst_addr, burst, dev_width,
+ 				       sg_dma_len(sg), direction);
 -		if (ret < 0)
++		if (ret < 0) {
++			kfree(edesc);
+ 			return NULL;
 +		}
  
- 		edesc->pset[i].opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
- 		/* Configure A or AB synchronized transfers */
- 		if (edesc->absync)
- 			edesc->pset[i].opt |= SYNCDIM;
+ 		edesc->absync = ret;
  
  		/* If this is the last in a current SG set of transactions,
  		   enable interrupts so that next set is processed */