From: Evan Cheng <evan.cheng@apple.com>
Date: Fri, 20 Apr 2007 21:20:10 +0000 (+0000)
Subject: Specify S registers as D registers' sub-registers.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=ba647becb98fbb01cc02aa6a522971a639ea2534;p=oota-llvm.git

Specify S registers as D registers' sub-registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36280 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td
index b46a9522049..691514cd8ee 100644
--- a/lib/Target/ARM/ARMRegisterInfo.td
+++ b/lib/Target/ARM/ARMRegisterInfo.td
@@ -13,10 +13,10 @@
 //===----------------------------------------------------------------------===//
 
 // Registers are identified with 4-bit ID numbers.
-class ARMReg<bits<4> num, string n, list<Register> aliases = []> : Register<n> {
+class ARMReg<bits<4> num, string n, list<Register> subregs = []> : Register<n> {
   field bits<4> Num;
   let Namespace = "ARM";
-  let Aliases = aliases;
+  let SubRegs = subregs;
 }
 
 class ARMFReg<bits<5> num, string n> : Register<n> {