From: Matt Arsenault Date: Sun, 13 Jul 2014 03:06:39 +0000 (+0000) Subject: R600: Make ShaderType private X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=bb098a4d87b17040b629bea3c6df345330f2c43d;p=oota-llvm.git R600: Make ShaderType private git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212896 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/R600/AMDGPUAsmPrinter.cpp b/lib/Target/R600/AMDGPUAsmPrinter.cpp index a6e217b969a..15b11f6497b 100644 --- a/lib/Target/R600/AMDGPUAsmPrinter.cpp +++ b/lib/Target/R600/AMDGPUAsmPrinter.cpp @@ -16,7 +16,6 @@ //===----------------------------------------------------------------------===// // - #include "AMDGPUAsmPrinter.h" #include "AMDGPU.h" #include "AMDGPUSubtarget.h" @@ -179,7 +178,7 @@ void AMDGPUAsmPrinter::EmitProgramInfoR600(MachineFunction &MF) { unsigned RsrcReg; if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) { // Evergreen / Northern Islands - switch (MFI->ShaderType) { + switch (MFI->getShaderType()) { default: // Fall through case ShaderType::COMPUTE: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break; case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break; @@ -188,7 +187,7 @@ void AMDGPUAsmPrinter::EmitProgramInfoR600(MachineFunction &MF) { } } else { // R600 / R700 - switch (MFI->ShaderType) { + switch (MFI->getShaderType()) { default: // Fall through case ShaderType::GEOMETRY: // Fall through case ShaderType::COMPUTE: // Fall through @@ -203,7 +202,7 @@ void AMDGPUAsmPrinter::EmitProgramInfoR600(MachineFunction &MF) { OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4); OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4); - if (MFI->ShaderType == ShaderType::COMPUTE) { + if (MFI->getShaderType() == ShaderType::COMPUTE) { OutStreamer.EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4); OutStreamer.EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4); } @@ -324,7 +323,7 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF, SIMachineFunctionInfo *MFI = MF.getInfo(); unsigned RsrcReg; - switch (MFI->ShaderType) { + switch (MFI->getShaderType()) { default: // Fall through case ShaderType::COMPUTE: RsrcReg = R_00B848_COMPUTE_PGM_RSRC1; break; case ShaderType::GEOMETRY: RsrcReg = R_00B228_SPI_SHADER_PGM_RSRC1_GS; break; @@ -344,7 +343,7 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF, unsigned LDSBlocks = RoundUpToAlignment(MFI->LDSSize, 1 << LDSAlignShift) >> LDSAlignShift; - if (MFI->ShaderType == ShaderType::COMPUTE) { + if (MFI->getShaderType() == ShaderType::COMPUTE) { OutStreamer.EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4); const uint32_t ComputePGMRSrc1 = @@ -367,7 +366,7 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF, S_00B028_SGPRS(KernelInfo.NumSGPR / 8), 4); } - if (MFI->ShaderType == ShaderType::PIXEL) { + if (MFI->getShaderType() == ShaderType::PIXEL) { OutStreamer.EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4); OutStreamer.EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(LDSBlocks), 4); OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4); diff --git a/lib/Target/R600/AMDGPUCallingConv.td b/lib/Target/R600/AMDGPUCallingConv.td index 5f8ad8c3b17..3586c882690 100644 --- a/lib/Target/R600/AMDGPUCallingConv.td +++ b/lib/Target/R600/AMDGPUCallingConv.td @@ -62,11 +62,11 @@ def CC_AMDGPU : CallingConv<[ CCIf<"State.getTarget().getSubtarget().getGeneration() >= " "AMDGPUSubtarget::SOUTHERN_ISLANDS && " "State.getMachineFunction().getInfo()->"# - "ShaderType == ShaderType::COMPUTE", CCDelegateTo>, + "getShaderType() == ShaderType::COMPUTE", CCDelegateTo>, CCIf<"State.getTarget().getSubtarget().getGeneration() < " "AMDGPUSubtarget::SOUTHERN_ISLANDS && " "State.getMachineFunction().getInfo()->" - "ShaderType == ShaderType::COMPUTE", CCDelegateTo>, + "getShaderType() == ShaderType::COMPUTE", CCDelegateTo>, CCIf<"State.getTarget().getSubtarget()"# ".getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS", CCDelegateTo>, CCIf<"State.getTarget().getSubtarget()"# diff --git a/lib/Target/R600/AMDGPUMachineFunction.cpp b/lib/Target/R600/AMDGPUMachineFunction.cpp index 14171f46020..90af80113ec 100644 --- a/lib/Target/R600/AMDGPUMachineFunction.cpp +++ b/lib/Target/R600/AMDGPUMachineFunction.cpp @@ -10,9 +10,9 @@ static const char *const ShaderTypeAttribute = "ShaderType"; void AMDGPUMachineFunction::anchor() {} AMDGPUMachineFunction::AMDGPUMachineFunction(const MachineFunction &MF) : - MachineFunctionInfo() { - ShaderType = ShaderType::COMPUTE; - LDSSize = 0; + MachineFunctionInfo(), + ShaderType(ShaderType::COMPUTE), + LDSSize(0) { AttributeSet Set = MF.getFunction()->getAttributes(); Attribute A = Set.getAttribute(AttributeSet::FunctionIndex, ShaderTypeAttribute); diff --git a/lib/Target/R600/AMDGPUMachineFunction.h b/lib/Target/R600/AMDGPUMachineFunction.h index fea0b39e91e..0854d588eeb 100644 --- a/lib/Target/R600/AMDGPUMachineFunction.h +++ b/lib/Target/R600/AMDGPUMachineFunction.h @@ -20,14 +20,19 @@ namespace llvm { class AMDGPUMachineFunction : public MachineFunctionInfo { virtual void anchor(); + unsigned ShaderType; + public: AMDGPUMachineFunction(const MachineFunction &MF); - unsigned ShaderType; /// A map to keep track of local memory objects and their offsets within /// the local memory space. std::map LocalMemoryObjects; /// Number of bytes in the LDS that are being used. unsigned LDSSize; + + unsigned getShaderType() const { + return ShaderType; + } }; } diff --git a/lib/Target/R600/R600ControlFlowFinalizer.cpp b/lib/Target/R600/R600ControlFlowFinalizer.cpp index d98a6dbb37b..e37767a0719 100644 --- a/lib/Target/R600/R600ControlFlowFinalizer.cpp +++ b/lib/Target/R600/R600ControlFlowFinalizer.cpp @@ -481,14 +481,14 @@ public: TRI=static_cast(MF.getTarget().getRegisterInfo()); R600MachineFunctionInfo *MFI = MF.getInfo(); - CFStack CFStack(ST, MFI->ShaderType); + CFStack CFStack(ST, MFI->getShaderType()); for (MachineFunction::iterator MB = MF.begin(), ME = MF.end(); MB != ME; ++MB) { MachineBasicBlock &MBB = *MB; unsigned CfCount = 0; std::vector > > LoopStack; std::vector IfThenElseStack; - if (MFI->ShaderType == 1) { + if (MFI->getShaderType() == ShaderType::VERTEX) { BuildMI(MBB, MBB.begin(), MBB.findDebugLoc(MBB.begin()), getHWInstrDesc(CF_CALL_FS)); CfCount++; diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp index 50411f40443..c9e072a8327 100644 --- a/lib/Target/R600/R600ISelLowering.cpp +++ b/lib/Target/R600/R600ISelLowering.cpp @@ -1680,7 +1680,7 @@ SDValue R600TargetLowering::LowerFormalArguments( CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), getTargetMachine(), ArgLocs, *DAG.getContext()); MachineFunction &MF = DAG.getMachineFunction(); - unsigned ShaderType = MF.getInfo()->ShaderType; + unsigned ShaderType = MF.getInfo()->getShaderType(); SmallVector LocalIns; diff --git a/lib/Target/R600/R600InstrInfo.cpp b/lib/Target/R600/R600InstrInfo.cpp index 3972e2f0373..65dce6e5a7d 100644 --- a/lib/Target/R600/R600InstrInfo.cpp +++ b/lib/Target/R600/R600InstrInfo.cpp @@ -209,8 +209,10 @@ bool R600InstrInfo::usesVertexCache(unsigned Opcode) const { } bool R600InstrInfo::usesVertexCache(const MachineInstr *MI) const { - const R600MachineFunctionInfo *MFI = MI->getParent()->getParent()->getInfo(); - return MFI->ShaderType != ShaderType::COMPUTE && usesVertexCache(MI->getOpcode()); + const MachineFunction *MF = MI->getParent()->getParent(); + const R600MachineFunctionInfo *MFI = MF->getInfo(); + return MFI->getShaderType() != ShaderType::COMPUTE && + usesVertexCache(MI->getOpcode()); } bool R600InstrInfo::usesTextureCache(unsigned Opcode) const { @@ -218,9 +220,11 @@ bool R600InstrInfo::usesTextureCache(unsigned Opcode) const { } bool R600InstrInfo::usesTextureCache(const MachineInstr *MI) const { - const R600MachineFunctionInfo *MFI = MI->getParent()->getParent()->getInfo(); - return (MFI->ShaderType == ShaderType::COMPUTE && usesVertexCache(MI->getOpcode())) || - usesTextureCache(MI->getOpcode()); + const MachineFunction *MF = MI->getParent()->getParent(); + const R600MachineFunctionInfo *MFI = MF->getInfo(); + return (MFI->getShaderType() == ShaderType::COMPUTE && + usesVertexCache(MI->getOpcode())) || + usesTextureCache(MI->getOpcode()); } bool R600InstrInfo::mustBeLastInClause(unsigned Opcode) const { diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp index 63d3d385217..a7db2a9a3d9 100644 --- a/lib/Target/R600/SIISelLowering.cpp +++ b/lib/Target/R600/SIISelLowering.cpp @@ -327,7 +327,7 @@ SDValue SITargetLowering::LowerFormalArguments( const ISD::InputArg &Arg = Ins[i]; // First check if it's a PS input addr - if (Info->ShaderType == ShaderType::PIXEL && !Arg.Flags.isInReg() && + if (Info->getShaderType() == ShaderType::PIXEL && !Arg.Flags.isInReg() && !Arg.Flags.isByVal()) { assert((PSInputNum <= 15) && "Too many PS inputs!"); @@ -343,7 +343,7 @@ SDValue SITargetLowering::LowerFormalArguments( } // Second split vertices into their elements - if (Info->ShaderType != ShaderType::COMPUTE && Arg.VT.isVector()) { + if (Info->getShaderType() != ShaderType::COMPUTE && Arg.VT.isVector()) { ISD::InputArg NewArg = Arg; NewArg.Flags.setSplit(); NewArg.VT = Arg.VT.getVectorElementType(); @@ -359,7 +359,7 @@ SDValue SITargetLowering::LowerFormalArguments( NewArg.PartOffset += NewArg.VT.getStoreSize(); } - } else if (Info->ShaderType != ShaderType::COMPUTE) { + } else if (Info->getShaderType() != ShaderType::COMPUTE) { Splits.push_back(Arg); } } @@ -369,20 +369,21 @@ SDValue SITargetLowering::LowerFormalArguments( getTargetMachine(), ArgLocs, *DAG.getContext()); // At least one interpolation mode must be enabled or else the GPU will hang. - if (Info->ShaderType == ShaderType::PIXEL && (Info->PSInputAddr & 0x7F) == 0) { + if (Info->getShaderType() == ShaderType::PIXEL && + (Info->PSInputAddr & 0x7F) == 0) { Info->PSInputAddr |= 1; CCInfo.AllocateReg(AMDGPU::VGPR0); CCInfo.AllocateReg(AMDGPU::VGPR1); } // The pointer to the list of arguments is stored in SGPR0, SGPR1 - if (Info->ShaderType == ShaderType::COMPUTE) { + if (Info->getShaderType() == ShaderType::COMPUTE) { CCInfo.AllocateReg(AMDGPU::SGPR0); CCInfo.AllocateReg(AMDGPU::SGPR1); MF.addLiveIn(AMDGPU::SGPR0_SGPR1, &AMDGPU::SReg_64RegClass); } - if (Info->ShaderType == ShaderType::COMPUTE) { + if (Info->getShaderType() == ShaderType::COMPUTE) { getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins, Splits); } diff --git a/lib/Target/R600/SILowerControlFlow.cpp b/lib/Target/R600/SILowerControlFlow.cpp index 9f5ff29ad93..75b5a5e027f 100644 --- a/lib/Target/R600/SILowerControlFlow.cpp +++ b/lib/Target/R600/SILowerControlFlow.cpp @@ -147,7 +147,7 @@ void SILowerControlFlowPass::SkipIfDead(MachineInstr &MI) { MachineBasicBlock &MBB = *MI.getParent(); DebugLoc DL = MI.getDebugLoc(); - if (MBB.getParent()->getInfo()->ShaderType != + if (MBB.getParent()->getInfo()->getShaderType() != ShaderType::PIXEL || !shouldSkip(&MBB, &MBB.getParent()->back())) return; @@ -298,11 +298,13 @@ void SILowerControlFlowPass::Kill(MachineInstr &MI) { DebugLoc DL = MI.getDebugLoc(); const MachineOperand &Op = MI.getOperand(0); - // Kill is only allowed in pixel / geometry shaders - assert(MBB.getParent()->getInfo()->ShaderType == - ShaderType::PIXEL || - MBB.getParent()->getInfo()->ShaderType == - ShaderType::GEOMETRY); +#ifndef NDEBUG + const SIMachineFunctionInfo *MFI + = MBB.getParent()->getInfo(); + // Kill is only allowed in pixel / geometry shaders. + assert(MFI->getShaderType() == ShaderType::PIXEL || + MFI->getShaderType() == ShaderType::GEOMETRY); +#endif // Clear this thread from the exec mask if the operand is negative if ((Op.isImm() || Op.isFPImm())) { @@ -540,7 +542,7 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) { InitM0ForLDS(MBB.getFirstNonPHI()); } - if (NeedWQM && MFI->ShaderType == ShaderType::PIXEL) { + if (NeedWQM && MFI->getShaderType() == ShaderType::PIXEL) { MachineBasicBlock &MBB = MF.front(); BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_WQM_B64), AMDGPU::EXEC).addReg(AMDGPU::EXEC);