From: Jack Carter <jcarter@mips.com>
Date: Tue, 10 Jul 2012 22:41:20 +0000 (+0000)
Subject:    Mips specific inline asm operand modifier 'L'.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=bb78930489aceab797eecffe6771c6e52ff0c80c;p=oota-llvm.git

   Mips specific inline asm operand modifier 'L'.

   Low order register of a double word register operand. Operands
   are defined by the name of the variable they are marked with in
   the inline assembler code. This is a way to specify that the
   operand just refers to the low order register for that variable.

   It is the opposite of modifier 'D' which specifies the high order
   register.

   Example:

 main()
{

    long long ll_input = 0x1111222233334444LL;
    long long ll_val = 3;
    int i_result = 0;

    __asm__ __volatile__(
		   "or	%0, %L1, %2"
	     : "=r" (i_result)
	     : "r" (ll_input), "r" (ll_val));
}

   Which results in:

   	lui	$2, %hi(_gp_disp)
	addiu	$2, $2, %lo(_gp_disp)
	addiu	$sp, $sp, -8
	addu	$2, $2, $25
	sw	$2, 0($sp)
	lui	$2, 13107
	ori	$3, $2, 17476     <-- Low 32 bits of ll_input
	lui	$2, 4369
	ori	$4, $2, 8738      <-- High 32 bits of ll_input
	addiu	$5, $zero, 3  <-- Low 32 bits of ll_val
	addiu	$2, $zero, 0  <-- High 32 bits of ll_val
	#APP
	or	$3, $4, $5        <-- or i_result, high 32 ll_input, low 32 of ll_val
	#NO_APP
	addiu	$sp, $sp, 8
	jr	$ra

If not direction is done for the long long for 32 bit variables results
in using the low 32 bits as ll_val shows.

There is an existing bug if 'L' or 'D' is used for the destination register
for 32 bit long longs in that the target value will be updated incorrectly
for the non-specified part unless explicitly set within the inline asm code.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160028 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Mips/MipsAsmPrinter.cpp b/lib/Target/Mips/MipsAsmPrinter.cpp
index fc47ba5bfd6..3c50bae071a 100644
--- a/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -333,8 +333,9 @@ bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
         O << "$0";
       return false;
     }
-    case 'D': {
-      // Second part of a double word register operand
+    case 'D': // Second part of a double word register operand
+    case 'L': // Low order register of a double word register operand
+    {
       if (OpNum == 0)
         return true;
       const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
@@ -353,19 +354,26 @@ bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
         return true;
       }
       unsigned RegOp;
-      switch(ExtraCode[0]) {
-      case 'D':
-        RegOp = (!Subtarget->isGP32bit()) ? OpNum : OpNum + 1;
-        break;
+      if (Subtarget->isGP64bit())
+        RegOp = OpNum;
+      else {
+        // Endianess reverses which register holds the high or low value
+        switch(ExtraCode[0]) {
+        case 'D':
+          RegOp = (Subtarget->isLittle()) ? OpNum : OpNum+1;
+          break;
+        case 'L':
+          RegOp = (Subtarget->isLittle()) ? OpNum+1 : OpNum;
+        }
+        if (RegOp >= MI->getNumOperands())
+          return true;
+        const MachineOperand &MO = MI->getOperand(RegOp);
+        if (!MO.isReg())
+          return true;
+        unsigned Reg = MO.getReg();
+        O << '$' << MipsInstPrinter::getRegisterName(Reg);
+        return false;
       }
-      if (RegOp >= MI->getNumOperands())
-        return true;
-      const MachineOperand &MO = MI->getOperand(RegOp);
-      if (!MO.isReg())
-        return true;
-      unsigned Reg = MO.getReg();
-      O << '$' << MipsInstPrinter::getRegisterName(Reg);
-      return false;
     }
     }
   }
diff --git a/test/CodeGen/Mips/inlineasm-operand-code.ll b/test/CodeGen/Mips/inlineasm-operand-code.ll
index 8398cb0e38e..97ec629db20 100644
--- a/test/CodeGen/Mips/inlineasm-operand-code.ll
+++ b/test/CodeGen/Mips/inlineasm-operand-code.ll
@@ -56,7 +56,7 @@ entry:
 ;LITTLE:    lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
 ;LITTLE-NEXT: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
 ;LITTLE:	#APP
-;LITTLE:    or	${{[0-9]+}},$[[SECOND]],${{[0-9]+}}
+;LITTLE:    or	${{[0-9]+}},$[[FIRST]],${{[0-9]+}}
 ;LITTLE:    #NO_APP
 
 ; D, in big endian the source reg will also be 4 bytes into the long long
@@ -77,6 +77,16 @@ entry:
   %trunc1 = trunc i64 %7 to i32
   tail call i32 asm sideeffect "or $0,${1:D},$2", "=r,r,r"(i64 %7, i32 %trunc1) nounwind
 
+; L, in little endian the source reg will be 4 bytes into the long long
+;LITTLE:	#APP
+;LITTLE:	     or	${{[0-9]+}},$[[SECOND]],${{[0-9]+}}
+;LITTLE:	#NO_APP
+; L, in big endian the source reg will be 0 bytes into the long long
+;BIG:	#APP
+;BIG:	     or	${{[0-9]+}},$[[FIRST]],${{[0-9]+}}
+;BIG:	#NO_APP
+  tail call i32 asm sideeffect "or $0,${1:L},$2", "=r,r,r"(i64 %7, i32 %trunc1) nounwind
+
   ret i32 0
 }