From: Shuxin Yang <shuxin.llvm@gmail.com>
Date: Tue, 4 Dec 2012 03:28:32 +0000 (+0000)
Subject: rdar://12329730 (2nd part, revised)
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=bba3eb054a4e0e052cdeff22e678c52c4e59f07e;p=oota-llvm.git

rdar://12329730 (2nd part, revised)

The type of shirt-right (logical or arithemetic) should remain unchanged
when transforming  "X << C1 >> C2" into "X << (C1-C2)"


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169209 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index c65076e8831..c832ca5644a 100644
--- a/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -876,7 +876,8 @@ Value *InstCombiner::SimplifyShrShlDemandedBits(Instruction *Shr,
       New->setHasNoUnsignedWrap(Orig->hasNoUnsignedWrap());
     } else {
       Constant *Amt = ConstantInt::get(VarX->getType(), ShrAmt - ShlAmt);
-      New = BinaryOperator::CreateLShr(VarX, Amt);
+      New = isLshr ? BinaryOperator::CreateLShr(VarX, Amt) :
+                     BinaryOperator::CreateAShr(VarX, Amt);
     }
 
     return InsertNewInstWith(New, *Shl);
diff --git a/test/Transforms/InstCombine/shift.ll b/test/Transforms/InstCombine/shift.ll
index b152816d2b7..fad0bd7ede3 100644
--- a/test/Transforms/InstCombine/shift.ll
+++ b/test/Transforms/InstCombine/shift.ll
@@ -723,7 +723,7 @@ define i32 @test60(i32 %x) {
   %or = or i32 %shl, 1
   ret i32 %or
 ; CHECK: @test60
-; CHECK: lshr i32 %x, 3
+; CHECK: ashr i32 %x, 3
 }