From: dkl <dkl@rock-chips.com>
Date: Fri, 7 Feb 2014 12:19:16 +0000 (+0800)
Subject: ARM: rockchip: correct L2 latency setting
X-Git-Tag: firefly_0821_release~6354
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=bd1ad1b0a64f70a3af09494047ec8626fedd0715;p=firefly-linux-kernel-4.4.55.git

ARM: rockchip: correct L2 latency setting
---

diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index bbc3462b07f5..1f3572540bec 100755
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -69,7 +69,7 @@
 		cache-unified;
 		cache-level = <2>;
 		arm,tag-latency = <1 1 1>;
-		arm,data-latency = <2 3 1>;
+		arm,data-latency = <3 1 2>;
 		rockchip,prefetch-ctrl = <0x70000003>;
 		/* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
 		rockchip,power-ctrl = <0x3>;