From: Ville Syrjälä Date: Fri, 7 Jun 2013 07:47:03 +0000 (+0300) Subject: drm/i915: Disable trickle feed in ironlake_init_clock_gating() X-Git-Tag: firefly_0821_release~176^2~5752^2~61^2~49 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=bdad2b2f31852af4eb450d6a96e38940a0a1fdef;p=firefly-linux-kernel-4.4.55.git drm/i915: Disable trickle feed in ironlake_init_clock_gating() We disable trickle feed in all the (relevant) clock gating functions, except ironlake_init_clock_gating(). Copy paste the same code there as well. Signed-off-by: Ville Syrjälä Reviewed-by: Chris Wilson Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2948764d7e38..78addac68521 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4391,6 +4391,7 @@ static void ironlake_init_clock_gating(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; + int pipe; /* Required for FBC */ dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | @@ -4450,6 +4451,13 @@ static void ironlake_init_clock_gating(struct drm_device *dev) I915_WRITE(CACHE_MODE_0, _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); + for_each_pipe(pipe) { + I915_WRITE(DSPCNTR(pipe), + I915_READ(DSPCNTR(pipe)) | + DISPPLANE_TRICKLE_FEED_DISABLE); + intel_flush_display_plane(dev_priv, pipe); + } + ibx_init_clock_gating(dev); }