From: chenxing <chenxing@rock-chips.com>
Date: Sat, 8 Sep 2012 09:34:59 +0000 (+0800)
Subject: rk3066b: fix dclk_lcdc src bit
X-Git-Tag: firefly_0821_release~8680
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=be6e74287177956b8e433dff3eaf91c8b5e5b0cb;p=firefly-linux-kernel-4.4.55.git

rk3066b: fix dclk_lcdc src bit
---

diff --git a/arch/arm/mach-rk30/clock_data-rk3066b.c b/arch/arm/mach-rk30/clock_data-rk3066b.c
index 10eb5fc91513..e0b57663173e 100644
--- a/arch/arm/mach-rk30/clock_data-rk3066b.c
+++ b/arch/arm/mach-rk30/clock_data-rk3066b.c
@@ -1520,7 +1520,7 @@ static struct clk dclk_lcdc0 = {
 	.recalc		= clksel_recalc_div,
 	.gate_idx	= CLK_GATE_DCLK_LCDC0_SRC,
 	.clksel_con	= CRU_CLKSELS_CON(27),
-	CRU_SRC_SET(0x1, 4),
+	CRU_SRC_SET(0x1, 0),
 	CRU_DIV_SET(0xff, 8, 256),
 	CRU_PARENTS_SET(dclk_lcdc0_parents),
 };
@@ -1533,7 +1533,7 @@ static struct clk dclk_lcdc1 = {
 	.recalc		= clksel_recalc_div,
 	.gate_idx	= CLK_GATE_DCLK_LCDC1_SRC,
 	.clksel_con	= CRU_CLKSELS_CON(28),
-	CRU_SRC_SET(0x1, 4),
+	CRU_SRC_SET(0x1, 0),
 	CRU_DIV_SET(0xff, 8, 256),
 	CRU_PARENTS_SET(dclk_lcdc1_parents),
 };