From: Simon Pilgrim Date: Sun, 20 Sep 2015 15:41:35 +0000 (+0000) Subject: [X86][SSE] Intrinsics builtins test refresh. NFCI X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=bf48d8543ac44663f1538bd840b72d07e9773131;p=oota-llvm.git [X86][SSE] Intrinsics builtins test refresh. NFCI git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248122 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/test/CodeGen/X86/avx-intrinsics-x86.ll b/test/CodeGen/X86/avx-intrinsics-x86.ll index 28a0272ecf0..d63f5735cad 100644 --- a/test/CodeGen/X86/avx-intrinsics-x86.ll +++ b/test/CodeGen/X86/avx-intrinsics-x86.ll @@ -2,7 +2,7 @@ define <2 x i64> @test_x86_aesni_aesdec(<2 x i64> %a0, <2 x i64> %a1) { ; CHECK-LABEL: test_x86_aesni_aesdec: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vaesdec %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x i64> @llvm.x86.aesni.aesdec(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1] @@ -13,7 +13,7 @@ declare <2 x i64> @llvm.x86.aesni.aesdec(<2 x i64>, <2 x i64>) nounwind readnone define <2 x i64> @test_x86_aesni_aesdeclast(<2 x i64> %a0, <2 x i64> %a1) { ; CHECK-LABEL: test_x86_aesni_aesdeclast: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vaesdeclast %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x i64> @llvm.x86.aesni.aesdeclast(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1] @@ -24,7 +24,7 @@ declare <2 x i64> @llvm.x86.aesni.aesdeclast(<2 x i64>, <2 x i64>) nounwind read define <2 x i64> @test_x86_aesni_aesenc(<2 x i64> %a0, <2 x i64> %a1) { ; CHECK-LABEL: test_x86_aesni_aesenc: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vaesenc %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1] @@ -35,7 +35,7 @@ declare <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64>, <2 x i64>) nounwind readnone define <2 x i64> @test_x86_aesni_aesenclast(<2 x i64> %a0, <2 x i64> %a1) { ; CHECK-LABEL: test_x86_aesni_aesenclast: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vaesenclast %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x i64> @llvm.x86.aesni.aesenclast(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1] @@ -46,7 +46,7 @@ declare <2 x i64> @llvm.x86.aesni.aesenclast(<2 x i64>, <2 x i64>) nounwind read define <2 x i64> @test_x86_aesni_aesimc(<2 x i64> %a0) { ; CHECK-LABEL: test_x86_aesni_aesimc: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vaesimc %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x i64> @llvm.x86.aesni.aesimc(<2 x i64> %a0) ; <<2 x i64>> [#uses=1] @@ -57,7 +57,7 @@ declare <2 x i64> @llvm.x86.aesni.aesimc(<2 x i64>) nounwind readnone define <2 x i64> @test_x86_aesni_aeskeygenassist(<2 x i64> %a0) { ; CHECK-LABEL: test_x86_aesni_aeskeygenassist: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vaeskeygenassist $7, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64> %a0, i8 7) ; <<2 x i64>> [#uses=1] @@ -68,7 +68,7 @@ declare <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64>, i8) nounwind readno define <2 x double> @test_x86_sse2_add_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse2_add_sd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vaddsd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1] @@ -79,7 +79,7 @@ declare <2 x double> @llvm.x86.sse2.add.sd(<2 x double>, <2 x double>) nounwind define <2 x double> @test_x86_sse2_cmp_pd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse2_cmp_pd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcmpordpd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x double>> [#uses=1] @@ -90,7 +90,7 @@ declare <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double>, <2 x double>, i8) nounw define <2 x double> @test_x86_sse2_cmp_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse2_cmp_sd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcmpordsd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x double>> [#uses=1] @@ -101,7 +101,7 @@ declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8) nounw define i32 @test_x86_sse2_comieq_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse2_comieq_sd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcomisd %xmm1, %xmm0 ; CHECK-NEXT: sete %al ; CHECK-NEXT: movzbl %al, %eax @@ -114,7 +114,7 @@ declare i32 @llvm.x86.sse2.comieq.sd(<2 x double>, <2 x double>) nounwind readno define i32 @test_x86_sse2_comige_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse2_comige_sd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcomisd %xmm1, %xmm0 ; CHECK-NEXT: setae %al ; CHECK-NEXT: movzbl %al, %eax @@ -127,7 +127,7 @@ declare i32 @llvm.x86.sse2.comige.sd(<2 x double>, <2 x double>) nounwind readno define i32 @test_x86_sse2_comigt_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse2_comigt_sd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcomisd %xmm1, %xmm0 ; CHECK-NEXT: seta %al ; CHECK-NEXT: movzbl %al, %eax @@ -140,7 +140,7 @@ declare i32 @llvm.x86.sse2.comigt.sd(<2 x double>, <2 x double>) nounwind readno define i32 @test_x86_sse2_comile_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse2_comile_sd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcomisd %xmm1, %xmm0 ; CHECK-NEXT: setbe %al ; CHECK-NEXT: movzbl %al, %eax @@ -153,7 +153,7 @@ declare i32 @llvm.x86.sse2.comile.sd(<2 x double>, <2 x double>) nounwind readno define i32 @test_x86_sse2_comilt_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse2_comilt_sd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcomisd %xmm1, %xmm0 ; CHECK-NEXT: sbbl %eax, %eax ; CHECK-NEXT: andl $1, %eax @@ -166,7 +166,7 @@ declare i32 @llvm.x86.sse2.comilt.sd(<2 x double>, <2 x double>) nounwind readno define i32 @test_x86_sse2_comineq_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse2_comineq_sd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcomisd %xmm1, %xmm0 ; CHECK-NEXT: setne %al ; CHECK-NEXT: movzbl %al, %eax @@ -179,7 +179,7 @@ declare i32 @llvm.x86.sse2.comineq.sd(<2 x double>, <2 x double>) nounwind readn define <2 x double> @test_x86_sse2_cvtdq2pd(<4 x i32> %a0) { ; CHECK-LABEL: test_x86_sse2_cvtdq2pd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcvtdq2pd %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.sse2.cvtdq2pd(<4 x i32> %a0) ; <<2 x double>> [#uses=1] @@ -190,7 +190,7 @@ declare <2 x double> @llvm.x86.sse2.cvtdq2pd(<4 x i32>) nounwind readnone define <4 x float> @test_x86_sse2_cvtdq2ps(<4 x i32> %a0) { ; CHECK-LABEL: test_x86_sse2_cvtdq2ps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %a0) ; <<4 x float>> [#uses=1] @@ -201,7 +201,7 @@ declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone define <4 x i32> @test_x86_sse2_cvtpd2dq(<2 x double> %a0) { ; CHECK-LABEL: test_x86_sse2_cvtpd2dq: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcvtpd2dq %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %a0) ; <<4 x i32>> [#uses=1] @@ -212,7 +212,7 @@ declare <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double>) nounwind readnone define <4 x float> @test_x86_sse2_cvtpd2ps(<2 x double> %a0) { ; CHECK-LABEL: test_x86_sse2_cvtpd2ps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcvtpd2ps %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> %a0) ; <<4 x float>> [#uses=1] @@ -223,7 +223,7 @@ declare <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double>) nounwind readnone define <4 x i32> @test_x86_sse2_cvtps2dq(<4 x float> %a0) { ; CHECK-LABEL: test_x86_sse2_cvtps2dq: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcvtps2dq %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %a0) ; <<4 x i32>> [#uses=1] @@ -234,7 +234,7 @@ declare <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float>) nounwind readnone define <2 x double> @test_x86_sse2_cvtps2pd(<4 x float> %a0) { ; CHECK-LABEL: test_x86_sse2_cvtps2pd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcvtps2pd %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.sse2.cvtps2pd(<4 x float> %a0) ; <<2 x double>> [#uses=1] @@ -245,7 +245,7 @@ declare <2 x double> @llvm.x86.sse2.cvtps2pd(<4 x float>) nounwind readnone define i32 @test_x86_sse2_cvtsd2si(<2 x double> %a0) { ; CHECK-LABEL: test_x86_sse2_cvtsd2si: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcvtsd2si %xmm0, %eax ; CHECK-NEXT: retl %res = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %a0) ; [#uses=1] @@ -256,7 +256,7 @@ declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>) nounwind readnone define <4 x float> @test_x86_sse2_cvtsd2ss(<4 x float> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse2_cvtsd2ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcvtsd2ss %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> %a0, <2 x double> %a1) ; <<4 x float>> [#uses=1] @@ -267,7 +267,7 @@ declare <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float>, <2 x double>) nounwind define <2 x double> @test_x86_sse2_cvtsi2sd(<2 x double> %a0) { ; CHECK-LABEL: test_x86_sse2_cvtsi2sd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl $7, %eax ; CHECK-NEXT: vcvtsi2sdl %eax, %xmm0, %xmm0 ; CHECK-NEXT: retl @@ -279,7 +279,7 @@ declare <2 x double> @llvm.x86.sse2.cvtsi2sd(<2 x double>, i32) nounwind readnon define <2 x double> @test_x86_sse2_cvtss2sd(<2 x double> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse2_cvtss2sd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcvtss2sd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double> %a0, <4 x float> %a1) ; <<2 x double>> [#uses=1] @@ -290,7 +290,7 @@ declare <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double>, <4 x float>) nounwind define <4 x i32> @test_x86_sse2_cvttpd2dq(<2 x double> %a0) { ; CHECK-LABEL: test_x86_sse2_cvttpd2dq: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcvttpd2dq %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %a0) ; <<4 x i32>> [#uses=1] @@ -301,7 +301,7 @@ declare <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double>) nounwind readnone define <4 x i32> @test_x86_sse2_cvttps2dq(<4 x float> %a0) { ; CHECK-LABEL: test_x86_sse2_cvttps2dq: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcvttps2dq %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a0) ; <<4 x i32>> [#uses=1] @@ -312,7 +312,7 @@ declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>) nounwind readnone define i32 @test_x86_sse2_cvttsd2si(<2 x double> %a0) { ; CHECK-LABEL: test_x86_sse2_cvttsd2si: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcvttsd2si %xmm0, %eax ; CHECK-NEXT: retl %res = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %a0) ; [#uses=1] @@ -323,7 +323,7 @@ declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>) nounwind readnone define <2 x double> @test_x86_sse2_div_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse2_div_sd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vdivsd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.sse2.div.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1] @@ -335,7 +335,7 @@ declare <2 x double> @llvm.x86.sse2.div.sd(<2 x double>, <2 x double>) nounwind define <2 x double> @test_x86_sse2_max_pd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse2_max_pd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vmaxpd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.sse2.max.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1] @@ -346,7 +346,7 @@ declare <2 x double> @llvm.x86.sse2.max.pd(<2 x double>, <2 x double>) nounwind define <2 x double> @test_x86_sse2_max_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse2_max_sd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vmaxsd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1] @@ -357,7 +357,7 @@ declare <2 x double> @llvm.x86.sse2.max.sd(<2 x double>, <2 x double>) nounwind define <2 x double> @test_x86_sse2_min_pd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse2_min_pd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vminpd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1] @@ -368,7 +368,7 @@ declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind define <2 x double> @test_x86_sse2_min_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse2_min_sd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vminsd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1] @@ -379,7 +379,7 @@ declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind define i32 @test_x86_sse2_movmsk_pd(<2 x double> %a0) { ; CHECK-LABEL: test_x86_sse2_movmsk_pd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vmovmskpd %xmm0, %eax ; CHECK-NEXT: retl %res = call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> %a0) ; [#uses=1] @@ -392,7 +392,7 @@ declare i32 @llvm.x86.sse2.movmsk.pd(<2 x double>) nounwind readnone define <2 x double> @test_x86_sse2_mul_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse2_mul_sd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vmulsd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.sse2.mul.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1] @@ -403,7 +403,7 @@ declare <2 x double> @llvm.x86.sse2.mul.sd(<2 x double>, <2 x double>) nounwind define <8 x i16> @test_x86_sse2_packssdw_128(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK-LABEL: test_x86_sse2_packssdw_128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpackssdw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %a0, <4 x i32> %a1) ; <<8 x i16>> [#uses=1] @@ -414,7 +414,7 @@ declare <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32>, <4 x i32>) nounwind rea define <16 x i8> @test_x86_sse2_packsswb_128(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_sse2_packsswb_128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> %a0, <8 x i16> %a1) ; <<16 x i8>> [#uses=1] @@ -425,7 +425,7 @@ declare <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16>, <8 x i16>) nounwind rea define <16 x i8> @test_x86_sse2_packuswb_128(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_sse2_packuswb_128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpackuswb %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> %a0, <8 x i16> %a1) ; <<16 x i8>> [#uses=1] @@ -436,7 +436,7 @@ declare <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16>, <8 x i16>) nounwind rea define <16 x i8> @test_x86_sse2_padds_b(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK-LABEL: test_x86_sse2_padds_b: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpaddsb %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <16 x i8> @llvm.x86.sse2.padds.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1] @@ -447,7 +447,7 @@ declare <16 x i8> @llvm.x86.sse2.padds.b(<16 x i8>, <16 x i8>) nounwind readnone define <8 x i16> @test_x86_sse2_padds_w(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_sse2_padds_w: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpaddsw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -458,7 +458,7 @@ declare <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16>, <8 x i16>) nounwind readnone define <16 x i8> @test_x86_sse2_paddus_b(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK-LABEL: test_x86_sse2_paddus_b: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpaddusb %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <16 x i8> @llvm.x86.sse2.paddus.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1] @@ -469,7 +469,7 @@ declare <16 x i8> @llvm.x86.sse2.paddus.b(<16 x i8>, <16 x i8>) nounwind readnon define <8 x i16> @test_x86_sse2_paddus_w(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_sse2_paddus_w: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpaddusw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.sse2.paddus.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -480,7 +480,7 @@ declare <8 x i16> @llvm.x86.sse2.paddus.w(<8 x i16>, <8 x i16>) nounwind readnon define <16 x i8> @test_x86_sse2_pavg_b(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK-LABEL: test_x86_sse2_pavg_b: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpavgb %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1] @@ -491,7 +491,7 @@ declare <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8>, <16 x i8>) nounwind readnone define <8 x i16> @test_x86_sse2_pavg_w(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_sse2_pavg_w: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpavgw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -502,7 +502,7 @@ declare <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16>, <8 x i16>) nounwind readnone define <4 x i32> @test_x86_sse2_pmadd_wd(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_sse2_pmadd_wd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmaddwd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a0, <8 x i16> %a1) ; <<4 x i32>> [#uses=1] @@ -513,7 +513,7 @@ declare <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16>, <8 x i16>) nounwind readnon define <8 x i16> @test_x86_sse2_pmaxs_w(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_sse2_pmaxs_w: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.sse2.pmaxs.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -524,7 +524,7 @@ declare <8 x i16> @llvm.x86.sse2.pmaxs.w(<8 x i16>, <8 x i16>) nounwind readnone define <16 x i8> @test_x86_sse2_pmaxu_b(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK-LABEL: test_x86_sse2_pmaxu_b: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <16 x i8> @llvm.x86.sse2.pmaxu.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1] @@ -535,7 +535,7 @@ declare <16 x i8> @llvm.x86.sse2.pmaxu.b(<16 x i8>, <16 x i8>) nounwind readnone define <8 x i16> @test_x86_sse2_pmins_w(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_sse2_pmins_w: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpminsw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -546,7 +546,7 @@ declare <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16>, <8 x i16>) nounwind readnone define <16 x i8> @test_x86_sse2_pminu_b(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK-LABEL: test_x86_sse2_pminu_b: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpminub %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <16 x i8> @llvm.x86.sse2.pminu.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1] @@ -557,7 +557,7 @@ declare <16 x i8> @llvm.x86.sse2.pminu.b(<16 x i8>, <16 x i8>) nounwind readnone define i32 @test_x86_sse2_pmovmskb_128(<16 x i8> %a0) { ; CHECK-LABEL: test_x86_sse2_pmovmskb_128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmovmskb %xmm0, %eax ; CHECK-NEXT: retl %res = call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %a0) ; [#uses=1] @@ -568,7 +568,7 @@ declare i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8>) nounwind readnone define <8 x i16> @test_x86_sse2_pmulh_w(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_sse2_pmulh_w: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmulhw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -579,7 +579,7 @@ declare <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16>, <8 x i16>) nounwind readnone define <8 x i16> @test_x86_sse2_pmulhu_w(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_sse2_pmulhu_w: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmulhuw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -590,7 +590,7 @@ declare <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16>, <8 x i16>) nounwind readnon define <2 x i64> @test_x86_sse2_pmulu_dq(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK-LABEL: test_x86_sse2_pmulu_dq: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmuludq %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %a0, <4 x i32> %a1) ; <<2 x i64>> [#uses=1] @@ -601,7 +601,7 @@ declare <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32>, <4 x i32>) nounwind readnon define <2 x i64> @test_x86_sse2_psad_bw(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK-LABEL: test_x86_sse2_psad_bw: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %a0, <16 x i8> %a1) ; <<2 x i64>> [#uses=1] @@ -612,7 +612,7 @@ declare <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8>, <16 x i8>) nounwind readnone define <4 x i32> @test_x86_sse2_psll_d(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK-LABEL: test_x86_sse2_psll_d: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpslld %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] @@ -623,7 +623,7 @@ declare <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32>, <4 x i32>) nounwind readnone define <2 x i64> @test_x86_sse2_psll_q(<2 x i64> %a0, <2 x i64> %a1) { ; CHECK-LABEL: test_x86_sse2_psll_q: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpsllq %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1] @@ -634,7 +634,7 @@ declare <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64>, <2 x i64>) nounwind readnone define <8 x i16> @test_x86_sse2_psll_w(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_sse2_psll_w: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpsllw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -645,7 +645,7 @@ declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) nounwind readnone define <4 x i32> @test_x86_sse2_pslli_d(<4 x i32> %a0) { ; CHECK-LABEL: test_x86_sse2_pslli_d: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpslld $7, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %a0, i32 7) ; <<4 x i32>> [#uses=1] @@ -656,7 +656,7 @@ declare <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32>, i32) nounwind readnone define <2 x i64> @test_x86_sse2_pslli_q(<2 x i64> %a0) { ; CHECK-LABEL: test_x86_sse2_pslli_q: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpsllq $7, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1] @@ -667,7 +667,7 @@ declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32) nounwind readnone define <8 x i16> @test_x86_sse2_pslli_w(<8 x i16> %a0) { ; CHECK-LABEL: test_x86_sse2_pslli_w: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpsllw $7, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %a0, i32 7) ; <<8 x i16>> [#uses=1] @@ -678,7 +678,7 @@ declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32) nounwind readnone define <4 x i32> @test_x86_sse2_psra_d(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK-LABEL: test_x86_sse2_psra_d: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpsrad %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] @@ -689,7 +689,7 @@ declare <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32>, <4 x i32>) nounwind readnone define <8 x i16> @test_x86_sse2_psra_w(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_sse2_psra_w: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpsraw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -700,7 +700,7 @@ declare <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16>, <8 x i16>) nounwind readnone define <4 x i32> @test_x86_sse2_psrai_d(<4 x i32> %a0) { ; CHECK-LABEL: test_x86_sse2_psrai_d: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpsrad $7, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %a0, i32 7) ; <<4 x i32>> [#uses=1] @@ -711,7 +711,7 @@ declare <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32>, i32) nounwind readnone define <8 x i16> @test_x86_sse2_psrai_w(<8 x i16> %a0) { ; CHECK-LABEL: test_x86_sse2_psrai_w: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpsraw $7, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %a0, i32 7) ; <<8 x i16>> [#uses=1] @@ -722,7 +722,7 @@ declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32) nounwind readnone define <4 x i32> @test_x86_sse2_psrl_d(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK-LABEL: test_x86_sse2_psrl_d: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpsrld %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] @@ -733,7 +733,7 @@ declare <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32>, <4 x i32>) nounwind readnone define <2 x i64> @test_x86_sse2_psrl_q(<2 x i64> %a0, <2 x i64> %a1) { ; CHECK-LABEL: test_x86_sse2_psrl_q: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpsrlq %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1] @@ -744,7 +744,7 @@ declare <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64>, <2 x i64>) nounwind readnone define <8 x i16> @test_x86_sse2_psrl_w(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_sse2_psrl_w: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -755,7 +755,7 @@ declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>) nounwind readnone define <4 x i32> @test_x86_sse2_psrli_d(<4 x i32> %a0) { ; CHECK-LABEL: test_x86_sse2_psrli_d: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpsrld $7, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %a0, i32 7) ; <<4 x i32>> [#uses=1] @@ -766,7 +766,7 @@ declare <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32>, i32) nounwind readnone define <2 x i64> @test_x86_sse2_psrli_q(<2 x i64> %a0) { ; CHECK-LABEL: test_x86_sse2_psrli_q: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpsrlq $7, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1] @@ -777,7 +777,7 @@ declare <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64>, i32) nounwind readnone define <8 x i16> @test_x86_sse2_psrli_w(<8 x i16> %a0) { ; CHECK-LABEL: test_x86_sse2_psrli_w: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpsrlw $7, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %a0, i32 7) ; <<8 x i16>> [#uses=1] @@ -788,7 +788,7 @@ declare <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16>, i32) nounwind readnone define <16 x i8> @test_x86_sse2_psubs_b(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK-LABEL: test_x86_sse2_psubs_b: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpsubsb %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <16 x i8> @llvm.x86.sse2.psubs.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1] @@ -799,7 +799,7 @@ declare <16 x i8> @llvm.x86.sse2.psubs.b(<16 x i8>, <16 x i8>) nounwind readnone define <8 x i16> @test_x86_sse2_psubs_w(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_sse2_psubs_w: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpsubsw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -810,7 +810,7 @@ declare <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16>, <8 x i16>) nounwind readnone define <16 x i8> @test_x86_sse2_psubus_b(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK-LABEL: test_x86_sse2_psubus_b: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <16 x i8> @llvm.x86.sse2.psubus.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1] @@ -821,7 +821,7 @@ declare <16 x i8> @llvm.x86.sse2.psubus.b(<16 x i8>, <16 x i8>) nounwind readnon define <8 x i16> @test_x86_sse2_psubus_w(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_sse2_psubus_w: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpsubusw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.sse2.psubus.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -832,7 +832,7 @@ declare <8 x i16> @llvm.x86.sse2.psubus.w(<8 x i16>, <8 x i16>) nounwind readnon define <2 x double> @test_x86_sse2_sqrt_pd(<2 x double> %a0) { ; CHECK-LABEL: test_x86_sse2_sqrt_pd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vsqrtpd %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double> %a0) ; <<2 x double>> [#uses=1] @@ -843,7 +843,7 @@ declare <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double>) nounwind readnone define <2 x double> @test_x86_sse2_sqrt_sd(<2 x double> %a0) { ; CHECK-LABEL: test_x86_sse2_sqrt_sd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %a0) ; <<2 x double>> [#uses=1] @@ -854,7 +854,7 @@ declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>) nounwind readnone define void @test_x86_sse2_storel_dq(i8* %a0, <4 x i32> %a1) { ; CHECK-LABEL: test_x86_sse2_storel_dq: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vmovlps %xmm0, (%eax) ; CHECK-NEXT: retl @@ -867,7 +867,7 @@ declare void @llvm.x86.sse2.storel.dq(i8*, <4 x i32>) nounwind define void @test_x86_sse2_storeu_dq(i8* %a0, <16 x i8> %a1) { ; add operation forces the execution domain. ; CHECK-LABEL: test_x86_sse2_storeu_dq: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vpaddb LCPI77_0, %xmm0, %xmm0 ; CHECK-NEXT: vmovdqu %xmm0, (%eax) @@ -882,7 +882,7 @@ declare void @llvm.x86.sse2.storeu.dq(i8*, <16 x i8>) nounwind define void @test_x86_sse2_storeu_pd(i8* %a0, <2 x double> %a1) { ; fadd operation forces the execution domain. ; CHECK-LABEL: test_x86_sse2_storeu_pd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero ; CHECK-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7] @@ -898,7 +898,7 @@ declare void @llvm.x86.sse2.storeu.pd(i8*, <2 x double>) nounwind define <2 x double> @test_x86_sse2_sub_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse2_sub_sd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vsubsd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.sse2.sub.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1] @@ -909,7 +909,7 @@ declare <2 x double> @llvm.x86.sse2.sub.sd(<2 x double>, <2 x double>) nounwind define i32 @test_x86_sse2_ucomieq_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse2_ucomieq_sd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vucomisd %xmm1, %xmm0 ; CHECK-NEXT: sete %al ; CHECK-NEXT: movzbl %al, %eax @@ -922,7 +922,7 @@ declare i32 @llvm.x86.sse2.ucomieq.sd(<2 x double>, <2 x double>) nounwind readn define i32 @test_x86_sse2_ucomige_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse2_ucomige_sd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vucomisd %xmm1, %xmm0 ; CHECK-NEXT: setae %al ; CHECK-NEXT: movzbl %al, %eax @@ -935,7 +935,7 @@ declare i32 @llvm.x86.sse2.ucomige.sd(<2 x double>, <2 x double>) nounwind readn define i32 @test_x86_sse2_ucomigt_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse2_ucomigt_sd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vucomisd %xmm1, %xmm0 ; CHECK-NEXT: seta %al ; CHECK-NEXT: movzbl %al, %eax @@ -948,7 +948,7 @@ declare i32 @llvm.x86.sse2.ucomigt.sd(<2 x double>, <2 x double>) nounwind readn define i32 @test_x86_sse2_ucomile_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse2_ucomile_sd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vucomisd %xmm1, %xmm0 ; CHECK-NEXT: setbe %al ; CHECK-NEXT: movzbl %al, %eax @@ -961,7 +961,7 @@ declare i32 @llvm.x86.sse2.ucomile.sd(<2 x double>, <2 x double>) nounwind readn define i32 @test_x86_sse2_ucomilt_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse2_ucomilt_sd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vucomisd %xmm1, %xmm0 ; CHECK-NEXT: sbbl %eax, %eax ; CHECK-NEXT: andl $1, %eax @@ -974,7 +974,7 @@ declare i32 @llvm.x86.sse2.ucomilt.sd(<2 x double>, <2 x double>) nounwind readn define i32 @test_x86_sse2_ucomineq_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse2_ucomineq_sd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vucomisd %xmm1, %xmm0 ; CHECK-NEXT: setne %al ; CHECK-NEXT: movzbl %al, %eax @@ -987,7 +987,7 @@ declare i32 @llvm.x86.sse2.ucomineq.sd(<2 x double>, <2 x double>) nounwind read define <2 x double> @test_x86_sse3_addsub_pd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse3_addsub_pd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vaddsubpd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1] @@ -998,7 +998,7 @@ declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>) nounwi define <4 x float> @test_x86_sse3_addsub_ps(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse3_addsub_ps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vaddsubps %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1] @@ -1009,7 +1009,7 @@ declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>) nounwind define <2 x double> @test_x86_sse3_hadd_pd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse3_hadd_pd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vhaddpd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1] @@ -1020,7 +1020,7 @@ declare <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double>, <2 x double>) nounwind define <4 x float> @test_x86_sse3_hadd_ps(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse3_hadd_ps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vhaddps %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1] @@ -1031,7 +1031,7 @@ declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>) nounwind re define <2 x double> @test_x86_sse3_hsub_pd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse3_hsub_pd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vhsubpd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1] @@ -1042,7 +1042,7 @@ declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind define <4 x float> @test_x86_sse3_hsub_ps(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse3_hsub_ps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vhsubps %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1] @@ -1053,7 +1053,7 @@ declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>) nounwind re define <16 x i8> @test_x86_sse3_ldu_dq(i8* %a0) { ; CHECK-LABEL: test_x86_sse3_ldu_dq: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vlddqu (%eax), %xmm0 ; CHECK-NEXT: retl @@ -1065,7 +1065,7 @@ declare <16 x i8> @llvm.x86.sse3.ldu.dq(i8*) nounwind readonly define <2 x double> @test_x86_sse41_blendvpd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) { ; CHECK-LABEL: test_x86_sse41_blendvpd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vblendvpd %xmm2, %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.sse41.blendvpd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) ; <<2 x double>> [#uses=1] @@ -1076,7 +1076,7 @@ declare <2 x double> @llvm.x86.sse41.blendvpd(<2 x double>, <2 x double>, <2 x d define <4 x float> @test_x86_sse41_blendvps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) { ; CHECK-LABEL: test_x86_sse41_blendvps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) ; <<4 x float>> [#uses=1] @@ -1087,7 +1087,7 @@ declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>, <4 x floa define <2 x double> @test_x86_sse41_dppd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse41_dppd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vdppd $7, %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.sse41.dppd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x double>> [#uses=1] @@ -1098,7 +1098,7 @@ declare <2 x double> @llvm.x86.sse41.dppd(<2 x double>, <2 x double>, i8) nounwi define <4 x float> @test_x86_sse41_dpps(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse41_dpps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vdpps $7, %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse41.dpps(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1] @@ -1109,7 +1109,7 @@ declare <4 x float> @llvm.x86.sse41.dpps(<4 x float>, <4 x float>, i8) nounwind define <4 x float> @test_x86_sse41_insertps(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse41_insertps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = zero,zero,zero,xmm0[3] ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1] @@ -1121,7 +1121,7 @@ declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i8) nounw define <8 x i16> @test_x86_sse41_mpsadbw(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK-LABEL: test_x86_sse41_mpsadbw: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vmpsadbw $7, %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <<8 x i16>> [#uses=1] @@ -1132,7 +1132,7 @@ declare <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8>, <16 x i8>, i8) nounwind rea define <8 x i16> @test_x86_sse41_packusdw(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK-LABEL: test_x86_sse41_packusdw: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpackusdw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1) ; <<8 x i16>> [#uses=1] @@ -1143,7 +1143,7 @@ declare <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32>, <4 x i32>) nounwind readno define <16 x i8> @test_x86_sse41_pblendvb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %a2) { ; CHECK-LABEL: test_x86_sse41_pblendvb: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %a2) ; <<16 x i8>> [#uses=1] @@ -1154,7 +1154,7 @@ declare <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8>, <16 x i8>, <16 x i8>) noun define <8 x i16> @test_x86_sse41_phminposuw(<8 x i16> %a0) { ; CHECK-LABEL: test_x86_sse41_phminposuw: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vphminposuw %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.sse41.phminposuw(<8 x i16> %a0) ; <<8 x i16>> [#uses=1] @@ -1165,7 +1165,7 @@ declare <8 x i16> @llvm.x86.sse41.phminposuw(<8 x i16>) nounwind readnone define <16 x i8> @test_x86_sse41_pmaxsb(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK-LABEL: test_x86_sse41_pmaxsb: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <16 x i8> @llvm.x86.sse41.pmaxsb(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1] @@ -1176,7 +1176,7 @@ declare <16 x i8> @llvm.x86.sse41.pmaxsb(<16 x i8>, <16 x i8>) nounwind readnone define <4 x i32> @test_x86_sse41_pmaxsd(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK-LABEL: test_x86_sse41_pmaxsd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] @@ -1187,7 +1187,7 @@ declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone define <4 x i32> @test_x86_sse41_pmaxud(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK-LABEL: test_x86_sse41_pmaxud: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] @@ -1198,7 +1198,7 @@ declare <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32>, <4 x i32>) nounwind readnone define <8 x i16> @test_x86_sse41_pmaxuw(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_sse41_pmaxuw: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmaxuw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.sse41.pmaxuw(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -1209,7 +1209,7 @@ declare <8 x i16> @llvm.x86.sse41.pmaxuw(<8 x i16>, <8 x i16>) nounwind readnone define <16 x i8> @test_x86_sse41_pminsb(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK-LABEL: test_x86_sse41_pminsb: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpminsb %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <16 x i8> @llvm.x86.sse41.pminsb(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1] @@ -1220,7 +1220,7 @@ declare <16 x i8> @llvm.x86.sse41.pminsb(<16 x i8>, <16 x i8>) nounwind readnone define <4 x i32> @test_x86_sse41_pminsd(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK-LABEL: test_x86_sse41_pminsd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpminsd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] @@ -1231,7 +1231,7 @@ declare <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32>, <4 x i32>) nounwind readnone define <4 x i32> @test_x86_sse41_pminud(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK-LABEL: test_x86_sse41_pminud: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpminud %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] @@ -1242,7 +1242,7 @@ declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>) nounwind readnone define <8 x i16> @test_x86_sse41_pminuw(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_sse41_pminuw: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpminuw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.sse41.pminuw(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -1253,7 +1253,7 @@ declare <8 x i16> @llvm.x86.sse41.pminuw(<8 x i16>, <8 x i16>) nounwind readnone define <4 x i32> @test_x86_sse41_pmovsxbd(<16 x i8> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovsxbd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmovsxbd %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %a0) ; <<4 x i32>> [#uses=1] @@ -1264,7 +1264,7 @@ declare <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8>) nounwind readnone define <2 x i64> @test_x86_sse41_pmovsxbq(<16 x i8> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovsxbq: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmovsxbq %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8> %a0) ; <<2 x i64>> [#uses=1] @@ -1275,7 +1275,7 @@ declare <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8>) nounwind readnone define <8 x i16> @test_x86_sse41_pmovsxbw(<16 x i8> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovsxbw: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmovsxbw %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8> %a0) ; <<8 x i16>> [#uses=1] @@ -1286,7 +1286,7 @@ declare <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8>) nounwind readnone define <2 x i64> @test_x86_sse41_pmovsxdq(<4 x i32> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovsxdq: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmovsxdq %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32> %a0) ; <<2 x i64>> [#uses=1] @@ -1297,7 +1297,7 @@ declare <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32>) nounwind readnone define <4 x i32> @test_x86_sse41_pmovsxwd(<8 x i16> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovsxwd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmovsxwd %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %a0) ; <<4 x i32>> [#uses=1] @@ -1308,7 +1308,7 @@ declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone define <2 x i64> @test_x86_sse41_pmovsxwq(<8 x i16> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovsxwq: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmovsxwq %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16> %a0) ; <<2 x i64>> [#uses=1] @@ -1319,7 +1319,7 @@ declare <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16>) nounwind readnone define <4 x i32> @test_x86_sse41_pmovzxbd(<16 x i8> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovzxbd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; CHECK-NEXT: retl %res = call <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8> %a0) ; <<4 x i32>> [#uses=1] @@ -1330,7 +1330,7 @@ declare <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8>) nounwind readnone define <2 x i64> @test_x86_sse41_pmovzxbq(<16 x i8> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovzxbq: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero ; CHECK-NEXT: retl %res = call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %a0) ; <<2 x i64>> [#uses=1] @@ -1341,7 +1341,7 @@ declare <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8>) nounwind readnone define <8 x i16> @test_x86_sse41_pmovzxbw(<16 x i8> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovzxbw: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8> %a0) ; <<8 x i16>> [#uses=1] @@ -1352,7 +1352,7 @@ declare <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8>) nounwind readnone define <2 x i64> @test_x86_sse41_pmovzxdq(<4 x i32> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovzxdq: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero ; CHECK-NEXT: retl %res = call <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32> %a0) ; <<2 x i64>> [#uses=1] @@ -1363,7 +1363,7 @@ declare <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32>) nounwind readnone define <4 x i32> @test_x86_sse41_pmovzxwd(<8 x i16> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovzxwd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero ; CHECK-NEXT: retl %res = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %a0) ; <<4 x i32>> [#uses=1] @@ -1374,7 +1374,7 @@ declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone define <2 x i64> @test_x86_sse41_pmovzxwq(<8 x i16> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovzxwq: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero ; CHECK-NEXT: retl %res = call <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16> %a0) ; <<2 x i64>> [#uses=1] @@ -1385,7 +1385,7 @@ declare <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16>) nounwind readnone define <2 x i64> @test_x86_sse41_pmuldq(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK-LABEL: test_x86_sse41_pmuldq: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmuldq %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32> %a0, <4 x i32> %a1) ; <<2 x i64>> [#uses=1] @@ -1396,7 +1396,7 @@ declare <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32>, <4 x i32>) nounwind readnone define i32 @test_x86_sse41_ptestc(<2 x i64> %a0, <2 x i64> %a1) { ; CHECK-LABEL: test_x86_sse41_ptestc: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vptest %xmm1, %xmm0 ; CHECK-NEXT: sbbl %eax, %eax ; CHECK-NEXT: andl $1, %eax @@ -1409,7 +1409,7 @@ declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) nounwind readnone define i32 @test_x86_sse41_ptestnzc(<2 x i64> %a0, <2 x i64> %a1) { ; CHECK-LABEL: test_x86_sse41_ptestnzc: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vptest %xmm1, %xmm0 ; CHECK-NEXT: seta %al ; CHECK-NEXT: movzbl %al, %eax @@ -1422,7 +1422,7 @@ declare i32 @llvm.x86.sse41.ptestnzc(<2 x i64>, <2 x i64>) nounwind readnone define i32 @test_x86_sse41_ptestz(<2 x i64> %a0, <2 x i64> %a1) { ; CHECK-LABEL: test_x86_sse41_ptestz: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vptest %xmm1, %xmm0 ; CHECK-NEXT: sete %al ; CHECK-NEXT: movzbl %al, %eax @@ -1435,7 +1435,7 @@ declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) nounwind readnone define <2 x double> @test_x86_sse41_round_pd(<2 x double> %a0) { ; CHECK-LABEL: test_x86_sse41_round_pd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vroundpd $7, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.sse41.round.pd(<2 x double> %a0, i32 7) ; <<2 x double>> [#uses=1] @@ -1446,7 +1446,7 @@ declare <2 x double> @llvm.x86.sse41.round.pd(<2 x double>, i32) nounwind readno define <4 x float> @test_x86_sse41_round_ps(<4 x float> %a0) { ; CHECK-LABEL: test_x86_sse41_round_ps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vroundps $7, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse41.round.ps(<4 x float> %a0, i32 7) ; <<4 x float>> [#uses=1] @@ -1457,7 +1457,7 @@ declare <4 x float> @llvm.x86.sse41.round.ps(<4 x float>, i32) nounwind readnone define <2 x double> @test_x86_sse41_round_sd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse41_round_sd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vroundsd $7, %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %a0, <2 x double> %a1, i32 7) ; <<2 x double>> [#uses=1] @@ -1468,7 +1468,7 @@ declare <2 x double> @llvm.x86.sse41.round.sd(<2 x double>, <2 x double>, i32) n define <4 x float> @test_x86_sse41_round_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse41_round_ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vroundss $7, %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %a0, <4 x float> %a1, i32 7) ; <<4 x float>> [#uses=1] @@ -1479,7 +1479,7 @@ declare <4 x float> @llvm.x86.sse41.round.ss(<4 x float>, <4 x float>, i32) noun define i32 @test_x86_sse42_pcmpestri128(<16 x i8> %a0, <16 x i8> %a2) { ; CHECK-LABEL: test_x86_sse42_pcmpestri128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl $7, %eax ; CHECK-NEXT: movl $7, %edx ; CHECK-NEXT: vpcmpestri $7, %xmm1, %xmm0 @@ -1493,7 +1493,7 @@ declare i32 @llvm.x86.sse42.pcmpestri128(<16 x i8>, i32, <16 x i8>, i32, i8) nou define i32 @test_x86_sse42_pcmpestri128_load(<16 x i8>* %a0, <16 x i8>* %a2) { ; CHECK-LABEL: test_x86_sse42_pcmpestri128_load: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vmovdqa (%eax), %xmm0 @@ -1511,7 +1511,7 @@ define i32 @test_x86_sse42_pcmpestri128_load(<16 x i8>* %a0, <16 x i8>* %a2) { define i32 @test_x86_sse42_pcmpestria128(<16 x i8> %a0, <16 x i8> %a2) { ; CHECK-LABEL: test_x86_sse42_pcmpestria128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl $7, %eax ; CHECK-NEXT: movl $7, %edx ; CHECK-NEXT: vpcmpestri $7, %xmm1, %xmm0 @@ -1526,7 +1526,7 @@ declare i32 @llvm.x86.sse42.pcmpestria128(<16 x i8>, i32, <16 x i8>, i32, i8) no define i32 @test_x86_sse42_pcmpestric128(<16 x i8> %a0, <16 x i8> %a2) { ; CHECK-LABEL: test_x86_sse42_pcmpestric128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl $7, %eax ; CHECK-NEXT: movl $7, %edx ; CHECK-NEXT: vpcmpestri $7, %xmm1, %xmm0 @@ -1541,7 +1541,7 @@ declare i32 @llvm.x86.sse42.pcmpestric128(<16 x i8>, i32, <16 x i8>, i32, i8) no define i32 @test_x86_sse42_pcmpestrio128(<16 x i8> %a0, <16 x i8> %a2) { ; CHECK-LABEL: test_x86_sse42_pcmpestrio128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl $7, %eax ; CHECK-NEXT: movl $7, %edx ; CHECK-NEXT: vpcmpestri $7, %xmm1, %xmm0 @@ -1556,7 +1556,7 @@ declare i32 @llvm.x86.sse42.pcmpestrio128(<16 x i8>, i32, <16 x i8>, i32, i8) no define i32 @test_x86_sse42_pcmpestris128(<16 x i8> %a0, <16 x i8> %a2) { ; CHECK-LABEL: test_x86_sse42_pcmpestris128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl $7, %eax ; CHECK-NEXT: movl $7, %edx ; CHECK-NEXT: vpcmpestri $7, %xmm1, %xmm0 @@ -1571,7 +1571,7 @@ declare i32 @llvm.x86.sse42.pcmpestris128(<16 x i8>, i32, <16 x i8>, i32, i8) no define i32 @test_x86_sse42_pcmpestriz128(<16 x i8> %a0, <16 x i8> %a2) { ; CHECK-LABEL: test_x86_sse42_pcmpestriz128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl $7, %eax ; CHECK-NEXT: movl $7, %edx ; CHECK-NEXT: vpcmpestri $7, %xmm1, %xmm0 @@ -1586,7 +1586,7 @@ declare i32 @llvm.x86.sse42.pcmpestriz128(<16 x i8>, i32, <16 x i8>, i32, i8) no define <16 x i8> @test_x86_sse42_pcmpestrm128(<16 x i8> %a0, <16 x i8> %a2) { ; CHECK-LABEL: test_x86_sse42_pcmpestrm128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl $7, %eax ; CHECK-NEXT: movl $7, %edx ; CHECK-NEXT: vpcmpestrm $7, %xmm1, %xmm0 @@ -1599,7 +1599,7 @@ declare <16 x i8> @llvm.x86.sse42.pcmpestrm128(<16 x i8>, i32, <16 x i8>, i32, i define <16 x i8> @test_x86_sse42_pcmpestrm128_load(<16 x i8> %a0, <16 x i8>* %a2) { ; CHECK-LABEL: test_x86_sse42_pcmpestrm128_load: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl $7, %eax ; CHECK-NEXT: movl $7, %edx @@ -1613,7 +1613,7 @@ define <16 x i8> @test_x86_sse42_pcmpestrm128_load(<16 x i8> %a0, <16 x i8>* %a2 define i32 @test_x86_sse42_pcmpistri128(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK-LABEL: test_x86_sse42_pcmpistri128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpistri $7, %xmm1, %xmm0 ; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: retl @@ -1625,7 +1625,7 @@ declare i32 @llvm.x86.sse42.pcmpistri128(<16 x i8>, <16 x i8>, i8) nounwind read define i32 @test_x86_sse42_pcmpistri128_load(<16 x i8>* %a0, <16 x i8>* %a1) { ; CHECK-LABEL: test_x86_sse42_pcmpistri128_load: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: vmovdqa (%ecx), %xmm0 @@ -1641,7 +1641,7 @@ define i32 @test_x86_sse42_pcmpistri128_load(<16 x i8>* %a0, <16 x i8>* %a1) { define i32 @test_x86_sse42_pcmpistria128(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK-LABEL: test_x86_sse42_pcmpistria128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpistri $7, %xmm1, %xmm0 ; CHECK-NEXT: seta %al ; CHECK-NEXT: movzbl %al, %eax @@ -1654,7 +1654,7 @@ declare i32 @llvm.x86.sse42.pcmpistria128(<16 x i8>, <16 x i8>, i8) nounwind rea define i32 @test_x86_sse42_pcmpistric128(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK-LABEL: test_x86_sse42_pcmpistric128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpistri $7, %xmm1, %xmm0 ; CHECK-NEXT: sbbl %eax, %eax ; CHECK-NEXT: andl $1, %eax @@ -1667,7 +1667,7 @@ declare i32 @llvm.x86.sse42.pcmpistric128(<16 x i8>, <16 x i8>, i8) nounwind rea define i32 @test_x86_sse42_pcmpistrio128(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK-LABEL: test_x86_sse42_pcmpistrio128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpistri $7, %xmm1, %xmm0 ; CHECK-NEXT: seto %al ; CHECK-NEXT: movzbl %al, %eax @@ -1680,7 +1680,7 @@ declare i32 @llvm.x86.sse42.pcmpistrio128(<16 x i8>, <16 x i8>, i8) nounwind rea define i32 @test_x86_sse42_pcmpistris128(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK-LABEL: test_x86_sse42_pcmpistris128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpistri $7, %xmm1, %xmm0 ; CHECK-NEXT: sets %al ; CHECK-NEXT: movzbl %al, %eax @@ -1693,7 +1693,7 @@ declare i32 @llvm.x86.sse42.pcmpistris128(<16 x i8>, <16 x i8>, i8) nounwind rea define i32 @test_x86_sse42_pcmpistriz128(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK-LABEL: test_x86_sse42_pcmpistriz128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpistri $7, %xmm1, %xmm0 ; CHECK-NEXT: sete %al ; CHECK-NEXT: movzbl %al, %eax @@ -1706,7 +1706,7 @@ declare i32 @llvm.x86.sse42.pcmpistriz128(<16 x i8>, <16 x i8>, i8) nounwind rea define <16 x i8> @test_x86_sse42_pcmpistrm128(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK-LABEL: test_x86_sse42_pcmpistrm128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpistrm $7, %xmm1, %xmm0 ; CHECK-NEXT: retl %res = call <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <<16 x i8>> [#uses=1] @@ -1717,7 +1717,7 @@ declare <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8>, <16 x i8>, i8) nounwin define <16 x i8> @test_x86_sse42_pcmpistrm128_load(<16 x i8> %a0, <16 x i8>* %a1) { ; CHECK-LABEL: test_x86_sse42_pcmpistrm128_load: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vpcmpistrm $7, (%eax), %xmm0 ; CHECK-NEXT: retl @@ -1729,7 +1729,7 @@ define <16 x i8> @test_x86_sse42_pcmpistrm128_load(<16 x i8> %a0, <16 x i8>* %a1 define <4 x float> @test_x86_sse_add_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_add_ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse.add.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1] @@ -1740,7 +1740,7 @@ declare <4 x float> @llvm.x86.sse.add.ss(<4 x float>, <4 x float>) nounwind read define <4 x float> @test_x86_sse_cmp_ps(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_cmp_ps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcmpordps %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1] @@ -1751,7 +1751,7 @@ declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8) nounwind define <4 x float> @test_x86_sse_cmp_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_cmp_ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcmpordss %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1] @@ -1762,7 +1762,7 @@ declare <4 x float> @llvm.x86.sse.cmp.ss(<4 x float>, <4 x float>, i8) nounwind define i32 @test_x86_sse_comieq_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_comieq_ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcomiss %xmm1, %xmm0 ; CHECK-NEXT: sete %al ; CHECK-NEXT: movzbl %al, %eax @@ -1775,7 +1775,7 @@ declare i32 @llvm.x86.sse.comieq.ss(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_sse_comige_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_comige_ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcomiss %xmm1, %xmm0 ; CHECK-NEXT: setae %al ; CHECK-NEXT: movzbl %al, %eax @@ -1788,7 +1788,7 @@ declare i32 @llvm.x86.sse.comige.ss(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_sse_comigt_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_comigt_ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcomiss %xmm1, %xmm0 ; CHECK-NEXT: seta %al ; CHECK-NEXT: movzbl %al, %eax @@ -1801,7 +1801,7 @@ declare i32 @llvm.x86.sse.comigt.ss(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_sse_comile_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_comile_ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcomiss %xmm1, %xmm0 ; CHECK-NEXT: setbe %al ; CHECK-NEXT: movzbl %al, %eax @@ -1814,7 +1814,7 @@ declare i32 @llvm.x86.sse.comile.ss(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_sse_comilt_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_comilt_ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcomiss %xmm1, %xmm0 ; CHECK-NEXT: sbbl %eax, %eax ; CHECK-NEXT: andl $1, %eax @@ -1827,7 +1827,7 @@ declare i32 @llvm.x86.sse.comilt.ss(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_sse_comineq_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_comineq_ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcomiss %xmm1, %xmm0 ; CHECK-NEXT: setne %al ; CHECK-NEXT: movzbl %al, %eax @@ -1840,7 +1840,7 @@ declare i32 @llvm.x86.sse.comineq.ss(<4 x float>, <4 x float>) nounwind readnone define <4 x float> @test_x86_sse_cvtsi2ss(<4 x float> %a0) { ; CHECK-LABEL: test_x86_sse_cvtsi2ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl $7, %eax ; CHECK-NEXT: vcvtsi2ssl %eax, %xmm0, %xmm0 ; CHECK-NEXT: retl @@ -1852,7 +1852,7 @@ declare <4 x float> @llvm.x86.sse.cvtsi2ss(<4 x float>, i32) nounwind readnone define i32 @test_x86_sse_cvtss2si(<4 x float> %a0) { ; CHECK-LABEL: test_x86_sse_cvtss2si: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcvtss2si %xmm0, %eax ; CHECK-NEXT: retl %res = call i32 @llvm.x86.sse.cvtss2si(<4 x float> %a0) ; [#uses=1] @@ -1863,7 +1863,7 @@ declare i32 @llvm.x86.sse.cvtss2si(<4 x float>) nounwind readnone define i32 @test_x86_sse_cvttss2si(<4 x float> %a0) { ; CHECK-LABEL: test_x86_sse_cvttss2si: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcvttss2si %xmm0, %eax ; CHECK-NEXT: retl %res = call i32 @llvm.x86.sse.cvttss2si(<4 x float> %a0) ; [#uses=1] @@ -1874,7 +1874,7 @@ declare i32 @llvm.x86.sse.cvttss2si(<4 x float>) nounwind readnone define <4 x float> @test_x86_sse_div_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_div_ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vdivss %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse.div.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1] @@ -1885,7 +1885,7 @@ declare <4 x float> @llvm.x86.sse.div.ss(<4 x float>, <4 x float>) nounwind read define void @test_x86_sse_ldmxcsr(i8* %a0) { ; CHECK-LABEL: test_x86_sse_ldmxcsr: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vldmxcsr (%eax) ; CHECK-NEXT: retl @@ -1898,7 +1898,7 @@ declare void @llvm.x86.sse.ldmxcsr(i8*) nounwind define <4 x float> @test_x86_sse_max_ps(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_max_ps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vmaxps %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1] @@ -1909,7 +1909,7 @@ declare <4 x float> @llvm.x86.sse.max.ps(<4 x float>, <4 x float>) nounwind read define <4 x float> @test_x86_sse_max_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_max_ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1] @@ -1920,7 +1920,7 @@ declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>) nounwind read define <4 x float> @test_x86_sse_min_ps(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_min_ps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vminps %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1] @@ -1931,7 +1931,7 @@ declare <4 x float> @llvm.x86.sse.min.ps(<4 x float>, <4 x float>) nounwind read define <4 x float> @test_x86_sse_min_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_min_ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vminss %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1] @@ -1942,7 +1942,7 @@ declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>) nounwind read define i32 @test_x86_sse_movmsk_ps(<4 x float> %a0) { ; CHECK-LABEL: test_x86_sse_movmsk_ps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vmovmskps %xmm0, %eax ; CHECK-NEXT: retl %res = call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %a0) ; [#uses=1] @@ -1954,7 +1954,7 @@ declare i32 @llvm.x86.sse.movmsk.ps(<4 x float>) nounwind readnone define <4 x float> @test_x86_sse_mul_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_mul_ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vmulss %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse.mul.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1] @@ -1965,7 +1965,7 @@ declare <4 x float> @llvm.x86.sse.mul.ss(<4 x float>, <4 x float>) nounwind read define <4 x float> @test_x86_sse_rcp_ps(<4 x float> %a0) { ; CHECK-LABEL: test_x86_sse_rcp_ps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vrcpps %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1] @@ -1976,7 +1976,7 @@ declare <4 x float> @llvm.x86.sse.rcp.ps(<4 x float>) nounwind readnone define <4 x float> @test_x86_sse_rcp_ss(<4 x float> %a0) { ; CHECK-LABEL: test_x86_sse_rcp_ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vrcpss %xmm0, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1] @@ -1987,7 +1987,7 @@ declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) nounwind readnone define <4 x float> @test_x86_sse_rsqrt_ps(<4 x float> %a0) { ; CHECK-LABEL: test_x86_sse_rsqrt_ps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vrsqrtps %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1] @@ -1998,7 +1998,7 @@ declare <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float>) nounwind readnone define <4 x float> @test_x86_sse_rsqrt_ss(<4 x float> %a0) { ; CHECK-LABEL: test_x86_sse_rsqrt_ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vrsqrtss %xmm0, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1] @@ -2009,7 +2009,7 @@ declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone define <4 x float> @test_x86_sse_sqrt_ps(<4 x float> %a0) { ; CHECK-LABEL: test_x86_sse_sqrt_ps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vsqrtps %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1] @@ -2020,7 +2020,7 @@ declare <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float>) nounwind readnone define <4 x float> @test_x86_sse_sqrt_ss(<4 x float> %a0) { ; CHECK-LABEL: test_x86_sse_sqrt_ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1] @@ -2031,7 +2031,7 @@ declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone define void @test_x86_sse_stmxcsr(i8* %a0) { ; CHECK-LABEL: test_x86_sse_stmxcsr: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vstmxcsr (%eax) ; CHECK-NEXT: retl @@ -2043,7 +2043,7 @@ declare void @llvm.x86.sse.stmxcsr(i8*) nounwind define void @test_x86_sse_storeu_ps(i8* %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_storeu_ps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vmovups %xmm0, (%eax) ; CHECK-NEXT: retl @@ -2055,7 +2055,7 @@ declare void @llvm.x86.sse.storeu.ps(i8*, <4 x float>) nounwind define <4 x float> @test_x86_sse_sub_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_sub_ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vsubss %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.sse.sub.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1] @@ -2066,7 +2066,7 @@ declare <4 x float> @llvm.x86.sse.sub.ss(<4 x float>, <4 x float>) nounwind read define i32 @test_x86_sse_ucomieq_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_ucomieq_ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vucomiss %xmm1, %xmm0 ; CHECK-NEXT: sete %al ; CHECK-NEXT: movzbl %al, %eax @@ -2079,7 +2079,7 @@ declare i32 @llvm.x86.sse.ucomieq.ss(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_sse_ucomige_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_ucomige_ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vucomiss %xmm1, %xmm0 ; CHECK-NEXT: setae %al ; CHECK-NEXT: movzbl %al, %eax @@ -2092,7 +2092,7 @@ declare i32 @llvm.x86.sse.ucomige.ss(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_sse_ucomigt_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_ucomigt_ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vucomiss %xmm1, %xmm0 ; CHECK-NEXT: seta %al ; CHECK-NEXT: movzbl %al, %eax @@ -2105,7 +2105,7 @@ declare i32 @llvm.x86.sse.ucomigt.ss(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_sse_ucomile_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_ucomile_ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vucomiss %xmm1, %xmm0 ; CHECK-NEXT: setbe %al ; CHECK-NEXT: movzbl %al, %eax @@ -2118,7 +2118,7 @@ declare i32 @llvm.x86.sse.ucomile.ss(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_sse_ucomilt_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_ucomilt_ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vucomiss %xmm1, %xmm0 ; CHECK-NEXT: sbbl %eax, %eax ; CHECK-NEXT: andl $1, %eax @@ -2131,7 +2131,7 @@ declare i32 @llvm.x86.sse.ucomilt.ss(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_sse_ucomineq_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_ucomineq_ss: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vucomiss %xmm1, %xmm0 ; CHECK-NEXT: setne %al ; CHECK-NEXT: movzbl %al, %eax @@ -2144,7 +2144,7 @@ declare i32 @llvm.x86.sse.ucomineq.ss(<4 x float>, <4 x float>) nounwind readnon define <16 x i8> @test_x86_ssse3_pabs_b_128(<16 x i8> %a0) { ; CHECK-LABEL: test_x86_ssse3_pabs_b_128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpabsb %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8> %a0) ; <<16 x i8>> [#uses=1] @@ -2155,7 +2155,7 @@ declare <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8>) nounwind readnone define <4 x i32> @test_x86_ssse3_pabs_d_128(<4 x i32> %a0) { ; CHECK-LABEL: test_x86_ssse3_pabs_d_128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpabsd %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32> %a0) ; <<4 x i32>> [#uses=1] @@ -2166,7 +2166,7 @@ declare <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32>) nounwind readnone define <8 x i16> @test_x86_ssse3_pabs_w_128(<8 x i16> %a0) { ; CHECK-LABEL: test_x86_ssse3_pabs_w_128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpabsw %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16> %a0) ; <<8 x i16>> [#uses=1] @@ -2177,7 +2177,7 @@ declare <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16>) nounwind readnone define <4 x i32> @test_x86_ssse3_phadd_d_128(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK-LABEL: test_x86_ssse3_phadd_d_128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vphaddd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] @@ -2188,7 +2188,7 @@ declare <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32>, <4 x i32>) nounwind rea define <8 x i16> @test_x86_ssse3_phadd_sw_128(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_ssse3_phadd_sw_128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vphaddsw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -2199,7 +2199,7 @@ declare <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16>, <8 x i16>) nounwind re define <8 x i16> @test_x86_ssse3_phadd_w_128(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_ssse3_phadd_w_128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vphaddw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -2210,7 +2210,7 @@ declare <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16>, <8 x i16>) nounwind rea define <4 x i32> @test_x86_ssse3_phsub_d_128(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK-LABEL: test_x86_ssse3_phsub_d_128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vphsubd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] @@ -2221,7 +2221,7 @@ declare <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32>, <4 x i32>) nounwind rea define <8 x i16> @test_x86_ssse3_phsub_sw_128(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_ssse3_phsub_sw_128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vphsubsw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.ssse3.phsub.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -2232,7 +2232,7 @@ declare <8 x i16> @llvm.x86.ssse3.phsub.sw.128(<8 x i16>, <8 x i16>) nounwind re define <8 x i16> @test_x86_ssse3_phsub_w_128(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_ssse3_phsub_w_128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vphsubw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -2243,7 +2243,7 @@ declare <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16>, <8 x i16>) nounwind rea define <8 x i16> @test_x86_ssse3_pmadd_ub_sw_128(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK-LABEL: test_x86_ssse3_pmadd_ub_sw_128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmaddubsw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<16 x i8> %a0, <16 x i8> %a1) ; <<8 x i16>> [#uses=1] @@ -2254,7 +2254,7 @@ declare <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<16 x i8>, <16 x i8>) nounwind define <8 x i16> @test_x86_ssse3_pmul_hr_sw_128(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_ssse3_pmul_hr_sw_128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpmulhrsw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.ssse3.pmul.hr.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -2265,7 +2265,7 @@ declare <8 x i16> @llvm.x86.ssse3.pmul.hr.sw.128(<8 x i16>, <8 x i16>) nounwind define <16 x i8> @test_x86_ssse3_pshuf_b_128(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK-LABEL: test_x86_ssse3_pshuf_b_128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpshufb %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1] @@ -2276,7 +2276,7 @@ declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>) nounwind rea define <16 x i8> @test_x86_ssse3_psign_b_128(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK-LABEL: test_x86_ssse3_psign_b_128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpsignb %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <16 x i8> @llvm.x86.ssse3.psign.b.128(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1] @@ -2287,7 +2287,7 @@ declare <16 x i8> @llvm.x86.ssse3.psign.b.128(<16 x i8>, <16 x i8>) nounwind rea define <4 x i32> @test_x86_ssse3_psign_d_128(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK-LABEL: test_x86_ssse3_psign_d_128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpsignd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x i32> @llvm.x86.ssse3.psign.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] @@ -2298,7 +2298,7 @@ declare <4 x i32> @llvm.x86.ssse3.psign.d.128(<4 x i32>, <4 x i32>) nounwind rea define <8 x i16> @test_x86_ssse3_psign_w_128(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_ssse3_psign_w_128: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpsignw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <8 x i16> @llvm.x86.ssse3.psign.w.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -2309,7 +2309,7 @@ declare <8 x i16> @llvm.x86.ssse3.psign.w.128(<8 x i16>, <8 x i16>) nounwind rea define <4 x double> @test_x86_avx_addsub_pd_256(<4 x double> %a0, <4 x double> %a1) { ; CHECK-LABEL: test_x86_avx_addsub_pd_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vaddsubpd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1] @@ -2320,7 +2320,7 @@ declare <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double>, <4 x double>) nou define <8 x float> @test_x86_avx_addsub_ps_256(<8 x float> %a0, <8 x float> %a1) { ; CHECK-LABEL: test_x86_avx_addsub_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vaddsubps %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1] @@ -2331,7 +2331,7 @@ declare <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float>, <8 x float>) nounwi define <4 x double> @test_x86_avx_blendv_pd_256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) { ; CHECK-LABEL: test_x86_avx_blendv_pd_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vblendvpd %ymm2, %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) ; <<4 x double>> [#uses=1] @@ -2342,7 +2342,7 @@ declare <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double>, <4 x double>, <4 define <8 x float> @test_x86_avx_blendv_ps_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) { ; CHECK-LABEL: test_x86_avx_blendv_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vblendvps %ymm2, %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) ; <<8 x float>> [#uses=1] @@ -2353,7 +2353,7 @@ declare <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>, <8 x float>, <8 x f define <4 x double> @test_x86_avx_cmp_pd_256(<4 x double> %a0, <4 x double> %a1) { ; CHECK-LABEL: test_x86_avx_cmp_pd_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcmpordpd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double> %a0, <4 x double> %a1, i8 7) ; <<4 x double>> [#uses=1] @@ -2364,7 +2364,7 @@ declare <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double>, <4 x double>, i8) no define <8 x float> @test_x86_avx_cmp_ps_256(<8 x float> %a0, <8 x float> %a1) { ; CHECK-LABEL: test_x86_avx_cmp_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcmpordps %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 7) ; <<8 x float>> [#uses=1] @@ -2373,7 +2373,7 @@ define <8 x float> @test_x86_avx_cmp_ps_256(<8 x float> %a0, <8 x float> %a1) { define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x float> %a1) { ; CHECK-LABEL: test_x86_avx_cmp_ps_256_pseudo_op: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcmpeqps %ymm1, %ymm0, %ymm1 ; CHECK-NEXT: vcmpltps %ymm1, %ymm0, %ymm1 ; CHECK-NEXT: vcmpleps %ymm1, %ymm0, %ymm1 @@ -2446,7 +2446,7 @@ declare <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float>, <8 x float>, i8) nounw define <4 x float> @test_x86_avx_cvt_pd2_ps_256(<4 x double> %a0) { ; CHECK-LABEL: test_x86_avx_cvt_pd2_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcvtpd2psy %ymm0, %xmm0 ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retl @@ -2458,7 +2458,7 @@ declare <4 x float> @llvm.x86.avx.cvt.pd2.ps.256(<4 x double>) nounwind readnone define <4 x i32> @test_x86_avx_cvt_pd2dq_256(<4 x double> %a0) { ; CHECK-LABEL: test_x86_avx_cvt_pd2dq_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcvtpd2dqy %ymm0, %xmm0 ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retl @@ -2470,7 +2470,7 @@ declare <4 x i32> @llvm.x86.avx.cvt.pd2dq.256(<4 x double>) nounwind readnone define <4 x double> @test_x86_avx_cvt_ps2_pd_256(<4 x float> %a0) { ; CHECK-LABEL: test_x86_avx_cvt_ps2_pd_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcvtps2pd %xmm0, %ymm0 ; CHECK-NEXT: retl %res = call <4 x double> @llvm.x86.avx.cvt.ps2.pd.256(<4 x float> %a0) ; <<4 x double>> [#uses=1] @@ -2481,7 +2481,7 @@ declare <4 x double> @llvm.x86.avx.cvt.ps2.pd.256(<4 x float>) nounwind readnone define <8 x i32> @test_x86_avx_cvt_ps2dq_256(<8 x float> %a0) { ; CHECK-LABEL: test_x86_avx_cvt_ps2dq_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcvtps2dq %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <8 x i32> @llvm.x86.avx.cvt.ps2dq.256(<8 x float> %a0) ; <<8 x i32>> [#uses=1] @@ -2492,7 +2492,7 @@ declare <8 x i32> @llvm.x86.avx.cvt.ps2dq.256(<8 x float>) nounwind readnone define <4 x double> @test_x86_avx_cvtdq2_pd_256(<4 x i32> %a0) { ; CHECK-LABEL: test_x86_avx_cvtdq2_pd_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcvtdq2pd %xmm0, %ymm0 ; CHECK-NEXT: retl %res = call <4 x double> @llvm.x86.avx.cvtdq2.pd.256(<4 x i32> %a0) ; <<4 x double>> [#uses=1] @@ -2503,7 +2503,7 @@ declare <4 x double> @llvm.x86.avx.cvtdq2.pd.256(<4 x i32>) nounwind readnone define <8 x float> @test_x86_avx_cvtdq2_ps_256(<8 x i32> %a0) { ; CHECK-LABEL: test_x86_avx_cvtdq2_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcvtdq2ps %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <8 x float> @llvm.x86.avx.cvtdq2.ps.256(<8 x i32> %a0) ; <<8 x float>> [#uses=1] @@ -2514,7 +2514,7 @@ declare <8 x float> @llvm.x86.avx.cvtdq2.ps.256(<8 x i32>) nounwind readnone define <4 x i32> @test_x86_avx_cvtt_pd2dq_256(<4 x double> %a0) { ; CHECK-LABEL: test_x86_avx_cvtt_pd2dq_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcvttpd2dqy %ymm0, %xmm0 ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retl @@ -2526,7 +2526,7 @@ declare <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double>) nounwind readnone define <8 x i32> @test_x86_avx_cvtt_ps2dq_256(<8 x float> %a0) { ; CHECK-LABEL: test_x86_avx_cvtt_ps2dq_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vcvttps2dq %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %a0) ; <<8 x i32>> [#uses=1] @@ -2537,7 +2537,7 @@ declare <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float>) nounwind readnone define <8 x float> @test_x86_avx_dp_ps_256(<8 x float> %a0, <8 x float> %a1) { ; CHECK-LABEL: test_x86_avx_dp_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vdpps $7, %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 7) ; <<8 x float>> [#uses=1] @@ -2548,7 +2548,7 @@ declare <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float>, <8 x float>, i8) nounwi define <4 x double> @test_x86_avx_hadd_pd_256(<4 x double> %a0, <4 x double> %a1) { ; CHECK-LABEL: test_x86_avx_hadd_pd_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vhaddpd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1] @@ -2559,7 +2559,7 @@ declare <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double>, <4 x double>) nounw define <8 x float> @test_x86_avx_hadd_ps_256(<8 x float> %a0, <8 x float> %a1) { ; CHECK-LABEL: test_x86_avx_hadd_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vhaddps %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1] @@ -2570,7 +2570,7 @@ declare <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float>, <8 x float>) nounwind define <4 x double> @test_x86_avx_hsub_pd_256(<4 x double> %a0, <4 x double> %a1) { ; CHECK-LABEL: test_x86_avx_hsub_pd_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vhsubpd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1] @@ -2581,7 +2581,7 @@ declare <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double>, <4 x double>) nounw define <8 x float> @test_x86_avx_hsub_ps_256(<8 x float> %a0, <8 x float> %a1) { ; CHECK-LABEL: test_x86_avx_hsub_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vhsubps %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1] @@ -2592,7 +2592,7 @@ declare <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float>, <8 x float>) nounwind define <32 x i8> @test_x86_avx_ldu_dq_256(i8* %a0) { ; CHECK-LABEL: test_x86_avx_ldu_dq_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vlddqu (%eax), %ymm0 ; CHECK-NEXT: retl @@ -2604,7 +2604,7 @@ declare <32 x i8> @llvm.x86.avx.ldu.dq.256(i8*) nounwind readonly define <2 x double> @test_x86_avx_maskload_pd(i8* %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_avx_maskload_pd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vmaskmovpd (%eax), %xmm0, %xmm0 ; CHECK-NEXT: retl @@ -2616,7 +2616,7 @@ declare <2 x double> @llvm.x86.avx.maskload.pd(i8*, <2 x double>) nounwind reado define <4 x double> @test_x86_avx_maskload_pd_256(i8* %a0, <4 x double> %a1) { ; CHECK-LABEL: test_x86_avx_maskload_pd_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vmaskmovpd (%eax), %ymm0, %ymm0 ; CHECK-NEXT: retl @@ -2628,7 +2628,7 @@ declare <4 x double> @llvm.x86.avx.maskload.pd.256(i8*, <4 x double>) nounwind r define <4 x float> @test_x86_avx_maskload_ps(i8* %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_avx_maskload_ps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vmaskmovps (%eax), %xmm0, %xmm0 ; CHECK-NEXT: retl @@ -2640,7 +2640,7 @@ declare <4 x float> @llvm.x86.avx.maskload.ps(i8*, <4 x float>) nounwind readonl define <8 x float> @test_x86_avx_maskload_ps_256(i8* %a0, <8 x float> %a1) { ; CHECK-LABEL: test_x86_avx_maskload_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vmaskmovps (%eax), %ymm0, %ymm0 ; CHECK-NEXT: retl @@ -2652,7 +2652,7 @@ declare <8 x float> @llvm.x86.avx.maskload.ps.256(i8*, <8 x float>) nounwind rea define void @test_x86_avx_maskstore_pd(i8* %a0, <2 x double> %a1, <2 x double> %a2) { ; CHECK-LABEL: test_x86_avx_maskstore_pd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vmaskmovpd %xmm1, %xmm0, (%eax) ; CHECK-NEXT: retl @@ -2664,7 +2664,7 @@ declare void @llvm.x86.avx.maskstore.pd(i8*, <2 x double>, <2 x double>) nounwin define void @test_x86_avx_maskstore_pd_256(i8* %a0, <4 x double> %a1, <4 x double> %a2) { ; CHECK-LABEL: test_x86_avx_maskstore_pd_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vmaskmovpd %ymm1, %ymm0, (%eax) ; CHECK-NEXT: vzeroupper @@ -2677,7 +2677,7 @@ declare void @llvm.x86.avx.maskstore.pd.256(i8*, <4 x double>, <4 x double>) nou define void @test_x86_avx_maskstore_ps(i8* %a0, <4 x float> %a1, <4 x float> %a2) { ; CHECK-LABEL: test_x86_avx_maskstore_ps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vmaskmovps %xmm1, %xmm0, (%eax) ; CHECK-NEXT: retl @@ -2689,7 +2689,7 @@ declare void @llvm.x86.avx.maskstore.ps(i8*, <4 x float>, <4 x float>) nounwind define void @test_x86_avx_maskstore_ps_256(i8* %a0, <8 x float> %a1, <8 x float> %a2) { ; CHECK-LABEL: test_x86_avx_maskstore_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vmaskmovps %ymm1, %ymm0, (%eax) ; CHECK-NEXT: vzeroupper @@ -2702,7 +2702,7 @@ declare void @llvm.x86.avx.maskstore.ps.256(i8*, <8 x float>, <8 x float>) nounw define <4 x double> @test_x86_avx_max_pd_256(<4 x double> %a0, <4 x double> %a1) { ; CHECK-LABEL: test_x86_avx_max_pd_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vmaxpd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <4 x double> @llvm.x86.avx.max.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1] @@ -2713,7 +2713,7 @@ declare <4 x double> @llvm.x86.avx.max.pd.256(<4 x double>, <4 x double>) nounwi define <8 x float> @test_x86_avx_max_ps_256(<8 x float> %a0, <8 x float> %a1) { ; CHECK-LABEL: test_x86_avx_max_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vmaxps %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <8 x float> @llvm.x86.avx.max.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1] @@ -2724,7 +2724,7 @@ declare <8 x float> @llvm.x86.avx.max.ps.256(<8 x float>, <8 x float>) nounwind define <4 x double> @test_x86_avx_min_pd_256(<4 x double> %a0, <4 x double> %a1) { ; CHECK-LABEL: test_x86_avx_min_pd_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vminpd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <4 x double> @llvm.x86.avx.min.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1] @@ -2735,7 +2735,7 @@ declare <4 x double> @llvm.x86.avx.min.pd.256(<4 x double>, <4 x double>) nounwi define <8 x float> @test_x86_avx_min_ps_256(<8 x float> %a0, <8 x float> %a1) { ; CHECK-LABEL: test_x86_avx_min_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vminps %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <8 x float> @llvm.x86.avx.min.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1] @@ -2746,7 +2746,7 @@ declare <8 x float> @llvm.x86.avx.min.ps.256(<8 x float>, <8 x float>) nounwind define i32 @test_x86_avx_movmsk_pd_256(<4 x double> %a0) { ; CHECK-LABEL: test_x86_avx_movmsk_pd_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vmovmskpd %ymm0, %eax ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retl @@ -2758,7 +2758,7 @@ declare i32 @llvm.x86.avx.movmsk.pd.256(<4 x double>) nounwind readnone define i32 @test_x86_avx_movmsk_ps_256(<8 x float> %a0) { ; CHECK-LABEL: test_x86_avx_movmsk_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vmovmskps %ymm0, %eax ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retl @@ -2775,7 +2775,7 @@ declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>) nounwind readnone define i32 @test_x86_avx_ptestc_256(<4 x i64> %a0, <4 x i64> %a1) { ; CHECK-LABEL: test_x86_avx_ptestc_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vptest %ymm1, %ymm0 ; CHECK-NEXT: sbbl %eax, %eax ; CHECK-NEXT: andl $1, %eax @@ -2789,7 +2789,7 @@ declare i32 @llvm.x86.avx.ptestc.256(<4 x i64>, <4 x i64>) nounwind readnone define i32 @test_x86_avx_ptestnzc_256(<4 x i64> %a0, <4 x i64> %a1) { ; CHECK-LABEL: test_x86_avx_ptestnzc_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vptest %ymm1, %ymm0 ; CHECK-NEXT: seta %al ; CHECK-NEXT: movzbl %al, %eax @@ -2803,7 +2803,7 @@ declare i32 @llvm.x86.avx.ptestnzc.256(<4 x i64>, <4 x i64>) nounwind readnone define i32 @test_x86_avx_ptestz_256(<4 x i64> %a0, <4 x i64> %a1) { ; CHECK-LABEL: test_x86_avx_ptestz_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vptest %ymm1, %ymm0 ; CHECK-NEXT: sete %al ; CHECK-NEXT: movzbl %al, %eax @@ -2817,7 +2817,7 @@ declare i32 @llvm.x86.avx.ptestz.256(<4 x i64>, <4 x i64>) nounwind readnone define <8 x float> @test_x86_avx_rcp_ps_256(<8 x float> %a0) { ; CHECK-LABEL: test_x86_avx_rcp_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vrcpps %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <8 x float> @llvm.x86.avx.rcp.ps.256(<8 x float> %a0) ; <<8 x float>> [#uses=1] @@ -2828,7 +2828,7 @@ declare <8 x float> @llvm.x86.avx.rcp.ps.256(<8 x float>) nounwind readnone define <4 x double> @test_x86_avx_round_pd_256(<4 x double> %a0) { ; CHECK-LABEL: test_x86_avx_round_pd_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vroundpd $7, %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <4 x double> @llvm.x86.avx.round.pd.256(<4 x double> %a0, i32 7) ; <<4 x double>> [#uses=1] @@ -2839,7 +2839,7 @@ declare <4 x double> @llvm.x86.avx.round.pd.256(<4 x double>, i32) nounwind read define <8 x float> @test_x86_avx_round_ps_256(<8 x float> %a0) { ; CHECK-LABEL: test_x86_avx_round_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vroundps $7, %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <8 x float> @llvm.x86.avx.round.ps.256(<8 x float> %a0, i32 7) ; <<8 x float>> [#uses=1] @@ -2850,7 +2850,7 @@ declare <8 x float> @llvm.x86.avx.round.ps.256(<8 x float>, i32) nounwind readno define <8 x float> @test_x86_avx_rsqrt_ps_256(<8 x float> %a0) { ; CHECK-LABEL: test_x86_avx_rsqrt_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vrsqrtps %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <8 x float> @llvm.x86.avx.rsqrt.ps.256(<8 x float> %a0) ; <<8 x float>> [#uses=1] @@ -2861,7 +2861,7 @@ declare <8 x float> @llvm.x86.avx.rsqrt.ps.256(<8 x float>) nounwind readnone define <4 x double> @test_x86_avx_sqrt_pd_256(<4 x double> %a0) { ; CHECK-LABEL: test_x86_avx_sqrt_pd_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vsqrtpd %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <4 x double> @llvm.x86.avx.sqrt.pd.256(<4 x double> %a0) ; <<4 x double>> [#uses=1] @@ -2872,7 +2872,7 @@ declare <4 x double> @llvm.x86.avx.sqrt.pd.256(<4 x double>) nounwind readnone define <8 x float> @test_x86_avx_sqrt_ps_256(<8 x float> %a0) { ; CHECK-LABEL: test_x86_avx_sqrt_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vsqrtps %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <8 x float> @llvm.x86.avx.sqrt.ps.256(<8 x float> %a0) ; <<8 x float>> [#uses=1] @@ -2885,7 +2885,7 @@ define void @test_x86_avx_storeu_dq_256(i8* %a0, <32 x i8> %a1) { ; FIXME: unfortunately the execution domain fix pass changes this to vmovups and its hard to force with no 256-bit integer instructions ; add operation forces the execution domain. ; CHECK-LABEL: test_x86_avx_storeu_dq_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1 ; CHECK-NEXT: vmovdqa {{.*#+}} xmm2 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1] @@ -2905,7 +2905,7 @@ declare void @llvm.x86.avx.storeu.dq.256(i8*, <32 x i8>) nounwind define void @test_x86_avx_storeu_pd_256(i8* %a0, <4 x double> %a1) { ; add operation forces the execution domain. ; CHECK-LABEL: test_x86_avx_storeu_pd_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0 @@ -2921,7 +2921,7 @@ declare void @llvm.x86.avx.storeu.pd.256(i8*, <4 x double>) nounwind define void @test_x86_avx_storeu_ps_256(i8* %a0, <8 x float> %a1) { ; CHECK-LABEL: test_x86_avx_storeu_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vmovups %ymm0, (%eax) ; CHECK-NEXT: vzeroupper @@ -2934,7 +2934,7 @@ declare void @llvm.x86.avx.storeu.ps.256(i8*, <8 x float>) nounwind define <4 x double> @test_x86_avx_vbroadcastf128_pd_256(i8* %a0) { ; CHECK-LABEL: test_x86_avx_vbroadcastf128_pd_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vbroadcastf128 (%eax), %ymm0 ; CHECK-NEXT: retl @@ -2946,7 +2946,7 @@ declare <4 x double> @llvm.x86.avx.vbroadcastf128.pd.256(i8*) nounwind readonly define <8 x float> @test_x86_avx_vbroadcastf128_ps_256(i8* %a0) { ; CHECK-LABEL: test_x86_avx_vbroadcastf128_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vbroadcastf128 (%eax), %ymm0 ; CHECK-NEXT: retl @@ -2958,7 +2958,7 @@ declare <8 x float> @llvm.x86.avx.vbroadcastf128.ps.256(i8*) nounwind readonly define <4 x double> @test_x86_avx_vperm2f128_pd_256(<4 x double> %a0, <4 x double> %a1) { ; CHECK-LABEL: test_x86_avx_vperm2f128_pd_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[0,1] ; CHECK-NEXT: retl %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 7) ; <<4 x double>> [#uses=1] @@ -2969,7 +2969,7 @@ declare <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double>, <4 x double>, define <8 x float> @test_x86_avx_vperm2f128_ps_256(<8 x float> %a0, <8 x float> %a1) { ; CHECK-LABEL: test_x86_avx_vperm2f128_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[0,1] ; CHECK-NEXT: retl %res = call <8 x float> @llvm.x86.avx.vperm2f128.ps.256(<8 x float> %a0, <8 x float> %a1, i8 7) ; <<8 x float>> [#uses=1] @@ -2980,7 +2980,7 @@ declare <8 x float> @llvm.x86.avx.vperm2f128.ps.256(<8 x float>, <8 x float>, i8 define <8 x i32> @test_x86_avx_vperm2f128_si_256(<8 x i32> %a0, <8 x i32> %a1) { ; CHECK-LABEL: test_x86_avx_vperm2f128_si_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[0,1] ; CHECK-NEXT: retl %res = call <8 x i32> @llvm.x86.avx.vperm2f128.si.256(<8 x i32> %a0, <8 x i32> %a1, i8 7) ; <<8 x i32>> [#uses=1] @@ -2991,7 +2991,7 @@ declare <8 x i32> @llvm.x86.avx.vperm2f128.si.256(<8 x i32>, <8 x i32>, i8) noun define <2 x double> @test_x86_avx_vpermil_pd(<2 x double> %a0) { ; CHECK-LABEL: test_x86_avx_vpermil_pd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.avx.vpermil.pd(<2 x double> %a0, i8 1) ; <<2 x double>> [#uses=1] @@ -3002,7 +3002,7 @@ declare <2 x double> @llvm.x86.avx.vpermil.pd(<2 x double>, i8) nounwind readnon define <4 x double> @test_x86_avx_vpermil_pd_256(<4 x double> %a0) { ; CHECK-LABEL: test_x86_avx_vpermil_pd_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,1,3,2] ; CHECK-NEXT: retl %res = call <4 x double> @llvm.x86.avx.vpermil.pd.256(<4 x double> %a0, i8 7) ; <<4 x double>> [#uses=1] @@ -3013,7 +3013,7 @@ declare <4 x double> @llvm.x86.avx.vpermil.pd.256(<4 x double>, i8) nounwind rea define <4 x float> @test_x86_avx_vpermil_ps(<4 x float> %a0) { ; CHECK-LABEL: test_x86_avx_vpermil_ps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,0,0] ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.avx.vpermil.ps(<4 x float> %a0, i8 7) ; <<4 x float>> [#uses=1] @@ -3024,7 +3024,7 @@ declare <4 x float> @llvm.x86.avx.vpermil.ps(<4 x float>, i8) nounwind readnone define <8 x float> @test_x86_avx_vpermil_ps_256(<8 x float> %a0) { ; CHECK-LABEL: test_x86_avx_vpermil_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,1,0,0,7,5,4,4] ; CHECK-NEXT: retl %res = call <8 x float> @llvm.x86.avx.vpermil.ps.256(<8 x float> %a0, i8 7) ; <<8 x float>> [#uses=1] @@ -3035,7 +3035,7 @@ declare <8 x float> @llvm.x86.avx.vpermil.ps.256(<8 x float>, i8) nounwind readn define <2 x double> @test_x86_avx_vpermilvar_pd(<2 x double> %a0, <2 x i64> %a1) { ; CHECK-LABEL: test_x86_avx_vpermilvar_pd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpermilpd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %a0, <2 x i64> %a1) ; <<2 x double>> [#uses=1] @@ -3046,7 +3046,7 @@ declare <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double>, <2 x i64>) nounwi define <4 x double> @test_x86_avx_vpermilvar_pd_256(<4 x double> %a0, <4 x i64> %a1) { ; CHECK-LABEL: test_x86_avx_vpermilvar_pd_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpermilpd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %a0, <4 x i64> %a1) ; <<4 x double>> [#uses=1] @@ -3057,7 +3057,7 @@ declare <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double>, <4 x i64>) no define <4 x float> @test_x86_avx_vpermilvar_ps(<4 x float> %a0, <4 x i32> %a1) { ; CHECK-LABEL: test_x86_avx_vpermilvar_ps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpermilps %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> %a1) ; <<4 x float>> [#uses=1] @@ -3065,7 +3065,7 @@ define <4 x float> @test_x86_avx_vpermilvar_ps(<4 x float> %a0, <4 x i32> %a1) { } define <4 x float> @test_x86_avx_vpermilvar_ps_load(<4 x float> %a0, <4 x i32>* %a1) { ; CHECK-LABEL: test_x86_avx_vpermilvar_ps_load: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vpermilps (%eax), %xmm0, %xmm0 ; CHECK-NEXT: retl @@ -3078,7 +3078,7 @@ declare <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float>, <4 x i32>) nounwind define <8 x float> @test_x86_avx_vpermilvar_ps_256(<8 x float> %a0, <8 x i32> %a1) { ; CHECK-LABEL: test_x86_avx_vpermilvar_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpermilps %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: retl %res = call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> %a1) ; <<8 x float>> [#uses=1] @@ -3089,7 +3089,7 @@ declare <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float>, <8 x i32>) noun define i32 @test_x86_avx_vtestc_pd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_avx_vtestc_pd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vtestpd %xmm1, %xmm0 ; CHECK-NEXT: sbbl %eax, %eax ; CHECK-NEXT: andl $1, %eax @@ -3102,7 +3102,7 @@ declare i32 @llvm.x86.avx.vtestc.pd(<2 x double>, <2 x double>) nounwind readnon define i32 @test_x86_avx_vtestc_pd_256(<4 x double> %a0, <4 x double> %a1) { ; CHECK-LABEL: test_x86_avx_vtestc_pd_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vtestpd %ymm1, %ymm0 ; CHECK-NEXT: sbbl %eax, %eax ; CHECK-NEXT: andl $1, %eax @@ -3116,7 +3116,7 @@ declare i32 @llvm.x86.avx.vtestc.pd.256(<4 x double>, <4 x double>) nounwind rea define i32 @test_x86_avx_vtestc_ps(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_avx_vtestc_ps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vtestps %xmm1, %xmm0 ; CHECK-NEXT: sbbl %eax, %eax ; CHECK-NEXT: andl $1, %eax @@ -3129,7 +3129,7 @@ declare i32 @llvm.x86.avx.vtestc.ps(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_avx_vtestc_ps_256(<8 x float> %a0, <8 x float> %a1) { ; CHECK-LABEL: test_x86_avx_vtestc_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vtestps %ymm1, %ymm0 ; CHECK-NEXT: sbbl %eax, %eax ; CHECK-NEXT: andl $1, %eax @@ -3143,7 +3143,7 @@ declare i32 @llvm.x86.avx.vtestc.ps.256(<8 x float>, <8 x float>) nounwind readn define i32 @test_x86_avx_vtestnzc_pd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_avx_vtestnzc_pd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vtestpd %xmm1, %xmm0 ; CHECK-NEXT: seta %al ; CHECK-NEXT: movzbl %al, %eax @@ -3156,7 +3156,7 @@ declare i32 @llvm.x86.avx.vtestnzc.pd(<2 x double>, <2 x double>) nounwind readn define i32 @test_x86_avx_vtestnzc_pd_256(<4 x double> %a0, <4 x double> %a1) { ; CHECK-LABEL: test_x86_avx_vtestnzc_pd_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vtestpd %ymm1, %ymm0 ; CHECK-NEXT: seta %al ; CHECK-NEXT: movzbl %al, %eax @@ -3170,7 +3170,7 @@ declare i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double>, <4 x double>) nounwind r define i32 @test_x86_avx_vtestnzc_ps(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_avx_vtestnzc_ps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vtestps %xmm1, %xmm0 ; CHECK-NEXT: seta %al ; CHECK-NEXT: movzbl %al, %eax @@ -3183,7 +3183,7 @@ declare i32 @llvm.x86.avx.vtestnzc.ps(<4 x float>, <4 x float>) nounwind readnon define i32 @test_x86_avx_vtestnzc_ps_256(<8 x float> %a0, <8 x float> %a1) { ; CHECK-LABEL: test_x86_avx_vtestnzc_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vtestps %ymm1, %ymm0 ; CHECK-NEXT: seta %al ; CHECK-NEXT: movzbl %al, %eax @@ -3197,7 +3197,7 @@ declare i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float>, <8 x float>) nounwind rea define i32 @test_x86_avx_vtestz_pd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_avx_vtestz_pd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vtestpd %xmm1, %xmm0 ; CHECK-NEXT: sete %al ; CHECK-NEXT: movzbl %al, %eax @@ -3210,7 +3210,7 @@ declare i32 @llvm.x86.avx.vtestz.pd(<2 x double>, <2 x double>) nounwind readnon define i32 @test_x86_avx_vtestz_pd_256(<4 x double> %a0, <4 x double> %a1) { ; CHECK-LABEL: test_x86_avx_vtestz_pd_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vtestpd %ymm1, %ymm0 ; CHECK-NEXT: sete %al ; CHECK-NEXT: movzbl %al, %eax @@ -3224,7 +3224,7 @@ declare i32 @llvm.x86.avx.vtestz.pd.256(<4 x double>, <4 x double>) nounwind rea define i32 @test_x86_avx_vtestz_ps(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_avx_vtestz_ps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vtestps %xmm1, %xmm0 ; CHECK-NEXT: sete %al ; CHECK-NEXT: movzbl %al, %eax @@ -3237,7 +3237,7 @@ declare i32 @llvm.x86.avx.vtestz.ps(<4 x float>, <4 x float>) nounwind readnone define i32 @test_x86_avx_vtestz_ps_256(<8 x float> %a0, <8 x float> %a1) { ; CHECK-LABEL: test_x86_avx_vtestz_ps_256: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vtestps %ymm1, %ymm0 ; CHECK-NEXT: sete %al ; CHECK-NEXT: movzbl %al, %eax @@ -3251,7 +3251,7 @@ declare i32 @llvm.x86.avx.vtestz.ps.256(<8 x float>, <8 x float>) nounwind readn define void @test_x86_avx_vzeroall() { ; CHECK-LABEL: test_x86_avx_vzeroall: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vzeroall ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retl @@ -3263,7 +3263,7 @@ declare void @llvm.x86.avx.vzeroall() nounwind define void @test_x86_avx_vzeroupper() { ; CHECK-LABEL: test_x86_avx_vzeroupper: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retl @@ -3276,7 +3276,7 @@ declare void @llvm.x86.avx.vzeroupper() nounwind define void @monitor(i8* %P, i32 %E, i32 %H) nounwind { ; CHECK-LABEL: monitor: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax @@ -3290,7 +3290,7 @@ declare void @llvm.x86.sse3.monitor(i8*, i32, i32) nounwind define void @mwait(i32 %E, i32 %H) nounwind { ; CHECK-LABEL: mwait: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: mwait @@ -3302,7 +3302,7 @@ declare void @llvm.x86.sse3.mwait(i32, i32) nounwind define void @sfence() nounwind { ; CHECK-LABEL: sfence: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: sfence ; CHECK-NEXT: retl tail call void @llvm.x86.sse.sfence() @@ -3312,7 +3312,7 @@ declare void @llvm.x86.sse.sfence() nounwind define void @lfence() nounwind { ; CHECK-LABEL: lfence: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: lfence ; CHECK-NEXT: retl tail call void @llvm.x86.sse2.lfence() @@ -3322,7 +3322,7 @@ declare void @llvm.x86.sse2.lfence() nounwind define void @mfence() nounwind { ; CHECK-LABEL: mfence: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: mfence ; CHECK-NEXT: retl tail call void @llvm.x86.sse2.mfence() @@ -3332,7 +3332,7 @@ declare void @llvm.x86.sse2.mfence() nounwind define void @clflush(i8* %p) nounwind { ; CHECK-LABEL: clflush: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: clflush (%eax) ; CHECK-NEXT: retl @@ -3343,7 +3343,7 @@ declare void @llvm.x86.sse2.clflush(i8*) nounwind define i32 @crc32_32_8(i32 %a, i8 %b) nounwind { ; CHECK-LABEL: crc32_32_8: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: crc32b {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: retl @@ -3354,7 +3354,7 @@ declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8) nounwind define i32 @crc32_32_16(i32 %a, i16 %b) nounwind { ; CHECK-LABEL: crc32_32_16: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: crc32w {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: retl @@ -3365,7 +3365,7 @@ declare i32 @llvm.x86.sse42.crc32.32.16(i32, i16) nounwind define i32 @crc32_32_32(i32 %a, i32 %b) nounwind { ; CHECK-LABEL: crc32_32_32: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: crc32l {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: retl @@ -3376,7 +3376,7 @@ declare i32 @llvm.x86.sse42.crc32.32.32(i32, i32) nounwind define void @movnt_dq(i8* %p, <2 x i64> %a1) nounwind { ; CHECK-LABEL: movnt_dq: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vpaddq LCPI282_0, %xmm0, %xmm0 ; CHECK-NEXT: vmovntdq %ymm0, (%eax) @@ -3391,7 +3391,7 @@ declare void @llvm.x86.avx.movnt.dq.256(i8*, <4 x i64>) nounwind define void @movnt_ps(i8* %p, <8 x float> %a) nounwind { ; CHECK-LABEL: movnt_ps: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vmovntps %ymm0, (%eax) ; CHECK-NEXT: vzeroupper @@ -3404,7 +3404,7 @@ declare void @llvm.x86.avx.movnt.ps.256(i8*, <8 x float>) nounwind define void @movnt_pd(i8* %p, <4 x double> %a1) nounwind { ; add operation forces the execution domain. ; CHECK-LABEL: movnt_pd: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0 @@ -3421,7 +3421,7 @@ declare void @llvm.x86.avx.movnt.pd.256(i8*, <4 x double>) nounwind ; Check for pclmulqdq define <2 x i64> @test_x86_pclmulqdq(<2 x i64> %a0, <2 x i64> %a1) { ; CHECK-LABEL: test_x86_pclmulqdq: -; CHECK: # BB#0: +; CHECK: ## BB#0: ; CHECK-NEXT: vpclmulqdq $0, %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retl %res = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %a0, <2 x i64> %a1, i8 0) ; <<2 x i64>> [#uses=1] diff --git a/test/CodeGen/X86/sse41.ll b/test/CodeGen/X86/sse41.ll index 8532c012aa9..02ad55ebd02 100644 --- a/test/CodeGen/X86/sse41.ll +++ b/test/CodeGen/X86/sse41.ll @@ -204,7 +204,7 @@ declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32) noun define <4 x float> @blendps_not_insertps_1(<4 x float> %t1, float %t2) nounwind { ; X32-LABEL: blendps_not_insertps_1: ; X32: ## BB#0: -; X32-NEXT: movss {{.*#+}} xmm1 +; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X32-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; X32-NEXT: retl ;