From: Colin Cross Date: Wed, 3 Nov 2010 23:32:15 +0000 (-0700) Subject: ARM: tegra: clock: Add a pass-through set_rate to super clocks X-Git-Tag: firefly_0821_release~9833^2~123^2~2 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=c41283c28bf8296cfe27f843a7fa287b4d2ab9dd;p=firefly-linux-kernel-4.4.55.git ARM: tegra: clock: Add a pass-through set_rate to super clocks Change-Id: I55027c93415a59cbf701b1f30e436203316c0d61 Signed-off-by: Colin Cross --- diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 8bc46e7e0988..2c667fab39ab 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -351,11 +351,24 @@ static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p) return -EINVAL; } +/* + * Super clocks have "clock skippers" instead of dividers. Dividing using + * a clock skipper does not allow the voltage to be scaled down, so instead + * adjust the rate of the parent clock. This requires that the parent of a + * super clock have no other children, otherwise the rate will change + * underneath the other children. + */ +static int tegra2_super_clk_set_rate(struct clk *c, unsigned long rate) +{ + return clk_set_rate(c->parent, rate); +} + static struct clk_ops tegra_super_ops = { .init = tegra2_super_clk_init, .enable = tegra2_super_clk_enable, .disable = tegra2_super_clk_disable, .set_parent = tegra2_super_clk_set_parent, + .set_rate = tegra2_super_clk_set_rate, }; /* virtual cpu clock functions */