From: Kieran Bingham Date: Tue, 17 Jan 2017 08:29:01 +0000 (+0200) Subject: UPSTREAM: drm: bridge: dw-hdmi: Remove PHY configuration resolution parameter X-Git-Tag: release-20171130_firefly~4^2~719 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=c459f31828a834d51047af0458b5da550611d42e;p=firefly-linux-kernel-4.4.55.git UPSTREAM: drm: bridge: dw-hdmi: Remove PHY configuration resolution parameter The current code hard codes the call of hdmi_phy_configure() to be 8bpp and provides extraneous error checking to verify that this hardcoded value is correct. Simplify the implementation by removing the argument. Signed-off-by: Kieran Bingham Signed-off-by: Laurent Pinchart Reviewed-by: Jose Abreu Signed-off-by: Archit Taneja Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-12-laurent.pinchart+renesas@ideasonboard.com Change-Id: I45ce56616a06d322c5f5fb9e9d01971e65bcf23c Signed-off-by: Zheng Yang (cherry pick from 1acc6bdeee1ef2ecac3ba070a403827ab8f16be5) --- diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c index 99d51b21d077..a481fc461327 100644 --- a/drivers/gpu/drm/bridge/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/dw-hdmi.c @@ -1183,31 +1183,14 @@ static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) HDMI_PHY_CONF0_SELDIPIF_MASK); } -static int hdmi_phy_configure(struct dw_hdmi *hdmi, - unsigned char res, int cscon) +static int hdmi_phy_configure(struct dw_hdmi *hdmi, int cscon) { - unsigned res_idx; u8 val, msec, tmds_cfg; const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; - switch (res) { - case 0: /* color resolution 0 is 8 bit colour depth */ - case 8: - res_idx = DW_HDMI_RES_8; - break; - case 10: - res_idx = DW_HDMI_RES_10; - break; - case 12: - res_idx = DW_HDMI_RES_12; - break; - default: - return -EINVAL; - } - /* PLL/MPLL Cfg - always match on final entry */ for (; mpll_config->mpixelclock != ~0UL; mpll_config++) if (hdmi->hdmi_data.video_mode.mpixelclock <= @@ -1273,14 +1256,14 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, */ if (hdmi->hdmi_data.enc_in_format == YCBCR420 && (hdmi->dev_type == RK3399_HDMI || hdmi->dev_type == RK3368_HDMI)) - hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce | 4, + hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce | 4, 0x06); else - hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06); - hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15); + hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 0x06); + hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 0x15); /* CURRCTRL */ - hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10); + hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 0x10); hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */ hdmi_phy_i2c_write(hdmi, 0x0006, 0x17); @@ -1346,7 +1329,7 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi) dw_hdmi_phy_enable_powerdown(hdmi, true); /* Enable CSC */ - ret = hdmi_phy_configure(hdmi, 8, cscon); + ret = hdmi_phy_configure(hdmi, cscon); if (ret) return ret; }