From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Tue, 18 Aug 2015 21:21:35 +0000 (+0000)
Subject: [X86] Refreshed sign extension tests.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=c5181355d96a5879bfc77fe7f63cd3bbb5b019fe;p=oota-llvm.git

[X86] Refreshed sign extension tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245358 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/X86/pr15267.ll b/test/CodeGen/X86/pr15267.ll
index 95d7deb3417..cca27d65027 100644
--- a/test/CodeGen/X86/pr15267.ll
+++ b/test/CodeGen/X86/pr15267.ll
@@ -1,138 +1,146 @@
 ; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=corei7-avx | FileCheck %s
 
 define <4 x i3> @test1(<4 x i3>* %in) nounwind {
+; CHECK-LABEL: test1:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movzwl (%rdi), %eax
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shrl $3, %ecx
+; CHECK-NEXT:    andl $7, %ecx
+; CHECK-NEXT:    movl %eax, %edx
+; CHECK-NEXT:    andl $7, %edx
+; CHECK-NEXT:    vmovd %edx, %xmm0
+; CHECK-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm0
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shrl $6, %ecx
+; CHECK-NEXT:    andl $7, %ecx
+; CHECK-NEXT:    vpinsrd $2, %ecx, %xmm0, %xmm0
+; CHECK-NEXT:    shrl $9, %eax
+; CHECK-NEXT:    andl $7, %eax
+; CHECK-NEXT:    vpinsrd $3, %eax, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %ret = load <4 x i3>, <4 x i3>* %in, align 1
   ret <4 x i3> %ret
 }
-; CHECK-LABEL: test1
-; CHECK: movzwl
-; CHECK: shrl $3
-; CHECK: andl $7
-; CHECK: andl $7
-; CHECK: vmovd
-; CHECK: pinsrd $1
-; CHECK: shrl $6
-; CHECK: andl $7
-; CHECK: pinsrd $2
-; CHECK: shrl $9
-; CHECK: andl $7
-; CHECK: pinsrd $3
-; CHECK: ret
 
 define <4 x i1> @test2(<4 x i1>* %in) nounwind {
+; CHECK-LABEL: test2:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movzbl (%rdi), %eax
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shrl %ecx
+; CHECK-NEXT:    andl $1, %ecx
+; CHECK-NEXT:    movl %eax, %edx
+; CHECK-NEXT:    andl $1, %edx
+; CHECK-NEXT:    vmovd %edx, %xmm0
+; CHECK-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm0
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shrl $2, %ecx
+; CHECK-NEXT:    andl $1, %ecx
+; CHECK-NEXT:    vpinsrd $2, %ecx, %xmm0, %xmm0
+; CHECK-NEXT:    shrl $3, %eax
+; CHECK-NEXT:    andl $1, %eax
+; CHECK-NEXT:    vpinsrd $3, %eax, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %ret = load <4 x i1>, <4 x i1>* %in, align 1
   ret <4 x i1> %ret
 }
 
-; CHECK-LABEL: test2
-; CHECK: movzbl
-; CHECK: shrl
-; CHECK: andl $1
-; CHECK: andl $1
-; CHECK: vmovd
-; CHECK: pinsrd $1
-; CHECK: shrl $2
-; CHECK: andl $1
-; CHECK: pinsrd $2
-; CHECK: shrl $3
-; CHECK: andl $1
-; CHECK: pinsrd $3
-; CHECK: ret
-
 define <4 x i64> @test3(<4 x i1>* %in) nounwind {
+; CHECK-LABEL: test3:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movzbl (%rdi), %eax
+; CHECK-NEXT:    movq %rax, %rcx
+; CHECK-NEXT:    shlq $62, %rcx
+; CHECK-NEXT:    sarq $63, %rcx
+; CHECK-NEXT:    movq %rax, %rdx
+; CHECK-NEXT:    shlq $63, %rdx
+; CHECK-NEXT:    sarq $63, %rdx
+; CHECK-NEXT:    vmovd %edx, %xmm0
+; CHECK-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm0
+; CHECK-NEXT:    movq %rax, %rcx
+; CHECK-NEXT:    shlq $61, %rcx
+; CHECK-NEXT:    sarq $63, %rcx
+; CHECK-NEXT:    vpinsrd $2, %ecx, %xmm0, %xmm0
+; CHECK-NEXT:    shlq $60, %rax
+; CHECK-NEXT:    sarq $63, %rax
+; CHECK-NEXT:    vpinsrd $3, %eax, %xmm0, %xmm0
+; CHECK-NEXT:    vpmovsxdq %xmm0, %xmm0
+; CHECK-NEXT:    vmovd %ecx, %xmm1
+; CHECK-NEXT:    vpinsrd $1, %eax, %xmm1, %xmm1
+; CHECK-NEXT:    vpmovsxdq %xmm1, %xmm1
+; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
   %wide.load35 = load <4 x i1>, <4 x i1>* %in, align 1
   %sext = sext <4 x i1> %wide.load35 to <4 x i64>
   ret <4 x i64> %sext
 }
 
-; CHECK-LABEL: test3
-; CHECK: movzbl
-; CHECK: movq
-; CHECK: shlq
-; CHECK: sarq
-; CHECK: movq
-; CHECK: shlq
-; CHECK: sarq
-; CHECK: vmovd
-; CHECK: vpinsrd
-; CHECK: movq
-; CHECK: shlq
-; CHECK: sarq
-; CHECK: vpinsrd
-; CHECK: shlq
-; CHECK: sarq
-; CHECK: vpinsrd
-; CHECK: vpmovsxdq
-; CHECK: vmovd
-; CHECK: vpinsrd
-; CHECK: vpmovsxdq
-; CHECK: vinsertf128
-; CHECK: ret
-
 define <16 x i4> @test4(<16 x i4>* %in) nounwind {
+; CHECK-LABEL: test4:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movq (%rdi), %rax
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shrl $4, %ecx
+; CHECK-NEXT:    andl $15, %ecx
+; CHECK-NEXT:    movl %eax, %edx
+; CHECK-NEXT:    andl $15, %edx
+; CHECK-NEXT:    vmovd %edx, %xmm0
+; CHECK-NEXT:    vpinsrb $1, %ecx, %xmm0, %xmm0
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shrl $8, %ecx
+; CHECK-NEXT:    andl $15, %ecx
+; CHECK-NEXT:    vpinsrb $2, %ecx, %xmm0, %xmm0
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shrl $12, %ecx
+; CHECK-NEXT:    andl $15, %ecx
+; CHECK-NEXT:    vpinsrb $3, %ecx, %xmm0, %xmm0
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shrl $16, %ecx
+; CHECK-NEXT:    andl $15, %ecx
+; CHECK-NEXT:    vpinsrb $4, %ecx, %xmm0, %xmm0
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shrl $20, %ecx
+; CHECK-NEXT:    andl $15, %ecx
+; CHECK-NEXT:    vpinsrb $5, %ecx, %xmm0, %xmm0
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shrl $24, %ecx
+; CHECK-NEXT:    andl $15, %ecx
+; CHECK-NEXT:    vpinsrb $6, %ecx, %xmm0, %xmm0
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shrl $28, %ecx
+; CHECK-NEXT:    vpinsrb $7, %ecx, %xmm0, %xmm0
+; CHECK-NEXT:    movq %rax, %rcx
+; CHECK-NEXT:    shrq $32, %rcx
+; CHECK-NEXT:    andl $15, %ecx
+; CHECK-NEXT:    vpinsrb $8, %ecx, %xmm0, %xmm0
+; CHECK-NEXT:    movq %rax, %rcx
+; CHECK-NEXT:    shrq $36, %rcx
+; CHECK-NEXT:    andl $15, %ecx
+; CHECK-NEXT:    vpinsrb $9, %ecx, %xmm0, %xmm0
+; CHECK-NEXT:    movq %rax, %rcx
+; CHECK-NEXT:    shrq $40, %rcx
+; CHECK-NEXT:    andl $15, %ecx
+; CHECK-NEXT:    vpinsrb $10, %ecx, %xmm0, %xmm0
+; CHECK-NEXT:    movq %rax, %rcx
+; CHECK-NEXT:    shrq $44, %rcx
+; CHECK-NEXT:    andl $15, %ecx
+; CHECK-NEXT:    vpinsrb $11, %ecx, %xmm0, %xmm0
+; CHECK-NEXT:    movq %rax, %rcx
+; CHECK-NEXT:    shrq $48, %rcx
+; CHECK-NEXT:    andl $15, %ecx
+; CHECK-NEXT:    vpinsrb $12, %ecx, %xmm0, %xmm0
+; CHECK-NEXT:    movq %rax, %rcx
+; CHECK-NEXT:    shrq $52, %rcx
+; CHECK-NEXT:    andl $15, %ecx
+; CHECK-NEXT:    vpinsrb $13, %ecx, %xmm0, %xmm0
+; CHECK-NEXT:    movq %rax, %rcx
+; CHECK-NEXT:    shrq $56, %rcx
+; CHECK-NEXT:    andl $15, %ecx
+; CHECK-NEXT:    vpinsrb $14, %ecx, %xmm0, %xmm0
+; CHECK-NEXT:    shrq $60, %rax
+; CHECK-NEXT:    vpinsrb $15, %eax, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %ret = load <16 x i4>, <16 x i4>* %in, align 1
   ret <16 x i4> %ret
 }
-
-; CHECK-LABEL: test4
-; CHECK: movl
-; CHECK-NEXT: shrl
-; CHECK-NEXT: andl
-; CHECK-NEXT: movl
-; CHECK-NEXT: andl
-; CHECK-NEXT: vmovd
-; CHECK-NEXT: vpinsrb
-; CHECK-NEXT: movl
-; CHECK-NEXT: shrl
-; CHECK-NEXT: andl
-; CHECK-NEXT: vpinsrb
-; CHECK-NEXT: movl
-; CHECK-NEXT: shrl
-; CHECK-NEXT: andl
-; CHECK-NEXT: vpinsrb
-; CHECK-NEXT: movl
-; CHECK-NEXT: shrl
-; CHECK-NEXT: andl
-; CHECK-NEXT: vpinsrb
-; CHECK-NEXT: movl
-; CHECK-NEXT: shrl
-; CHECK-NEXT: andl
-; CHECK-NEXT: vpinsrb
-; CHECK-NEXT: movl
-; CHECK-NEXT: shrl
-; CHECK-NEXT: andl
-; CHECK-NEXT: vpinsrb
-; CHECK-NEXT: movl
-; CHECK-NEXT: shrl
-; CHECK-NEXT: vpinsrb
-; CHECK-NEXT: movq
-; CHECK-NEXT: shrq
-; CHECK-NEXT: andl
-; CHECK-NEXT: vpinsrb
-; CHECK-NEXT: movq
-; CHECK-NEXT: shrq
-; CHECK-NEXT: andl
-; CHECK-NEXT: vpinsrb
-; CHECK-NEXT: movq
-; CHECK-NEXT: shrq
-; CHECK-NEXT: andl
-; CHECK-NEXT: vpinsrb
-; CHECK-NEXT: movq
-; CHECK-NEXT: shrq
-; CHECK-NEXT: andl
-; CHECK-NEXT: vpinsrb
-; CHECK-NEXT: movq
-; CHECK-NEXT: shrq
-; CHECK-NEXT: andl
-; CHECK-NEXT: vpinsrb
-; CHECK-NEXT: movq
-; CHECK-NEXT: shrq
-; CHECK-NEXT: andl
-; CHECK-NEXT: vpinsrb
-; CHECK-NEXT: movq
-; CHECK-NEXT: shrq
-; CHECK-NEXT: andl
-; CHECK-NEXT: vpinsrb
-; CHECK-NEXT: shrq
-; CHECK-NEXT: vpinsrb
-; CHECK-NEXT: retq