From: Evan Cheng Date: Sat, 25 Jul 2009 01:55:25 +0000 (+0000) Subject: 80 col violation. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=c7423aff68630d7fd1250337505a8e4be09d0f15;p=oota-llvm.git 80 col violation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77041 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 6b0692c7639..2405bd03fd0 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -959,7 +959,8 @@ void emitARMRegPlusImmediate(MachineBasicBlock &MBB, assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); // Build the new ADD / SUB. - BuildMI(MBB, MBBI, dl, TII.get(TII.getOpcode(isSub ? ARMII::SUBri : ARMII::ADDri)), DestReg) + unsigned Opc = TII.getOpcode(isSub ? ARMII::SUBri : ARMII::ADDri); + BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) .addReg(BaseReg, RegState::Kill).addImm(ThisVal) .addImm((unsigned)Pred).addReg(PredReg).addReg(0); BaseReg = DestReg;