From: zhangqing Date: Mon, 25 Jan 2016 16:56:01 +0000 (-0800) Subject: UPSTREAM: clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for spdif_8ch X-Git-Tag: firefly_0821_release~3453 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=c9c8007ff799644219b71f12c6b5b1720a7ef516;p=firefly-linux-kernel-4.4.55.git UPSTREAM: clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for spdif_8ch SPDIF_8CH set freq need to select parent and calculate parent freq. so just mark it as the CLK_SET_RATE_PARENT flag. Signed-off-by: zhangqing Signed-off-by: Heiko Stuebner (cherry picked from git.kernel.org mmind/linux-rockchip.git v4.6-clk/next commit 0bbe62eb92755ff7c16c859e96a3877de56e32c9) Change-Id: I3deed226430c492dc3b70337ae3e89d201aeb66d --- diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c index 98218500f78e..d276a55cbd39 100644 --- a/drivers/clk/rockchip/clk-rk3368.c +++ b/drivers/clk/rockchip/clk-rk3368.c @@ -353,7 +353,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = { COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(32), 0, RK3368_CLKGATE_CON(6), 5, GFLAGS), - COMPOSITE_NODIV(SCLK_SPDIF_8CH, "sclk_spdif_8ch", mux_spdif_8ch_p, 0, + COMPOSITE_NODIV(SCLK_SPDIF_8CH, "sclk_spdif_8ch", mux_spdif_8ch_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(31), 8, 2, MFLAGS, RK3368_CLKGATE_CON(6), 6, GFLAGS), COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,