From: Akira Hatanaka Date: Thu, 20 Dec 2012 03:00:16 +0000 (+0000) Subject: [mips] Delete ArithOverflowR and ArithOverflow and use ArithLogicR and X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=c9e30ea42c428ca3ccf9d70a88c4171c6be71f41;p=oota-llvm.git [mips] Delete ArithOverflowR and ArithOverflow and use ArithLogicR and ArithLogicI as the instruction base classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170642 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 1c852e2fc41..26ade789dc1 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -83,26 +83,25 @@ let usesCustomInserter = 1, Predicates = [HasStdEnc], //===----------------------------------------------------------------------===// let DecoderNamespace = "Mips64" in { /// Arithmetic Instructions (ALU Immediate) -def DADDi : ArithOverflowI<0x18, "daddi", add, simm16_64, immSExt16, - CPU64Regs>; -def DADDiu : ArithLogicI<0x19, "daddiu", add, simm16_64, immSExt16, - CPU64Regs>, IsAsCheapAsAMove; -def DANDi : ArithLogicI<0x0c, "andi", and, uimm16_64, immZExt16, CPU64Regs>; +def DADDi : ArithLogicI<0x18, "daddi", simm16_64, immSExt16, CPU64Regs>; +def DADDiu : ArithLogicI<0x19, "daddiu", simm16_64, immSExt16, CPU64Regs, + add>, IsAsCheapAsAMove; +def DANDi : ArithLogicI<0x0c, "andi", uimm16_64, immZExt16, CPU64Regs, and>; def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>; def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>; -def ORi64 : ArithLogicI<0x0d, "ori", or, uimm16_64, immZExt16, CPU64Regs>; -def XORi64 : ArithLogicI<0x0e, "xori", xor, uimm16_64, immZExt16, CPU64Regs>; +def ORi64 : ArithLogicI<0x0d, "ori", uimm16_64, immZExt16, CPU64Regs, or>; +def XORi64 : ArithLogicI<0x0e, "xori", uimm16_64, immZExt16, CPU64Regs, xor>; def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>; /// Arithmetic Instructions (3-Operand, R-Type) -def DADD : ArithOverflowR<0x00, 0x2C, "dadd", IIAlu, CPU64Regs, 1>; -def DADDu : ArithLogicR<0x00, 0x2d, "daddu", add, IIAlu, CPU64Regs, 1>; -def DSUBu : ArithLogicR<0x00, 0x2f, "dsubu", sub, IIAlu, CPU64Regs>; +def DADD : ArithLogicR<0x00, 0x2C, "dadd", IIAlu, CPU64Regs, 1>; +def DADDu : ArithLogicR<0x00, 0x2d, "daddu", IIAlu, CPU64Regs, 1, add>; +def DSUBu : ArithLogicR<0x00, 0x2f, "dsubu", IIAlu, CPU64Regs, 0, sub>; def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>; def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>; -def AND64 : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPU64Regs, 1>; -def OR64 : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPU64Regs, 1>; -def XOR64 : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPU64Regs, 1>; +def AND64 : ArithLogicR<0x00, 0x24, "and", IIAlu, CPU64Regs, 1, and>; +def OR64 : ArithLogicR<0x00, 0x25, "or", IIAlu, CPU64Regs, 1, or>; +def XOR64 : ArithLogicR<0x00, 0x26, "xor", IIAlu, CPU64Regs, 1, xor>; def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>; /// Shift Instructions diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index dc694716a37..f8ebabf8547 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -345,8 +345,9 @@ def MTC2_3OP : MFC3OP<0x12, 4, (outs CPURegs:$rd, uimm16:$sel), def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>; // Arithmetic and logical instructions with 3 register operands. -class ArithLogicR op, bits<6> func, string instr_asm, SDNode OpNode, - InstrItinClass itin, RegisterClass RC, bit isComm = 0>: +class ArithLogicR op, bits<6> func, string instr_asm, + InstrItinClass itin, RegisterClass RC, bit isComm = 0, + SDPatternOperator OpNode = null_frag>: FR { @@ -355,28 +356,15 @@ class ArithLogicR op, bits<6> func, string instr_asm, SDNode OpNode, let isReMaterializable = 1; } -class ArithOverflowR op, bits<6> func, string instr_asm, - InstrItinClass itin, RegisterClass RC, bit isComm = 0>: - FR { - let shamt = 0; - let isCommutable = isComm; -} - // Arithmetic and logical instructions with 2 register operands. -class ArithLogicI op, string instr_asm, SDNode OpNode, - Operand Od, PatLeaf imm_type, RegisterClass RC> : +class ArithLogicI op, string instr_asm, Operand Od, PatLeaf imm_type, + RegisterClass RC, SDPatternOperator OpNode = null_frag> : FI { let isReMaterializable = 1; } -class ArithOverflowI op, string instr_asm, SDNode OpNode, - Operand Od, PatLeaf imm_type, RegisterClass RC> : - FI; - // Arithmetic Multiply ADD/SUB let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in class MArithR func, string instr_asm, SDNode op, bit isComm = 0> : @@ -931,26 +919,26 @@ def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>; //===----------------------------------------------------------------------===// /// Arithmetic Instructions (ALU Immediate) -def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>, +def ADDiu : ArithLogicI<0x09, "addiu", simm16, immSExt16, CPURegs, add>, IsAsCheapAsAMove; -def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>; +def ADDi : ArithLogicI<0x08, "addi", simm16, immSExt16, CPURegs>; def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>; def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>; -def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>; -def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>; -def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>; +def ANDi : ArithLogicI<0x0c, "andi", uimm16, immZExt16, CPURegs, and>; +def ORi : ArithLogicI<0x0d, "ori", uimm16, immZExt16, CPURegs, or>; +def XORi : ArithLogicI<0x0e, "xori", uimm16, immZExt16, CPURegs, xor>; def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>; /// Arithmetic Instructions (3-Operand, R-Type) -def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>; -def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>; -def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>; -def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>; +def ADDu : ArithLogicR<0x00, 0x21, "addu", IIAlu, CPURegs, 1, add>; +def SUBu : ArithLogicR<0x00, 0x23, "subu", IIAlu, CPURegs, 0, sub>; +def ADD : ArithLogicR<0x00, 0x20, "add", IIAlu, CPURegs, 1>; +def SUB : ArithLogicR<0x00, 0x22, "sub", IIAlu, CPURegs, 0>; def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>; def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>; -def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>; -def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>; -def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>; +def AND : ArithLogicR<0x00, 0x24, "and", IIAlu, CPURegs, 1, and>; +def OR : ArithLogicR<0x00, 0x25, "or", IIAlu, CPURegs, 1, or>; +def XOR : ArithLogicR<0x00, 0x26, "xor", IIAlu, CPURegs, 1, xor>; def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>; /// Shift Instructions @@ -1075,7 +1063,7 @@ def MSUBU : MArithR<5, "msubu", MipsMSubu>; // MUL is a assembly macro in the current used ISAs. In recent ISA's // it is a real instruction. -def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>, +def MUL : ArithLogicR<0x1c, 0x02, "mul", IIImul, CPURegs, 1, mul>, Requires<[HasStdEnc]>; def RDHWR : ReadHardware;