From: Nadav Rotem <nadav.rotem@intel.com>
Date: Sun, 18 Sep 2011 19:00:23 +0000 (+0000)
Subject: Fix typos in my prev commit, found by Tobi.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=ca6f296b483e203b33a050fe52ebab2eae1541b0;p=oota-llvm.git

Fix typos in my prev commit, found by Tobi.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140003 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index cc904d9a1da..a570cd16093 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -13445,7 +13445,7 @@ static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
 
   ISD::LoadExtType Ext = Ld->getExtensionType();
 
-  // If yhis is a vector EXT Load then attempt to optimize it using a
+  // If this is a vector EXT Load then attempt to optimize it using a
   // shuffle. We need SSE4 for the shuffles.
   // TODO: It is possible to support ZExt by zeroing the undef values
   // during the shuffle phase or after the shuffle.
@@ -13457,7 +13457,7 @@ static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
     unsigned RegSz = RegVT.getSizeInBits();
     unsigned MemSz = MemVT.getSizeInBits();
     assert(RegSz > MemSz && "Register size must be greater than the mem size");
-    // All sized must be a power of two
+    // All sizes must be a power of two
     if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
 
     // Attempt to load the original value using a single load op.