From: Xing Zheng Date: Mon, 22 Feb 2016 10:13:20 +0000 (+0800) Subject: clk: rockchip: update dt-binding header for rk3399 X-Git-Tag: firefly_0821_release~3368 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=cb2b8e529aada23467e2e77d5990e1a7560e7b44;p=firefly-linux-kernel-4.4.55.git clk: rockchip: update dt-binding header for rk3399 Because the RK3399 CRU TRM is updating, so we need to maintain a consistent naming clock IDs. Change-Id: I1724827f05f4f44b197c14a5d81fec5afc1202b5 Signed-off-by: Xing Zheng --- diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 9fa6183db766..edf687860fd4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -212,7 +212,7 @@ interrupts = , ; #dma-cells = <1>; - clocks = <&cru ACLK_DMAC_BUS>; + clocks = <&cru ACLK_DMAC0_PERILP>; clock-names = "apb_pclk"; }; @@ -222,7 +222,7 @@ interrupts = , ; #dma-cells = <1>; - clocks = <&cru ACLK_DMAC_PERI>; + clocks = <&cru ACLK_DMAC1_PERILP>; clock-names = "apb_pclk"; }; }; @@ -279,7 +279,7 @@ uart4: serial@ff370000 { compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; reg = <0x0 0xff370000 0x0 0x100>; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>; clock-names = "baudclk", "apb_pclk"; interrupts = ; reg-shift = <2>; diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 292e717fa165..77916886c180 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -17,212 +17,332 @@ #define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H /* core clocks */ -#define PLL_APLLL 1 -#define PLL_APLLB 2 -#define PLL_DPLL 3 -#define PLL_CPLL 4 -#define PLL_GPLL 5 -#define PLL_NPLL 6 -#define PLL_VPLL 7 -#define PLL_PPLL 8 -#define ARMCLKL 9 -#define ARMCLKB 10 +#define PLL_APLLL 1 +#define PLL_APLLB 2 +#define PLL_DPLL 3 +#define PLL_CPLL 4 +#define PLL_GPLL 5 +#define PLL_NPLL 6 +#define PLL_VPLL 7 +#define PLL_PPLL 8 +#define ARMCLKL 9 +#define ARMCLKB 10 /* sclk gates (special clocks) */ -#define SCLK_GPU_CORE 64 -#define SCLK_SPI0 65 -#define SCLK_SPI1 66 -#define SCLK_SPI2 68 -#define SCLK_SPI3 69 -#define SCLK_SPI4 70 -#define SCLK_SDMMC 71 -#define SCLK_SDIO0 72 -#define SCLK_EMMC 73 -#define SCLK_TSADC 74 -#define SCLK_SARADC 75 -#define SCLK_NANDC0 76 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_UART3 80 -#define SCLK_UART4 81 -#define SCLK_SPDIF_8CH 82 -#define SCLK_I2S0_8CH 83 -#define SCLK_I2S1_8CH 84 -#define SCLK_I2S2_8CH 85 -#define SCLK_TIMER00 86 -#define SCLK_TIMER01 87 -#define SCLK_TIMER02 88 -#define SCLK_TIMER03 89 -#define SCLK_TIMER04 90 -#define SCLK_TIMER05 91 -#define SCLK_TIMER06 92 -#define SCLK_TIMER07 93 -#define SCLK_TIMER08 94 -#define SCLK_TIMER09 95 -#define SCLK_TIMER10 96 -#define SCLK_TIMER11 97 -#define SCLK_HSICPHY480M 98 -#define SCLK_HSICPHY12M 99 -#define SCLK_MACREF 100 -#define SCLK_VOPB_PWM 101 -#define SCLK_VOPL_PWM 102 -#define SCLK_EDP_24M 104 -#define SCLK_EDP 105 -#define SCLK_RGA 106 -#define SCLK_ISP 107 -#define SCLK_HDCP 108 -#define SCLK_HDMI_HDCP 109 -#define SCLK_HDMI_CEC 110 -#define SCLK_HEVC_CABAC 111 -#define SCLK_HEVC_CORE 112 -#define SCLK_I2S_8CH_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO0_DRV 115 -#define SCLK_SDIO1_DRV 116 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO0_SAMPLE 119 -#define SCLK_SDIO1_SAMPLE 120 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_USBPHY480M 122 -#define SCLK_PVTM_CORE_L 123 -#define SCLK_PVTM_CORE_B 124 -#define SCLK_PVTM_GPU 125 -#define SCLK_PVTM_PMU 126 -#define SCLK_SFC 127 -#define SCLK_MAC_RX 128 -#define SCLK_MAC_TX 129 -#define SCLK_MAC 130 -#define SCLK_MACREF_OUT 131 -#define SCLK_USB2_PHY0_REF 132 -#define SCLK_USB2_PHY1_REF 133 -#define SCLK_USB3_OTG0_REF 134 -#define SCLK_USB3_OTG1_REF 135 -#define SCLK_USB3_OTG0_SUSPEND 136 -#define SCLK_USB3_OTG1_SUSPEND 137 -#define SCLK_CRYPTO 138 -#define SCLK_CRYPTO1 139 - -#define DCLK_VOPB 170 -#define DCLK_VOPL 171 -#define MCLK_CRYPTO 172 -#define MCLK_CRYPTO1 173 +#define SCLK_I2C1 65 +#define SCLK_I2C2 66 +#define SCLK_I2C3 67 +#define SCLK_I2C5 68 +#define SCLK_I2C6 69 +#define SCLK_I2C7 70 +#define SCLK_SPI0 71 +#define SCLK_SPI1 72 +#define SCLK_SPI2 73 +#define SCLK_SPI4 74 +#define SCLK_SPI5 75 +#define SCLK_SDMMC 76 +#define SCLK_SDIO 77 +#define SCLK_EMMC 78 +#define SCLK_TSADC 79 +#define SCLK_SARADC 80 +#define SCLK_UART0 81 +#define SCLK_UART1 82 +#define SCLK_UART2 83 +#define SCLK_UART3 84 +#define SCLK_SPDIF_8CH 85 +#define SCLK_I2S0_8CH 86 +#define SCLK_I2S1_8CH 87 +#define SCLK_I2S2_8CH 88 +#define SCLK_I2S_8CH_OUT 89 +#define SCLK_TIMER00 90 +#define SCLK_TIMER01 91 +#define SCLK_TIMER02 92 +#define SCLK_TIMER03 93 +#define SCLK_TIMER04 94 +#define SCLK_TIMER05 95 +#define SCLK_TIMER06 96 +#define SCLK_TIMER07 97 +#define SCLK_TIMER08 98 +#define SCLK_TIMER09 99 +#define SCLK_TIMER10 100 +#define SCLK_TIMER11 101 +#define SCLK_MACREF 102 +#define SCLK_MAC_RX 103 +#define SCLK_MAC_TX 104 +#define SCLK_MAC 105 +#define SCLK_MACREF_OUT 106 +#define SCLK_VOP0_PWM 107 +#define SCLK_VOP1_PWM 108 +#define SCLK_RGA 109 +#define SCLK_ISP0 110 +#define SCLK_ISP1 111 +#define SCLK_HDMI_CEC 112 +#define SCLK_HDMI_SFR 113 +#define SCLK_DP_CORE_SRC 114 +#define SCLK_PVTM_CORE_L 115 +#define SCLK_PVTM_CORE_B 116 +#define SCLK_PVTM_GPU 117 +#define SCLK_PVTM_DDR 118 +#define SCLK_MIPIDPHY_REF 119 +#define SCLK_MIPIDPHY_CFG 120 +#define SCLK_HSICPHY 121 +#define SCLK_USBPHY480M 122 +#define SCLK_USB2PHY0_REF 123 +#define SCLK_USB2PHY1_REF 124 +#define SCLK_UPHY0_TCPDPHY_REF 125 +#define SCLK_UPHY0_TCPDCORE 126 +#define SCLK_UPHY1_TCPDPHY_REF 127 +#define SCLK_UPHY1_TCPDCORE 128 +#define SCLK_USB3OTG0_REF 129 +#define SCLK_USB3OTG1_REF 130 +#define SCLK_USB3OTG0_SUSPEND 131 +#define SCLK_USB3OTG1_SUSPEND 132 +#define SCLK_CRYPTO0 133 +#define SCLK_CRYPTO1 134 +#define SCLK_CCI_TRACE 135 +#define SCLK_CS 136 +#define SCLK_CIF_OUT 137 +#define SCLK_PCIEPHY_REF 138 +#define SCLK_PCIE_CORE 139 +#define SCLK_MO_PERILP 140 +#define SCLK_M0_PERILP_DEC 141 +#define SCLK_CM0S 142 +#define SCLK_DBG_NOC 143 +#define SCLK_DBG_PD_CORE_B 144 +#define SCLK_DBG_PD_CORE_L 145 +#define SCLK_DFIMON0_TIMER 146 +#define SCLK_DFIMON1_TIMER 147 +#define SCLK_INTMEM0 148 +#define SCLK_INTMEM1 149 +#define SCLK_INTMEM2 150 +#define SCLK_INTMEM3 151 +#define SCLK_INTMEM4 152 +#define SCLK_INTMEM5 153 + +#define DCLK_VOP0 170 +#define DCLK_VOP1 171 /* aclk gates */ -#define ACLK_GPU_MEM 192 -#define ACLK_GPU_CFG 193 -#define ACLK_DMAC_BUS 194 -#define ACLK_DMAC_PERI 195 -#define ACLK_PERI_MMU 196 -#define ACLK_GMAC 197 -#define ACLK_VOPB 198 -#define ACLK_VOPL 199 -#define ACLK_RGA 200 -#define ACLK_HDCP 201 -#define ACLK_IEP 202 -#define ACLK_VIO0_NOC 203 -#define ACLK_VIP 204 -#define ACLK_ISP 205 -#define ACLK_VIO1_NOC 206 -#define ACLK_VIDEO 208 -#define ACLK_BUS 209 -#define ACLK_PERI 210 -#define ACLK_EMMC_GPLL 211 -#define ACLK_EMMC_CPLL 212 -#define ACLK_EMMC_CORE 213 -#define ACLK_EMMC_NIU 214 -#define ACLK_EMMC_GRF 215 -#define ACLK_USB3_OTG0 216 -#define ACLK_USB3_OTG1 217 -#define ACLK_USB3_GRF 218 +#define ACLK_PERIHP 192 +#define ACLK_PERIHP_NOC 193 +#define ACLK_PERILP0 194 +#define ACLK_PERILP0_NOC 195 +#define ACLK_PERF_PCIE 196 +#define ACLK_PCIE 197 +#define ACLK_INTMEM 198 +#define ACLK_TZMA 199 +#define ACLK_DCF 200 +#define ACLK_CCI 201 +#define ACLK_CCI_NOC0 202 +#define ACLK_CCI_NOC1 203 +#define ACLK_CCI_GRF 204 +#define ACLK_CENTER 205 +#define ACLK_CENTER_MAIN_NOC 206 +#define ACLK_CENTER_PERI_NOC 207 +#define ACLK_GPU 208 +#define ACLK_PERF_GPU 209 +#define ACLK_GPU_GRF 210 +#define ACLK_DMAC0_PERILP 211 +#define ACLK_DMAC1_PERILP 212 +#define ACLK_GMAC 213 +#define ACLK_GMAC_NOC 214 +#define ACLK_PERF_GMAC 215 +#define ACLK_VOP0_NOC 216 +#define ACLK_VOP0 217 +#define ACLK_VOP1_NOC 218 +#define ACLK_VOP1 219 +#define ACLK_RGA 220 +#define ACLK_RGA_NOC 221 +#define ACLK_HDCP 222 +#define ACLK_HDCP_NOC 223 +#define ACLK_HDCP22 224 +#define ACLK_IEP 225 +#define ACLK_IEP_NOC 226 +#define ACLK_VIO 227 +#define ACLK_VIO_NOC 228 +#define ACLK_ISP0 229 +#define ACLK_ISP1 230 +#define ACLK_ISP0_NOC 231 +#define ACLK_ISP1_NOC 232 +#define ACLK_ISP0_WRAPPER 233 +#define ACLK_ISP1_WRAPPER 234 +#define ACLK_VCODEC 235 +#define ACLK_VCODEC_NOC 236 +#define ACLK_VDU 237 +#define ACLK_VDU_NOC 238 +#define ACLK_PERI 239 +#define ACLK_EMMC 240 +#define ACLK_EMMC_CORE 241 +#define ACLK_EMMC_NOC 242 +#define ACLK_EMMC_GRF 243 +#define ACLK_USB3 244 +#define ACLK_USB3_NOC 245 +#define ACLK_USB3OTG0 246 +#define ACLK_USB3OTG1 247 +#define ACLK_USB3_RKSOC_AXI_PERF 248 +#define ACLK_USB3_GRF 249 +#define ACLK_GIC 250 +#define ACLK_GIC_NOC 251 +#define ACLK_GIC_ADB400_CORE_L_2_GIC 252 +#define ACLK_GIC_ADB400_CORE_B_2_GIC 253 +#define ACLK_GIC_ADB400_GIC_2_CORE_L 254 +#define ACLK_GIC_ADB400_GIC_2_CORE_B 255 /* pclk gates */ -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GPIO3 323 -#define PCLK_GPIO4 324 -#define PCLK_PMUGRF 325 -#define PCLK_MAILBOX 326 -#define PCLK_GRF 329 -#define PCLK_SGRF 330 -#define PCLK_PMU 331 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_I2C3 335 -#define PCLK_I2C4 336 -#define PCLK_I2C5 337 -#define PCLK_SPI0 338 -#define PCLK_SPI1 339 -#define PCLK_SPI2 340 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_UART3 344 -#define PCLK_UART4 345 -#define PCLK_TSADC 346 -#define PCLK_SARADC 347 -#define PCLK_SIM 348 -#define PCLK_GMAC 349 -#define PCLK_PWM0 350 -#define PCLK_PWM1 351 -#define PCLK_TIMER0 353 -#define PCLK_TIMER1 354 -#define PCLK_EDP_CTRL 355 -#define PCLK_MIPI_DSI0 356 -#define PCLK_MIPI_CSI 358 -#define PCLK_HDCP 359 -#define PCLK_HDMI_CTRL 360 -#define PCLK_VIO_H2P 361 -#define PCLK_BUS 362 -#define PCLK_PERI 363 -#define PCLK_DDRUPCTL 364 -#define PCLK_DDRPHY 365 -#define PCLK_ISP 366 -#define PCLK_VIP 367 -#define PCLK_WDT 368 +#define PCLK_PERIHP 320 +#define PCLK_PERIHP_NOC 321 +#define PCLK_PERILP0 322 +#define PCLK_PERILP1 323 +#define PCLK_PERILP1_NOC 324 +#define PCLK_PERILP_SGRF 325 +#define PCLK_PERIHP_GRF 326 +#define PCLK_PCIE 327 +#define PCLK_SGRF 328 +#define PCLK_INTR_ARB 329 +#define PCLK_CENTER_MAIN_NOC 330 +#define PCLK_CIC 331 +#define PCLK_COREDBG_B 332 +#define PCLK_COREDBG_L 333 +#define PCLK_DBG_CXCS_PD_CORE_B 334 +#define PCLK_DCF 335 +#define PCLK_GPIO2 336 +#define PCLK_GPIO3 337 +#define PCLK_GPIO4 338 +#define PCLK_GRF 339 +#define PCLK_HSICPHY 340 +#define PCLK_I2C1 341 +#define PCLK_I2C2 342 +#define PCLK_I2C3 343 +#define PCLK_I2C5 344 +#define PCLK_I2C6 345 +#define PCLK_I2C7 346 +#define PCLK_SPI0 347 +#define PCLK_SPI1 348 +#define PCLK_SPI2 349 +#define PCLK_SPI4 350 +#define PCLK_SPI5 351 +#define PCLK_UART0 352 +#define PCLK_UART1 353 +#define PCLK_UART2 354 +#define PCLK_UART3 355 +#define PCLK_TSADC 356 +#define PCLK_SARADC 357 +#define PCLK_GMAC 358 +#define PCLK_GMAC_NOC 359 +#define PCLK_TIMER0 360 +#define PCLK_TIMER1 361 +#define PCLK_EDP 362 +#define PCLK_EDP_NOC 363 +#define PCLK_EDP_CTRL 364 +#define PCLK_VIO 365 +#define PCLK_VIO_NOC 366 +#define PCLK_VIO_GRF 367 +#define PCLK_MIPI_DSI0 368 +#define PCLK_MIPI_DSI1 369 +#define PCLK_HDCP 370 +#define PCLK_HDCP_NOC 371 +#define PCLK_HDMI_CTRL 372 +#define PCLK_DP_CTRL 373 +#define PCLK_HDCP22 374 +#define PCLK_GASKET 375 +#define PCLK_DDR 376 +#define PCLK_DDR_MON 377 +#define PCLK_DDR_SGRF 378 +#define PCLK_ISP1_WRAPPER 379 +#define PCLK_WDT 380 +#define PCLK_EFUSE1024NS 381 +#define PCLK_EFUSE1024S 382 +#define PCLK_PMU_INTR_ARB 383 +#define PCLK_MAILBOX0 384 /* hclk gates */ -#define HCLK_SFC 448 -#define HCLK_HOST0 450 -#define HCLK_HOST1 451 -#define HCLK_HSIC 452 -#define HCLK_NANDC0 453 -#define HCLK_TSP 455 -#define HCLK_SDMMC 456 -#define HCLK_SDIO0 457 -#define HCLK_EMMC 459 -#define HCLK_HSADC 460 -#define HCLK_CRYPTO 461 -#define HCLK_I2S0_8CH 462 -#define HCLK_I2S1_8CH 463 -#define HCLK_I2S2_8CH 464 -#define HCLK_SPDIF 465 -#define HCLK_VOPB 466 -#define HCLK_VOPL 467 -#define HCLK_ROM 468 -#define HCLK_IEP 469 -#define HCLK_ISP 470 -#define HCLK_RGA 471 -#define HCLK_VIO_AHB_ARBI 472 -#define HCLK_VIO_NOC 473 -#define HCLK_VIP 474 -#define HCLK_VIO_H2P 475 -#define HCLK_VIO_HDCPMMU 476 -#define HCLK_VIDEO 477 -#define HCLK_BUS 478 -#define HCLK_PERI 479 +#define HCLK_PERIHP 448 +#define HCLK_PERILP0 449 +#define HCLK_PERILP1 450 +#define HCLK_PERILP0_NOC 451 +#define HCLK_PERILP1_NOC 452 +#define HCLK_M0_PERILP 453 +#define HCLK_M0_PERILP_NOC 454 +#define HCLK_AHB1TOM 455 +#define HCLK_HOST0 456 +#define HCLK_HOST0_ARB 457 +#define HCLK_HOST1 458 +#define HCLK_HOST1_ARB 459 +#define HCLK_HSIC 460 +#define HCLK_SD 461 +#define HCLK_SDMMC 462 +#define HCLK_SDMMC_NOC 463 +#define HCLK_M_CRYPTO0 464 +#define HCLK_M_CRYPTO1 465 +#define HCLK_S_CRYPTO0 466 +#define HCLK_S_CRYPTO1 467 +#define HCLK_I2S0_8CH 468 +#define HCLK_I2S1_8CH 469 +#define HCLK_I2S2_8CH 470 +#define HCLK_SPDIF 471 +#define HCLK_VOP0_NOC 472 +#define HCLK_VOP0 473 +#define HCLK_VOP1_NOC 474 +#define HCLK_VOP1 475 +#define HCLK_ROM 476 +#define HCLK_IEP 477 +#define HCLK_IEP_NOC 478 +#define HCLK_ISP0 479 +#define HCLK_ISP1 480 +#define HCLK_ISP0_NOC 481 +#define HCLK_ISP1_NOC 482 +#define HCLK_ISP0_WRAPPER 483 +#define HCLK_ISP1_WRAPPER 484 +#define HCLK_RGA 485 +#define HCLK_RGA_NOC 486 +#define HCLK_HDCP 487 +#define HCLK_HDCP_NOC 488 +#define HCLK_HDCP22 489 +#define HCLK_VCODEC 490 +#define HCLK_VCODEC_NOC 491 +#define HCLK_VDU 492 +#define HCLK_VDU_NOC 493 +#define HCLK_SDIO 494 +#define HCLK_SDIO_NOC 495 +#define HCLK_SDIOAUDIO_NOC 496 /* pmu-clocks indices */ -#define SCLK_CM0S 500 -#define SCLK_SPI5 501 -#define SCLK_TIMER12 502 -#define SCLK_TIMER13 503 -#define SCLK_UART 504 - -#define CLK_NR_CLKS (SCLK_UART + 1) +#define SCLK_32K_SUSPEND_PMU 521 +#define SCLK_SPI3_PMU 522 +#define SCLK_TIMER12_PMU 523 +#define SCLK_TIMER13_PMU 524 +#define SCLK_UART4_PMU 525 +#define SCLK_PVTM_PMU 526 +#define SCLK_WIFI_PMU 527 +#define SCLK_I2C0_PMU 528 +#define SCLK_I2C4_PMU 529 +#define SCLK_I2C8_PMU 530 + +#define PCLK_PMU 540 +#define PCLK_PMUGRF_PMU 541 +#define PCLK_INTMEM1_PMU 542 +#define PCLK_GPIO0_PMU 543 +#define PCLK_GPIO1_PMU 544 +#define PCLK_SGRF_PMU 545 +#define PCLK_NOC_PMU 546 +#define PCLK_I2C0_PMU 547 +#define PCLK_I2C4_PMU 548 +#define PCLK_I2C8_PMU 549 +#define PCLK_RKPWM_PMU 550 +#define PCLK_SPI3_PMU 551 +#define PCLK_TIMER_PMU 552 +#define PCLK_MAILBOX_PMU 553 +#define PCLK_UART4_PMU 554 +#define PCLK_WDT_M0_PMU 555 + +#define FCLK_CM0S_PMU 560 +#define SCLK_CM0S_PMU 561 +#define HCLK_CM0S_PMU 562 +#define DCLK_CM0S_PMU 563 +#define PCLK_INTR_ARB_PMU 564 +#define HCLK_NOC_PMU 565 + +#define CLK_NR_CLKS (HCLK_NOC_PMU + 1) /* soft-reset indices */ @@ -236,9 +356,9 @@ #define SRST_ADB_L 6 #define SRST_ADB_B 7 #define SRST_A_CCI 8 -#define SRST_A_CCIM0_NIU 9 -#define SRST_A_CCIM1_NIU 10 -#define SRST_DBG_NIU 11 +#define SRST_A_CCIM0_NOC 9 +#define SRST_A_CCIM1_NOC 10 +#define SRST_DBG_NOC 11 /* cru_softrst_con1 */ #define SRST_CORE_L0_T 16 @@ -249,13 +369,12 @@ #define SRST_CORE_PO_L1 21 #define SRST_CORE_PO_L2 22 #define SRST_CORE_PO_L3 23 -#define SRST_A_ADB400_GIC2_CORE_L 24 -#define SRST_A_ADB400_CORE_L_GIC2 25 +#define SRST_A_ADB400_GIC2COREL 24 +#define SRST_A_ADB400_COREL2GIC 25 #define SRST_P_DBG_L 26 -#define SRST_SOC_DBG_L 27 #define SRST_L2_L_T 28 #define SRST_ADB_L_T 29 -#define SRST_A_RKREF_L 30 +#define SRST_A_RKPERF_L 30 #define SRST_PVTM_CORE_L 31 /* cru_softrst_con2 */ @@ -263,31 +382,30 @@ #define SRST_CORE_B1 33 #define SRST_CORE_PO_B0_T 36 #define SRST_CORE_PO_B1 37 -#define SRST_A_ADB400_GIC2_CORE_B 40 -#define SRST_A_ADB400_CORE_B_GIC2 41 +#define SRST_A_ADB400_GIC2COREB 40 +#define SRST_A_ADB400_COREB2GIC 41 #define SRST_P_DBG_B 42 #define SRST_L2_B_T 43 -#define SRST_SOC_DBG_B 44 #define SRST_ADB_B_T 45 -#define SRST_A_RKREF_B 46 +#define SRST_A_RKPERF_B 46 #define SRST_PVTM_CORE_B 47 /* cru_softrst_con3 */ #define SRST_A_CCI_T 50 -#define SRST_A_CCIM0_NIU_T 51 -#define SRST_A_CCIM1_NIU_T 52 +#define SRST_A_CCIM0_NOC_T 51 +#define SRST_A_CCIM1_NOC_T 52 #define SRST_A_ADB400M_PD_CORE_B_T 53 #define SRST_A_ADB400M_PD_CORE_L_T 54 -#define SRST_DBG_NIU_T 55 +#define SRST_DBG_NOC_T 55 #define SRST_DBG_CXCS 56 #define SRST_CCI_TRACE 57 #define SRST_P_CCI_GRF 58 /* cru_softrst_con4 */ -#define SRST_A_CENTER_MAIN_NIU 64 -#define SRST_A_CENTER_PERI_NIU 65 +#define SRST_A_CENTER_MAIN_NOC 64 +#define SRST_A_CENTER_PERI_NOC 65 #define SRST_P_CENTER_MAIN 66 -#define SRST_P_DDRMAON 67 +#define SRST_P_DDRMON 67 #define SRST_P_CIC 68 #define SRST_P_CENTER_SGRF 69 #define SRST_DDR0_MSCH 70 @@ -302,49 +420,48 @@ #define SRST_PVTM_DDR 79 /* cru_softrst_con5 */ -#define SRST_A_VCODEC_NIU 80 +#define SRST_A_VCODEC_NOC 80 #define SRST_A_VCODEC 81 -#define SRST_H_VCODEC_NIU 82 +#define SRST_H_VCODEC_NOC 82 #define SRST_H_VCODEC 83 -#define SRST_A_VDU_NIU 88 -#define SRST_A_VDU 89 -#define SRST_H_VDU_NIU 90 +#define SRST_A_VDU_NOC 88 +#define SRST_A_VDU 89 +#define SRST_H_VDU_NOC 90 #define SRST_H_VDU 91 #define SRST_VDU_CORE 92 #define SRST_VDU_CA 93 /* cru_softrst_con6 */ -#define SRST_A_IEP_NIU 96 +#define SRST_A_IEP_NOC 96 #define SRST_A_VOP_IEP 97 #define SRST_A_IEP 98 -#define SRST_H_IEP_NIU 99 +#define SRST_H_IEP_NOC 99 #define SRST_H_IEP 100 -#define SRST_A_RGA_NIU 102 +#define SRST_A_RGA_NOC 102 #define SRST_A_RGA 103 -#define SRST_H_RGA_NIU 104 +#define SRST_H_RGA_NOC 104 #define SRST_H_RGA 105 #define SRST_RGA_CORE 106 -#define SRST_EMMC_NIU 108 +#define SRST_EMMC_NOC 108 #define SRST_EMMC 109 #define SRST_EMMC_GRF 110 -#define SRST_EMMCPHY_SYSRX 111 /* cru_softrst_con7 */ -#define SRST_A_PERIHP_NIU 112 -#define SRST_A_PERIHP_GRF 113 -#define SRST_H_PERIHP_NIU 114 -#define SRST_USBHOST0 115 +#define SRST_A_PERIHP_NOC 112 +#define SRST_P_PERIHP_GRF 113 +#define SRST_H_PERIHP_NOC 114 +#define SRST_USBHOST0 115 #define SRST_HOSTC0_AUX 116 -#define SRST_HOSTC0_ARB 117 +#define SRST_HOST0_ARB 117 #define SRST_USBHOST1 118 #define SRST_HOSTC1_AUX 119 -#define SRST_HOSTC1_ARB 120 +#define SRST_HOST1_ARB 120 #define SRST_SDIO0 121 #define SRST_SDMMC 122 #define SRST_HSIC 123 #define SRST_HSIC_AUX 124 #define SRST_AHB1TOM 125 -#define SRST_P_PERIHP_NIU 126 +#define SRST_P_PERIHP_NOC 126 #define SRST_HSICPHY 127 /* cru_softrst_con8 */ @@ -356,10 +473,9 @@ #define SRST_PCIE_PIPE 133 #define SRST_PCIE_PM 134 #define SRST_PCIEPHY 135 -#define SRST_A_GMAC_NIU 136 -#define SRST_A_GMAC 137 -#define SRST_P_GMAC_NIU 138 -#define SRST_P_GMAC 139 +#define SRST_A_GMAC_NOC 136 +#define SRST_A_GMAC 137 +#define SRST_P_GMAC_NOC 138 #define SRST_P_GMAC_GRF 140 #define SRST_HSICPHY_POR 142 #define SRST_HSICPHY_UTMI 143 @@ -381,7 +497,7 @@ #define SRST_UPHY1_TCPDPWRUP 158 /* cru_softrst_con10 */ -#define SRST_A_PERILP0_NIU 160 +#define SRST_A_PERILP0_NOC 160 #define SRST_A_DCF 161 #define SRST_GIC500 162 #define SRST_DMAC0_PERILP0 163 @@ -393,14 +509,14 @@ #define SRST_ADB400_SLV0 169 #define SRST_ADB400_SLV1 170 #define SRST_H_PERILP0 171 -#define SRST_H_PERILP0_NIU 172 +#define SRST_H_PERILP0_NOC 172 #define SRST_ROM 173 #define SRST_CRYPTO_S 174 #define SRST_CRYPTO_M 175 /* cru_softrst_con11 */ #define SRST_P_DCF 176 -#define SRST_CM0S_NIU 177 +#define SRST_CM0S_NOC 177 #define SRST_CM0S 178 #define SRST_CM0S_DBG 179 #define SRST_CM0S_PO 180 @@ -410,18 +526,18 @@ #define SRST_CRYPTO1_S 184 #define SRST_CRYPTO1_M 185 #define SRST_CRYPTO1 186 -#define SRST_GIC_NIU 188 -#define SRST_SD_NIU 189 +#define SRST_GIC_NOC 188 +#define SRST_SD_NOC 189 #define SRST_SDIOAUDIO_BRG 190 /* cru_softrst_con12 */ #define SRST_H_PERILP1 192 -#define SRST_H_PERILP1_NIU 193 +#define SRST_H_PERILP1_NOC 193 #define SRST_H_I2S0_8CH 194 #define SRST_H_I2S1_8CH 195 #define SRST_H_I2S2_8CH 196 #define SRST_H_SPDIF_8CH 197 -#define SRST_P_PERILP1_NIU 198 +#define SRST_P_PERILP1_NOC 198 #define SRST_P_EFUSE_1024 199 #define SRST_P_EFUSE_1024S 200 #define SRST_P_I2C0 201 @@ -466,15 +582,15 @@ #define SRST_I2C3 236 #define SRST_I2C4 237 #define SRST_I2C5 238 -#define SRST_SDIOAUDIO_NIU 239 +#define SRST_SDIOAUDIO_NOC 239 /* cru_softrst_con15 */ -#define SRST_A_VIO_NIU 240 -#define SRST_A_HDCP_NIU 241 +#define SRST_A_VIO_NOC 240 +#define SRST_A_HDCP_NOC 241 #define SRST_A_HDCP 242 -#define SRST_H_HDCP_NIU 243 +#define SRST_H_HDCP_NOC 243 #define SRST_H_HDCP 244 -#define SRST_P_HDCP_NIU 245 +#define SRST_P_HDCP_NOC 245 #define SRST_P_HDCP 246 #define SRST_P_HDMI_CTRL 247 #define SRST_P_DP_CTRL 248 @@ -484,53 +600,47 @@ #define SRST_P_MIPI_DSI1 252 #define SRST_DP_CORE 253 #define SRST_DP_I2S 254 -#define SRST_DP_VIF 255 /* cru_softrst_con16 */ #define SRST_GASKET 256 -#define SRST_VIO_SGRF 257 #define SRST_VIO_GRF 258 #define SRST_DPTX_SPDIF_REC 259 #define SRST_HDMI_CTRL 260 #define SRST_HDCP_CTRL 261 -#define SRST_A_ISP0_NIU 262 -#define SRST_A_ISP1_NIU 263 -#define SRST_A_ISP0 264 -#define SRST_A_ISP1 265 -#define SRST_H_ISP0_NIU 266 -#define SRST_H_ISP1_NIU 267 +#define SRST_A_ISP0_NOC 262 +#define SRST_A_ISP1_NOC 263 +#define SRST_H_ISP0_NOC 266 +#define SRST_H_ISP1_NOC 267 #define SRST_H_ISP0 268 #define SRST_H_ISP1 269 #define SRST_ISP0 270 #define SRST_ISP1 271 /* cru_softrst_con17 */ -#define SRST_A_VOP0_NIU 272 -#define SRST_A_VOP1_NIU 273 +#define SRST_A_VOP0_NOC 272 +#define SRST_A_VOP1_NOC 273 #define SRST_A_VOP0 274 #define SRST_A_VOP1 275 -#define SRST_H_VOP0_NIU 276 -#define SRST_H_VOP1_NIU 277 +#define SRST_H_VOP0_NOC 276 +#define SRST_H_VOP1_NOC 277 #define SRST_H_VOP0 278 #define SRST_H_VOP1 279 #define SRST_D_VOP0 280 #define SRST_D_VOP1 281 #define SRST_VOP0_PWM 282 #define SRST_VOP1_PWM 283 -#define SRST_P_EDP_NIU 284 +#define SRST_P_EDP_NOC 284 #define SRST_P_EDP_CTRL 285 /* cru_softrst_con18 */ -#define SRST_A_GPU 288 -#define SRST_A_GPU_NIU 289 +#define SRST_A_GPU_NOC 289 #define SRST_A_GPU_GRF 290 #define SRST_PVTM_GPU 291 -#define SRST_A_USB3_NIU 292 +#define SRST_A_USB3_NOC 292 #define SRST_A_USB3_OTG0 293 #define SRST_A_USB3_OTG1 294 #define SRST_A_USB3_GRF 295 #define SRST_PMU 296 -#define SRST_PVTM_PMU 297 /* cru_softrst_con19 */ #define SRST_P_TIMER0_5 304 @@ -539,7 +649,7 @@ #define SRST_TIMER2 307 #define SRST_TIMER3 308 #define SRST_TIMER4 309 -#define SRST_TIME5 310 +#define SRST_TIMER5 310 #define SRST_P_TIMER6_11 311 #define SRST_TIMER6 312 #define SRST_TIMER7 313 @@ -555,14 +665,12 @@ #define SRST_P_GPIO3 321 #define SRST_P_GPIO4 322 #define SRST_P_GRF 323 -#define SRST_P_ALIVE_NIU 324 +#define SRST_P_ALIVE_NOC 324 #define SRST_P_WDT0 325 #define SRST_P_WDT1 326 -#define SRST_P_INTR_ARB 327 +#define SRST_P_INTR_ARB 327 #define SRST_P_UPHY0_DPTX 328 -#define SRST_P_UPHY1_DPTX 329 #define SRST_P_UPHY0_APB 330 -#define SRST_P_UPHY1_APB 331 #define SRST_P_UPHY0_TCPHY 332 #define SRST_P_UPHY1_TCPHY 333 #define SRST_P_UPHY0_TCPDCTRL 334 @@ -571,10 +679,10 @@ /* pmu soft-reset indices */ /* pmu_cru_softrst_con0 */ -#define SRST_P_NIU 0 -#define SRST_P_INTMEN 1 +#define SRST_P_NOC 0 +#define SRST_P_INTMEM 1 #define SRST_H_CM0S 2 -#define SRST_H_CM0S_NIU 3 +#define SRST_H_CM0S_NOC 3 #define SRST_DBG_CM0S 4 #define SRST_PO_CM0S 5 #define SRST_P_SPI6 6 @@ -598,7 +706,7 @@ #define SRST_P_GPIO1 24 #define SRST_P_CRU 25 #define SRST_P_INTR 26 -#define SRST_PVTM 27 +#define SRST_PVTM 27 #define SRST_I2C6 28 #define SRST_I2C7 29 #define SRST_I2C8 30