From: 林辉辉 Date: Thu, 22 Apr 2010 04:26:22 +0000 (+0000) Subject: rk2818 for linux2.6.32 X-Git-Tag: firefly_0821_release~11602 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=cb338334b977d6a8bb8e020046cb6734b835876a;p=firefly-linux-kernel-4.4.55.git rk2818 for linux2.6.32 --- diff --git a/.config b/.config new file mode 100644 index 000000000000..33d630c01c18 --- /dev/null +++ b/.config @@ -0,0 +1,1481 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.32.9 +# Tue Apr 20 14:32:55 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SWAP is not set +# CONFIG_SYSVIPC is not set +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_RT_GROUP_SCHED=y +# CONFIG_USER_SCHED is not set +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +# CONFIG_CGROUP_NS is not set +CONFIG_CGROUP_FREEZER=y +# CONFIG_CGROUP_DEVICE is not set +# CONFIG_CPUSETS is not set +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +# CONFIG_CGROUP_MEM_RES_CTLR is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_PANIC_TIMEOUT=5 +CONFIG_EMBEDDED=y +CONFIG_UID16=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +# CONFIG_ELF_CORE is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_ASHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +CONFIG_ARCH_RK2818=y + +# +# ROCKCHIP rk2818 Board Type +# +CONFIG_MACH_RK2818MID=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="mem=128M console=ttyS1,115200n8" +# CONFIG_XIP_KERNEL is not set +CONFIG_KEXEC=y +CONFIG_ATAGS_PROC=y + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +# CONFIG_BINFMT_ELF is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +CONFIG_PM_DEBUG=y +# CONFIG_PM_VERBOSE is not set +CONFIG_CAN_PM_TRACE=y +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_WAKELOCK is not set +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=y +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +# CONFIG_IP_PNP is not set +CONFIG_NET_IPIP=y +CONFIG_NET_IPGRE=y +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +CONFIG_INET_XFRM_TUNNEL=y +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_TUNNEL=y +CONFIG_INET6_TUNNEL=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=y +CONFIG_IPV6_SIT=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=y +CONFIG_IPV6_MULTIPLE_TABLES=y +# CONFIG_IPV6_SUBTREES is not set +# CONFIG_IPV6_MROUTE is not set +CONFIG_ANDROID_PARANOID_NETWORK=y +CONFIG_NETWORK_SECMARK=y +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=y +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_HFSC is not set +# CONFIG_NET_SCH_PRIO is not set +# CONFIG_NET_SCH_MULTIQ is not set +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_DRR is not set +CONFIG_NET_SCH_INGRESS=y + +# +# Classification +# +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_FW is not set +CONFIG_NET_CLS_U32=y +# CONFIG_CLS_U32_PERF is not set +# CONFIG_CLS_U32_MARK is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_CLS_CGROUP is not set +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +# CONFIG_NET_EMATCH_CMP is not set +# CONFIG_NET_EMATCH_NBYTE is not set +CONFIG_NET_EMATCH_U32=y +# CONFIG_NET_EMATCH_META is not set +# CONFIG_NET_EMATCH_TEXT is not set +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_ACT_GACT=y +# CONFIG_GACT_PROB is not set +CONFIG_NET_ACT_MIRRED=y +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_SIMP is not set +# CONFIG_NET_ACT_SKBEDIT is not set +# CONFIG_NET_CLS_IND is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +CONFIG_BT=y +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +# CONFIG_BT_BNEP_MC_FILTER is not set +# CONFIG_BT_BNEP_PROTO_FILTER is not set +CONFIG_BT_HIDP=y + +# +# Bluetooth device drivers +# +# CONFIG_BT_HCIBTSDIO is not set +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +# CONFIG_BT_HCIUART_BCSP is not set +CONFIG_BT_HCIUART_LL=y +# CONFIG_BT_HCIVHCI is not set +# CONFIG_BT_MRVL is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +CONFIG_CFG80211_DEFAULT_PS_VALUE=0 +CONFIG_WIRELESS_OLD_REGULATORY=y +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +# CONFIG_RFKILL_PM is not set +CONFIG_RFKILL_LEDS=y +# CONFIG_RFKILL_INPUT is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +CONFIG_ANDROID_PMEM=y +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +CONFIG_KERNEL_DEBUGGER_CORE=y +# CONFIG_ISL29003 is not set +CONFIG_UID_STAT=y +# CONFIG_WL127X_RFKILL is not set +# CONFIG_APANIC is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +CONFIG_MD=y +# CONFIG_BLK_DEV_MD is not set +CONFIG_BLK_DEV_DM=y +CONFIG_DM_DEBUG=y +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +CONFIG_DM_UEVENT=y +CONFIG_NETDEVICES=y +CONFIG_IFB=y +CONFIG_DUMMY=y +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +CONFIG_SMC91X=y +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +CONFIG_NETDEV_1000=y +CONFIG_NETDEV_10000=y +CONFIG_WLAN=y +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +CONFIG_PPP=y +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=y +# CONFIG_PPP_SYNC_TTY is not set +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_MPPE=y +# CONFIG_PPPOE is not set +# CONFIG_PPPOL2TP is not set +CONFIG_PPPOLAC=y +CONFIG_PPPOPNS=y +# CONFIG_SLIP is not set +CONFIG_SLHC=y +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set +CONFIG_INPUT_KEYRESET=y + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI=y +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +CONFIG_INPUT_KEYCHORD=y +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_GPIO=y + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_DEVMEM is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_DCC_TTY is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +# CONFIG_I2C_CHARDEV is not set +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_PCA963X is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_W1=y + +# +# 1-wire Bus Masters +# +CONFIG_W1_MASTER_DS2482=y + +# +# 1-wire Slaves +# +# CONFIG_W1_SLAVE_THERM is not set +# CONFIG_W1_SLAVE_SMEM is not set +# CONFIG_W1_SLAVE_DS2431 is not set +# CONFIG_W1_SLAVE_DS2433 is not set +# CONFIG_W1_SLAVE_DS2760 is not set +# CONFIG_W1_SLAVE_BQ27000 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_AB3100_CORE is not set +CONFIG_REGULATOR=y +CONFIG_REGULATOR_DEBUG=y +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_LP3971 is not set +CONFIG_REGULATOR_TPS65023=y +# CONFIG_REGULATOR_TPS6507X is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +# CONFIG_VIDEO_ALLOW_V4L1 is not set +CONFIG_VIDEO_V4L1_COMPAT=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +CONFIG_MEDIA_TUNER_CUSTOMISE=y +# CONFIG_MEDIA_TUNER_SIMPLE is not set +# CONFIG_MEDIA_TUNER_TDA8290 is not set +# CONFIG_MEDIA_TUNER_TDA827X is not set +# CONFIG_MEDIA_TUNER_TDA18271 is not set +# CONFIG_MEDIA_TUNER_TDA9887 is not set +# CONFIG_MEDIA_TUNER_TEA5761 is not set +# CONFIG_MEDIA_TUNER_TEA5767 is not set +# CONFIG_MEDIA_TUNER_MT20XX is not set +# CONFIG_MEDIA_TUNER_MT2060 is not set +# CONFIG_MEDIA_TUNER_MT2266 is not set +# CONFIG_MEDIA_TUNER_MT2131 is not set +# CONFIG_MEDIA_TUNER_QT1010 is not set +# CONFIG_MEDIA_TUNER_XC2028 is not set +# CONFIG_MEDIA_TUNER_XC5000 is not set +# CONFIG_MEDIA_TUNER_MXL5005S is not set +# CONFIG_MEDIA_TUNER_MXL5007T is not set +# CONFIG_MEDIA_TUNER_MC44S803 is not set +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_SOC_CAMERA is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_I2C_SI4713 is not set +# CONFIG_RADIO_SI4713 is not set +# CONFIG_RADIO_SI470X is not set +# CONFIG_RADIO_TEA5764 is not set +CONFIG_DAB=y + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=y +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_LOGO is not set +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +# CONFIG_HID_APPLE is not set +# CONFIG_HID_WACOM is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=500 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +CONFIG_USB_GADGET_R8A66597=y +CONFIG_USB_R8A66597=y +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +CONFIG_USB_ANDROID=y +# CONFIG_USB_ANDROID_ACM is not set +CONFIG_USB_ANDROID_ADB=y +CONFIG_USB_ANDROID_MASS_STORAGE=y +CONFIG_USB_ANDROID_RNDIS=y +CONFIG_USB_ANDROID_RNDIS_WCEIS=y +# CONFIG_USB_CDC_COMPOSITE is not set + +# +# OTG and related infrastructure +# +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_EMBEDDED_SDIO=y +CONFIG_MMC_PARANOID_SD_INIT=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +CONFIG_MMC_BLOCK_DEFERRED_RESUME=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_AT91 is not set +# CONFIG_MMC_ATMELMCI is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_BD2802 is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set + +# +# iptables trigger is under Netfilter config (LED target) +# +CONFIG_SWITCH=y +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +# CONFIG_RTC_INTF_SYSFS is not set +# CONFIG_RTC_INTF_PROC is not set +# CONFIG_RTC_INTF_DEV is not set +CONFIG_RTC_INTF_ALARM=y +CONFIG_RTC_INTF_ALARM_DEV=y +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +CONFIG_STAGING=y +# CONFIG_STAGING_EXCLUDE_BUILD is not set +# CONFIG_ECHO is not set + +# +# Android +# +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_LOGGER=y +CONFIG_ANDROID_RAM_CONSOLE=y +CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y +CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y +CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_DATA_SIZE=128 +CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_ECC_SIZE=16 +CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE=8 +CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_POLYNOMIAL=0x11d +# CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT is not set +CONFIG_ANDROID_TIMED_OUTPUT=y +CONFIG_ANDROID_LOW_MEMORY_KILLER=y + +# +# Qualcomm MSM Camera And Video +# + +# +# Camera Sensor Selection +# +# CONFIG_DST is not set +# CONFIG_POHMELFS is not set +# CONFIG_PLAN9AUTH is not set + +# +# RAR Register Driver +# +# CONFIG_RAR_REGISTER is not set +# CONFIG_IIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +# CONFIG_SCHED_DEBUG is not set +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_SPINLOCK_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ICEDCC is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_REED_SOLOMON=y +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/Makefile b/Makefile index ec932b2155b5..dfdd53c9c678 100644 --- a/Makefile +++ b/Makefile @@ -180,8 +180,11 @@ SUBARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \ # Default value for CROSS_COMPILE is not to prefix executables # Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile export KBUILD_BUILDHOST := $(SUBARCH) -ARCH ?= $(SUBARCH) -CROSS_COMPILE ?= +#ARCH ?= $(SUBARCH) +#CROSS_COMPILE ?= +ARCH ?= arm +#CROSS_COMPILE :=/opt/android0320/mydroid/prebuilt/linux-x86/toolchain/arm-eabi-4.2.1/bin/arm-eabi- +CROSS_COMPILE ?=../toolchain/arm-eabi-4.2.1/bin/arm-eabi- # Architecture as present in compile.h UTS_MACHINE := $(ARCH) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1c4119c60040..4c21765ecb71 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -701,6 +701,15 @@ config ARCH_BCMRING select ARCH_WANT_OPTIONAL_GPIOLIB help Support for Broadcom's BCMRing platform. +config ARCH_RK2818 + bool "Rockchip soc rk2818" + select CPU_ARM926T + select CPU_CP15_MMU + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + help + Support for Rockchip RK2818 soc. + endchoice @@ -803,6 +812,7 @@ source "arch/arm/mach-u300/Kconfig" source "arch/arm/mach-w90x900/Kconfig" source "arch/arm/mach-bcmring/Kconfig" +source "arch/arm/mach-rk2818/Kconfig" # Definitions to make life easier config ARCH_ACORN diff --git a/arch/arm/Makefile b/arch/arm/Makefile index a73caaf66763..49d1e52b8576 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -170,6 +170,7 @@ machine-$(CONFIG_ARCH_VERSATILE) := versatile machine-$(CONFIG_ARCH_W90X900) := w90x900 machine-$(CONFIG_FOOTBRIDGE) := footbridge machine-$(CONFIG_ARCH_MXC91231) := mxc91231 +machine-$(CONFIG_ARCH_RK2818) := rk2818 # Platform directory name. This list is sorted alphanumerically # by CONFIG_* macro name. diff --git a/arch/arm/mach-rk2818/Kconfig b/arch/arm/mach-rk2818/Kconfig new file mode 100644 index 000000000000..e12193100199 --- /dev/null +++ b/arch/arm/mach-rk2818/Kconfig @@ -0,0 +1,13 @@ +if ARCH_RK2818 + +comment "ROCKCHIP rk2818 Board Type" + depends on ARCH_RK2818 + +config MACH_RK2818MID + depends on ARCH_RK2818 + default y + bool "ROCKCHIP Board For Mid" + help + Support for the ROCKCHIP Board For Rk2818 Mid. + +endif diff --git a/arch/arm/mach-rk2818/Makefile b/arch/arm/mach-rk2818/Makefile new file mode 100644 index 000000000000..f1000ca5146d --- /dev/null +++ b/arch/arm/mach-rk2818/Makefile @@ -0,0 +1,8 @@ +obj-y += io.o idle.o irq.o timer.o +obj-y += devices.o +obj-y += proc_comm.o +obj-y += vreg.o +obj-y += clock.o clock-rk2818.o + +obj-$(CONFIG_MACH_RK2818MID) += board-midsdk.o + diff --git a/arch/arm/mach-rk2818/Makefile.boot b/arch/arm/mach-rk2818/Makefile.boot new file mode 100644 index 000000000000..24dfbf8c07c4 --- /dev/null +++ b/arch/arm/mach-rk2818/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x10008000 +params_phys-y := 0x10000100 +initrd_phys-y := 0x10800000 diff --git a/arch/arm/mach-rk2818/board-midsdk.c b/arch/arm/mach-rk2818/board-midsdk.c new file mode 100644 index 000000000000..cf8d509b848c --- /dev/null +++ b/arch/arm/mach-rk2818/board-midsdk.c @@ -0,0 +1,106 @@ +/* linux/arch/arm/mach-rk2818/board-midsdk.c + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "devices.h" +//IOÓ³É䷽ʽÃèÊö £¬Ã¿¸öΪһ¶ÎÏßÐÔÁ¬ÐøÓ³Éä +static struct map_desc rk2818_io_desc[] __initdata = { + + { + .virtual = RK2818_AHB_BASE, //ÐéÄâµØÖ· + .pfn = __phys_to_pfn(RK2818_AHB_PHYS), //ÎïÀíµØÖ·£¬ÐëÓëÒ³±í¶ÔÆë + .length = RK2818_AHB_SIZE, //³¤¶È + .type = MT_DEVICE //Ó³É䷽ʽ + }, + + { + .virtual = RK2818_APB_BASE, + .pfn = __phys_to_pfn(RK2818_APB_PHYS), + .length = RK2818_APB_SIZE, + .type = MT_DEVICE + }, + + { + .virtual = RK2818_DSP_BASE, + .pfn = __phys_to_pfn(RK2818_DSP_PHYS), + .length = RK2818_DSP_SIZE, + .type = MT_DEVICE + }, + + { + .virtual = 0xff400000, /* for itcm , vir = phy , for reboot */ + .pfn = __phys_to_pfn(0xff400000), + .length = SZ_16K, + .type = MT_DEVICE + } + +}; + +static struct platform_device *devices[] __initdata = { + //&rk2818_add_device_serial, +}; + +extern struct sys_timer rk2818_timer; + +static void __init machine_rk2818_init_irq(void) +{ + rk2818_init_irq(); +} + +static void __init machine_rk2818_board_init(void) +{ + platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +static void __init machine_rk2818_mapio(void) +{ + iotable_init(rk2818_io_desc, ARRAY_SIZE(rk2818_io_desc)); + rk2818_clock_init(); + //rk2818_iomux_init(); + +/* Setup the serial ports and console*/ + // rk2818_init_serial(&rk2818_uart_config); +} + +MACHINE_START(RK2818, "rk2818midsdk") + +/* UART for LL DEBUG */ + .phys_io = 0x18002000, + .io_pg_offst = ((0xFF100000) >> 18) & 0xfffc, + .boot_params = RK2818_SDRAM_PHYS + 0x100, + .map_io = machine_rk2818_mapio, + .init_irq = machine_rk2818_init_irq, + .init_machine = machine_rk2818_board_init, + .timer = &rk2818_timer, +MACHINE_END diff --git a/arch/arm/mach-rk2818/clock-rk2818.c b/arch/arm/mach-rk2818/clock-rk2818.c new file mode 100644 index 000000000000..5010e0693c08 --- /dev/null +++ b/arch/arm/mach-rk2818/clock-rk2818.c @@ -0,0 +1,111 @@ +/* arch/arm/mach-rk2818/clock-rk2818.c + * + * + * Copyright (C) 2010 Rockchip, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include + +#include "clock.h" +#include "devices.h" + +/* clock IDs used by the modem processor */ + +#define ACPU_CLK 0 /* Applications processor clock */ +#define ADM_CLK 1 /* Applications data mover clock */ +#define ADSP_CLK 2 /* ADSP clock */ +#define EBI1_CLK 3 /* External bus interface 1 clock */ +#define EBI2_CLK 4 /* External bus interface 2 clock */ +#define ECODEC_CLK 5 /* External CODEC clock */ +#define EMDH_CLK 6 /* External MDDI host clock */ +#define GP_CLK 7 /* General purpose clock */ +#define GRP_CLK 8 /* Graphics clock */ +#define I2C_CLK 9 /* I2C clock */ +#define ICODEC_RX_CLK 10 /* Internal CODEX RX clock */ +#define ICODEC_TX_CLK 11 /* Internal CODEX TX clock */ +#define IMEM_CLK 12 /* Internal graphics memory clock */ +#define MDC_CLK 13 /* MDDI client clock */ +#define MDP_CLK 14 /* Mobile display processor clock */ +#define PBUS_CLK 15 /* Peripheral bus clock */ +#define PCM_CLK 16 /* PCM clock */ +#define PMDH_CLK 17 /* Primary MDDI host clock */ +#define SDAC_CLK 18 /* Stereo DAC clock */ +#define SDC1_CLK 19 /* Secure Digital Card clocks */ +#define SDC1_PCLK 20 +#define SDC2_CLK 21 +#define SDC2_PCLK 22 +#define SDC3_CLK 23 +#define SDC3_PCLK 24 +#define SDC4_CLK 25 +#define SDC4_PCLK 26 +#define TSIF_CLK 27 /* Transport Stream Interface clocks */ +#define TSIF_REF_CLK 28 +#define TV_DAC_CLK 29 /* TV clocks */ +#define TV_ENC_CLK 30 +#define UART1_CLK 31 /* UART clocks */ +#define UART2_CLK 32 +#define UART3_CLK 33 +#define UART1DM_CLK 34 +#define UART2DM_CLK 35 +#define USB_HS_CLK 36 /* High speed USB core clock */ +#define USB_HS_PCLK 37 /* High speed USB pbus clock */ +#define USB_OTG_CLK 38 /* Full speed USB clock */ +#define VDC_CLK 39 /* Video controller clock */ +#define VFE_CLK 40 /* Camera / Video Front End clock */ +#define VFE_MDC_CLK 41 /* VFE MDDI client clock */ + +#define NR_CLKS 42 + +#define CLOCK(clk_name, clk_id, clk_dev, clk_flags) { \ + .name = clk_name, \ + .id = clk_id, \ + .flags = clk_flags, \ + .dev = clk_dev, \ + } + +#define OFF CLKFLAG_AUTO_OFF +#define MINMAX CLKFLAG_USE_MIN_MAX_TO_SET + +struct clk rk2818_clocks[] = { + CLOCK("adm_clk", ADM_CLK, NULL, 0), + CLOCK("adsp_clk", ADSP_CLK, NULL, 0), + CLOCK("ebi1_clk", EBI1_CLK, NULL, 0), + CLOCK("ebi2_clk", EBI2_CLK, NULL, 0), + CLOCK("ecodec_clk", ECODEC_CLK, NULL, 0), + CLOCK("emdh_clk", EMDH_CLK, NULL, OFF), + CLOCK("gp_clk", GP_CLK, NULL, 0), + CLOCK("grp_clk", GRP_CLK, NULL, OFF), + CLOCK("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0), + CLOCK("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0), + CLOCK("imem_clk", IMEM_CLK, NULL, OFF), + CLOCK("mdc_clk", MDC_CLK, NULL, 0), + CLOCK("mdp_clk", MDP_CLK, NULL, OFF), + CLOCK("pbus_clk", PBUS_CLK, NULL, 0), + CLOCK("pcm_clk", PCM_CLK, NULL, 0), + CLOCK("pmdh_clk", PMDH_CLK, NULL, OFF | MINMAX), + CLOCK("sdac_clk", SDAC_CLK, NULL, OFF), + CLOCK("tsif_clk", TSIF_CLK, NULL, 0), + CLOCK("tsif_ref_clk", TSIF_REF_CLK, NULL, 0), + CLOCK("tv_dac_clk", TV_DAC_CLK, NULL, 0), + CLOCK("tv_enc_clk", TV_ENC_CLK, NULL, 0), + ///CLOCK("uart_clk", UART1_CLK, &rk2818_device_uart1.dev, OFF), + CLOCK("uart1dm_clk", UART1DM_CLK, NULL, OFF), + CLOCK("uart2dm_clk", UART2DM_CLK, NULL, 0), + CLOCK("usb_otg_clk", USB_OTG_CLK, NULL, 0), + CLOCK("vdc_clk", VDC_CLK, NULL, OFF | MINMAX), + CLOCK("vfe_clk", VFE_CLK, NULL, OFF), + CLOCK("vfe_mdc_clk", VFE_MDC_CLK, NULL, OFF), +}; + +unsigned rk2818_num_clocks = ARRAY_SIZE(rk2818_clocks); diff --git a/arch/arm/mach-rk2818/clock.c b/arch/arm/mach-rk2818/clock.c new file mode 100644 index 000000000000..01c1cedf945c --- /dev/null +++ b/arch/arm/mach-rk2818/clock.c @@ -0,0 +1,217 @@ +/* arch/arm/mach-rk2818/clock.c + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clock.h" +#include "proc_comm.h" + +static DEFINE_MUTEX(clocks_mutex); +static DEFINE_SPINLOCK(clocks_lock); +static LIST_HEAD(clocks); + +/* + * glue for the proc_comm interface + */ +static inline int pc_clk_enable(unsigned id) +{ + return rk2818_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL); +} + +static inline void pc_clk_disable(unsigned id) +{ + rk2818_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL); +} + +static inline int pc_clk_set_rate(unsigned id, unsigned rate) +{ + return rk2818_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate); +} + +static inline int pc_clk_set_min_rate(unsigned id, unsigned rate) +{ + return rk2818_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate); +} + +static inline int pc_clk_set_max_rate(unsigned id, unsigned rate) +{ + return rk2818_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate); +} + +static inline int pc_clk_set_flags(unsigned id, unsigned flags) +{ + return rk2818_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags); +} + +static inline unsigned pc_clk_get_rate(unsigned id) +{ + if (rk2818_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL)) + return 0; + else + return id; +} + +static inline unsigned pc_clk_is_enabled(unsigned id) +{ + if (rk2818_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL)) + return 0; + else + return id; +} + +static inline int pc_pll_request(unsigned id, unsigned on) +{ + on = !!on; + return rk2818_proc_comm(PCOM_CLKCTL_RPC_PLL_REQUEST, &id, &on); +} + +/* + * Standard clock functions defined in include/linux/clk.h + */ +struct clk *clk_get(struct device *dev, const char *id) +{ + struct clk *clk; + + mutex_lock(&clocks_mutex); + + list_for_each_entry(clk, &clocks, list) + if (!strcmp(id, clk->name) && clk->dev == dev) + goto found_it; + + list_for_each_entry(clk, &clocks, list) + if (!strcmp(id, clk->name) && clk->dev == NULL) + goto found_it; + + clk = ERR_PTR(-ENOENT); +found_it: + mutex_unlock(&clocks_mutex); + return clk; +} +EXPORT_SYMBOL(clk_get); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); + +int clk_enable(struct clk *clk) +{ + unsigned long flags; + spin_lock_irqsave(&clocks_lock, flags); + clk->count++; + if (clk->count == 1) + pc_clk_enable(clk->id); + spin_unlock_irqrestore(&clocks_lock, flags); + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ + unsigned long flags; + spin_lock_irqsave(&clocks_lock, flags); + BUG_ON(clk->count == 0); + clk->count--; + if (clk->count == 0) + pc_clk_disable(clk->id); + spin_unlock_irqrestore(&clocks_lock, flags); +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return pc_clk_get_rate(clk->id); +} +EXPORT_SYMBOL(clk_get_rate); + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + int ret; + if (clk->flags & CLKFLAG_USE_MIN_MAX_TO_SET) { + ret = pc_clk_set_max_rate(clk->id, rate); + if (ret) + return ret; + return pc_clk_set_min_rate(clk->id, rate); + } + return pc_clk_set_rate(clk->id, rate); +} +EXPORT_SYMBOL(clk_set_rate); + +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + return -ENOSYS; +} +EXPORT_SYMBOL(clk_set_parent); + +struct clk *clk_get_parent(struct clk *clk) +{ + return ERR_PTR(-ENOSYS); +} +EXPORT_SYMBOL(clk_get_parent); + +int clk_set_flags(struct clk *clk, unsigned long flags) +{ + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + return pc_clk_set_flags(clk->id, flags); +} +EXPORT_SYMBOL(clk_set_flags); + + +void __init rk2818_clock_init(void) +{ + unsigned n; + + spin_lock_init(&clocks_lock); + mutex_lock(&clocks_mutex); + for (n = 0; n < rk2818_num_clocks; n++) + list_add_tail(&rk2818_clocks[n].list, &clocks); + mutex_unlock(&clocks_mutex); +} + +/* The bootloader and/or AMSS may have left various clocks enabled. + * Disable any clocks that belong to us (CLKFLAG_AUTO_OFF) but have + * not been explicitly enabled by a clk_enable() call. + */ +static int __init clock_late_init(void) +{ + unsigned long flags; + struct clk *clk; + unsigned count = 0; + + mutex_lock(&clocks_mutex); + list_for_each_entry(clk, &clocks, list) { + if (clk->flags & CLKFLAG_AUTO_OFF) { + spin_lock_irqsave(&clocks_lock, flags); + if (!clk->count) { + count++; + pc_clk_disable(clk->id); + } + spin_unlock_irqrestore(&clocks_lock, flags); + } + } + mutex_unlock(&clocks_mutex); + pr_info("clock_late_init() disabled %d unused clocks\n", count); + return 0; +} + +late_initcall(clock_late_init); diff --git a/arch/arm/mach-rk2818/clock.h b/arch/arm/mach-rk2818/clock.h new file mode 100644 index 000000000000..4059b10090ba --- /dev/null +++ b/arch/arm/mach-rk2818/clock.h @@ -0,0 +1,47 @@ +/* arch/arm/mach-rk2818/clock.h + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ARCH_ARM_MACH_RK2818_CLOCK_H +#define __ARCH_ARM_MACH_RK2818_CLOCK_H + +#include + +#define CLKFLAG_INVERT 0x00000001 +#define CLKFLAG_NOINVERT 0x00000002 +#define CLKFLAG_NONEST 0x00000004 +#define CLKFLAG_NORESET 0x00000008 + +#define CLK_FIRST_AVAILABLE_FLAG 0x00000100 +#define CLKFLAG_USE_MIN_MAX_TO_SET 0x00000200 +#define CLKFLAG_AUTO_OFF 0x00000400 + +struct clk { + uint32_t id; + uint32_t count; + uint32_t flags; + const char *name; + struct list_head list; + struct device *dev; +}; + +//#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100) +//#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104) +//#define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124) + +extern struct clk rk2818_clocks[]; +extern unsigned rk2818_num_clocks; + +#endif + diff --git a/arch/arm/mach-rk2818/devices.c b/arch/arm/mach-rk2818/devices.c new file mode 100644 index 000000000000..44e57d826170 --- /dev/null +++ b/arch/arm/mach-rk2818/devices.c @@ -0,0 +1,48 @@ +/* arch/arm/mach-rk2818/devices.c + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include + +#include +#include +#include "devices.h" + +#include +#include +#include + +static struct resource resources_uart1[] = { + { + .start = IRQ_NR_UART1,//INT_UART1, + .end = IRQ_NR_UART1,//INT_UART1, + .flags = IORESOURCE_IRQ, + }, + { + .start = RK2818_UART1_PHYS, + .end = RK2818_UART1_PHYS + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, +}; + + +struct platform_device msm_device_uart1 = { + .name = "rk2818_serial", + .id = 0, + .num_resources = ARRAY_SIZE(resources_uart1), + .resource = resources_uart1, +}; + + diff --git a/arch/arm/mach-rk2818/devices.h b/arch/arm/mach-rk2818/devices.h new file mode 100644 index 000000000000..9228e5398aaa --- /dev/null +++ b/arch/arm/mach-rk2818/devices.h @@ -0,0 +1,22 @@ +/* linux/arch/arm/mach-rk2818/devices.h + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ARCH_ARM_MACH_RK2818_DEVICES_H +#define __ARCH_ARM_MACH_RK2818_DEVICES_H + +extern struct platform_device rk2818_device_uart1; + + +#endif diff --git a/arch/arm/mach-rk2818/idle.S b/arch/arm/mach-rk2818/idle.S new file mode 100644 index 000000000000..4cc2c11aab91 --- /dev/null +++ b/arch/arm/mach-rk2818/idle.S @@ -0,0 +1,35 @@ +/* arch/arm/mach-rk2818/include/mach/idle.S + * + * Idle processing for MSM7K - work around bugs with SWFI. + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include + +ENTRY(arch_idle) +#ifdef CONFIG_RK2818_IDLE + mrc p15, 0, r1, c1, c0, 0 /* read current CR */ + bic r0, r1, #(1 << 2) /* clear dcache bit */ + bic r0, r0, #(1 << 12) /* clear icache bit */ + mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */ + + mov r0, #0 /* prepare wfi value */ + mcr p15, 0, r0, c7, c10, 0 /* flush the cache */ + mcr p15, 0, r0, c7, c10, 4 /* memory barrier */ + mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */ + + mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */ +#endif + mov pc, lr diff --git a/arch/arm/mach-rk2818/include/mach/board.h b/arch/arm/mach-rk2818/include/mach/board.h new file mode 100644 index 000000000000..e21c023c7418 --- /dev/null +++ b/arch/arm/mach-rk2818/include/mach/board.h @@ -0,0 +1,37 @@ +/* arch/arm/mach-rk2818/include/mach/board.h + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_RK2818_BOARD_H +#define __ASM_ARCH_RK2818_BOARD_H + +#include + +/* platform device data structures */ + +struct RK2818_mddi_platform_data +{ + void (*panel_power)(int on); + unsigned has_vsync_irq:1; +}; + +/* common init routines for use by arch/arm/mach-msm/board-*.c */ + +void __init rk2818_add_devices(void); +void __init rk2818_map_common_io(void); +void __init rk2818_init_irq(void); +void __init rk2818_init_gpio(void); +void __init rk2818_clock_init(void); + +#endif diff --git a/arch/arm/mach-rk2818/include/mach/debug-macro.S b/arch/arm/mach-rk2818/include/mach/debug-macro.S new file mode 100644 index 000000000000..b29c353ed427 --- /dev/null +++ b/arch/arm/mach-rk2818/include/mach/debug-macro.S @@ -0,0 +1,39 @@ +/* arch/arm/mach-rk2818/include/mach/debug-macro.S + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include + + .macro addruart,rx + @ see if the MMU is enabled and select appropriate base address + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 + ldreq \rx, =RK2818_UART1_PHYS + ldrne \rx, =RK2818_UART1_BASE + .endm + + .macro senduart,rd,rx + str \rd, [\rx, #0x00] + .endm + + .macro waituart,rd,rx + @ wait for TX_READY +1: ldr \rd, [\rx, #0x7C] + tst \rd, #0x02 + beq 1b + .endm + + .macro busyuart,rd,rx + .endm diff --git a/arch/arm/mach-rk2818/include/mach/dma.h b/arch/arm/mach-rk2818/include/mach/dma.h new file mode 100644 index 000000000000..8612af837945 --- /dev/null +++ b/arch/arm/mach-rk2818/include/mach/dma.h @@ -0,0 +1,209 @@ +/* + * arch/arm/mach-rk2818/include/mach/dma.h + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_RK2818_DMA_H +#define __ASM_RK2818_DMA_H + +#include + + +#define SAR 0x000 /* Source Address Register */ +#define DAR 0x008 /* Destination Address Register */ +#define LLP 0x010 /* Linked List Pointer Register */ +#define CTL_L 0x018 /* Control Register LOW */ +#define CTL_H 0x01C /* Control Register HIGH */ +#define CFG_L 0x040 /* Configuration Register */ +#define CFG_H 0x044 /* Configuration Register */ +#define SGR 0x048 /* Source Gather Register */ +#define DSR 0x050 /* Destination Scatter Register */ + +#define RawTfr 0x2c0 /* Raw Status for IntTfr Interrupt */ +#define RawBlock 0x2c8 /* Raw Status for IntBlock Interrupt */ +#define RawSrcTran 0x2d0 /* Raw Status for IntSrcTran Interrupt */ +#define RawDstTran 0x2d8 /* Raw Status for IntDstTran Interrupt */ +#define RawErr 0x2e0 /* Raw Status for IntErr Interrupt */ + +#define StatusTfr 0x2e8 /* Status for IntTfr Interrupt */ +#define StatusBlock 0x2f0 /* Status for IntBlock Interrupt */ +#define StatusSrcTran 0x2f8 /* Status for IntSrcTran Interrupt */ +#define StatusDstTran 0x300 /* Status for IntDstTran Interrupt */ +#define StatusErr 0x308 /* Status for IntErr Interrupt */ + +#define MaskTfr 0x310 /*Mask for IntTfr Interrupt */ +#define MaskBlock 0x318 /*Mask for IntBlock Interrupt */ +#define MaskSrcTran 0x320 /*Mask for IntSrcTran Interrupt */ +#define MaskDstTran 0x328 /*Mask for IntDstTran Interrupt */ +#define MaskErr 0x330 /*Mask for IntErr Interrupt */ + +#define ClearTfr 0x338 /* Clear for IntTfr Interrupt */ +#define ClearBlock 0x340 /* Clear for IntBlock Interrupt */ +#define ClearSrcTran 0x348 /* Clear for IntSrcTran Interrupt */ +#define ClearDstTran 0x350 /* Clear for IntDstTran Interrupt */ +#define ClearErr 0x358 /* Clear for IntErr Interrupt */ +#define StatusInt 0x360 /* Status for each interrupt type */ + +#define DmaCfgReg 0x398 /* DMA Configuration Register */ +#define ChEnReg 0x3a0 /* DMA Channel Enable Register */ + +/* Detail CFG_L Register Description */ +#define CH_PRIOR_MASK (0x7 << 5) +#define CH_PRIOR_OFFSET 5 +#define CH_SUSP (0x1 << 8) +#define FIFO_EMPTY (0x1 << 9) +#define HS_SEL_DST (0x1 << 10) +#define HS_SEL_SRC (0x1 << 11) +#define LOCK_CH_L_MASK (0x3 << 12) +#define LOCK_CH_L_OFFSET 12 +#define LOCK_B_L_MASK (0x3 << 14) +#define LOCK_B_L_OFFSET 14 +#define LOCK_CH (0x1 << 16) +#define LOCK_B (0x1 << 17) +#define DST_HS_POL (0x1 << 18) +#define SRC_HS_POL (0x1 << 19) +#define MAX_ABRST_MASK (0x3FF << 20) +#define MAX_ABRST_OFFSET 20 +#define RELOAD_SRC (0x1 << 30) +#define RELOAD_DST (0x1 << 31) + +/* Detail CFG_H Register Description */ +#define FCMODE (0x1 << 0) +#define FIFO_MODE (0x1 << 1) +#define PROTCTL_MASK (0x7 << 2) +#define PROTCTL_OFFSET 2 +#define DS_UPD_EN (0x1 << 5) +#define SS_UPD_EN (0x1 << 6) +#define SRC_PER_MASK (0xF << 7) +#define SRC_PER_OFFSET 7 +#define DST_PER_MASK (0xF << 11) +#define DST_PER_OFFSET 11 + +/* Detail CTL_L Register Description */ +#define INT_EN (0x1 << 0) +#define DST_TR_WIDTH_MASK (0x7 << 1) +#define DST_TR_WIDTH_OFFSET 1 +#define SRC_TR_WIDTH_MASK (0x7 << 4) +#define SRC_TR_WIDTH_OFFSET 4 +#define DINC_MASK (0x3 << 7) +#define DINC_OFFSET 7 +#define SINC_MASK (0x3 << 9) +#define SINC_OFFSET 9 +#define DST_MSIZE_MASK (0x7 << 11) +#define DST_MSIZE_OFFSET 11 +#define SRC_MSIZE_MASK (0x7 << 14) +#define SRC_MSIZE_OFFSET 14 +#define SRC_GATHER_EN (0x1 << 17) +#define DST_SCATTER_EN (0x1 << 18) +#define TT_FC_MASK (0x7 << 20) +#define TT_FC_OFFSET 20 +#define DMS_MASK (0x3 << 23) +#define DMS_OFFSET 23 +#define SMS_MASK (0x3 << 25) +#define SMS_OFFSET 25 +#define LLP_DST_EN (0x1 << 27) +#define LLP_SRC_EN (0x1 << 28) + +#define AHBMASTER_1 0x0 +#define AHBMASTER_2 0x1 + +#define INCREMENT 0x0 +#define DECREMENT 0x1 +#define NOCHANGE 0x2 + +#define MSIZE_1 0x0 +#define MSIZE_4 0x1 +#define MSIZE_8 0x2 +#define MSIZE_16 0x3 +#define MSIZE_32 0x4 + +#define TR_WIDTH_8 0x0 +#define TR_WIDTH_16 0x1 +#define TR_WIDTH_32 0x2 + +#define M2M 0x0 +#define M2P 0x1 +#define P2M 0x2 +#define P2P 0x3 + +/* Detail ChEnReg Register Description */ +#define CH_EN_MASK (0xF << 0) +#define CH_EN_OFFSET 0 +#define CH_EN_WE_MASK (0xF << 8) +#define CH_EN_WE_OFFSET 8 + + +/* Detail DmaCfgReg Register Description */ +#define DMA_EN (0x1 << 0) + + +#define ROCKCHIP_DMA_CHANNELS 3 +typedef enum { + DMA_PRIO_HIGH = 0, + DMA_PRIO_MEDIUM = 1, + DMA_PRIO_LOW = 2 +} rockchip_dma_prio; + +struct rockchip_dma_channel { + const char *name; + void (*irq_handler) (int, void *); + void (*err_handler) (int, void *, int errcode); + void *data; + unsigned int dma_mode; + struct scatterlist *sg; + unsigned int sgbc; + unsigned int sgcount; + unsigned int resbytes; + dma_addr_t LLI; + void *dma_vaddr; + unsigned int curLLI; + unsigned int lli_count; + int dma_num; + unsigned int channel_base; +}; + +struct LLI_INFO { + unsigned int SARx; + unsigned int DARx; + unsigned int LLPx; + unsigned int CTL_Lx; + unsigned int CTL_Hx; +// unsigned int SSATx; +// unsigned int DSATx; +}; + +extern struct rockchip_dma_channel rockchip_dma_channels[ROCKCHIP_DMA_CHANNELS]; + +int rockchip_dma_setup_single(int dma_ch, dma_addr_t dma_address, + unsigned int dma_length, unsigned int dev_addr, + unsigned int dmamode); + +int rockchip_dma_setup_sg(int dma_ch, + struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length, + unsigned int dev_addr, unsigned int dmamode); + +int rockchip_dma_setup_handlers(int dma_ch, + void (*irq_handler) (int, void *), + void (*err_handler) (int, void *, int), void *data); + +void rockchip_dma_enable(int dma_ch); + +void rockchip_dma_disable(int dma_ch); + +int rockchip_dma_request(int dma_ch, const char *name); + +void rockchip_dma_free(int dma_ch); + +int rockchip_dma_request_by_prio(const char *name, rockchip_dma_prio prio); + +#endif diff --git a/arch/arm/mach-rk2818/include/mach/entry-macro.S b/arch/arm/mach-rk2818/include/mach/entry-macro.S new file mode 100644 index 000000000000..765e0b95def6 --- /dev/null +++ b/arch/arm/mach-rk2818/include/mach/entry-macro.S @@ -0,0 +1,53 @@ +/* arch/arm/mach-rk2818/include/mach/entry-macro.S + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "irqs.h" + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base,=0xff0aa000 + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp +1001: + ldr \irqstat, [\base, #IRQ_REG_FINALSTATUS_L] + cmp \irqstat, #0 + beq 1002f + + clz \irqnr, \irqstat + rsb \irqnr, \irqnr, #31 + b 1003f + +1002: + ldr \irqstat, [\base, #IRQ_REG_FINALSTATUS_H] + lsr \tmp, \irqstat, #8 + and \tmp, \tmp, #0xff + lsl \tmp, \tmp, #8 + and \irqstat, \irqstat, #0xff + orr \irqstat, \irqstat, \tmp + + cmp \irqstat, #0 + beq 1003f + + clz \irqnr, \irqstat + rsb \irqnr, \irqnr, #31 + add \irqnr, \irqnr, #32 +1003: + .endm diff --git a/arch/arm/mach-rk2818/include/mach/hardware.h b/arch/arm/mach-rk2818/include/mach/hardware.h new file mode 100644 index 000000000000..0a94f7c90a99 --- /dev/null +++ b/arch/arm/mach-rk2818/include/mach/hardware.h @@ -0,0 +1,25 @@ +/* arch/arm/mach-rk2818/include/mach/hardware.h + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_RK2818_HARDWARE_H + + +#ifndef __ASSEMBLY__ +# define __REG(x) (*((volatile u32 *)IO_ADDRESS(x))) + +# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) +#endif + +#endif diff --git a/arch/arm/mach-rk2818/include/mach/io.h b/arch/arm/mach-rk2818/include/mach/io.h new file mode 100644 index 000000000000..87ea8857d541 --- /dev/null +++ b/arch/arm/mach-rk2818/include/mach/io.h @@ -0,0 +1,33 @@ +/* arch/arm/mach-rk2818/include/mach/io.h + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __arch_ioremap __rk2818_ioremap +#define __arch_iounmap __iounmap + +void __iomem *__rk2818_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype); + +static inline void __iomem *__io(unsigned long addr) +{ + return (void __iomem *)addr; +} +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#endif diff --git a/arch/arm/mach-rk2818/include/mach/irqs.h b/arch/arm/mach-rk2818/include/mach/irqs.h new file mode 100644 index 000000000000..52cdef1b0fc8 --- /dev/null +++ b/arch/arm/mach-rk2818/include/mach/irqs.h @@ -0,0 +1,99 @@ +/* arch/arm/mach-rk2818/include/mach/irqs.h + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + + +#ifndef __ARCH_ARM_MACH_RK2818_IRQS_H +#define __ARCH_ARM_MACH_RK2818_IRQS_H + + + +#define IRQ_REG_INTEN_L 0x00//IRQ interrupt source enable register (low) +#define IRQ_REG_INTEN_H 0x04//IRQ interrupt source enable register (high) +#define IRQ_REG_INTMASK_L 0x08//IRQ interrupt source mask register (low). +#define IRQ_REG_INTMASK_H 0x0c//IRQ interrupt source mask register (high). +#define IRQ_REG_INTFORCE_L 0x10//IRQ interrupt force register +#define IRQ_REG_INTFORCE_H 0x14// +#define IRQ_REG_RAWSTATUS_L 0x18//IRQ raw status register +#define IRQ_REG_RAWSTATUS_H 0x1c// +#define IRQ_REG_STATUS_L 0x20//IRQ status register +#define IRQ_REG_STATUS_H 0x24// +#define IRQ_REG_MASKSTATUS_L 0x28//IRQ interrupt mask status register +#define IRQ_REG_MASKSTATUS_H 0x2c// +#define IRQ_REG_FINALSTATUS_L 0x30//IRQ interrupt final status +#define IRQ_REG_FINALSTATUS_H 0x34 +#define FIQ_REG_INTEN 0xc0//Fast interrupt enable register +#define FIQ_REG_INTMASK 0xc4//Fast interrupt mask register +#define FIQ_REG_INTFORCE 0xc8//Fast interrupt force register +#define FIQ_REG_RAWSTATUS 0xcc//Fast interrupt source raw status register +#define FIQ_REG_STATUS 0xd0//Fast interrupt status register +#define FIQ_REG_FINALSTATUS 0xd4//Fast interrupt final status register +#define IRQ_REG_PLEVEL 0xd8//IRQ System Priority Level Register + + +#define NR_IRQS (48) + + +/*irq number*/ +#define IRQ_NR_DWDMA 0 // -- low +#define IRQ_NR_HOST 1 // -- Host Interface +#define IRQ_NR_NANDC 2 +#define IRQ_NR_LCDC 3 +#define IRQ_NR_SDMMC0 4 +#define IRQ_NR_VIP 5 +#define IRQ_NR_GPIO0 6 +#define IRQ_NR_GPIO1 7 +#define IRQ_NR_OTG 8 // -- USB OTG +#define IRQ_NR_ABTARMD 9 // -- Arbiter in ARMD BUS +#define IRQ_NR_ABTEXP 10//-- Arbiter in EXP BUS +#define IRQ_NR_I2C0 11 +#define IRQ_NR_I2C1 12 +#define IRQ_NR_I2S 13 +#define IRQ_NR_SPIM 14// -- SPI Master +#define IRQ_NR_SPIS 15//-- SPI Slave +#define IRQ_NR_TIMER1 16 +#define IRQ_NR_TIMER2 17 +#define IRQ_NR_TIMER3 18 +#define IRQ_NR_UART0 19 +#define IRQ_NR_UART1 20 +#define IRQ_NR_WDT 21 +#define IRQ_NR_PWM0 22 +#define IRQ_NR_PWM1 23 +#define IRQ_NR_PWM2 24 +#define IRQ_NR_PWM3 25 +#define IRQ_NR_ADC 26 +#define IRQ_NR_RTC 27 +#define IRQ_NR_PIUSEM0 28// -- PIU Semphore 0 +#define IRQ_NR_PIUSEM1 29 +#define IRQ_NR_PIUSEM3 30 +#define IRQ_NR_PIUCMD 31// -- PIU command/reply +#define IRQ_NR_XDMA 32 +#define IRQ_NR_SDMMC1 33 +#define IRQ_NR_DSPSEI 34// -- DSP slave interface error interrupt +#define IRQ_NR_DSPSWI 35// -- DSP interrupt by software set +#define IRQ_NR_SCU 36 +#define IRQ_NR_SWI 37// -- Software Interrupt +#define IRQ_NR_DSPMEI 38// -- DSP master interface error interrupt +#define IRQ_NR_DSPSAEI 39// -- DSP system access error interrupt +#define IRQ_GPU_M55_INT 40 +#define IRQ_GPU_MMU_INT 41 +#define IRQ_DDRII_MOBILE_CTR_INIT 42 +#define IRQ_MC_DMA_INT 43 +#define IRQ_NAND_FLASH_RDY_INT 44 +#define IRQ_APB_UART2 45 +#define IRQ_APB_UART3 46 +#define IRQ_USB_HOST 47 + + +#endif diff --git a/arch/arm/mach-rk2818/include/mach/memory.h b/arch/arm/mach-rk2818/include/mach/memory.h new file mode 100644 index 000000000000..dba9818eb166 --- /dev/null +++ b/arch/arm/mach-rk2818/include/mach/memory.h @@ -0,0 +1,27 @@ +/* arch/arm/mach-rk2818/include/mach/memory.h + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +/* physical offset of RAM */ +#define PHYS_OFFSET UL(0x60000000) + +/* bus address and physical addresses are identical */ +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt(x) __phys_to_virt(x) + +#endif + diff --git a/arch/arm/mach-rk2818/include/mach/rk2818_iomap.h b/arch/arm/mach-rk2818/include/mach/rk2818_iomap.h new file mode 100644 index 000000000000..15df1c5a539a --- /dev/null +++ b/arch/arm/mach-rk2818/include/mach/rk2818_iomap.h @@ -0,0 +1,206 @@ +/* arch/arm/mach-rk2818/include/mach/rk281x_iomap.h + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * + */ + +#ifndef __ASM_ARCH_RK2818_IOMAP_H +#define __ASM_ARCH_RK2818_IOMAP_H + +#include + +/* defines */ + +#define SZ_22K 0x5800 + +/* Physical base address and size of peripherals. + * Ordered by the virtual base addresses they will be mapped at. + * + * RK2818_VIC_BASE must be an value that can be loaded via a "mov" + * instruction, otherwise entry-macro.S will not compile. + * + * If you add or remove entries here, you'll want to edit the + * rk2818_io_desc array in arch/arm/mach-rk2818/io.c to reflect your + * changes. + * + */ +//ÄÚ´æÎïÀíµØÖ· +#ifdef CONFIG_DRAM_BASE +#define RK2818_SDRAM_BASE 0x60000000//CONFIG_DRAM_BASE +#else +#define RK2818_SDRAM_PHYS 0x60000000 +#define RK2818_SDRAM_SIZE (0x00100000*64) +#endif + +#define RK2818_AHB_BASE 0xFF000000 +#define RK2818_AHB_PHYS 0x10000000 //AHB ×ÜÏßÉ豸»ùÎïÀíµØÖ· +#define RK2818_AHB_SIZE 0x00100000 // size:1M + +#define RK2818_APB_BASE 0xFF100000 +#define RK2818_APB_PHYS 0x18000000 // APB×ÜÏßÉ豸»ùÎïÀíµØÖ· +#define RK2818_APB_SIZE 0x00100000 // size:1M + +#define RK2818_BOOTROM_BASE 0xFF000000 +#define RK2818_BOOTROM_PHYS 0x10000000 +#define RK2818_BOOTROM_SIZE SZ_8K + +#define RK2818_SRAM_BASE 0xFF002000 +#define RK2818_SRAM_PHYS 0x10002000 +#define RK2818_SRAM_SIZE SZ_8K + +#define RK2818_USBOTG_BASE 0xFF040000 +#define RK2818_USBOTG_PHYS 0x10040000 +#define RK2818_USBOTG_SIZE SZ_256K + +#define RK2818_MCDMA_BASE 0xFF080000 +#define RK2818_MCDMA_PHYS 0x10080000 +#define RK2818_MCDMA_SIZE SZ_8K + +#define RK2818_SHAREMEM_BASE 0xFF090000 +#define RK2818_SHAREMEM_PHYS 0x10090000 +#define RK2818_SHAREMEM_SIZE SZ_64K + +#define RK2818_DWDMA_BASE 0xFF0A0000 +#define RK2818_DWDMA_PHYS 0x100A0000 +#define RK2818_DWDMA_SIZE SZ_8K + +#define RK2818_HOSTIF_BASE 0xFF0A2000 +#define RK2818_HOSTIF_PHYS 0x100A2000 +#define RK2818_HOSTIF_SIZE SZ_8K + +#define RK2818_LCDC_BASE 0xFF0A4000 +#define RK2818_LCDC_PHYS 0x100A4000 +#define RK2818_LCDC_SIZE SZ_8K + +#define RK2818_VIP_BASE 0xFF0A6000 +#define RK2818_VIP_PHYS 0x100A6000 +#define RK2818_VIP_SIZE SZ_8K + +#define RK2818_SDMMC1_BASE 0xFF0A8000 +#define RK2818_SDMMC1_PHYS 0x100A8000 +#define RK2818_SDMMC1_SIZE SZ_8K + +#define RK2818_INTC_BASE 0xFF0AA000 +#define RK2818_INTC_PHYS 0x100AA000 +#define RK2818_INTC_SIZE SZ_8K + +#define RK2818_SDMMC0_BASE 0xFF0AC000 +#define RK2818_SDMMC0_PHYS 0x100AC000 +#define RK2818_SDMMC0_SIZE SZ_8K + +#define RK2818_NANDC_BASE 0xFF0AE000 +#define RK2818_NANDC_PHYS 0x100AE000 +#define RK2818_NANDC_SIZE SZ_16K + +#define RK2818_SDRAMC_BASE 0xFF0B0000 +#define RK2818_SDRAMC_PHYS 0x100B0000 +#define RK2818_SDRAMC_SIZE SZ_8K + +#define RK2818_ARMDARBITER_BASE 0xFF0B4000 +#define RK2818_ARMDARBITER_PHYS 0x100B4000 +#define RK2818_ARMDARBITER_SIZE SZ_8K + +#define RK2818_VIDEOCOP_BASE 0xFF0B8000 +#define RK2818_VIDEOCOP_PHYS 0x100B8000 +#define RK2818_VIDEOCOP_SIZE SZ_8K + +#define RK2818_ESRAM_BASE 0xFF0BA000 +#define RK2818_ESRAM_PHYS 0x100BA000 +#define RK2818_ESRAM_SIZE SZ_8K + +#define RK2818_USBHOST_BASE 0xFF10000 +#define RK2818_USBHOST_PHYS 0x1010000 +#define RK2818_USBHOST_SIZE SZ_256K + +#define RK2818_UART0_BASE 0xFF100000 +#define RK2818_UART0_PHYS 0x18000000 +#define RK2818_UART0_SIZE SZ_4K + +#define RK2818_UART2_BASE 0xFF101000 +#define RK2818_UART2_PHYS 0x18001000 +#define RK2818_UART2_SIZE SZ_4K + +#define RK2818_UART1_BASE 0xFF102000 +#define RK2818_UART1_PHYS 0x18002000 +#define RK2818_UART1_SIZE SZ_4K + +#define RK2818_UART3_BASE 0xFF103000 +#define RK2818_UART3_PHYS 0x18003000 +#define RK2818_UART3_SIZE SZ_4K + +#define RK2818_TIMER_BASE 0xFF104000 +#define RK2818_TIMER_PHYS 0x18004000 +#define RK2818_TIMER_SIZE SZ_8K + +#define RK2818_eFUSE_BASE 0xFF106000 +#define RK2818_eFUSE_PHYS 0x18006000 +#define RK2818_eFUSE_SIZE SZ_8K + +#define RK2818_GPIO0_BASE 0xFF108000 +#define RK2818_GPIO0_PHYS 0x18008000 +#define RK2818_GPIO0_SIZE SZ_8K + +#define RK2818_GPIO1_BASE 0xFF109000 +#define RK2818_GPIO1_PHYS 0x18009000 +#define RK2818_GPIO1_SIZE SZ_8K + +#define RK2818_I2S_BASE 0xFF10A000 +#define RK2818_I2S_PHYS 0x1800A000 +#define RK2818_I2S_SIZE SZ_8K + +#define RK2818_I2C0_BASE 0xFF10C000 +#define RK2818_I2C0_PHYS 0x1800C000 +#define RK2818_I2C0_SIZE SZ_4K + +#define RK2818_I2C1_BASE 0xFF10D000 +#define RK2818_I2C1_PHYS 0x1800D000 +#define RK2818_I2C1_SIZE SZ_4K + +#define RK2818_SPIMASTER_BASE 0xFF10E000 +#define RK2818_SPIMASTER_PHYS 0x1800E000 +#define RK2818_SPIMASTER_SIZE SZ_4K + +#define RK2818_SPISLAVE_BASE 0xFF10F000 +#define RK2818_SPISLAVE_PHYS 0x1800F000 +#define RK2818_SPISLAVE_SIZE SZ_4K + +#define RK2818_WDT_BASE 0xFF110000 +#define RK2818_WDT_PHYS 0x18010000 +#define RK2818_WDT_SIZE SZ_8K + +#define RK2818_PWM_BASE 0xFF112000 +#define RK2818_PWM_PHYS 0x18012000 +#define RK2818_PWM_SIZE SZ_8K + +#define RK2818_RTC_BASE 0xFF114000 +#define RK2818_RTC_PHYS 0x18014000 +#define RK2818_RTC_SIZE SZ_8K + +#define RK2818_ADC_BASE 0xFF116000 +#define RK2818_ADC_PHYS 0x18016000 +#define RK2818_ADC_SIZE SZ_8K + +#define RK2818_SCU_BASE 0xFF118000 +#define RK2818_SCU_PHYS 0x18018000 +#define RK2818_SCU_SIZE SZ_4K + +#define RK2818_REGFILE_BASE 0xFF119000 +#define RK2818_REGFILE_PHYS 0x18019000 +#define RK2818_REGFILE_SIZE SZ_4K + +#define RK2818_DSP_BASE 0xE0000000 +#define RK2818_DSP_PHYS 0x80000000 +#define RK2818_DSP_SIZE 0x00600000 + +#endif diff --git a/arch/arm/mach-rk2818/include/mach/system.h b/arch/arm/mach-rk2818/include/mach/system.h new file mode 100644 index 000000000000..7e7d0c27956a --- /dev/null +++ b/arch/arm/mach-rk2818/include/mach/system.h @@ -0,0 +1,23 @@ +/* arch/arm/mach-rk2818/include/mach/system.h + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include + +void arch_idle(void); + +static inline void arch_reset(char mode, const char *cmd) +{ + for (;;) ; /* depends on IPC w/ other core */ +} diff --git a/arch/arm/mach-rk2818/include/mach/timex.h b/arch/arm/mach-rk2818/include/mach/timex.h new file mode 100644 index 000000000000..c54088022102 --- /dev/null +++ b/arch/arm/mach-rk2818/include/mach/timex.h @@ -0,0 +1,21 @@ +/* arch/arm/mach-rk2818/include/mach/timex.h + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_RK2818_TIMEX_H +#define __ASM_ARCH_RK2818_TIMEX_H + +#define CLOCK_TICK_RATE 50000000 + +#endif diff --git a/arch/arm/mach-rk2818/include/mach/uncompress.h b/arch/arm/mach-rk2818/include/mach/uncompress.h new file mode 100644 index 000000000000..c6f711b6fbf1 --- /dev/null +++ b/arch/arm/mach-rk2818/include/mach/uncompress.h @@ -0,0 +1,36 @@ +/* arch/arm/mach-rk2818/include/mach/uncompress.h + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_RK2818_UNCOMPRESS_H + +#include "hardware.h" + +static void putc(int c) +{ +} + +static inline void flush(void) +{ +} + +static inline void arch_decomp_setup(void) +{ +} + +static inline void arch_decomp_wdog(void) +{ +} + +#endif diff --git a/arch/arm/mach-rk2818/include/mach/vmalloc.h b/arch/arm/mach-rk2818/include/mach/vmalloc.h new file mode 100644 index 000000000000..dc22dadfe03b --- /dev/null +++ b/arch/arm/mach-rk2818/include/mach/vmalloc.h @@ -0,0 +1,22 @@ +/* arch/arm/mach-rk2818/include/mach/vmalloc.h + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_RK2818_VMALLOC_H +#define __ASM_ARCH_RK2818_VMALLOC_H + +#define VMALLOC_END (PAGE_OFFSET + 0x18000000) + +#endif + diff --git a/arch/arm/mach-rk2818/include/mach/vreg.h b/arch/arm/mach-rk2818/include/mach/vreg.h new file mode 100644 index 000000000000..85aca9c10366 --- /dev/null +++ b/arch/arm/mach-rk2818/include/mach/vreg.h @@ -0,0 +1,28 @@ +/* linux/include/asm-arm/arch-rk2818/vreg.h + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ARCH_ARM_MACH_RK2818_VREG_H +#define __ARCH_ARM_MACH_RK2818_VREG_H + +struct vreg; + +struct vreg *vreg_get(struct device *dev, const char *id); +void vreg_put(struct vreg *vreg); + +int vreg_enable(struct vreg *vreg); +void vreg_disable(struct vreg *vreg); +int vreg_set_level(struct vreg *vreg, unsigned mv); + +#endif diff --git a/arch/arm/mach-rk2818/io.c b/arch/arm/mach-rk2818/io.c new file mode 100644 index 000000000000..70bc7e6898a0 --- /dev/null +++ b/arch/arm/mach-rk2818/io.c @@ -0,0 +1,74 @@ +/* arch/arm/mach-rk2818/io.c + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include + +#define RK2818_DEVICE(name) { \ + .virtual = (unsigned long) RK2818_##name##_BASE, \ + .pfn = __phys_to_pfn(RK2818_##name##_PHYS), \ + .length = RK2818_##name##_SIZE, \ + .type = MT_DEVICE_NONSHARED, \ + } + +static struct map_desc rk2818_io_desc[] __initdata = { + /*RK2818_DEVICE(VIC), + RK2818_DEVICE(CSR), + RK2818_DEVICE(GPT), + RK2818_DEVICE(DMOV), + RK2818_DEVICE(GPIO1), + RK2818_DEVICE(GPIO2), + RK2818_DEVICE(CLK_CTL), + { + .virtual = (unsigned long) RK2818_SHARED_RAM_BASE, + .pfn = __phys_to_pfn(RK2818_SHARED_RAM_PHYS), + .length = RK2818_SHARED_RAM_SIZE, + .type = MT_DEVICE, + },*/ +}; + +void __init rk2818_map_common_io(void) +{ + /* Make sure the peripheral register window is closed, since + * we will use PTE flags (TEX[1]=1,B=0,C=1) to determine which + * pages are peripheral interface or not. + */ + asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0)); + + iotable_init(rk2818_io_desc, ARRAY_SIZE(rk2818_io_desc)); +} + +void __iomem * +__rk2818_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) +{ + if (mtype == MT_DEVICE) { + /* The peripherals in the 88000000 - D0000000 range + * are only accessable by type MT_DEVICE_NONSHARED. + * Adjust mtype as necessary to make this "just work." + */ + if ((phys_addr >= 0x88000000) && (phys_addr < 0xD0000000)) + mtype = MT_DEVICE_NONSHARED; + } + + return __arm_ioremap(phys_addr, size, mtype); +} diff --git a/arch/arm/mach-rk2818/irq.c b/arch/arm/mach-rk2818/irq.c new file mode 100644 index 000000000000..1198f6739aee --- /dev/null +++ b/arch/arm/mach-rk2818/irq.c @@ -0,0 +1,166 @@ +/* linux/arch/arm/mach-rk2818/irq.c + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + + +#include +#include +#include +#include + +//#include +//#include +#include +//#include + +//#include +//#include +#include +#include + +//#include "include/mach/irqs.h" +//#include "include/mach/rk2818_iomap.h" + +//#include +#include +//#include +//#include + +#include + + +#define which_irq_l(irq) (0x01u << (irq)) +#define which_irq_h(irq) (0x01u << ((irq) & 0x1f)) + +#define write_irq_reg(addr, val) __raw_writel(val, addr+(RK2818_INTC_BASE)) +#define read_irq_reg(addr) __raw_readl(addr+(RK2818_INTC_BASE)) +#define set_irq_reg(addr, val) write_irq_reg(addr, ((val) | read_irq_reg(addr))) +#define clear_irq_reg(addr, val) write_irq_reg(addr, (~(val) & read_irq_reg(addr))) + + + +u32 int_priority[NR_IRQS]={ + /* priority name number */ + 0, //IRQ_DWDMA, 0 -- low + 0, //IRQ_UHI, 1 -- USB Host Interface + 0, //IRQ_NANDC, 2 + 0, //IRQ_LCDC, 3 + 0, //IRQ_SDMMC0, 4 + 0, //IRQ_VIP, 5 + 0, //IRQ_GPIO0, 6 + 0, //IRQ_GPIO1, 7 + 0, //IRQ_OTG, 8 -- USB OTG + 0, //IRQ_ABTARMD, 9 -- Arbiter in ARMD BUS + 0, //IRQ_ABTEXP, 10 -- Arbiter in EXP BUS + 0, //IRQ_I2C0, 11 + 0, //IRQ_I2C1, 12 + 0, //IRQ_I2S, 13 + 0, //IRQ_SPIM, 14 -- SPI Master + 0, //IRQ_SPIS, 15 -- SPI Slave + 0, //IRQ_TIMER1, 16 + 0, //IRQ_TIMER2, 17 + 0, //IRQ_TIMER3, 18 + 0, //IRQ_UART0, 19 + 0, //IRQ_UART1, 20 + 0, //IRQ_WDT, 21 + 0, //IRQ_PWM0, 22 + 0, //IRQ_PWM1, 23 + 0, //IRQ_PWM2, 24 + 0, //IRQ_PWM3, 25 + 0, //IRQ_ADC, 26 + 0, //IRQ_RTC, 27 + 0, //IRQ_PIUSEM0, 28 -- PIU Semphore 0 + 0, //IRQ_PIUSEM1, 29 + 0, //IRQ_PIUSEM3, 30 + 0, //IRQ_PIUCMD, 31 -- PIU command/reply + 0, //IRQ_XDMA, 32 + 0, //IRQ_SDMMC1, 33 + 0, //IRQ_DSPSEI, 34 -- DSP slave interface error interrupt + 0, //IRQ_DSPSWI, 35 -- DSP interrupt by software set + 0, //IRQ_SCU, 36 + 0, //IRQ_SWI, 37 -- Software Interrupt + 0, //IRQ_DSPMEI, 38 -- DSP master interface error interrupt + 0, //IRQ_DSPSAEI, 39 -- DSP system access error interrupt + 0 //IRQ_MAXNUM 40 -- interrupt +}; + +static void rk2818_irq_ack(u32 irq) +{ +//rk28 no irq ack +} + +static void rk2818_irq_mask(u32 irq) +{ + if (irq >= 32) + { + set_irq_reg(IRQ_REG_INTMASK_H, which_irq_h(irq)); + } + else + { + set_irq_reg(IRQ_REG_INTMASK_L, which_irq_l(irq)); + } + +} + +static void rk2818_irq_unmask(u32 irq) +{ + if (irq >= 32) + { + clear_irq_reg(IRQ_REG_INTMASK_H, which_irq_h(irq)); + } + else + { + clear_irq_reg(IRQ_REG_INTMASK_L, which_irq_l(irq)); + } +} + +static s32 rk2818_irq_wake(u32 irq, u32 value) +{ +//rk28 no irq wake + return 0; +} + + +static struct irq_chip rk2818_irq_chip = { + .name = "rk2818_irq", + .ack = rk2818_irq_ack, + .mask = rk2818_irq_mask, + .unmask = rk2818_irq_unmask, + .set_wake = rk2818_irq_wake, +}; + + +/* + * Initialize the AIC interrupt controller. + */ +void __init rk2818_init_irq(u32 priority[NR_IRQS]) +{ + u32 i; + + write_irq_reg(IRQ_REG_INTEN_L, 0xffffffff);//enable irq interrupt + write_irq_reg(IRQ_REG_INTEN_H, 0xffffffff); + write_irq_reg(IRQ_REG_INTMASK_L, 0xffffffff); //mask all irq interrupt + write_irq_reg(IRQ_REG_INTMASK_H, 0xffffffff); + write_irq_reg(IRQ_REG_INTFORCE_L, 0); + write_irq_reg(IRQ_REG_INTFORCE_H, 0); + write_irq_reg(FIQ_REG_INTEN, 0x03); //enable fiq interrupt + write_irq_reg(FIQ_REG_INTMASK, 0x03); //mask fiq interrupt + write_irq_reg(IRQ_REG_PLEVEL, 0); + + for (i = 0; i < NR_IRQS; i++) { + set_irq_chip(i, &rk2818_irq_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID);//no probe and auto enable + } +} diff --git a/arch/arm/mach-rk2818/proc_comm.c b/arch/arm/mach-rk2818/proc_comm.c new file mode 100644 index 000000000000..28c35cfb62d3 --- /dev/null +++ b/arch/arm/mach-rk2818/proc_comm.c @@ -0,0 +1,110 @@ +/* arch/arm/mach-rk2818/proc_comm.c + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include + +#include "proc_comm.h" + +//#define MSM_A2M_INT(n) (MSM_CSR_BASE + 0x400 + (n) * 4) + +static inline void notify_other_proc_comm(void) +{ + //writel(1, MSM_A2M_INT(6)); +} + +#define APP_COMMAND 0x00 +#define APP_STATUS 0x04 +#define APP_DATA1 0x08 +#define APP_DATA2 0x0C + +#define MDM_COMMAND 0x10 +#define MDM_STATUS 0x14 +#define MDM_DATA1 0x18 +#define MDM_DATA2 0x1C + +static DEFINE_SPINLOCK(proc_comm_lock); + +/* The higher level SMD support will install this to + * provide a way to check for and handle modem restart. + */ +int (*rk2818_check_for_modem_crash)(void); + +/* Poll for a state change, checking for possible + * modem crashes along the way (so we don't wait + * forever while the ARM9 is blowing up). + * + * Return an error in the event of a modem crash and + * restart so the msm_proc_comm() routine can restart + * the operation from the beginning. + */ +static int proc_comm_wait_for(void __iomem *addr, unsigned value) +{ + for (;;) { + if (readl(addr) == value) + return 0; + + if (rk2818_check_for_modem_crash) + if (rk2818_check_for_modem_crash()) + return -EAGAIN; + } +} + +int rk2818_proc_comm(unsigned cmd, unsigned *data1, unsigned *data2) +{ + + //void __iomem *base = MSM_SHARED_RAM_BASE; + unsigned long flags; + int ret=0; + + spin_lock_irqsave(&proc_comm_lock, flags); + #if 0 + for (;;) { + if (proc_comm_wait_for(base + MDM_STATUS, PCOM_READY)) + continue; + + writel(cmd, base + APP_COMMAND); + writel(data1 ? *data1 : 0, base + APP_DATA1); + writel(data2 ? *data2 : 0, base + APP_DATA2); + + notify_other_proc_comm(); + + if (proc_comm_wait_for(base + APP_COMMAND, PCOM_CMD_DONE)) + continue; + + if (readl(base + APP_STATUS) != PCOM_CMD_FAIL) { + if (data1) + *data1 = readl(base + APP_DATA1); + if (data2) + *data2 = readl(base + APP_DATA2); + ret = 0; + } else { + ret = -EIO; + } + break; + } + + writel(PCOM_CMD_IDLE, base + APP_COMMAND); + #endif + spin_unlock_irqrestore(&proc_comm_lock, flags); + + return ret; +} + + diff --git a/arch/arm/mach-rk2818/proc_comm.h b/arch/arm/mach-rk2818/proc_comm.h new file mode 100644 index 000000000000..0cfc93fc6044 --- /dev/null +++ b/arch/arm/mach-rk2818/proc_comm.h @@ -0,0 +1,165 @@ +/* arch/arm/mach-rk2818/proc_comm.h + * + * Copyright (c) 2010 ROCKCHIP + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _ARCH_ARM_MACH_RK2818_PROC_COMM_H_ +#define _ARCH_ARM_MACH_RK2818_PROC_COMM_H_ + +enum { + PCOM_CMD_IDLE = 0x0, + PCOM_CMD_DONE, + PCOM_RESET_APPS, + PCOM_RESET_CHIP, + PCOM_CONFIG_NAND_MPU, + PCOM_CONFIG_USB_CLKS, + PCOM_GET_POWER_ON_STATUS, + PCOM_GET_WAKE_UP_STATUS, + PCOM_GET_BATT_LEVEL, + PCOM_CHG_IS_CHARGING, + PCOM_POWER_DOWN, + PCOM_USB_PIN_CONFIG, + PCOM_USB_PIN_SEL, + PCOM_SET_RTC_ALARM, + PCOM_NV_READ, + PCOM_NV_WRITE, + PCOM_GET_UUID_HIGH, + PCOM_GET_UUID_LOW, + PCOM_GET_HW_ENTROPY, + PCOM_RPC_GPIO_TLMM_CONFIG_REMOTE, + PCOM_CLKCTL_RPC_ENABLE, + PCOM_CLKCTL_RPC_DISABLE, + PCOM_CLKCTL_RPC_RESET, + PCOM_CLKCTL_RPC_SET_FLAGS, + PCOM_CLKCTL_RPC_SET_RATE, + PCOM_CLKCTL_RPC_MIN_RATE, + PCOM_CLKCTL_RPC_MAX_RATE, + PCOM_CLKCTL_RPC_RATE, + PCOM_CLKCTL_RPC_PLL_REQUEST, + PCOM_CLKCTL_RPC_ENABLED, + PCOM_VREG_SWITCH, + PCOM_VREG_SET_LEVEL, + PCOM_GPIO_TLMM_CONFIG_GROUP, + PCOM_GPIO_TLMM_UNCONFIG_GROUP, + PCOM_NV_WRITE_BYTES_4_7, + PCOM_CONFIG_DISP, + PCOM_GET_FTM_BOOT_COUNT, + PCOM_RPC_GPIO_TLMM_CONFIG_EX, + PCOM_PM_MPP_CONFIG, + PCOM_GPIO_IN, + PCOM_GPIO_OUT, + PCOM_RESET_MODEM, + PCOM_RESET_CHIP_IMM, + PCOM_PM_VID_EN, + PCOM_VREG_PULLDOWN, + PCOM_NUM_CMDS, +}; + +enum { + PCOM_INVALID_STATUS = 0x0, + PCOM_READY, + PCOM_CMD_RUNNING, + PCOM_CMD_SUCCESS, + PCOM_CMD_FAIL, +}; + +/* List of VREGs that support the Pull Down Resistor setting. */ +enum { + PM_VREG_PDOWN_MSMA_ID, + PM_VREG_PDOWN_MSMP_ID, + PM_VREG_PDOWN_MSME1_ID, /* Not supported in Panoramix */ + PM_VREG_PDOWN_MSMC1_ID, /* Not supported in PM6620 */ + PM_VREG_PDOWN_MSMC2_ID, /* Supported in PM7500 only */ + PM_VREG_PDOWN_GP3_ID, /* Supported in PM7500 only */ + PM_VREG_PDOWN_MSME2_ID, /* Supported in PM7500 and Panoramix only */ + PM_VREG_PDOWN_GP4_ID, /* Supported in PM7500 only */ + PM_VREG_PDOWN_GP1_ID, /* Supported in PM7500 only */ + PM_VREG_PDOWN_TCXO_ID, + PM_VREG_PDOWN_PA_ID, + PM_VREG_PDOWN_RFTX_ID, + PM_VREG_PDOWN_RFRX1_ID, + PM_VREG_PDOWN_RFRX2_ID, + PM_VREG_PDOWN_SYNT_ID, + PM_VREG_PDOWN_WLAN_ID, + PM_VREG_PDOWN_USB_ID, + PM_VREG_PDOWN_MMC_ID, + PM_VREG_PDOWN_RUIM_ID, + PM_VREG_PDOWN_MSMC0_ID, /* Supported in PM6610 only */ + PM_VREG_PDOWN_GP2_ID, /* Supported in PM7500 only */ + PM_VREG_PDOWN_GP5_ID, /* Supported in PM7500 only */ + PM_VREG_PDOWN_GP6_ID, /* Supported in PM7500 only */ + PM_VREG_PDOWN_RF_ID, + PM_VREG_PDOWN_RF_VCO_ID, + PM_VREG_PDOWN_MPLL_ID, + PM_VREG_PDOWN_S2_ID, + PM_VREG_PDOWN_S3_ID, + PM_VREG_PDOWN_RFUBM_ID, + + /* new for HAN */ + PM_VREG_PDOWN_RF1_ID, + PM_VREG_PDOWN_RF2_ID, + PM_VREG_PDOWN_RFA_ID, + PM_VREG_PDOWN_CDC2_ID, + PM_VREG_PDOWN_RFTX2_ID, + PM_VREG_PDOWN_USIM_ID, + PM_VREG_PDOWN_USB2P6_ID, + PM_VREG_PDOWN_USB3P3_ID, + PM_VREG_PDOWN_INVALID_ID, + + /* backward compatible enums only */ + PM_VREG_PDOWN_CAM_ID = PM_VREG_PDOWN_GP1_ID, + PM_VREG_PDOWN_MDDI_ID = PM_VREG_PDOWN_GP2_ID, + PM_VREG_PDOWN_RUIM2_ID = PM_VREG_PDOWN_GP3_ID, + PM_VREG_PDOWN_AUX_ID = PM_VREG_PDOWN_GP4_ID, + PM_VREG_PDOWN_AUX2_ID = PM_VREG_PDOWN_GP5_ID, + PM_VREG_PDOWN_BT_ID = PM_VREG_PDOWN_GP6_ID, + + PM_VREG_PDOWN_MSME_ID = PM_VREG_PDOWN_MSME1_ID, + PM_VREG_PDOWN_MSMC_ID = PM_VREG_PDOWN_MSMC1_ID, + PM_VREG_PDOWN_RFA1_ID = PM_VREG_PDOWN_RFRX2_ID, + PM_VREG_PDOWN_RFA2_ID = PM_VREG_PDOWN_RFTX2_ID, + PM_VREG_PDOWN_XO_ID = PM_VREG_PDOWN_TCXO_ID +}; + +/* gpio info for PCOM_RPC_GPIO_TLMM_CONFIG_EX */ + +#define GPIO_ENABLE 0 +#define GPIO_DISABLE 1 + +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +#define GPIO_NO_PULL 0 +#define GPIO_PULL_DOWN 1 +#define GPIO_KEEPER 2 +#define GPIO_PULL_UP 3 + +#define GPIO_2MA 0 +#define GPIO_4MA 1 +#define GPIO_6MA 2 +#define GPIO_8MA 3 +#define GPIO_10MA 4 +#define GPIO_12MA 5 +#define GPIO_14MA 6 +#define GPIO_16MA 7 + +#define PCOM_GPIO_CFG(gpio, func, dir, pull, drvstr) \ + ((((gpio) & 0x3FF) << 4) | \ + ((func) & 0xf) | \ + (((dir) & 0x1) << 14) | \ + (((pull) & 0x3) << 15) | \ + (((drvstr) & 0xF) << 17)) + +int rk2818_proc_comm(unsigned cmd, unsigned *data1, unsigned *data2); + +#endif diff --git a/arch/arm/mach-rk2818/timer.c b/arch/arm/mach-rk2818/timer.c new file mode 100644 index 000000000000..9de5b9e19e17 --- /dev/null +++ b/arch/arm/mach-rk2818/timer.c @@ -0,0 +1,192 @@ +/* linux/arch/arm/mach-rk2818/timer.c + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define RK2818_TIMER1_BASE RK2818_TIMER_BASE +#define RK2818_TIMER2_BASE RK2818_TIMER_BASE + 0x14 +#define RK2818_TIMER3_BASE RK2818_TIMER_BASE + 0x28 +#define TIMER_LOAD_COUNT 0x0000 +#define TIMER_CUR_VALUE 0x0004 +#define TIMER_CONTROL_REG 0x0008 +#define TIMER_EOI 0x000C +#define TIMER_INT_STATUS 0x0010 + +#define TIMER_MATCH_VAL 0x0000 +#define TIMER_COUNT_VAL 0x0004 +#define TIMER_ENABLE 0x0008 +#define TIMER_ENABLE_CLR_ON_MATCH_EN 2 +#define TIMER_ENABLE_EN 3 +#define TIMER_CLEAR 0x000C + +#define CSR_PROTECTION 0x0020 +#define CSR_PROTECTION_EN 1 + +#define TIMER_HZ 24000000 +#define timer_cycle (TIMER_HZ+HZ/2)/HZ +uint32_t tcount; +uint32_t mycycles = 0; +static int pit_cnt=0; +struct rk2818_clock { + struct clock_event_device clockevent; + struct clocksource clocksource; + struct irqaction irq; + uint32_t regbase; + uint32_t freq; + uint32_t shift; +}; + +static irqreturn_t rk2818_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + struct rk2818_clock *clock = container_of(evt, struct rk2818_clock, clockevent); + readl(clock->regbase + TIMER_EOI); + pit_cnt +=mycycles; + evt->event_handler(evt); + return IRQ_HANDLED; +} + +static cycle_t rk2818_timer_read(void) +{ + + unsigned int elapsed; + unsigned int t; + + t = readl(RK2818_TIMER3_BASE + TIMER_LOAD_COUNT); + + elapsed = __raw_readl(RK2818_TIMER3_BASE + TIMER_CUR_VALUE); + + elapsed = t - elapsed; + elapsed += pit_cnt; + return elapsed; +} + +static int rk2818_timer_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + + struct rk2818_clock *clock = container_of(evt, struct rk2818_clock, clockevent); + + writel(4, clock->regbase + TIMER_CONTROL_REG); + mycycles = cycles; + writel(cycles, clock->regbase + TIMER_LOAD_COUNT); + writel(TIMER_ENABLE_EN, clock->regbase + TIMER_CONTROL_REG); + return 0; +} + +static void rk2818_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + struct rk2818_clock *clock = container_of(evt, struct rk2818_clock, clockevent); + printk("%s::Enter--mode is %d\n",__FUNCTION__,mode); + switch (mode) { + case CLOCK_EVT_MODE_RESUME: + case CLOCK_EVT_MODE_PERIODIC: + break; + case CLOCK_EVT_MODE_ONESHOT: + readl(clock->regbase+TIMER_EOI); + writel((TIMER_HZ+ HZ/2) / HZ,clock->regbase+TIMER_LOAD_COUNT); + writel(TIMER_ENABLE_EN, clock->regbase + TIMER_CONTROL_REG); + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + writel(4, clock->regbase + TIMER_CONTROL_REG); + break; + } +} + +static struct rk2818_clock rk2818_clocks[] = { + { + .clockevent = { + .name = "timer", + .features = CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .rating = 200, + .set_next_event = rk2818_timer_set_next_event, + .set_mode = rk2818_timer_set_mode, + }, + .clocksource = { + .name = "timer", + .rating = 200, + .read = rk2818_timer_read, + .mask = CLOCKSOURCE_MASK(24), + .shift = 26, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, + }, + .irq = { + .name = "timer", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING, + .handler = rk2818_timer_interrupt, + .dev_id = &rk2818_clocks[0].clockevent, + .irq = IRQ_NR_TIMER3 + }, + .regbase = RK2818_TIMER3_BASE, + .freq = TIMER_HZ + } +}; + +static void __init rk2818_timer_init(void) +{ + int i; + int res; + printk("%s [%d]\n",__FUNCTION__,__LINE__); + //rk2818_clock_init(); + for (i = 0; i < ARRAY_SIZE(rk2818_clocks); i++) { + printk("%s::Enter %d\n",__FUNCTION__,i+1); + struct rk2818_clock *clock = &rk2818_clocks[i]; + struct clock_event_device *ce = &clock->clockevent; + struct clocksource *cs = &clock->clocksource; + + writel((TIMER_HZ+ HZ/2) / HZ,clock->regbase+TIMER_LOAD_COUNT); + + writel(0x04, clock->regbase + TIMER_CONTROL_REG); + + ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift); + /* allow at least 10 seconds to notice that the timer wrapped */ + ce->max_delta_ns = + clockevent_delta2ns(0xf0000000 >> clock->shift, ce); + /* 4 gets rounded down to 3 */ + ce->min_delta_ns = clockevent_delta2ns(4, ce); + ce->cpumask = cpumask_of(0); + + cs->mult = clocksource_hz2mult(clock->freq, cs->shift); + printk("mult is %x\n",cs->mult); + res = clocksource_register(cs); + if (res) + printk(KERN_ERR "rk2818_timer_init: clocksource_register " + "failed for %s\n", cs->name); + printk("%s::irq is %d\n",__FUNCTION__,clock->irq.irq); + res = setup_irq(clock->irq.irq, &clock->irq); + if (res) + printk(KERN_ERR "rk2818_timer_init: setup_irq " + "failed for %s\n", cs->name); + + clockevents_register_device(ce); + } +} + +struct sys_timer rk2818_timer = { + .init = rk2818_timer_init +}; diff --git a/arch/arm/mach-rk2818/vreg.c b/arch/arm/mach-rk2818/vreg.c new file mode 100644 index 000000000000..7afede9d491c --- /dev/null +++ b/arch/arm/mach-rk2818/vreg.c @@ -0,0 +1,142 @@ +/* arch/arm/mach-rk2818/vreg.c + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include + +#include "proc_comm.h" + +struct vreg { + const char *name; + unsigned id; +}; + +#define VREG(_name, _id) { .name = _name, .id = _id, } + +static struct vreg vregs[] = { + VREG("msma", 0), + VREG("msmp", 1), + VREG("msme1", 2), + VREG("msmc1", 3), + VREG("msmc2", 4), + VREG("gp3", 5), + VREG("msme2", 6), + VREG("gp4", 7), + VREG("gp1", 8), + VREG("tcxo", 9), + VREG("pa", 10), + VREG("rftx", 11), + VREG("rfrx1", 12), + VREG("rfrx2", 13), + VREG("synt", 14), + VREG("wlan", 15), + VREG("usb", 16), + VREG("boost", 17), + VREG("mmc", 18), + VREG("ruim", 19), + VREG("msmc0", 20), + VREG("gp2", 21), + VREG("gp5", 22), + VREG("gp6", 23), + VREG("rf", 24), + VREG("rf_vco", 26), + VREG("mpll", 27), + VREG("s2", 28), + VREG("s3", 29), + VREG("rfubm", 30), + VREG("ncp", 31), +}; + +struct vreg *vreg_get(struct device *dev, const char *id) +{ + int n; + for (n = 0; n < ARRAY_SIZE(vregs); n++) { + if (!strcmp(vregs[n].name, id)) + return vregs + n; + } + return 0; +} + +void vreg_put(struct vreg *vreg) +{ +} + +int vreg_enable(struct vreg *vreg) +{ + unsigned id = vreg->id; + unsigned enable = 1; + return rk2818_proc_comm(PCOM_VREG_SWITCH, &id, &enable); +} + +void vreg_disable(struct vreg *vreg) +{ + unsigned id = vreg->id; + unsigned enable = 0; + rk2818_proc_comm(PCOM_VREG_SWITCH, &id, &enable); +} + +int vreg_set_level(struct vreg *vreg, unsigned mv) +{ + unsigned id = vreg->id; + return rk2818_proc_comm(PCOM_VREG_SET_LEVEL, &id, &mv); +} + +#if defined(CONFIG_DEBUG_FS) + +static int vreg_debug_set(void *data, u64 val) +{ + struct vreg *vreg = data; + switch (val) { + case 0: + vreg_disable(vreg); + break; + case 1: + vreg_enable(vreg); + break; + default: + vreg_set_level(vreg, val); + break; + } + return 0; +} + +static int vreg_debug_get(void *data, u64 *val) +{ + return -ENOSYS; +} + +DEFINE_SIMPLE_ATTRIBUTE(vreg_fops, vreg_debug_get, vreg_debug_set, "%llu\n"); + +static int __init vreg_debug_init(void) +{ + struct dentry *dent; + int n; + + dent = debugfs_create_dir("vreg", 0); + if (IS_ERR(dent)) + return 0; + + for (n = 0; n < ARRAY_SIZE(vregs); n++) + (void) debugfs_create_file(vregs[n].name, 0644, + dent, vregs + n, &vreg_fops); + + return 0; +} + +device_initcall(vreg_debug_init); +#endif diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 07b976da6174..bbc21a40681e 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -1608,7 +1608,7 @@ kb9263 MACH_KB9263 KB9263 1612 mt7108 MACH_MT7108 MT7108 1613 smtr2440 MACH_SMTR2440 SMTR2440 1614 manao MACH_MANAO MANAO 1615 -cm_x300 MACH_CM_X300 CM_X300 1616 +rk2818 MACH_RK2818 RK2818 1616 gulfstream_kp MACH_GULFSTREAM_KP GULFSTREAM_KP 1617 lanreadyfn522 MACH_LANREADYFN522 LANREADYFN522 1618 arma37 MACH_ARMA37 ARMA37 1619