From: Heiko Stuebner Date: Wed, 20 Jan 2016 18:22:38 +0000 (+0100) Subject: UPSTREAM: clk: rockchip: rk3368: fix parents of video encoder/decoder X-Git-Tag: firefly_0821_release~3456 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=cb438027f718669b5ca5c655c4d3f3f58dabff70;p=firefly-linux-kernel-4.4.55.git UPSTREAM: clk: rockchip: rk3368: fix parents of video encoder/decoder The vdpu and vepu clocks can also be parented to the npll and current parent list also is wrong as it would use the npll as "usbphy" source, so adapt the parent to the correct one. Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller") Signed-off-by: Heiko Stuebner Reviewed-by: zhangqing Cc: stable@vger.kernel.org (cherry picked from git.kernel.org mmind/linux-rockchip.git v4.6-clk/next commit 0f28d98463498c61c61a38aacbf9f69e92e85e9d) Change-Id: Ie7e8f1e7d6de5e149705cc5f6d6207e839eca2bd --- diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c index adfeb38b3cc8..b765f95addd5 100644 --- a/drivers/clk/rockchip/clk-rk3368.c +++ b/drivers/clk/rockchip/clk-rk3368.c @@ -384,10 +384,10 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = { * Clock-Architecture Diagram 3 */ - COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_usb_p, 0, + COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_npll_usb_p, 0, RK3368_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS, RK3368_CLKGATE_CON(4), 6, GFLAGS), - COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb_p, 0, + COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_npll_usb_p, 0, RK3368_CLKSEL_CON(15), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3368_CLKGATE_CON(4), 7, GFLAGS),