From: cmc-ubuntu <cmc@ubuntu.(none)>
Date: Thu, 11 Nov 2010 14:02:39 +0000 (+0800)
Subject: add spi & touch screen driver
X-Git-Tag: firefly_0821_release~11032
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=cba07fe4a281eb98eae40e300512d44776156820;p=firefly-linux-kernel-4.4.55.git

add spi & touch screen driver
---

cba07fe4a281eb98eae40e300512d44776156820
diff --cc Makefile
index d7cf5448ee7b,d7cf5448ee7b..a6ff97dec8d4
--- a/Makefile
+++ b/Makefile
@@@ -184,7 -184,7 +184,7 @@@ export KBUILD_BUILDHOST := $(SUBARCH
  #CROSS_COMPILE	?=
  ARCH		?= arm
  #CROSS_COMPILE	:=/opt/android0320/mydroid/prebuilt/linux-x86/toolchain/arm-eabi-4.2.1/bin/arm-eabi-
--CROSS_COMPILE	?=../toolchain/arm-eabi-4.4.0/bin/arm-eabi-
++CROSS_COMPILE	?=../../google/myandroid/prebuilt/linux-x86/toolchain/arm-eabi-4.4.0/bin/arm-eabi-
  
  # Architecture as present in compile.h
  UTS_MACHINE 	:= $(ARCH)
diff --cc arch/arm/mach-rk29/board-rk29sdk.c
index 816156cd16f7,26201e6ab342..5dd72399ac5f
--- a/arch/arm/mach-rk29/board-rk29sdk.c
+++ b/arch/arm/mach-rk29/board-rk29sdk.c
@@@ -41,11 -44,31 +44,33 @@@
  #include <linux/mtd/partitions.h>
  
  #include "devices.h"
 +#include "../../../drivers/input/touchscreen/xpt2046_cbn_ts.h"
 +
  
+ /* Set memory size of pmem */
+ #define SDRAM_SIZE          SZ_128M
+ #define PMEM_GPU_SIZE       (12 * SZ_1M)
+ #define PMEM_UI_SIZE        SZ_16M
+ #define PMEM_VPU_SIZE       SZ_32M
+ 
+ #define PMEM_GPU_BASE       (RK29_SDRAM_PHYS + SDRAM_SIZE - PMEM_GPU_SIZE)
+ #define PMEM_UI_BASE        (PMEM_GPU_BASE - PMEM_UI_SIZE)
+ #define PMEM_VPU_BASE       (PMEM_UI_BASE - PMEM_VPU_SIZE)
+ #define LINUX_SIZE          (PMEM_VPU_BASE - RK29_SDRAM_PHYS)
+ 
  extern struct sys_timer rk29_timer;
  
+ int rk29_nand_io_init(void)
+ {
+     return 0;
+ }
+ 
+ struct rk29_nand_platform_data rk29_nand_data = {
+     .width      = 1,     /* data bus width in bytes */
+     .hw_ecc     = 1,     /* hw ecc 0: soft ecc */
+     .num_flash    = 1,
+     .io_init   = rk29_nand_io_init,
+ };
  
  static struct rk29_gpio_bank rk29_gpiobankinit[] = {
  	{
@@@ -78,202 -101,383 +103,573 @@@
  	},  	
  };
  
+ /*****************************************************************************************
+  * lcd  devices
+  * author: zyw@rock-chips.com
+  *****************************************************************************************/
+ //#ifdef  CONFIG_LCD_TD043MGEA1
+ #define LCD_TXD_PIN          RK29_PIN0_PA6   // ÂÒÌî,µÃÐÞ¸Ä
+ #define LCD_CLK_PIN          RK29_PIN0_PA7   // ÂÒÌî,µÃÐÞ¸Ä
+ #define LCD_CS_PIN           RK29_PIN0_PB6   // ÂÒÌî,µÃÐÞ¸Ä
+ #define LCD_TXD_MUX_NAME     GPIOE_U1IR_I2C1_NAME
+ #define LCD_CLK_MUX_NAME     NULL
+ #define LCD_CS_MUX_NAME      GPIOH6_IQ_SEL_NAME
+ #define LCD_TXD_MUX_MODE     0
+ #define LCD_CLK_MUX_MODE     0
+ #define LCD_CS_MUX_MODE      0
+ //#endif
+ static int rk29_lcd_io_init(void)
+ {
+     int ret = 0;
+ 
+ #if 0
+     rk29_mux_api_set(LCD_CS_MUX_NAME, LCD_CS_MUX_MODE);
+     if (LCD_CS_PIN != INVALID_GPIO) {
+         ret = gpio_request(LCD_CS_PIN, NULL);
+         if(ret != 0)
+         {
+             goto err1;
+             printk(">>>>>> lcd cs gpio_request err \n ");
+         }
+     }
+ 
+     rk29_mux_api_set(LCD_CLK_MUX_NAME, LCD_CLK_MUX_MODE);
+     if (LCD_CLK_PIN != INVALID_GPIO) {
+         ret = gpio_request(LCD_CLK_PIN, NULL);
+         if(ret != 0)
+         {
+             goto err2;
+             printk(">>>>>> lcd clk gpio_request err \n ");
+         }
+     }
+ 
+     rk29_mux_api_set(LCD_TXD_MUX_NAME, LCD_TXD_MUX_MODE);
+     if (LCD_TXD_PIN != INVALID_GPIO) {
+         ret = gpio_request(LCD_TXD_PIN, NULL);
+         if(ret != 0)
+         {
+             goto err3;
+             printk(">>>>>> lcd txd gpio_request err \n ");
+         }
+     }
+ 
+     return 0;
+ 
+ err3:
+     if (LCD_CLK_PIN != INVALID_GPIO) {
+         gpio_free(LCD_CLK_PIN);
+     }
+ err2:
+     if (LCD_CS_PIN != INVALID_GPIO) {
+         gpio_free(LCD_CS_PIN);
+     }
+ err1:
+ #endif
+     return ret;
+ }
+ 
+ static int rk29_lcd_io_deinit(void)
+ {
+     int ret = 0;
+ #if 0
+     gpio_direction_output(LCD_CLK_PIN, 0);
+     gpio_set_value(LCD_CLK_PIN, GPIO_HIGH);
+     gpio_direction_output(LCD_TXD_PIN, 0);
+     gpio_set_value(LCD_TXD_PIN, GPIO_HIGH);
+ 
+     gpio_free(LCD_CS_PIN);
+     rk29_mux_api_mode_resume(LCD_CS_MUX_NAME);
+     gpio_free(LCD_CLK_PIN);
+     gpio_free(LCD_TXD_PIN);
+     rk29_mux_api_mode_resume(LCD_TXD_MUX_NAME);
+     rk29_mux_api_mode_resume(LCD_CLK_MUX_NAME);
+ #endif
+     return ret;
+ }
+ 
+ struct rk29lcd_info rk29_lcd_info = {
+     //.txd_pin  = LCD_TXD_PIN,
+     //.clk_pin = LCD_CLK_PIN,
+     //.cs_pin = LCD_CS_PIN,
+     .io_init   = rk29_lcd_io_init,
+     .io_deinit = rk29_lcd_io_deinit,
+ };
+ 
+ 
+ /*****************************************************************************************
+  * frame buffe  devices
+  * author: zyw@rock-chips.com
+  *****************************************************************************************/
+ 
+ #define FB_ID                       0
+ #define FB_DISPLAY_ON_PIN           RK29_PIN0_PB1   // ÂÒÌî,µÃÐÞ¸Ä
+ #define FB_LCD_STANDBY_PIN          INVALID_GPIO
+ #define FB_MCU_FMK_PIN              INVALID_GPIO
+ 
+ #if 0
+ #define FB_DISPLAY_ON_VALUE         GPIO_LOW
+ #define FB_LCD_STANDBY_VALUE        0
+ 
+ #define FB_DISPLAY_ON_MUX_NAME      GPIOB1_SMCS1_MMC0PCA_NAME
+ #define FB_DISPLAY_ON_MUX_MODE      IOMUXA_GPIO0_B1
+ 
+ #define FB_LCD_STANDBY_MUX_NAME     NULL
+ #define FB_LCD_STANDBY_MUX_MODE     1
+ 
+ #define FB_MCU_FMK_PIN_MUX_NAME     NULL
+ #define FB_MCU_FMK_MUX_MODE         0
+ 
+ #define FB_DATA0_16_MUX_NAME       GPIOC_LCDC16BIT_SEL_NAME
+ #define FB_DATA0_16_MUX_MODE        1
+ 
+ #define FB_DATA17_18_MUX_NAME      GPIOC_LCDC18BIT_SEL_NAME
+ #define FB_DATA17_18_MUX_MODE       1
+ 
+ #define FB_DATA19_24_MUX_NAME      GPIOC_LCDC24BIT_SEL_NAME
+ #define FB_DATA19_24_MUX_MODE       1
+ 
+ #define FB_DEN_MUX_NAME            CXGPIO_LCDDEN_SEL_NAME
+ #define FB_DEN_MUX_MODE             1
+ 
+ #define FB_VSYNC_MUX_NAME          CXGPIO_LCDVSYNC_SEL_NAME
+ #define FB_VSYNC_MUX_MODE           1
+ 
+ #define FB_MCU_FMK_MUX_NAME        NULL
+ #define FB_MCU_FMK_MUX_MODE         0
+ #endif
+ static int rk29_fb_io_init(struct rk29_fb_setting_info *fb_setting)
+ {
+     int ret = 0;
+ #if 0
+     if(fb_setting->data_num <=16)
+         rk29_mux_api_set(FB_DATA0_16_MUX_NAME, FB_DATA0_16_MUX_MODE);
+     if(fb_setting->data_num >16 && fb_setting->data_num<=18)
+         rk29_mux_api_set(FB_DATA17_18_MUX_NAME, FB_DATA17_18_MUX_MODE);
+     if(fb_setting->data_num >18)
+         rk29_mux_api_set(FB_DATA19_24_MUX_NAME, FB_DATA19_24_MUX_MODE);
+ 
+     if(fb_setting->vsync_en)
+         rk29_mux_api_set(FB_VSYNC_MUX_NAME, FB_VSYNC_MUX_MODE);
+ 
+     if(fb_setting->den_en)
+         rk29_mux_api_set(FB_DEN_MUX_NAME, FB_DEN_MUX_MODE);
+ 
+     if(fb_setting->mcu_fmk_en && FB_MCU_FMK_MUX_NAME && (FB_MCU_FMK_PIN != INVALID_GPIO))
+     {
+         rk29_mux_api_set(FB_MCU_FMK_MUX_NAME, FB_MCU_FMK_MUX_MODE);
+         ret = gpio_request(FB_MCU_FMK_PIN, NULL);
+         if(ret != 0)
+         {
+             gpio_free(FB_MCU_FMK_PIN);
+             printk(">>>>>> FB_MCU_FMK_PIN gpio_request err \n ");
+         }
+         gpio_direction_input(FB_MCU_FMK_PIN);
+     }
+ 
+     if(fb_setting->disp_on_en && FB_DISPLAY_ON_MUX_NAME && (FB_DISPLAY_ON_PIN != INVALID_GPIO))
+     {
+         rk29_mux_api_set(FB_DISPLAY_ON_MUX_NAME, FB_DISPLAY_ON_MUX_MODE);
+         ret = gpio_request(FB_DISPLAY_ON_PIN, NULL);
+         if(ret != 0)
+         {
+             gpio_free(FB_DISPLAY_ON_PIN);
+             printk(">>>>>> FB_DISPLAY_ON_PIN gpio_request err \n ");
+         }
+     }
+ 
+     if(fb_setting->disp_on_en && FB_LCD_STANDBY_MUX_NAME && (FB_LCD_STANDBY_PIN != INVALID_GPIO))
+     {
+         rk29_mux_api_set(FB_LCD_STANDBY_MUX_NAME, FB_LCD_STANDBY_MUX_MODE);
+         ret = gpio_request(FB_LCD_STANDBY_PIN, NULL);
+         if(ret != 0)
+         {
+             gpio_free(FB_LCD_STANDBY_PIN);
+             printk(">>>>>> FB_LCD_STANDBY_PIN gpio_request err \n ");
+         }
+     }
+ #endif
+     return ret;
+ }
+ 
+ struct rk29fb_info rk29_fb_info = {
+     .fb_id   = FB_ID,
+     //.disp_on_pin = FB_DISPLAY_ON_PIN,
+     //.disp_on_value = FB_DISPLAY_ON_VALUE,
+     //.standby_pin = FB_LCD_STANDBY_PIN,
+     //.standby_value = FB_LCD_STANDBY_VALUE,
+     //.mcu_fmk_pin = FB_MCU_FMK_PIN,
+     .lcd_info = &rk29_lcd_info,
+     .io_init   = rk29_fb_io_init,
+ };
+ 
+ static struct android_pmem_platform_data android_pmem_pdata = {
+ 	.name		= "pmem",
+ 	.start		= PMEM_UI_BASE,
+ 	.size		= PMEM_UI_SIZE,
+ 	.no_allocator	= 0,
+ 	.cached		= 1,
+ };
+ 
+ static struct platform_device android_pmem_device = {
+ 	.name		= "android_pmem",
+ 	.id		= 0,
+ 	.dev		= {
+ 		.platform_data = &android_pmem_pdata,
+ 	},
+ };
+ 
+ 
+ static struct android_pmem_platform_data android_pmem_vpu_pdata = {
+ 	.name		= "pmem_vpu",
+ 	.start		= PMEM_VPU_BASE,
+ 	.size		= PMEM_VPU_SIZE,
+ 	.no_allocator	= 0,
+ 	.cached		= 1,
+ };
+ 
+ static struct platform_device android_pmem_vpu_device = {
+ 	.name		= "android_pmem",
+ 	.id		= 2,
+ 	.dev		= {
+ 		.platform_data = &android_pmem_vpu_pdata,
+ 	},
+ };
+ 
+ /*****************************************************************************************
+  * SDMMC devices
+ *****************************************************************************************/
+ #ifdef CONFIG_SDMMC0_RK29
+ void rk29_sdmmc0_cfg_gpio(struct platform_device *dev)
+ {
+ 	rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_SDMMC0_CMD);
+ 	rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_SDMMC0_CLKOUT);
+ 	rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_SDMMC0_DATA0);
+ 	rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_SDMMC0_DATA1);
+ 	rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2);
+ 	rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3);
+ 	rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_SDMMC0_DETECT_N);
+ }
+ 
+ #define CONFIG_SDMMC0_USE_DMA
+ struct rk29_sdmmc_platform_data default_sdmmc0_data = {
+ 	.num_slots		= 1,
+ 	.host_ocr_avail = (MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|
+ 					   MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33| 
+ 					   MMC_VDD_33_34|MMC_VDD_34_35| MMC_VDD_35_36),
+ 	.host_caps 	= (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
+ 	.io_init = rk29_sdmmc0_cfg_gpio,
+ 	.dma_name = "sd_mmc",
+ #ifdef CONFIG_SDMMC0_USE_DMA
+ 	.use_dma  = 1,
+ #else
+ 	.use_dma = 0,
+ #endif
+ };
+ #endif
+ #ifdef CONFIG_SDMMC1_RK29
+ #define CONFIG_SDMMC1_USE_DMA
+ void rk29_sdmmc1_cfg_gpio(struct platform_device *dev)
+ {
+ 	rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
+ 	rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
+ 	rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
+ 	rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
+ 	rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
+ 	rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
+ }
+ 
+ struct rk29_sdmmc_platform_data default_sdmmc1_data = {
+ 	.num_slots		= 1,
+ 	.host_ocr_avail = (MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|
+ 					   MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32|
+ 					   MMC_VDD_32_33|MMC_VDD_33_34),
+ 	.host_caps 	= (MMC_CAP_4_BIT_DATA|MMC_CAP_SDIO_IRQ|
+ 				   MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
+ 	.io_init = rk29_sdmmc1_cfg_gpio,
+ 	.dma_name = "sdio",
+ #ifdef CONFIG_SDMMC1_USE_DMA
+ 	.use_dma  = 1,
+ #else
+ 	.use_dma = 0,
+ #endif
+ };
+ #endif
+ 
 -#ifdef CONFIG_VIVANTE
 -static struct resource resources_gpu[] = {
 -    [0] = {
 -		.name 	= "gpu_irq",
 -        .start 	= IRQ_GPU,
 -        .end    = IRQ_GPU,
 -        .flags  = IORESOURCE_IRQ,
 -    },
 -    [1] = {
 -		.name = "gpu_base",
 -        .start  = RK29_GPU_PHYS,
 -        .end    = RK29_GPU_PHYS + (256 << 10),
 -        .flags  = IORESOURCE_MEM,
 -    },
 -    [2] = {
 -		.name = "gpu_mem",
++#ifdef CONFIG_VIVANTE
++static struct resource resources_gpu[] = {
++    [0] = {
++		.name 	= "gpu_irq",
++        .start 	= IRQ_GPU,
++        .end    = IRQ_GPU,
++        .flags  = IORESOURCE_IRQ,
++    },
++    [1] = {
++		.name = "gpu_base",
++        .start  = RK29_GPU_PHYS,
++        .end    = RK29_GPU_PHYS + (256 << 10),
++        .flags  = IORESOURCE_MEM,
++    },
++    [2] = {
++		.name = "gpu_mem",
+         .start  = PMEM_GPU_BASE,
+         .end    = PMEM_GPU_BASE + PMEM_GPU_SIZE,
 -        .flags  = IORESOURCE_MEM,
 -    },
 -};
 -struct platform_device rk29_device_gpu = {
 -    .name             = "galcore",
 -    .id               = 0,
 -    .num_resources    = ARRAY_SIZE(resources_gpu),
 -    .resource         = resources_gpu,
 -};
++        .flags  = IORESOURCE_MEM,
++    },
++};
++struct platform_device rk29_device_gpu = {
++    .name             = "galcore",
++    .id               = 0,
++    .num_resources    = ARRAY_SIZE(resources_gpu),
++    .resource         = resources_gpu,
++};
+ #endif
+ 
+ static void __init rk29_board_iomux_init(void)
+ {
+ 	#ifdef CONFIG_UART0_RK29	
+ 	rk29_mux_api_set(GPIO1B7_UART0SOUT_NAME, GPIO1L_UART0_SOUT);
+ 	rk29_mux_api_set(GPIO1B6_UART0SIN_NAME, GPIO1L_UART0_SIN);
+ 	#ifdef CONFIG_UART0_CTS_RTS_RK29
+ 	rk29_mux_api_set(GPIO1C1_UART0RTSN_SDMMC1WRITEPRT_NAME, GPIO1H_UART0_RTS_N);
+ 	rk29_mux_api_set(GPIO1C0_UART0CTSN_SDMMC1DETECTN_NAME, GPIO1H_UART0_CTS_N);
+ 	#endif
+ 	#endif
+ 	#ifdef CONFIG_UART1_RK29	
+ 	rk29_mux_api_set(GPIO2A5_UART1SOUT_NAME, GPIO2L_UART1_SOUT);
+ 	rk29_mux_api_set(GPIO2A4_UART1SIN_NAME, GPIO2L_UART1_SIN);
+ 	#endif
+ 	#ifdef CONFIG_UART2_RK29	
+ 	rk29_mux_api_set(GPIO2B1_UART2SOUT_NAME, GPIO2L_UART2_SOUT);
+ 	rk29_mux_api_set(GPIO2B0_UART2SIN_NAME, GPIO2L_UART2_SIN);
+ 	#ifdef CONFIG_UART2_CTS_RTS_RK29
+ 	rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_UART2_RTS_N);
+ 	rk29_mux_api_set(GPIO2A6_UART2CTSN_NAME, GPIO2L_UART2_CTS_N);
+ 	#endif
+ 	#endif
+ 	#ifdef CONFIG_UART3_RK29	
+ 	rk29_mux_api_set(GPIO2B3_UART3SOUT_NAME, GPIO2L_UART3_SOUT);
+ 	rk29_mux_api_set(GPIO2B2_UART3SIN_NAME, GPIO2L_UART3_SIN);
+ 	#ifdef CONFIG_UART3_CTS_RTS_RK29
+ 	rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_UART3_RTS_N);
+ 	rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_UART3_CTS_N);
+ 	#endif
+ 	#endif
+ }
+ 
  static struct platform_device *devices[] __initdata = {
- #ifdef CONFIG_UART1_RK29	
+ #ifdef CONFIG_UART1_RK29
  	&rk29_device_uart1,
  #endif	
 +#ifdef CONFIG_SPIM_RK29XX
 +    &rk29xx_device_spi0m,
 +    &rk29xx_device_spi1m,
 +#endif
+ #ifdef CONFIG_SDMMC0_RK29	
+ 	&rk29_device_sdmmc0,
+ #endif
+ #ifdef CONFIG_SDMMC1_RK29
+ 	&rk29_device_sdmmc1,
+ #endif
+ #ifdef CONFIG_MTD_NAND_RK29
+ 	&rk29_device_nand,
+ #endif
+ 
+ #ifdef CONFIG_FB_RK29
+ 	&rk29_device_fb,
+ #endif
+ #ifdef CONFIG_VIVANTE
+ 	&rk29_device_gpu,
+ #endif
+ 	&android_pmem_device,
+ 	&android_pmem_vpu_device,
  };
  
 +/*****************************************************************************************
 + * spi devices
 + * author: cmc@rock-chips.com
 + *****************************************************************************************/
 +#define SPI_CHIPSELECT_NUM 2
 +struct spi_cs_gpio rk29xx_spi0_cs_gpios[SPI_CHIPSELECT_NUM] = {
 +    {
 +		.name = "spi0 cs0",
 +		.cs_gpio = RK29_PIN2_PC1,
 +		.cs_iomux_name = NULL,
 +	},
 +	{
 +		.name = "spi0 cs1",
 +		.cs_gpio = RK29_PIN1_PA4,
 +		.cs_iomux_name = GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME,//if no iomux,set it NULL
 +		.cs_iomux_mode = GPIO1L_SPI0_CSN1,
 +	}
 +};
 +
 +struct spi_cs_gpio rk29xx_spi1_cs_gpios[SPI_CHIPSELECT_NUM] = {
 +    {
 +		.name = "spi1 cs0",
 +		.cs_gpio = RK29_PIN2_PC5,
 +		.cs_iomux_name = NULL,
 +	},
 +	{
 +		.name = "spi1 cs1",
 +		.cs_gpio = RK29_PIN1_PA3,
 +		.cs_iomux_name = GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,//if no iomux,set it NULL
 +		.cs_iomux_mode = GPIO1L_SPI0_CSN1,
 +	}
 +};
 +
 +static int spi_io_init(struct spi_cs_gpio *cs_gpios, int cs_num)
 +{	
 +	int i,j,ret;
 +	
 +	//cs
 +	if (cs_gpios) {
 +		for (i=0; i<cs_num; i++) {
 +			rk29_mux_api_set(cs_gpios[i].cs_iomux_name, cs_gpios[i].cs_iomux_mode);
 +			ret = gpio_request(cs_gpios[i].cs_gpio, cs_gpios[i].name);
 +			if (ret) {
 +				for (j=0;j<i;j++) {
 +					gpio_free(cs_gpios[j].cs_gpio);
 +					//rk29_mux_api_mode_resume(cs_gpios[j].cs_iomux_name);
 +				}
 +				printk("[fun:%s, line:%d], gpio request err\n", __func__, __LINE__);
 +				return -1;
 +			}			
 +			gpio_direction_output(cs_gpios[i].cs_gpio, GPIO_HIGH);
 +		}
 +	}
 +	return 0;
 +}
 +
 +static int spi_io_deinit(struct spi_cs_gpio *cs_gpios, int cs_num)
 +{
 +	int i;
 +	
 +	if (cs_gpios) {
 +		for (i=0; i<cs_num; i++) {
 +			gpio_free(cs_gpios[i].cs_gpio);
 +			//rk29_mux_api_mode_resume(cs_gpios[i].cs_iomux_name);
 +		}
 +	}
 +	
 +	return 0;
 +}
 +
 +static int spi_io_fix_leakage_bug(void)
 +{
 +	gpio_direction_output(RK29_PIN2_PC1, GPIO_LOW); 
 +	return 0;
 +}
 +
 +static int spi_io_resume_leakage_bug(void)
 +{
 +	gpio_direction_output(RK29_PIN2_PC1, GPIO_HIGH);
 +	return 0;
 +}
 +
 +struct rk29xx_spi_platform_data rk29xx_spi0_platdata = {
 +	.num_chipselect = SPI_CHIPSELECT_NUM,
 +	.chipselect_gpios = rk29xx_spi0_cs_gpios,
 +	.io_init = spi_io_init,
 +	.io_deinit = spi_io_deinit,
 +	.io_fix_leakage_bug = spi_io_fix_leakage_bug,
 +	.io_resume_leakage_bug = spi_io_resume_leakage_bug,
 +};
 +
 +struct rk29xx_spi_platform_data rk29xx_spi1_platdata = {
 +	.num_chipselect = SPI_CHIPSELECT_NUM,
 +	.chipselect_gpios = rk29xx_spi1_cs_gpios,
 +	.io_init = spi_io_init,
 +	.io_deinit = spi_io_deinit,
 +	.io_fix_leakage_bug = spi_io_fix_leakage_bug,
 +	.io_resume_leakage_bug = spi_io_resume_leakage_bug,
 +};
 +
 +/*****************************************************************************************
 + * xpt2046 touch panel
 + * author: cmc@rock-chips.com
 + *****************************************************************************************/
 +#define XPT2046_GPIO_INT           RK29_PIN0_PA3
 +#define DEBOUNCE_REPTIME  3
 +
 +#if defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI) 
 +static struct xpt2046_platform_data xpt2046_info = {
 +	.model			= 2046,
 +	.keep_vref_on 	= 1,
 +	.swap_xy		= 0,
 +	.x_min			= 0,
 +	.x_max			= 320,
 +	.y_min			= 0,
 +	.y_max			= 480,
 +	.debounce_max		= 7,
 +	.debounce_rep		= DEBOUNCE_REPTIME,
 +	.debounce_tol		= 20,
 +	.gpio_pendown		= XPT2046_GPIO_INT,
 +	.penirq_recheck_delay_usecs = 1,
 +};
 +#elif defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_CBN_SPI)
 +static struct xpt2046_platform_data xpt2046_info = {
 +	.model			= 2046,
 +	.keep_vref_on 	= 1,
 +	.swap_xy		= 0,
 +	.x_min			= 0,
 +	.x_max			= 320,
 +	.y_min			= 0,
 +	.y_max			= 480,
 +	.debounce_max		= 7,
 +	.debounce_rep		= DEBOUNCE_REPTIME,
 +	.debounce_tol		= 20,
 +	.gpio_pendown		= XPT2046_GPIO_INT,
 +	.penirq_recheck_delay_usecs = 1,
 +};
 +#elif defined(CONFIG_TOUCHSCREEN_XPT2046_SPI) 
 +static struct xpt2046_platform_data xpt2046_info = {
 +	.model			= 2046,
 +	.keep_vref_on 	= 1,
 +	.swap_xy		= 1,
 +	.x_min			= 0,
 +	.x_max			= 800,
 +	.y_min			= 0,
 +	.y_max			= 480,
 +	.debounce_max		= 7,
 +	.debounce_rep		= DEBOUNCE_REPTIME,
 +	.debounce_tol		= 20,
 +	.gpio_pendown		= XPT2046_GPIO_INT,
 +	
 +	.penirq_recheck_delay_usecs = 1,
 +};
 +#elif defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
 +static struct xpt2046_platform_data xpt2046_info = {
 +	.model			= 2046,
 +	.keep_vref_on 	= 1,
 +	.swap_xy		= 1,
 +	.x_min			= 0,
 +	.x_max			= 800,
 +	.y_min			= 0,
 +	.y_max			= 480,
 +	.debounce_max		= 7,
 +	.debounce_rep		= DEBOUNCE_REPTIME,
 +	.debounce_tol		= 20,
 +	.gpio_pendown		= XPT2046_GPIO_INT,
 +	
 +	.penirq_recheck_delay_usecs = 1,
 +};
 +#endif
 +
 +static struct spi_board_info board_spi_devices[] = {
 +#if defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI) || defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_CBN_SPI)\
 +    ||defined(CONFIG_TOUCHSCREEN_XPT2046_SPI) || defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
 +	{
 +		.modalias	= "xpt2046_ts",
 +		.chip_select	= 0,
 +		.max_speed_hz	= 125 * 1000 * 26,/* (max sample rate @ 3V) * (cmd + data + overhead) */
 +		.bus_num	= 0,
 +		.irq = XPT2046_GPIO_INT,
 +		.platform_data = &xpt2046_info,
 +	},
 +#endif
 +}; 
 +
 +
  static void __init rk29_gic_init_irq(void)
  {
  	gic_dist_init(0, (void __iomem *)RK29_GICPERI_BASE, 32);
@@@ -286,12 -490,22 +682,23 @@@ static void __init machine_rk29_init_ir
  	rk29_gpio_init(rk29_gpiobankinit, MAX_BANK);
  	rk29_gpio_irq_setup();
  }
+ 
  static void __init machine_rk29_board_init(void)
  { 
++        rk29_board_iomux_init();
  	platform_add_devices(devices, ARRAY_SIZE(devices));	
 -	rk29_board_iomux_init();
 +	spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
  }
  
+ static void __init machine_rk29_fixup(struct machine_desc *desc, struct tag *tags,
+ 					char **cmdline, struct meminfo *mi)
+ {
+ 	mi->nr_banks = 1;
+ 	mi->bank[0].start = RK29_SDRAM_PHYS;
+ 	mi->bank[0].node = PHYS_TO_NID(RK29_SDRAM_PHYS);
+ 	mi->bank[0].size = LINUX_SIZE;
+ }
+ 
  static void __init machine_rk29_mapio(void)
  {
  	rk29_map_common_io();
diff --cc arch/arm/mach-rk29/clock.c
index f0d2cb47fdb7,53c46c707452..6ba71e9602c5
mode 100755,100644..100755
--- a/arch/arm/mach-rk29/clock.c
+++ b/arch/arm/mach-rk29/clock.c
diff --cc arch/arm/mach-rk29/devices.c
index a950e87f2f15,492fc69ea471..6f9b03927938
--- a/arch/arm/mach-rk29/devices.c
+++ b/arch/arm/mach-rk29/devices.c
@@@ -19,9 -19,59 +19,61 @@@
  #include <linux/delay.h>
  #include <mach/irqs.h>
  #include <mach/rk29_iomap.h>
 +#include <mach/rk29-dma-pl330.h> 
  #include "devices.h"
-  
+ 
++
+ #ifdef CONFIG_SDMMC0_RK29 
+ static struct resource resources_sdmmc0[] = {
+ 	{
+ 		.start 	= IRQ_SDMMC,
+ 		.end 	= IRQ_SDMMC,
+ 		.flags 	= IORESOURCE_IRQ,
+ 	},
+ 	{
+ 		.start 	= RK29_SDMMC0_PHYS,
+ 		.end 	= RK29_SDMMC0_PHYS + RK29_SDMMC0_SIZE -1,
+ 		.flags 	= IORESOURCE_MEM,
+ 	}
+ };
+ #endif
+ #ifdef CONFIG_SDMMC1_RK29
+ static struct resource resources_sdmmc1[] = {
+ 	{
+ 		.start 	= IRQ_SDIO,
+ 		.end 	= IRQ_SDIO,
+ 		.flags 	= IORESOURCE_IRQ,
+ 	},
+ 	{
+ 		.start 	= RK29_SDMMC1_PHYS,
+ 		.end 	= RK29_SDMMC1_PHYS + RK29_SDMMC1_SIZE -1,
+ 		.flags 	= IORESOURCE_MEM,
+ 	}
+ }; 
+ #endif
+ /* sdmmc */
+ #ifdef CONFIG_SDMMC0_RK29
+ struct platform_device rk29_device_sdmmc0 = {
+ 	.name			= "rk29_sdmmc",
+ 	.id				= 0,
+ 	.num_resources	= ARRAY_SIZE(resources_sdmmc0),
+ 	.resource		= resources_sdmmc0,
+ 	.dev 			= {
+ 		.platform_data = &default_sdmmc0_data,
+ 	},
+ };
+ #endif
+ #ifdef CONFIG_SDMMC1_RK29
+ struct platform_device rk29_device_sdmmc1 = {
+ 	.name			= "rk29_sdmmc",
+ 	.id				= 1,
+ 	.num_resources	= ARRAY_SIZE(resources_sdmmc1),
+ 	.resource		= resources_sdmmc1,
+ 	.dev 			= {
+ 		.platform_data = &default_sdmmc1_data,
+ 	},
+ };
+ #endif
  /*
   * rk29 4 uarts device
   */
@@@ -117,73 -167,51 +169,120 @@@ struct platform_device rk29_device_uart
  };
  #endif
  
 +/*
 + * rk29xx spi master device
 + */
 +static struct resource rk29_spi0_resources[] = {
 +	{
 +		.start	= IRQ_SPI0,
 +		.end	= IRQ_SPI0,
 +		.flags	= IORESOURCE_IRQ,
 +	},
 +	{
 +		.start	= RK29_SPI0_PHYS,
 +		.end	= RK29_SPI0_PHYS + RK29_SPI0_SIZE - 1,
 +		.flags	= IORESOURCE_MEM,
 +	},
 +	{
 +		.start  = DMACH_SPI0_TX,
 +		.end    = DMACH_SPI0_TX,
 +		.flags  = IORESOURCE_DMA,
 +	},
 +	{
 +		.start  = DMACH_SPI0_RX,
 +		.end    = DMACH_SPI0_RX,
 +		.flags  = IORESOURCE_DMA,
 +	},
 +};
 +
 +struct platform_device rk29xx_device_spi0m = {
 +	.name	= "rk29xx_spim",
 +	.id	= 0,
 +	.num_resources	= ARRAY_SIZE(rk29_spi0_resources),
 +	.resource	= rk29_spi0_resources,
 +	.dev			= {
 +		.platform_data	= &rk29xx_spi0_platdata,
 +	},
 +};
 +
 +static struct resource rk29_spi1_resources[] = {
 +	{
 +		.start	= IRQ_SPI1,
 +		.end	= IRQ_SPI1,
 +		.flags	= IORESOURCE_IRQ,
 +	},
 +	{
 +		.start	= RK29_SPI1_PHYS,
 +		.end	= RK29_SPI1_PHYS + RK29_SPI1_SIZE - 1,
 +		.flags	= IORESOURCE_MEM,
 +	},
 +	{
 +		.start  = DMACH_SPI1_TX,
 +		.end    = DMACH_SPI1_TX,
 +		.flags  = IORESOURCE_DMA,
 +	},
 +	{
 +		.start  = DMACH_SPI1_RX,
 +		.end    = DMACH_SPI1_RX,
 +		.flags  = IORESOURCE_DMA,
 +	},
 +};
 +
 +struct platform_device rk29xx_device_spi1m = {
 +	.name	= "rk29xx_spim",
 +	.id	= 1,
 +	.num_resources	= ARRAY_SIZE(rk29_spi1_resources),
 +	.resource	= rk29_spi1_resources,
 +	.dev			= {
 +		.platform_data	= &rk29xx_spi1_platdata,
 +	},
 +};
 +
+ #ifdef CONFIG_FB_RK29
+ /* rk29 fb resource */
+ static struct resource rk29_fb_resource[] = {
+ 	[0] = {
+ 		.start = RK29_LCDC_PHYS,
+ 		.end   = RK29_LCDC_PHYS + RK29_LCDC_SIZE - 1,
+ 		.flags = IORESOURCE_MEM,
+ 	},
+ 	[1] = {
+ 		.start = IRQ_LCDC,
+ 		.end   = IRQ_LCDC,
+ 		.flags = IORESOURCE_IRQ,
+ 	},
+ };
+ 
+ /*platform_device*/
+ extern struct rk29fb_info rk29_fb_info;
+ struct platform_device rk29_device_fb = {
+ 	.name		  = "rk29-fb",
+ 	.id		  = 4,
+ 	.num_resources	  = ARRAY_SIZE(rk29_fb_resource),
+ 	.resource	  = rk29_fb_resource,
+ 	.dev            = {
+ 		.platform_data  = &rk29_fb_info,
+ 	}
+ };
+ #endif
+ #if defined(CONFIG_MTD_NAND_RK29)  
+ static struct resource nand_resources[] = {
+ 	{
+ 		.start	= RK29_NANDC_PHYS,
+ 		.end	= 	RK29_NANDC_PHYS+RK29_NANDC_SIZE -1,
+ 		.flags	= IORESOURCE_MEM,
+ 	}
+ };
+ 
+ struct platform_device rk29_device_nand = {
+ 	.name	= "rk29-nand",
+ 	.id		=  -1, 
+ 	.resource	= nand_resources,
+ 	.num_resources= ARRAY_SIZE(nand_resources),
+ 	.dev	= {
+ 		.platform_data= &rk29_nand_data,
+ 	},
+ 	
+ };
+ #endif
  
diff --cc arch/arm/mach-rk29/devices.h
index 8911ba3ab457,fd1fe6e5d97b..0d8291020843
--- a/arch/arm/mach-rk29/devices.h
+++ b/arch/arm/mach-rk29/devices.h
@@@ -21,9 -22,11 +22,15 @@@ extern struct platform_device rk29_devi
  extern struct platform_device rk29_device_uart1;
  extern struct platform_device rk29_device_uart2;
  extern struct platform_device rk29_device_uart3;
 +extern struct platform_device rk29xx_device_spi0m;
 +extern struct platform_device rk29xx_device_spi1m;
 +extern struct rk29xx_spi_platform_data rk29xx_spi0_platdata;
 +extern struct rk29xx_spi_platform_data rk29xx_spi1_platdata;
+ extern struct platform_device rk29_device_fb;
+ extern struct platform_device rk29_device_nand;
+ extern struct rk29_sdmmc_platform_data default_sdmmc0_data;
+ extern struct rk29_sdmmc_platform_data default_sdmmc1_data;
+ extern struct platform_device rk29_device_sdmmc0;
+ extern struct platform_device rk29_device_sdmmc1;
  
--#endif
++#endif
diff --cc arch/arm/mach-rk29/gpio.c
index a5acb1b99d90,b38b8fe37a7b..c1842835fedf
mode 100755,100644..100755
--- a/arch/arm/mach-rk29/gpio.c
+++ b/arch/arm/mach-rk29/gpio.c
@@@ -606,7 -602,7 +606,8 @@@ void __init rk29_gpio_irq_setup(void
  				irq = IRQ_GPIO6;
  				break;		
  		}
- 		set_irq_chip_data(irq+14, this);
++
+ 		set_irq_chip_data(NR_AIC_IRQS+this->bank->id,this);
  		set_irq_chained_handler(irq, gpio_irq_handler);
  		this += 1; 
  		pin += 32;
@@@ -630,4 -626,4 +631,4 @@@ void __init rk29_gpio_init(struct rk29_
  		gpiochip_add(&rk29_gpio->chip);
  	}
  	printk("rk29_gpio_init:nr_banks=%d\n",nr_banks);
--}
++}
diff --cc arch/arm/mach-rk29/include/mach/board.h
index 682786c51458,bb575a0e2311..52b7c1bb1d50
--- a/arch/arm/mach-rk29/include/mach/board.h
+++ b/arch/arm/mach-rk29/include/mach/board.h
@@@ -17,23 -17,50 +17,67 @@@
  
  #include <linux/types.h>
  
 +/*spi*/
 +struct spi_cs_gpio {
 +	const char *name;
 +	unsigned int cs_gpio;
 +	char *cs_iomux_name;
 +	unsigned int cs_iomux_mode;
 +};
 +
 +struct rk29xx_spi_platform_data {
 +	int (*io_init)(struct spi_cs_gpio*, int);
 +	int (*io_deinit)(struct spi_cs_gpio*, int);
 +	int (*io_fix_leakage_bug)(void);
 +	int (*io_resume_leakage_bug)(void);
 +	struct spi_cs_gpio *chipselect_gpios;	
 +	u16 num_chipselect;
 +};
 +
+ #define INVALID_GPIO        -1
+ 
+ struct rk29lcd_info{
+     u32 lcd_id;
+     u32 txd_pin;
+     u32 clk_pin;
+     u32 cs_pin;
+     int (*io_init)(void);
+     int (*io_deinit)(void);
+ };
+ 
+ struct rk29_fb_setting_info{
+     u8 data_num;
+     u8 vsync_en;
+     u8 den_en;
+     u8 mcu_fmk_en;
+     u8 disp_on_en;
+     u8 standby_en;
+ };
+ 
+ struct rk29fb_info{
+     u32 fb_id;
+     u32 disp_on_pin;
+     u8 disp_on_value;
+     u32 standby_pin;
+     u8 standby_value;
+     u32 mcu_fmk_pin;
+     struct rk29lcd_info *lcd_info;
+     int (*io_init)(struct rk29_fb_setting_info *fb_setting);
+     int (*io_deinit)(void);
+ };
+ 
+ struct rk29_sdmmc_platform_data {
+ 	unsigned int num_slots;
+ 	unsigned int host_caps;
+ 	unsigned int host_ocr_avail;
+ 	unsigned int use_dma:1;
+ 	char dma_name[8];
+ 	int (*io_init)(void);
+ 	int (*io_deinit)(void);
+ 	int (*status)(struct device *);
+ 	int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id);
+ };
+ 
  void __init rk29_map_common_io(void);
  void __init rk29_clock_init(void);
  
diff --cc arch/arm/mach-rk29/include/mach/gpio.h
index 155aad3e0404,575f48f8594f..7953ceb039ce
mode 100755,100644..100755
--- a/arch/arm/mach-rk29/include/mach/gpio.h
+++ b/arch/arm/mach-rk29/include/mach/gpio.h
diff --cc drivers/input/touchscreen/xpt2046_cbn_ts.c
index 50353c20eba4,d0c4eccc985f..98d3bec83303
mode 100755,100644..100755
--- a/drivers/input/touchscreen/xpt2046_cbn_ts.c
+++ b/drivers/input/touchscreen/xpt2046_cbn_ts.c
@@@ -382,7 -380,7 +382,7 @@@ static int xpt2046_debounce(void *xpt, 
  	static int average_val[2];
  	
  
--	xpt2046printk("***>%s:%d,%d,%d,%d,%d,%d,%d,%d\n",__FUNCTION__,
++	xpt2046printk("***>%s:%d,%d,%d,%d,%ld,%d,%d,%d\n",__FUNCTION__,
  		data_idx,ts->last_read,
  	  ts->read_cnt,ts->debounce_max,
  		abs(ts->last_read - *val),ts->debounce_tol,
@@@ -700,9 -695,9 +700,7 @@@ static int __devinit xpt2046_probe(stru
  	struct spi_transfer		*x;
  	int				vref;
  	int				err;
- 	int             i;
- 
  	
 -
 -	
  	if (!spi->irq) {
  		dev_dbg(&spi->dev, "no IRQ?\n");
  		return -ENODEV;
@@@ -955,12 -949,12 +953,14 @@@ static struct spi_driver xpt2046_drive
  
  static int __init xpt2046_init(void)
  {
++	int ret;
++	
  	xpt2046printk("Touch panel drive XPT2046 driver init...\n");
  	
  	gADPoint.x = 0;
  	gADPoint.y = 0;
  	
--	int ret = spi_register_driver(&xpt2046_driver);
++	ret = spi_register_driver(&xpt2046_driver);
      if (ret)
      {
   		printk("Register XPT2046 driver failed.\n");