From: 黄涛 <huangtao@rock-chips.com>
Date: Tue, 15 Apr 2014 08:54:17 +0000 (+0800)
Subject: Revert "ARM: rockchip: rk3288: fix build for SMP disable and static rk3288_sys_set_po... 
X-Git-Tag: firefly_0821_release~5551
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=cd24cdfbe7b4f4446d010585ed0176137bb9ebe4;p=firefly-linux-kernel-4.4.55.git

Revert "ARM: rockchip: rk3288: fix build for SMP disable and static rk3288_sys_set_power_domain"

This reverts commit bd34a0dcbdd257f029183000bd768d20bef71c8d.
---

diff --git a/arch/arm/mach-rockchip/rk3288.c b/arch/arm/mach-rockchip/rk3288.c
index 90d5489ad2eb..23dc1fd555ca 100644
--- a/arch/arm/mach-rockchip/rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288.c
@@ -37,7 +37,6 @@
 #include "cpu_axi.h"
 #include "loader.h"
 #include "sram.h"
-#include "pm.h"
 
 #define RK3288_DEVICE(name) \
 	{ \
@@ -325,14 +324,12 @@ static int rk3288_pmu_set_power_domain(enum pmu_power_domain pd, bool on)
 			RESTORE_QOS(hevc_r_qos, HEVC_R);
 			RESTORE_QOS(hevc_w_qos, HEVC_W);
 		} else if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
-#ifdef CONFIG_SMP
 			writel_relaxed(0x20000 << (pd - PD_CPU_1), RK_CRU_VIRT + RK3288_CRU_SOFTRSTS_CON(0));
 			dsb();
 			udelay(10);
 			writel_relaxed(virt_to_phys(secondary_startup), RK3288_IMEM_VIRT + 8);
 			writel_relaxed(0xDEADBEAF, RK3288_IMEM_VIRT + 4);
 			dsb_sev();
-#endif
 		}
                 else if (pd == PD_PERI) {
 			rk3288_pmu_set_idle_request(IDLE_REQ_PERI, false);
@@ -344,54 +341,7 @@ out:
 	return 0;
 }
 
-static int rk3288_sys_set_power_domain(enum pmu_power_domain pd, bool on)
-{
-	u32 clks_ungating[RK3288_CRU_CLKGATES_CON_CNT];
-	u32 clks_save[RK3288_CRU_CLKGATES_CON_CNT];
-	u32 i, ret;
-
-	for (i = 0; i < RK3288_CRU_CLKGATES_CON_CNT; i++) {
-		clks_save[i] = cru_readl(RK3288_CRU_CLKGATES_CON(i));
-		clks_ungating[i] = 0;
-	}
-
-	switch (pd) {
-	case PD_GPU:
-		clks_ungating[5] = 0x1 << 7;
-		break;
-	case PD_VIDEO:
-		clks_ungating[3] = 0x1 << 11 | 0x1 << 10 | 0x1 << 9;
-		break;
-	case PD_VIO:
-		clks_ungating[3] =
-		    0x1 << 0 | 0x1 << 1 | 0x1 << 2 | 0x1 << 3 | 0x1 << 4 | 0x1 << 5 |
-		    0x1 << 11 | 0x1 << 12 | 0x1 << 13 | 0x1 << 14 | 0x1 << 15;
-		break;
-	case PD_HEVC:
-		clks_ungating[13] = 0x1 << 15 | 0x1 << 14 | 0x1 << 13;
-		break;
-#if 0
-	case PD_CS:
-		clks_ungating[12] = 0x1 << 11 | 0x1 < 10 | 0x1 << 9 | 0x1 << 8;
-		break;
-#endif
-	default:
-		break;
-	}
-
-	for (i = 0; i < RK3288_CRU_CLKGATES_CON_CNT; i++) {
-		if (clks_ungating[i])
-			cru_writel(clks_ungating[i] << 16, RK3288_CRU_CLKGATES_CON(i));
-	}
-	ret = rk3288_pmu_set_power_domain(pd, on);
-
-	for (i = 0; i < RK3288_CRU_CLKGATES_CON_CNT; i++) {
-		if (clks_ungating[i])
-			cru_writel(clks_save[i] | 0xffff0000, RK3288_CRU_CLKGATES_CON(i));
-	}
-
-	return ret;
-}
+int rk3288_sys_set_power_domain(enum pmu_power_domain pd, bool on);
 
 static void __init rk3288_dt_init_timer(void)
 {
@@ -510,6 +460,56 @@ static int __init rk3288_pie_init(void)
 arch_initcall(rk3288_pie_init);
 #ifdef CONFIG_PM
 #include "pm-rk3288.c"
+int rk3288_sys_set_power_domain(enum pmu_power_domain pd, bool on)
+{   
+            u32 clks_ungating[RK3288_CRU_CLKGATES_CON_CNT];
+            u32 clks_save[RK3288_CRU_CLKGATES_CON_CNT];
+            u32 i,ret;
+            for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
+            {
+                clks_save[i]=cru_readl(RK3288_CRU_CLKGATES_CON(i));
+                clks_ungating[i]=0;
+            }
+            switch(pd)
+            {
+                case PD_GPU:                   
+                    clks_ungating[5]=0x1<<7;
+                    break;
+                case PD_VIDEO:
+                     clks_ungating[3]=0x1<<11|0x1<<10|0x1<<9;
+                    break;
+                case PD_VIO:
+                    clks_ungating[3]=0x1<<0|0x1<<2|0x1<<5|0x1<<4|0x1<<1|0x1<<3|0x1<<12|0x1<<13
+                        |0x1<<14|0x1<<15|0x1<<12|0x1<<11;
+                    break;
+                case  PD_HEVC:
+                    clks_ungating[13]=0x1<<15|0x1<<14|0x1<<13;
+                    break;
+                #if 0    
+                case  PD_CS:
+                    clks_ungating[12]=0x1<<11|0x1<10|0x1<<9|0x1<<8;
+                   break;
+                 #endif  
+                    default:
+                        break;
+            }
+            
+            for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
+            {
+                if(clks_ungating[i])                  
+                    cru_writel(clks_ungating[i]<<16,RK3288_CRU_CLKGATES_CON(i));           
+            }      
+            ret=rk3288_pmu_set_power_domain(pd,on);
+
+             for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
+            {
+                if(clks_ungating[i])
+                    cru_writel(clks_save[i]|0xffff0000,RK3288_CRU_CLKGATES_CON(i));
+            }
+
+            return ret;
+             
+}
 
 static u32 rk_pmu_pwrdn_st;
 static inline void rk_pm_soc_pd_suspend(void)