From: Dan Gohman <gohman@apple.com>
Date: Tue, 6 Jan 2009 01:28:56 +0000 (+0000)
Subject: Update these argument lists for the isNormalMemory
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=ce0d4b7a77da716f234d42edd0472e97b3ba5f57;p=oota-llvm.git

Update these argument lists for the isNormalMemory
argument. This doesn't affect current functionality.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61779 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 676a69bd633..25c8bfb3394 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -729,7 +729,8 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
           DOUT << "Adding an edge from SU # " << TrySU->NodeNum
                << " to SU #" << Copies.front()->NodeNum << "\n";
           AddPred(TrySU, SDep(Copies.front(), SDep::Order, /*Latency=*/1,
-                              /*Reg=*/0, /*isMustAlias=*/false,
+                              /*Reg=*/0, /*isNormalMemory=*/false,
+                              /*isMustAlias=*/false,
                               /*isArtificial=*/true));
           NewDef = Copies.back();
         }
@@ -738,7 +739,8 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
              << " to SU #" << TrySU->NodeNum << "\n";
         LiveRegDefs[Reg] = NewDef;
         AddPred(NewDef, SDep(TrySU, SDep::Order, /*Latency=*/1,
-                             /*Reg=*/0, /*isMustAlias=*/false,
+                             /*Reg=*/0, /*isNormalMemory=*/false,
+                             /*isMustAlias=*/false,
                              /*isArtificial=*/true));
         TrySU->isAvailable = false;
         CurSU = NewDef;
@@ -1253,7 +1255,8 @@ void RegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
           DOUT << "Adding a pseudo-two-addr edge from SU # " << SU->NodeNum
                << " to SU #" << SuccSU->NodeNum << "\n";
           scheduleDAG->AddPred(SU, SDep(SuccSU, SDep::Order, /*Latency=*/0,
-                                        /*Reg=*/0, /*isMustAlias=*/false,
+                                        /*Reg=*/0, /*isNormalMemory=*/false,
+                                        /*isMustAlias=*/false,
                                         /*isArtificial=*/true));
         }
       }