From: 黄涛 Date: Mon, 10 Mar 2014 11:32:34 +0000 (+0800) Subject: ARM: rockchip: move some head files to include/linux/rockchip X-Git-Tag: firefly_0821_release~6160 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=ce1d983988c12ddc7a799520ac6bdd2c9fc55807;p=firefly-linux-kernel-4.4.55.git ARM: rockchip: move some head files to include/linux/rockchip --- diff --git a/arch/arm/mach-rockchip/common.c b/arch/arm/mach-rockchip/common.c index cdeef164941c..9ab4d186f879 100644 --- a/arch/arm/mach-rockchip/common.c +++ b/arch/arm/mach-rockchip/common.c @@ -20,7 +20,7 @@ #include #include #include -#include "common.h" +#include #include "cpu_axi.h" #include "loader.h" #include "pmu.h" diff --git a/arch/arm/mach-rockchip/common.h b/arch/arm/mach-rockchip/common.h deleted file mode 100644 index 31b00d6479cb..000000000000 --- a/arch/arm/mach-rockchip/common.h +++ /dev/null @@ -1,39 +0,0 @@ -#ifndef __MACH_ROCKCHIP_COMMON_H -#define __MACH_ROCKCHIP_COMMON_H - -#define RK_DEVICE(VIRT,PHYS,SIZE) \ - { \ - .virtual = (unsigned long)(VIRT), \ - .pfn = __phys_to_pfn(PHYS), \ - .length = SIZE, \ - .type = MT_DEVICE, \ - } - -extern unsigned long rockchip_boot_fn; -extern struct smp_operations rockchip_smp_ops; - -extern int (*ddr_change_freq)(uint32_t nMHz); -extern long (*ddr_round_rate)(uint32_t nMHz); -extern void (*ddr_set_auto_self_refresh)(bool en); - -extern int rockchip_cpu_kill(unsigned int cpu); -extern void rockchip_cpu_die(unsigned int cpu); -extern int rockchip_cpu_disable(unsigned int cpu); - -#define BOOT_MODE_NORMAL 0 -#define BOOT_MODE_FACTORY2 1 -#define BOOT_MODE_RECOVERY 2 -#define BOOT_MODE_CHARGE 3 -#define BOOT_MODE_POWER_TEST 4 -#define BOOT_MODE_OFFMODE_CHARGING 5 -#define BOOT_MODE_REBOOT 6 -#define BOOT_MODE_PANIC 7 -#define BOOT_MODE_WATCHDOG 8 -#define BOOT_MODE_TSADC 9 - -extern int rockchip_boot_mode(void); -extern void __init rockchip_boot_mode_init(u32 flag, u32 mode); -extern void rockchip_restart_get_boot_mode(const char *cmd, u32 *flag, u32 *mode); -extern void __init rockchip_suspend_init(void); - -#endif diff --git a/arch/arm/mach-rockchip/cpu.c b/arch/arm/mach-rockchip/cpu.c index 114d5b219c9b..6ac8cc02892a 100644 --- a/arch/arm/mach-rockchip/cpu.c +++ b/arch/arm/mach-rockchip/cpu.c @@ -1,6 +1,6 @@ #include #include -#include "cpu.h" +#include unsigned long rockchip_soc_id; EXPORT_SYMBOL(rockchip_soc_id); diff --git a/arch/arm/mach-rockchip/cpu.h b/arch/arm/mach-rockchip/cpu.h deleted file mode 100644 index 40f424207cc3..000000000000 --- a/arch/arm/mach-rockchip/cpu.h +++ /dev/null @@ -1,57 +0,0 @@ -#ifndef __MACH_ROCKCHIP_CPU_H -#define __MACH_ROCKCHIP_CPU_H - -extern unsigned long rockchip_soc_id; - -static inline bool cpu_is_rockchip(void) { return rockchip_soc_id; } - -#define ROCKCHIP_CPU_MASK 0xffff0000 -#define ROCKCHIP_CPU_RK2928 0x29280000 -#define ROCKCHIP_CPU_RK3026 0x30260000 -#define ROCKCHIP_CPU_RK30XX 0x30660000 -#define ROCKCHIP_CPU_RK3066B 0x31680000 -#define ROCKCHIP_CPU_RK3188 0x31880000 -#define ROCKCHIP_CPU_RK319X 0x31900000 -#define ROCKCHIP_CPU_RK3288 0x32880000 - -static inline bool cpu_is_rk2928(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK2928; } -static inline bool cpu_is_rk3026(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3026; } -static inline bool cpu_is_rk30xx(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK30XX; } -static inline bool cpu_is_rk3066b(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3066B; } -static inline bool cpu_is_rk3188(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3188; } -static inline bool cpu_is_rk319x(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK319X; } -static inline bool cpu_is_rk3288(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3288; } - -#define ROCKCHIP_SOC_RK2926 (ROCKCHIP_CPU_RK2928 | 0x00) -#define ROCKCHIP_SOC_RK2928G (ROCKCHIP_CPU_RK2928 | 0x01) -#define ROCKCHIP_SOC_RK2928L (ROCKCHIP_CPU_RK2928 | 0x02) -#define ROCKCHIP_SOC_RK3028A (ROCKCHIP_CPU_RK3026 | 0x03) -#define ROCKCHIP_SOC_RK3026 (ROCKCHIP_CPU_RK3026 | 0x04) -#define ROCKCHIP_SOC_RK3000 (ROCKCHIP_CPU_RK30XX | 0x00) -#define ROCKCHIP_SOC_RK3066 (ROCKCHIP_CPU_RK30XX | 0x01) -#define ROCKCHIP_SOC_RK3068 (ROCKCHIP_CPU_RK30XX | 0x02) -#define ROCKCHIP_SOC_RK3066B (ROCKCHIP_CPU_RK3066B| 0x00) -#define ROCKCHIP_SOC_RK3168 (ROCKCHIP_CPU_RK3066B| 0x01) -#define ROCKCHIP_SOC_RK3028 (ROCKCHIP_CPU_RK3066B| 0x03) -#define ROCKCHIP_SOC_RK3188 (ROCKCHIP_CPU_RK3188 | 0x00) -#define ROCKCHIP_SOC_RK3188PLUS (ROCKCHIP_CPU_RK3188 | 0x10) -#define ROCKCHIP_SOC_RK3190 (ROCKCHIP_CPU_RK319X | 0x00) -#define ROCKCHIP_SOC_RK3288 (ROCKCHIP_CPU_RK3288 | 0x00) - -static inline bool soc_is_rk2926(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK2926; } -static inline bool soc_is_rk2928g(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK2928G; } -static inline bool soc_is_rk2928l(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK2928L; } -static inline bool soc_is_rk3028a(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3028A; } -static inline bool soc_is_rk3026(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3026; } -static inline bool soc_is_rk3000(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3000; } -static inline bool soc_is_rk3066(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3066; } -static inline bool soc_is_rk3068(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3068; } -static inline bool soc_is_rk3066b(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3066B; } -static inline bool soc_is_rk3168(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3168; } -static inline bool soc_is_rk3028(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3028; } -static inline bool soc_is_rk3188(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3188; } -static inline bool soc_is_rk3188plus(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3188PLUS; } -static inline bool soc_is_rk3190(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3190; } -static inline bool soc_is_rk3288(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3288; } - -#endif diff --git a/arch/arm/mach-rockchip/cpuidle.c b/arch/arm/mach-rockchip/cpuidle.c index 9788b3d6b5a5..d155b5c34506 100644 --- a/arch/arm/mach-rockchip/cpuidle.c +++ b/arch/arm/mach-rockchip/cpuidle.c @@ -16,7 +16,7 @@ #include #include #include -#include "cpu.h" +#include static void __iomem *gic_cpu_base; diff --git a/arch/arm/mach-rockchip/cru.h b/arch/arm/mach-rockchip/cru.h deleted file mode 100644 index 8e6255adbe6f..000000000000 --- a/arch/arm/mach-rockchip/cru.h +++ /dev/null @@ -1,57 +0,0 @@ -#ifndef __MACH_ROCKCHIP_CRU_H -#define __MACH_ROCKCHIP_CRU_H - -#include - - -/*******************CRU BITS*******************************/ -#define CRU_W_MSK(bits_shift, msk) ((msk) << ((bits_shift) + 16)) -#define CRU_SET_BITS(val, bits_shift, msk) (((val)&(msk)) << (bits_shift)) -#define CRU_W_MSK_SETBITS(val, bits_shift,msk) \ - (CRU_W_MSK(bits_shift, msk) | CRU_SET_BITS(val, bits_shift, msk)) - -/*******************RK3188********************************/ -/*******************CRU OFFSET*********************/ -#define RK3188_CRU_MODE_CON 0x40 -#define RK3188_CRU_CLKSEL_CON 0x44 -#define RK3188_CRU_CLKGATE_CON 0xd0 -#define RK3188_CRU_GLB_SRST_FST 0x100 -#define RK3188_CRU_GLB_SRST_SND 0x104 -#define RK3188_CRU_SOFTRST_CON 0x110 - -#define RK3188_PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4)) - -#define RK3188_CRU_CLKSELS_CON_CNT (35) -#define RK3188_CRU_CLKSELS_CON(i) (RK3188_CRU_CLKSEL_CON + ((i) * 4)) - -#define RK3188_CRU_CLKGATES_CON_CNT (10) -#define RK3188_CRU_CLKGATES_CON(i) (RK3188_CRU_CLKGATE_CON + ((i) * 4)) - -#define RK3188_CRU_SOFTRSTS_CON_CNT (9) -#define RK3188_CRU_SOFTRSTS_CON(i) (RK3188_CRU_SOFTRST_CON + ((i) * 4)) - -#define RK3188_CRU_MISC_CON (0x134) -#define RK3188_CRU_GLB_CNT_TH (0x140) - -/******************PLL MODE BITS*******************/ -#define RK3188_PLL_MODE_MSK(id) (0x3 << ((id) * 4)) -#define RK3188_PLL_MODE_SLOW(id) ((0x0<<((id)*4))|(0x3<<(16+(id)*4))) -#define RK3188_PLL_MODE_NORM(id) ((0x1<<((id)*4))|(0x3<<(16+(id)*4))) -#define RK3188_PLL_MODE_DEEP(id) ((0x2<<((id)*4))|(0x3<<(16+(id)*4))) - -#define RK3288_CRU_GLB_SRST_FST_VALUE 0x1b0 -#define RK3288_CRU_GLB_SRST_SND_VALUE 0x1b4 -#define RK3288_CRU_MISC_CON 0x1e8 -#define RK3288_CRU_GLB_CNT_TH 0x1ec -#define RK3288_CRU_GLB_RST_CON 0x1f0 -#define RK3288_CRU_GLB_RST_ST 0x1f8 -#define RK3288_CRU_SDMMC_CON0 0x200 -#define RK3288_CRU_SDMMC_CON1 0x204 -#define RK3288_CRU_SDIO0_CON0 0x208 -#define RK3288_CRU_SDIO0_CON1 0x20c -#define RK3288_CRU_SDIO1_CON0 0x210 -#define RK3288_CRU_SDIO1_CON1 0x214 -#define RK3288_CRU_EMMC_CON0 0x218 -#define RK3288_CRU_EMMC_CON1 0x21c - -#endif diff --git a/arch/arm/mach-rockchip/ddr_freq.c b/arch/arm/mach-rockchip/ddr_freq.c index b9c3b19e43ff..3a54cd3a96b1 100644 --- a/arch/arm/mach-rockchip/ddr_freq.c +++ b/arch/arm/mach-rockchip/ddr_freq.c @@ -16,11 +16,10 @@ #include #include #include +#include #include #include -#include "common.h" - enum { DEBUG_DDR = 1U << 0, DEBUG_VIDEO_STATE = 1U << 1, diff --git a/arch/arm/mach-rockchip/ddr_rk30.c b/arch/arm/mach-rockchip/ddr_rk30.c index 5fe2c7aade34..cb545b78e085 100644 --- a/arch/arm/mach-rockchip/ddr_rk30.c +++ b/arch/arm/mach-rockchip/ddr_rk30.c @@ -19,7 +19,7 @@ #include #include -#include "cru.h" +#include typedef uint32_t uint32; diff --git a/arch/arm/mach-rockchip/grf.h b/arch/arm/mach-rockchip/grf.h deleted file mode 100644 index 62a97b4d8420..000000000000 --- a/arch/arm/mach-rockchip/grf.h +++ /dev/null @@ -1,337 +0,0 @@ -#ifndef __MACH_ROCKCHIP_GRF_H -#define __MACH_ROCKCHIP_GRF_H - -#define RK3188_GRF_GPIO0L_DIR 0x0000 -#define RK3188_GRF_GPIO0H_DIR 0x0004 -#define RK3188_GRF_GPIO1L_DIR 0x0008 -#define RK3188_GRF_GPIO1H_DIR 0x000c -#define RK3188_GRF_GPIO2L_DIR 0x0010 -#define RK3188_GRF_GPIO2H_DIR 0x0014 -#define RK3188_GRF_GPIO3L_DIR 0x0018 -#define RK3188_GRF_GPIO3H_DIR 0x001c -#define RK3188_GRF_GPIO0L_DO 0x0020 -#define RK3188_GRF_GPIO0H_DO 0x0024 -#define RK3188_GRF_GPIO1L_DO 0x0028 -#define RK3188_GRF_GPIO1H_DO 0x002c -#define RK3188_GRF_GPIO2L_DO 0x0030 -#define RK3188_GRF_GPIO2H_DO 0x0034 -#define RK3188_GRF_GPIO3L_DO 0x0038 -#define RK3188_GRF_GPIO3H_DO 0x003c -#define RK3188_GRF_GPIO0L_EN 0x0040 -#define RK3188_GRF_GPIO0H_EN 0x0044 -#define RK3188_GRF_GPIO1L_EN 0x0048 -#define RK3188_GRF_GPIO1H_EN 0x004c -#define RK3188_GRF_GPIO2L_EN 0x0050 -#define RK3188_GRF_GPIO2H_EN 0x0054 -#define RK3188_GRF_GPIO3L_EN 0x0058 -#define RK3188_GRF_GPIO3H_EN 0x005c - -#define RK3188_GRF_GPIO0C_IOMUX 0x0068 -#define RK3188_GRF_GPIO0D_IOMUX 0x006c -#define RK3188_GRF_GPIO1A_IOMUX 0x0070 -#define RK3188_GRF_GPIO1B_IOMUX 0x0074 -#define RK3188_GRF_GPIO1C_IOMUX 0x0078 -#define RK3188_GRF_GPIO1D_IOMUX 0x007c -#define RK3188_GRF_GPIO2A_IOMUX 0x0080 -#define RK3188_GRF_GPIO2B_IOMUX 0x0084 -#define RK3188_GRF_GPIO2C_IOMUX 0x0088 -#define RK3188_GRF_GPIO2D_IOMUX 0x008c -#define RK3188_GRF_GPIO3A_IOMUX 0x0090 -#define RK3188_GRF_GPIO3B_IOMUX 0x0094 -#define RK3188_GRF_GPIO3C_IOMUX 0x0098 -#define RK3188_GRF_GPIO3D_IOMUX 0x009c -#define RK3188_GRF_SOC_CON0 0x00a0 -#define RK3188_GRF_SOC_CON1 0x00a4 -#define RK3188_GRF_SOC_CON2 0x00a8 -#define RK3188_GRF_SOC_STATUS0 0x00ac -#define RK3188_GRF_DMAC1_CON0 0x00b0 -#define RK3188_GRF_DMAC1_CON1 0x00b4 -#define RK3188_GRF_DMAC1_CON2 0x00b8 -#define RK3188_GRF_DMAC2_CON0 0x00bc -#define RK3188_GRF_DMAC2_CON1 0x00c0 -#define RK3188_GRF_DMAC2_CON2 0x00c4 -#define RK3188_GRF_DMAC2_CON3 0x00c8 -#define RK3188_GRF_CPU_CON0 0x00cc -#define RK3188_GRF_CPU_CON1 0x00d0 -#define RK3188_GRF_CPU_CON2 0x00d4 -#define RK3188_GRF_CPU_CON3 0x00d8 -#define RK3188_GRF_CPU_CON4 0x00dc -#define RK3188_GRF_CPU_CON5 0x00e0 - -#define RK3188_GRF_DDRC_CON0 0x00ec -#define RK3188_GRF_DDRC_STAT 0x00f0 -#define RK3188_GRF_IO_CON0 0x00f4 -#define RK3188_GRF_IO_CON1 0x00f8 -#define RK3188_GRF_IO_CON2 0x00fc -#define RK3188_GRF_IO_CON3 0x0100 -#define RK3188_GRF_IO_CON4 0x0104 -#define RK3188_GRF_SOC_STATUS1 0x0108 -#define RK3188_GRF_UOC0_CON0 0x010c -#define RK3188_GRF_UOC0_CON1 0x0110 -#define RK3188_GRF_UOC0_CON2 0x0114 -#define RK3188_GRF_UOC0_CON3 0x0118 -#define RK3188_GRF_UOC1_CON0 0x011c -#define RK3188_GRF_UOC1_CON1 0x0120 -#define RK3188_GRF_UOC1_CON2 0x0124 -#define RK3188_GRF_UOC1_CON3 0x0128 -#define RK3188_GRF_UOC2_CON0 0x012c -#define RK3188_GRF_UOC2_CON1 0x0130 - -#define RK3188_GRF_UOC3_CON0 0x0138 -#define RK3188_GRF_UOC3_CON1 0x013c -#define RK3188_GRF_HSIC_STAT 0x0140 -#define RK3188_GRF_OS_REG0 0x0144 -#define RK3188_GRF_OS_REG1 0x0148 -#define RK3188_GRF_OS_REG2 0x014c -#define RK3188_GRF_OS_REG3 0x0150 -#define RK3188_GRF_OS_REG4 0x0154 -#define RK3188_GRF_OS_REG5 0x0158 -#define RK3188_GRF_OS_REG6 0x015c -#define RK3188_GRF_OS_REG7 0x0160 -#define RK3188_GRF_GPIO0B_PULL 0x0164 -#define RK3188_GRF_GPIO0C_PULL 0x0168 -#define RK3188_GRF_GPIO0D_PULL 0x016c -#define RK3188_GRF_GPIO1A_PULL 0x0170 -#define RK3188_GRF_GPIO1B_PULL 0x0174 -#define RK3188_GRF_GPIO1C_PULL 0x0178 -#define RK3188_GRF_GPIO1D_PULL 0x017c -#define RK3188_GRF_GPIO2A_PULL 0x0180 -#define RK3188_GRF_GPIO2B_PULL 0x0184 -#define RK3188_GRF_GPIO2C_PULL 0x0188 -#define RK3188_GRF_GPIO2D_PULL 0x018c -#define RK3188_GRF_GPIO3A_PULL 0x0190 -#define RK3188_GRF_GPIO3B_PULL 0x0194 -#define RK3188_GRF_GPIO3C_PULL 0x0198 -#define RK3188_GRF_GPIO3D_PULL 0x019c -#define RK3188_GRF_FLASH_DATA_PULL 0x01a0 -#define RK3188_GRF_FLASH_CMD_PULL 0x01a4 - -#define RK3288_GRF_GPIO1D_IOMUX 0x000c -#define RK3288_GRF_GPIO2A_IOMUX 0x0010 -#define RK3288_GRF_GPIO2B_IOMUX 0x0014 -#define RK3288_GRF_GPIO2C_IOMUX 0x0018 - -#define RK3288_GRF_GPIO3A_IOMUX 0x0020 -#define RK3288_GRF_GPIO3B_IOMUX 0x0024 -#define RK3288_GRF_GPIO3C_IOMUX 0x0028 -#define RK3288_GRF_GPIO3DL_IOMUX 0x002c -#define RK3288_GRF_GPIO3DH_IOMUX 0x0030 -#define RK3288_GRF_GPIO4AL_IOMUX 0x0034 -#define RK3288_GRF_GPIO4AH_IOMUX 0x0038 -#define RK3288_GRF_GPIO4BL_IOMUX 0x003c - -#define RK3288_GRF_GPIO4C_IOMUX 0x0044 -#define RK3288_GRF_GPIO4D_IOMUX 0x0048 - -#define RK3288_GRF_GPIO5B_IOMUX 0x0050 -#define RK3288_GRF_GPIO5C_IOMUX 0x0054 - -#define RK3288_GRF_GPIO6A_IOMUX 0x005c -#define RK3288_GRF_GPIO6B_IOMUX 0x0060 -#define RK3288_GRF_GPIO6C_IOMUX 0x0064 - -#define RK3288_GRF_GPIO7A_IOMUX 0x006c -#define RK3288_GRF_GPIO7B_IOMUX 0x0070 -#define RK3288_GRF_GPIO7CL_IOMUX 0x0074 -#define RK3288_GRF_GPIO7CH_IOMUX 0x0078 - -#define RK3288_GRF_GPIO8A_IOMUX 0x0080 -#define RK3288_GRF_GPIO8B_IOMUX 0x0084 - -#define RK3288_GRF_GPIO1H_SR 0x0104 -#define RK3288_GRF_GPIO2L_SR 0x0108 -#define RK3288_GRF_GPIO2H_SR 0x010c -#define RK3288_GRF_GPIO3L_SR 0x0110 -#define RK3288_GRF_GPIO3H_SR 0x0114 -#define RK3288_GRF_GPIO4L_SR 0x0118 -#define RK3288_GRF_GPIO4H_SR 0x011c -#define RK3288_GRF_GPIO5L_SR 0x0120 -#define RK3288_GRF_GPIO5H_SR 0x0124 -#define RK3288_GRF_GPIO6L_SR 0x0128 -#define RK3288_GRF_GPIO6H_SR 0x012c -#define RK3288_GRF_GPIO7L_SR 0x0130 -#define RK3288_GRF_GPIO7H_SR 0x0134 -#define RK3288_GRF_GPIO8L_SR 0x0138 - -#define RK3288_GRF_GPIO1D_P 0x014c -#define RK3288_GRF_GPIO2A_P 0x0150 -#define RK3288_GRF_GPIO2B_P 0x0154 -#define RK3288_GRF_GPIO2C_P 0x0158 - -#define RK3288_GRF_GPIO3A_P 0x0160 -#define RK3288_GRF_GPIO3B_P 0x0164 -#define RK3288_GRF_GPIO3C_P 0x0168 -#define RK3288_GRF_GPIO3D_P 0x016c -#define RK3288_GRF_GPIO4A_P 0x0170 -#define RK3288_GRF_GPIO4B_P 0x0174 -#define RK3288_GRF_GPIO4C_P 0x0178 -#define RK3288_GRF_GPIO4D_P 0x017c - -#define RK3288_GRF_GPIO5B_P 0x0184 -#define RK3288_GRF_GPIO5C_P 0x0188 - -#define RK3288_GRF_GPIO6A_P 0x0190 -#define RK3288_GRF_GPIO6B_P 0x0194 -#define RK3288_GRF_GPIO6C_P 0x0198 - -#define RK3288_GRF_GPIO7A_P 0x01a0 -#define RK3288_GRF_GPIO7B_P 0x01a4 -#define RK3288_GRF_GPIO7C_P 0x01a8 - -#define RK3288_GRF_GPIO8A_P 0x01b0 -#define RK3288_GRF_GPIO8B_P 0x01b4 - -#define RK3288_GRF_GPIO1D_E 0x01cc -#define RK3288_GRF_GPIO2A_E 0x01d0 -#define RK3288_GRF_GPIO2B_E 0x01d4 -#define RK3288_GRF_GPIO2C_E 0x01d8 - -#define RK3288_GRF_GPIO3A_E 0x01e0 -#define RK3288_GRF_GPIO3B_E 0x01e4 -#define RK3288_GRF_GPIO3C_E 0x01e8 -#define RK3288_GRF_GPIO3D_E 0x01ec -#define RK3288_GRF_GPIO4A_E 0x01f0 -#define RK3288_GRF_GPIO4B_E 0x01f4 -#define RK3288_GRF_GPIO4C_E 0x01f8 -#define RK3288_GRF_GPIO4D_E 0x01fc - -#define RK3288_GRF_GPIO5B_E 0x0204 -#define RK3288_GRF_GPIO5C_E 0x0208 - -#define RK3288_GRF_GPIO6A_E 0x0210 -#define RK3288_GRF_GPIO6B_E 0x0214 -#define RK3288_GRF_GPIO6C_E 0x0218 - -#define RK3288_GRF_GPIO7A_E 0x0220 -#define RK3288_GRF_GPIO7B_E 0x0224 -#define RK3288_GRF_GPIO7C_E 0x0228 - -#define RK3288_GRF_GPIO8A_E 0x0230 -#define RK3288_GRF_GPIO8B_E 0x0234 - -#define RK3288_GRF_GPIO_SMT 0x0240 -#define RK3288_GRF_SOC_CON0 0x0244 -#define RK3288_GRF_SOC_CON1 0x0248 -#define RK3288_GRF_SOC_CON2 0x024c -#define RK3288_GRF_SOC_CON3 0x0250 -#define RK3288_GRF_SOC_CON4 0x0254 -#define RK3288_GRF_SOC_CON5 0x0258 -#define RK3288_GRF_SOC_CON6 0x025c -#define RK3288_GRF_SOC_CON7 0x0260 -#define RK3288_GRF_SOC_CON8 0x0264 -#define RK3288_GRF_SOC_CON9 0x0268 -#define RK3288_GRF_SOC_CON10 0x026c -#define RK3288_GRF_SOC_CON11 0x0270 -#define RK3288_GRF_SOC_CON12 0x0274 -#define RK3288_GRF_SOC_CON13 0x0278 -#define RK3288_GRF_SOC_CON14 0x027c -#define RK3288_GRF_SOC_STATUS0 0x0280 -#define RK3288_GRF_SOC_STATUS1 0x0284 -#define RK3288_GRF_SOC_STATUS2 0x0288 -#define RK3288_GRF_SOC_STATUS3 0x028c -#define RK3288_GRF_SOC_STATUS4 0x0290 -#define RK3288_GRF_SOC_STATUS5 0x0294 -#define RK3288_GRF_SOC_STATUS6 0x0298 -#define RK3288_GRF_SOC_STATUS7 0x029c -#define RK3288_GRF_SOC_STATUS8 0x02a0 -#define RK3288_GRF_SOC_STATUS9 0x02a4 -#define RK3288_GRF_SOC_STATUS10 0x02a8 -#define RK3288_GRF_SOC_STATUS11 0x02ac -#define RK3288_GRF_SOC_STATUS12 0x02b0 -#define RK3288_GRF_SOC_STATUS13 0x02b4 -#define RK3288_GRF_SOC_STATUS14 0x02b8 -#define RK3288_GRF_SOC_STATUS15 0x02bc -#define RK3288_GRF_SOC_STATUS16 0x02c0 -#define RK3288_GRF_SOC_STATUS17 0x02c4 -#define RK3288_GRF_SOC_STATUS18 0x02c8 -#define RK3288_GRF_SOC_STATUS19 0x02cc -#define RK3288_GRF_SOC_STATUS20 0x02d0 -#define RK3288_GRF_SOC_STATUS21 0x02d4 - -#define RK3288_GRF_PERIDMAC_CON0 0x02e0 -#define RK3288_GRF_PERIDMAC_CON1 0x02e4 -#define RK3288_GRF_PERIDMAC_CON2 0x02e8 -#define RK3288_GRF_PERIDMAC_CON3 0x02ec -#define RK3288_GRF_DDRC0_CON0 0x02f0 -#define RK3288_GRF_DDRC1_CON0 0x02f4 -#define RK3288_GRF_CPU_CON0 0x02f8 -#define RK3288_GRF_CPU_CON1 0x02fc -#define RK3288_GRF_CPU_CON2 0x0300 -#define RK3288_GRF_CPU_CON3 0x0304 -#define RK3288_GRF_CPU_CON4 0x0308 - -#define RK3288_GRF_CPU_STATUS0 0x0318 - -#define RK3288_GRF_UOC0_CON0 0x0320 -#define RK3288_GRF_UOC0_CON1 0x0324 -#define RK3288_GRF_UOC0_CON2 0x0328 -#define RK3288_GRF_UOC0_CON3 0x032c -#define RK3288_GRF_UOC0_CON4 0x0330 -#define RK3288_GRF_UOC1_CON0 0x0334 -#define RK3288_GRF_UOC1_CON1 0x0338 -#define RK3288_GRF_UOC1_CON2 0x033c -#define RK3288_GRF_UOC1_CON3 0x0340 -#define RK3288_GRF_UOC1_CON4 0x0344 -#define RK3288_GRF_UOC2_CON0 0x0348 -#define RK3288_GRF_UOC2_CON1 0x034c -#define RK3288_GRF_UOC2_CON2 0x0350 -#define RK3288_GRF_UOC2_CON3 0x0354 -#define RK3288_GRF_UOC3_CON0 0x0358 -#define RK3288_GRF_UOC3_CON1 0x035c -#define RK3288_GRF_UOC4_CON0 0x0360 -#define RK3288_GRF_UOC4_CON1 0x0364 -#define RK3288_GRF_PVTM_CON0 0x0368 -#define RK3288_GRF_PVTM_CON1 0x036c -#define RK3288_GRF_PVTM_CON2 0x0370 -#define RK3288_GRF_PVTM_STATUS0 0x0374 -#define RK3288_GRF_PVTM_STATUS1 0x0378 -#define RK3288_GRF_PVTM_STATUS2 0x037c -#define RK3288_GRF_IO_VSEL 0x0380 -#define RK3288_GRF_SARADC_TESTBIT 0x0384 -#define RK3288_GRF_TSADC_TESTBIT_L 0x0388 -#define RK3288_GRF_TSADC_TESTBIT_H 0x038c -#define RK3288_GRF_OS_REG0 0x0390 -#define RK3288_GRF_OS_REG1 0x0394 -#define RK3288_GRF_OS_REG2 0x0398 -#define RK3288_GRF_OS_REG3 0x039c - -#define RK3288_GRF_SOC_CON15 0x03a4 -#define RK3288_GRF_SOC_CON16 0x03a8 - -#define RK3288_SGRF_SOC_CON0 0x0000 -#define RK3288_SGRF_SOC_CON1 0x0004 -#define RK3288_SGRF_SOC_CON2 0x0008 -#define RK3288_SGRF_SOC_CON3 0x000c -#define RK3288_SGRF_SOC_CON4 0x0010 -#define RK3288_SGRF_SOC_CON5 0x0014 - -#define RK3288_SGRF_BUSDMAC_CON0 0x0020 -#define RK3288_SGRF_BUSDMAC_CON1 0x0024 - -#define RK3288_SGRF_CPU_CON0 0x0040 -#define RK3288_SGRF_CPU_CON1 0x0044 -#define RK3288_SGRF_CPU_CON2 0x0048 - -#define RK3288_SGRF_SOC_CON6 0x0050 -#define RK3288_SGRF_SOC_CON7 0x0054 -#define RK3288_SGRF_SOC_CON8 0x0058 -#define RK3288_SGRF_SOC_CON9 0x005c -#define RK3288_SGRF_SOC_CON10 0x0060 -#define RK3288_SGRF_SOC_CON11 0x0064 -#define RK3288_SGRF_SOC_CON12 0x0068 -#define RK3288_SGRF_SOC_CON13 0x006c -#define RK3288_SGRF_SOC_CON14 0x0070 -#define RK3288_SGRF_SOC_CON15 0x0074 -#define RK3288_SGRF_SOC_CON16 0x0078 -#define RK3288_SGRF_SOC_CON17 0x007c -#define RK3288_SGRF_SOC_CON18 0x0080 -#define RK3288_SGRF_SOC_CON19 0x0084 -#define RK3288_SGRF_SOC_CON20 0x0088 -#define RK3288_SGRF_SOC_CON21 0x008c - -#define RK3288_SGRF_SOC_STATUS0 0x0100 -#define RK3288_SGRF_SOC_STATUS1 0x0104 - -#define RK3288_SGRF_FAST_BOOT_ADDR 0x0120 - -#endif diff --git a/arch/arm/mach-rockchip/hotplug.c b/arch/arm/mach-rockchip/hotplug.c index cfd1627588cd..1d00865e8f0e 100644 --- a/arch/arm/mach-rockchip/hotplug.c +++ b/arch/arm/mach-rockchip/hotplug.c @@ -12,13 +12,13 @@ #include #include #include +#include #include #include #include #include -#include "common.h" #include "pmu.h" static cpumask_t dead_cpus; diff --git a/arch/arm/mach-rockchip/iomap.h b/arch/arm/mach-rockchip/iomap.h deleted file mode 100644 index af834fad8419..000000000000 --- a/arch/arm/mach-rockchip/iomap.h +++ /dev/null @@ -1,106 +0,0 @@ -#ifndef __MACH_ROCKCHIP_IOMAP_H -#define __MACH_ROCKCHIP_IOMAP_H - -#ifndef __ASSEMBLY__ -#include -#endif - -#define RK_IO_ADDRESS(x) IOMEM(0xFED00000 + x) - -#define RK_CRU_VIRT RK_IO_ADDRESS(0x00000000) -#define RK_GRF_VIRT RK_IO_ADDRESS(0x00010000) -#define RK_SGRF_VIRT (RK_GRF_VIRT + 0x1000) -#define RK_PMU_VIRT RK_IO_ADDRESS(0x00020000) -#define RK_ROM_VIRT RK_IO_ADDRESS(0x00030000) -#define RK_EFUSE_VIRT RK_IO_ADDRESS(0x00040000) -#define RK_GPIO_VIRT(n) RK_IO_ADDRESS(0x00050000 + (n) * 0x1000) -#define RK_DEBUG_UART_VIRT RK_IO_ADDRESS(0x00060000) -#define RK_CPU_AXI_BUS_VIRT RK_IO_ADDRESS(0x00070000) -#define RK_TIMER_VIRT RK_IO_ADDRESS(0x00080000) -#define RK_DDR_VIRT RK_IO_ADDRESS(0x000d0000) - -#define RK3188_CRU_PHYS 0x20000000 -#define RK3188_CRU_SIZE SZ_4K -#define RK3188_GRF_PHYS 0x20008000 -#define RK3188_GRF_SIZE SZ_4K -#define RK3188_PMU_PHYS 0x20004000 -#define RK3188_PMU_SIZE SZ_4K -#define RK3188_ROM_PHYS 0x10120000 -#define RK3188_ROM_SIZE SZ_16K -#define RK3188_EFUSE_PHYS 0x20010000 -#define RK3188_EFUSE_SIZE SZ_4K -#define RK3188_GPIO0_PHYS 0x2000a000 -#define RK3188_GPIO1_PHYS 0x2003c000 -#define RK3188_GPIO2_PHYS 0x2003e000 -#define RK3188_GPIO3_PHYS 0x20080000 -#define RK3188_GPIO_SIZE SZ_4K -#define RK3188_CPU_AXI_BUS_PHYS 0x10128000 -#define RK3188_CPU_AXI_BUS_SIZE SZ_32K -#define RK3188_TIMER0_PHYS 0x20038000 -#define RK3188_TIMER3_PHYS 0x2000e000 -#define RK3188_TIMER_SIZE SZ_4K -#define RK3188_DDR_PCTL_PHYS 0x20020000 -#define RK3188_DDR_PCTL_SIZE SZ_4K -#define RK3188_DDR_PUBL_PHYS 0x20040000 -#define RK3188_DDR_PUBL_SIZE SZ_4K -#define RK3188_UART0_PHYS 0x10124000 -#define RK3188_UART1_PHYS 0x10126000 -#define RK3188_UART2_PHYS 0x20064000 -#define RK3188_UART3_PHYS 0x20068000 -#define RK3188_UART_SIZE SZ_4K - -#define RK3288_CRU_PHYS 0xFF760000 -#define RK3288_CRU_SIZE SZ_4K -#define RK3288_GRF_PHYS 0xFF770000 -#define RK3288_GRF_SIZE SZ_4K -#define RK3288_SGRF_PHYS 0xFF740000 -#define RK3288_SGRF_SIZE SZ_4K -#define RK3288_PMU_PHYS 0xFF730000 -#define RK3288_PMU_SIZE SZ_4K -#define RK3288_ROM_PHYS 0xFFFD0000 -#define RK3288_ROM_SIZE (SZ_16K + SZ_4K) -#define RK3288_EFUSE_PHYS 0xFFB40000 -#define RK3288_EFUSE_SIZE SZ_4K -#define RK3288_GPIO0_PHYS 0xFF750000 -#define RK3288_GPIO1_PHYS 0xFF780000 -#define RK3288_GPIO2_PHYS 0xFF790000 -#define RK3288_GPIO3_PHYS 0xFF7A0000 -#define RK3288_GPIO4_PHYS 0xFF7B0000 -#define RK3288_GPIO5_PHYS 0xFF7C0000 -#define RK3288_GPIO6_PHYS 0xFF7D0000 -#define RK3288_GPIO7_PHYS 0xFF7E0000 -#define RK3288_GPIO8_PHYS 0xFF7F0000 -#define RK3288_GPIO_SIZE SZ_4K -#define RK3288_SERVICE_CORE_PHYS 0XFFA80000 -#define RK3288_SERVICE_CORE_SIZE SZ_4K -#define RK3288_SERVICE_DMAC_PHYS 0XFFA90000 -#define RK3288_SERVICE_DMAC_SIZE SZ_4K -#define RK3288_SERVICE_GPU_PHYS 0XFFAA0000 -#define RK3288_SERVICE_GPU_SIZE SZ_4K -#define RK3288_SERVICE_PERI_PHYS 0XFFAB0000 -#define RK3288_SERVICE_PERI_SIZE SZ_4K -#define RK3288_SERVICE_BUS_PHYS 0XFFAC0000 -#define RK3288_SERVICE_BUS_SIZE SZ_16K -#define RK3288_SERVICE_VIO_PHYS 0XFFAD0000 -#define RK3288_SERVICE_VIO_SIZE SZ_4K -#define RK3288_SERVICE_VPU_PHYS 0XFFAE0000 -#define RK3288_SERVICE_VPU_SIZE SZ_4K -#define RK3288_SERVICE_HEVC_PHYS 0XFFAF0000 -#define RK3288_SERVICE_HEVC_SIZE SZ_4K -#define RK3288_TIMER0_PHYS 0xFF6B0000 -#define RK3288_TIMER6_PHYS 0xFF810000 -#define RK3288_TIMER_SIZE SZ_4K -#define RK3288_DDR_PCTL0_PHYS 0xFF610000 -#define RK3288_DDR_PCTL1_PHYS 0xFF630000 -#define RK3288_DDR_PCTL_SIZE SZ_4K -#define RK3288_DDR_PUBL0_PHYS 0xFF620000 -#define RK3288_DDR_PUBL1_PHYS 0xFF640000 -#define RK3288_DDR_PUBL_SIZE SZ_4K -#define RK3288_UART_BT_PHYS 0xFF180000 -#define RK3288_UART_BB_PHYS 0xFF190000 -#define RK3288_UART_DBG_PHYS 0xFF690000 -#define RK3288_UART_GPS_PHYS 0xFF1B0000 -#define RK3288_UART_EXP_PHYS 0xFF1C0000 -#define RK3288_UART_SIZE SZ_4K - -#endif diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c index ce2be6cde566..d0358a372ae6 100644 --- a/arch/arm/mach-rockchip/platsmp.c +++ b/arch/arm/mach-rockchip/platsmp.c @@ -20,13 +20,13 @@ #include #include #include +#include #include #include #include #include -#include "common.h" #include "pmu.h" #define SCU_CTRL 0x00 diff --git a/arch/arm/mach-rockchip/rk3188-cpufreq.c b/arch/arm/mach-rockchip/rk3188-cpufreq.c index 3a66589d0f29..55f5ec04088d 100644 --- a/arch/arm/mach-rockchip/rk3188-cpufreq.c +++ b/arch/arm/mach-rockchip/rk3188-cpufreq.c @@ -26,14 +26,13 @@ #include #include #include +#include #include #include #include #include #include -#include "cpu.h" - #define VERSION "2.2" #ifdef DEBUG diff --git a/arch/arm/mach-rockchip/rk3188.c b/arch/arm/mach-rockchip/rk3188.c index 0d3b8c74af06..976de3a29db1 100644 --- a/arch/arm/mach-rockchip/rk3188.c +++ b/arch/arm/mach-rockchip/rk3188.c @@ -22,14 +22,14 @@ #include #include #include +#include +#include +#include +#include +#include #include #include -#include "common.h" -#include "cpu.h" #include "cpu_axi.h" -#include "cru.h" -#include "grf.h" -#include "iomap.h" #include "loader.h" #include "pmu.h" #include "sram.h" diff --git a/arch/arm/mach-rockchip/rk3288.c b/arch/arm/mach-rockchip/rk3288.c index d7fac3150ea0..d1aaeab4559b 100644 --- a/arch/arm/mach-rockchip/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288.c @@ -21,15 +21,15 @@ #include #include #include +#include +#include +#include +#include +#include +#include #include #include -#include -#include "common.h" -#include "cpu.h" #include "cpu_axi.h" -#include "cru.h" -#include "grf.h" -#include "iomap.h" #include "loader.h" #include "pmu.h" #include "sram.h" diff --git a/arch/arm/mach-rockchip/vcodec_service.c b/arch/arm/mach-rockchip/vcodec_service.c index 6298d3f0edda..24567074c3b5 100755 --- a/arch/arm/mach-rockchip/vcodec_service.c +++ b/arch/arm/mach-rockchip/vcodec_service.c @@ -33,6 +33,8 @@ #include #include #include +#include +#include #include #include @@ -41,14 +43,11 @@ #include #endif -#include "cru.h" - #if defined(CONFIG_ARCH_RK319X) #include #endif #include "vcodec_service.h" -#include "cpu.h" #define HEVC_TEST_ENABLE 0 #define HEVC_SIM_ENABLE 0 diff --git a/arch/arm/mach-rockchip/vpu_service.c b/arch/arm/mach-rockchip/vpu_service.c index 17bca4a72cf1..cdcc7f6786ca 100755 --- a/arch/arm/mach-rockchip/vpu_service.c +++ b/arch/arm/mach-rockchip/vpu_service.c @@ -38,6 +38,8 @@ #include #include #include +#include +#include #include #if 0 @@ -47,22 +49,12 @@ #define IRQ_VEPU 41 #define IRQ_VDPU 42 #endif -#if 0 -#include -#else -#include "cru.h" -#endif #if defined(CONFIG_ARCH_RK319X) #include #endif -#if 0 -#include -#include -#else + #include "vpu_service.h" -#include "cpu.h" -#endif typedef enum { VPU_DEC_ID_9190 = 0x6731, diff --git a/drivers/clk/rockchip/clk-ops.c b/drivers/clk/rockchip/clk-ops.c index 73a19d59c911..0f3f50c70cf8 100644 --- a/drivers/clk/rockchip/clk-ops.c +++ b/drivers/clk/rockchip/clk-ops.c @@ -6,11 +6,9 @@ #include #include #include +#include #include "clk-ops.h" -#include "../../../arch/arm/mach-rockchip/common.h" - - /* mux_ops */ struct clk_ops_table rk_clk_mux_ops_table[] = { diff --git a/drivers/clk/rockchip/clk-ops.h b/drivers/clk/rockchip/clk-ops.h index d5ab53e963a3..933bd029e795 100644 --- a/drivers/clk/rockchip/clk-ops.h +++ b/drivers/clk/rockchip/clk-ops.h @@ -1,9 +1,9 @@ #ifndef __RK_CLK_OPS_H #define __RK_CLK_OPS_H -#include -#include "../../../arch/arm/mach-rockchip/iomap.h" -#include "../../../arch/arm/mach-rockchip/grf.h" +#include +#include +#include #define MHZ (1000UL * 1000UL) #define KHZ (1000UL) diff --git a/drivers/clk/rockchip/clk-pll.h b/drivers/clk/rockchip/clk-pll.h index 53d8a7c55f8a..ba87874a7fba 100644 --- a/drivers/clk/rockchip/clk-pll.h +++ b/drivers/clk/rockchip/clk-pll.h @@ -3,7 +3,7 @@ #include #include -#include "../../../arch/arm/mach-rockchip/cru.h" +#include #define CLK_LOOPS_JIFFY_REF (11996091ULL) diff --git a/drivers/net/ethernet/rk/vmac/rk29_vmac_phy.c b/drivers/net/ethernet/rk/vmac/rk29_vmac_phy.c index 2adb9f9bc8ba..7bf19658bc24 100755 --- a/drivers/net/ethernet/rk/vmac/rk29_vmac_phy.c +++ b/drivers/net/ethernet/rk/vmac/rk29_vmac_phy.c @@ -21,8 +21,8 @@ #include #include -#include "../../../../../arch/arm/mach-rockchip/iomap.h" -#include "../../../../../arch/arm/mach-rockchip/grf.h" +#include +#include #include "rk29_vmac.h" diff --git a/drivers/video/rockchip/lcdc/rk3188_lcdc.c b/drivers/video/rockchip/lcdc/rk3188_lcdc.c index 8d26fe0475c8..55b77231efda 100755 --- a/drivers/video/rockchip/lcdc/rk3188_lcdc.c +++ b/drivers/video/rockchip/lcdc/rk3188_lcdc.c @@ -28,9 +28,9 @@ #include #include #include -#include "../../../arch/arm/mach-rockchip/cpu.h" -#include "../../../arch/arm/mach-rockchip/iomap.h" -#include "../../../arch/arm/mach-rockchip/grf.h" +#include +#include +#include #include "rk3188_lcdc.h" diff --git a/drivers/video/rockchip/lcdc/rk3288_lcdc.c b/drivers/video/rockchip/lcdc/rk3288_lcdc.c index 47400d42f36e..1bc6972b0307 100755 --- a/drivers/video/rockchip/lcdc/rk3288_lcdc.c +++ b/drivers/video/rockchip/lcdc/rk3288_lcdc.c @@ -26,11 +26,11 @@ #include #include #include +#include +#include +#include #include #include -#include "../../../arch/arm/mach-rockchip/cpu.h" -#include "../../../arch/arm/mach-rockchip/iomap.h" -#include "../../../arch/arm/mach-rockchip/grf.h" #include "rk3288_lcdc.h" diff --git a/drivers/video/rockchip/transmitter/rk32_dp.c b/drivers/video/rockchip/transmitter/rk32_dp.c index a321b4389b0d..d3bf948b490d 100644 --- a/drivers/video/rockchip/transmitter/rk32_dp.c +++ b/drivers/video/rockchip/transmitter/rk32_dp.c @@ -23,9 +23,9 @@ #include #include #include +#include +#include #include "rk32_dp.h" -#include "../../../arch/arm/mach-rockchip/iomap.h" -#include "../../../arch/arm/mach-rockchip/grf.h" #if defined(CONFIG_OF) #include diff --git a/drivers/video/rockchip/transmitter/rk32_dp_reg.c b/drivers/video/rockchip/transmitter/rk32_dp_reg.c index ae9c218b12b8..00fb1cec5700 100644 --- a/drivers/video/rockchip/transmitter/rk32_dp_reg.c +++ b/drivers/video/rockchip/transmitter/rk32_dp_reg.c @@ -13,9 +13,9 @@ #include #include #include -#include "../../../arch/arm/mach-rockchip/cpu.h" -#include "../../../arch/arm/mach-rockchip/iomap.h" -#include "../../../arch/arm/mach-rockchip/grf.h" +#include +#include +#include #include "rk32_dp.h" diff --git a/include/linux/rockchip/common.h b/include/linux/rockchip/common.h new file mode 100644 index 000000000000..31b00d6479cb --- /dev/null +++ b/include/linux/rockchip/common.h @@ -0,0 +1,39 @@ +#ifndef __MACH_ROCKCHIP_COMMON_H +#define __MACH_ROCKCHIP_COMMON_H + +#define RK_DEVICE(VIRT,PHYS,SIZE) \ + { \ + .virtual = (unsigned long)(VIRT), \ + .pfn = __phys_to_pfn(PHYS), \ + .length = SIZE, \ + .type = MT_DEVICE, \ + } + +extern unsigned long rockchip_boot_fn; +extern struct smp_operations rockchip_smp_ops; + +extern int (*ddr_change_freq)(uint32_t nMHz); +extern long (*ddr_round_rate)(uint32_t nMHz); +extern void (*ddr_set_auto_self_refresh)(bool en); + +extern int rockchip_cpu_kill(unsigned int cpu); +extern void rockchip_cpu_die(unsigned int cpu); +extern int rockchip_cpu_disable(unsigned int cpu); + +#define BOOT_MODE_NORMAL 0 +#define BOOT_MODE_FACTORY2 1 +#define BOOT_MODE_RECOVERY 2 +#define BOOT_MODE_CHARGE 3 +#define BOOT_MODE_POWER_TEST 4 +#define BOOT_MODE_OFFMODE_CHARGING 5 +#define BOOT_MODE_REBOOT 6 +#define BOOT_MODE_PANIC 7 +#define BOOT_MODE_WATCHDOG 8 +#define BOOT_MODE_TSADC 9 + +extern int rockchip_boot_mode(void); +extern void __init rockchip_boot_mode_init(u32 flag, u32 mode); +extern void rockchip_restart_get_boot_mode(const char *cmd, u32 *flag, u32 *mode); +extern void __init rockchip_suspend_init(void); + +#endif diff --git a/include/linux/rockchip/cpu.h b/include/linux/rockchip/cpu.h new file mode 100644 index 000000000000..40f424207cc3 --- /dev/null +++ b/include/linux/rockchip/cpu.h @@ -0,0 +1,57 @@ +#ifndef __MACH_ROCKCHIP_CPU_H +#define __MACH_ROCKCHIP_CPU_H + +extern unsigned long rockchip_soc_id; + +static inline bool cpu_is_rockchip(void) { return rockchip_soc_id; } + +#define ROCKCHIP_CPU_MASK 0xffff0000 +#define ROCKCHIP_CPU_RK2928 0x29280000 +#define ROCKCHIP_CPU_RK3026 0x30260000 +#define ROCKCHIP_CPU_RK30XX 0x30660000 +#define ROCKCHIP_CPU_RK3066B 0x31680000 +#define ROCKCHIP_CPU_RK3188 0x31880000 +#define ROCKCHIP_CPU_RK319X 0x31900000 +#define ROCKCHIP_CPU_RK3288 0x32880000 + +static inline bool cpu_is_rk2928(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK2928; } +static inline bool cpu_is_rk3026(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3026; } +static inline bool cpu_is_rk30xx(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK30XX; } +static inline bool cpu_is_rk3066b(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3066B; } +static inline bool cpu_is_rk3188(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3188; } +static inline bool cpu_is_rk319x(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK319X; } +static inline bool cpu_is_rk3288(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3288; } + +#define ROCKCHIP_SOC_RK2926 (ROCKCHIP_CPU_RK2928 | 0x00) +#define ROCKCHIP_SOC_RK2928G (ROCKCHIP_CPU_RK2928 | 0x01) +#define ROCKCHIP_SOC_RK2928L (ROCKCHIP_CPU_RK2928 | 0x02) +#define ROCKCHIP_SOC_RK3028A (ROCKCHIP_CPU_RK3026 | 0x03) +#define ROCKCHIP_SOC_RK3026 (ROCKCHIP_CPU_RK3026 | 0x04) +#define ROCKCHIP_SOC_RK3000 (ROCKCHIP_CPU_RK30XX | 0x00) +#define ROCKCHIP_SOC_RK3066 (ROCKCHIP_CPU_RK30XX | 0x01) +#define ROCKCHIP_SOC_RK3068 (ROCKCHIP_CPU_RK30XX | 0x02) +#define ROCKCHIP_SOC_RK3066B (ROCKCHIP_CPU_RK3066B| 0x00) +#define ROCKCHIP_SOC_RK3168 (ROCKCHIP_CPU_RK3066B| 0x01) +#define ROCKCHIP_SOC_RK3028 (ROCKCHIP_CPU_RK3066B| 0x03) +#define ROCKCHIP_SOC_RK3188 (ROCKCHIP_CPU_RK3188 | 0x00) +#define ROCKCHIP_SOC_RK3188PLUS (ROCKCHIP_CPU_RK3188 | 0x10) +#define ROCKCHIP_SOC_RK3190 (ROCKCHIP_CPU_RK319X | 0x00) +#define ROCKCHIP_SOC_RK3288 (ROCKCHIP_CPU_RK3288 | 0x00) + +static inline bool soc_is_rk2926(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK2926; } +static inline bool soc_is_rk2928g(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK2928G; } +static inline bool soc_is_rk2928l(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK2928L; } +static inline bool soc_is_rk3028a(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3028A; } +static inline bool soc_is_rk3026(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3026; } +static inline bool soc_is_rk3000(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3000; } +static inline bool soc_is_rk3066(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3066; } +static inline bool soc_is_rk3068(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3068; } +static inline bool soc_is_rk3066b(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3066B; } +static inline bool soc_is_rk3168(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3168; } +static inline bool soc_is_rk3028(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3028; } +static inline bool soc_is_rk3188(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3188; } +static inline bool soc_is_rk3188plus(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3188PLUS; } +static inline bool soc_is_rk3190(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3190; } +static inline bool soc_is_rk3288(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3288; } + +#endif diff --git a/include/linux/rockchip/cru.h b/include/linux/rockchip/cru.h new file mode 100644 index 000000000000..8e6255adbe6f --- /dev/null +++ b/include/linux/rockchip/cru.h @@ -0,0 +1,57 @@ +#ifndef __MACH_ROCKCHIP_CRU_H +#define __MACH_ROCKCHIP_CRU_H + +#include + + +/*******************CRU BITS*******************************/ +#define CRU_W_MSK(bits_shift, msk) ((msk) << ((bits_shift) + 16)) +#define CRU_SET_BITS(val, bits_shift, msk) (((val)&(msk)) << (bits_shift)) +#define CRU_W_MSK_SETBITS(val, bits_shift,msk) \ + (CRU_W_MSK(bits_shift, msk) | CRU_SET_BITS(val, bits_shift, msk)) + +/*******************RK3188********************************/ +/*******************CRU OFFSET*********************/ +#define RK3188_CRU_MODE_CON 0x40 +#define RK3188_CRU_CLKSEL_CON 0x44 +#define RK3188_CRU_CLKGATE_CON 0xd0 +#define RK3188_CRU_GLB_SRST_FST 0x100 +#define RK3188_CRU_GLB_SRST_SND 0x104 +#define RK3188_CRU_SOFTRST_CON 0x110 + +#define RK3188_PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4)) + +#define RK3188_CRU_CLKSELS_CON_CNT (35) +#define RK3188_CRU_CLKSELS_CON(i) (RK3188_CRU_CLKSEL_CON + ((i) * 4)) + +#define RK3188_CRU_CLKGATES_CON_CNT (10) +#define RK3188_CRU_CLKGATES_CON(i) (RK3188_CRU_CLKGATE_CON + ((i) * 4)) + +#define RK3188_CRU_SOFTRSTS_CON_CNT (9) +#define RK3188_CRU_SOFTRSTS_CON(i) (RK3188_CRU_SOFTRST_CON + ((i) * 4)) + +#define RK3188_CRU_MISC_CON (0x134) +#define RK3188_CRU_GLB_CNT_TH (0x140) + +/******************PLL MODE BITS*******************/ +#define RK3188_PLL_MODE_MSK(id) (0x3 << ((id) * 4)) +#define RK3188_PLL_MODE_SLOW(id) ((0x0<<((id)*4))|(0x3<<(16+(id)*4))) +#define RK3188_PLL_MODE_NORM(id) ((0x1<<((id)*4))|(0x3<<(16+(id)*4))) +#define RK3188_PLL_MODE_DEEP(id) ((0x2<<((id)*4))|(0x3<<(16+(id)*4))) + +#define RK3288_CRU_GLB_SRST_FST_VALUE 0x1b0 +#define RK3288_CRU_GLB_SRST_SND_VALUE 0x1b4 +#define RK3288_CRU_MISC_CON 0x1e8 +#define RK3288_CRU_GLB_CNT_TH 0x1ec +#define RK3288_CRU_GLB_RST_CON 0x1f0 +#define RK3288_CRU_GLB_RST_ST 0x1f8 +#define RK3288_CRU_SDMMC_CON0 0x200 +#define RK3288_CRU_SDMMC_CON1 0x204 +#define RK3288_CRU_SDIO0_CON0 0x208 +#define RK3288_CRU_SDIO0_CON1 0x20c +#define RK3288_CRU_SDIO1_CON0 0x210 +#define RK3288_CRU_SDIO1_CON1 0x214 +#define RK3288_CRU_EMMC_CON0 0x218 +#define RK3288_CRU_EMMC_CON1 0x21c + +#endif diff --git a/include/linux/rockchip/grf.h b/include/linux/rockchip/grf.h new file mode 100644 index 000000000000..62a97b4d8420 --- /dev/null +++ b/include/linux/rockchip/grf.h @@ -0,0 +1,337 @@ +#ifndef __MACH_ROCKCHIP_GRF_H +#define __MACH_ROCKCHIP_GRF_H + +#define RK3188_GRF_GPIO0L_DIR 0x0000 +#define RK3188_GRF_GPIO0H_DIR 0x0004 +#define RK3188_GRF_GPIO1L_DIR 0x0008 +#define RK3188_GRF_GPIO1H_DIR 0x000c +#define RK3188_GRF_GPIO2L_DIR 0x0010 +#define RK3188_GRF_GPIO2H_DIR 0x0014 +#define RK3188_GRF_GPIO3L_DIR 0x0018 +#define RK3188_GRF_GPIO3H_DIR 0x001c +#define RK3188_GRF_GPIO0L_DO 0x0020 +#define RK3188_GRF_GPIO0H_DO 0x0024 +#define RK3188_GRF_GPIO1L_DO 0x0028 +#define RK3188_GRF_GPIO1H_DO 0x002c +#define RK3188_GRF_GPIO2L_DO 0x0030 +#define RK3188_GRF_GPIO2H_DO 0x0034 +#define RK3188_GRF_GPIO3L_DO 0x0038 +#define RK3188_GRF_GPIO3H_DO 0x003c +#define RK3188_GRF_GPIO0L_EN 0x0040 +#define RK3188_GRF_GPIO0H_EN 0x0044 +#define RK3188_GRF_GPIO1L_EN 0x0048 +#define RK3188_GRF_GPIO1H_EN 0x004c +#define RK3188_GRF_GPIO2L_EN 0x0050 +#define RK3188_GRF_GPIO2H_EN 0x0054 +#define RK3188_GRF_GPIO3L_EN 0x0058 +#define RK3188_GRF_GPIO3H_EN 0x005c + +#define RK3188_GRF_GPIO0C_IOMUX 0x0068 +#define RK3188_GRF_GPIO0D_IOMUX 0x006c +#define RK3188_GRF_GPIO1A_IOMUX 0x0070 +#define RK3188_GRF_GPIO1B_IOMUX 0x0074 +#define RK3188_GRF_GPIO1C_IOMUX 0x0078 +#define RK3188_GRF_GPIO1D_IOMUX 0x007c +#define RK3188_GRF_GPIO2A_IOMUX 0x0080 +#define RK3188_GRF_GPIO2B_IOMUX 0x0084 +#define RK3188_GRF_GPIO2C_IOMUX 0x0088 +#define RK3188_GRF_GPIO2D_IOMUX 0x008c +#define RK3188_GRF_GPIO3A_IOMUX 0x0090 +#define RK3188_GRF_GPIO3B_IOMUX 0x0094 +#define RK3188_GRF_GPIO3C_IOMUX 0x0098 +#define RK3188_GRF_GPIO3D_IOMUX 0x009c +#define RK3188_GRF_SOC_CON0 0x00a0 +#define RK3188_GRF_SOC_CON1 0x00a4 +#define RK3188_GRF_SOC_CON2 0x00a8 +#define RK3188_GRF_SOC_STATUS0 0x00ac +#define RK3188_GRF_DMAC1_CON0 0x00b0 +#define RK3188_GRF_DMAC1_CON1 0x00b4 +#define RK3188_GRF_DMAC1_CON2 0x00b8 +#define RK3188_GRF_DMAC2_CON0 0x00bc +#define RK3188_GRF_DMAC2_CON1 0x00c0 +#define RK3188_GRF_DMAC2_CON2 0x00c4 +#define RK3188_GRF_DMAC2_CON3 0x00c8 +#define RK3188_GRF_CPU_CON0 0x00cc +#define RK3188_GRF_CPU_CON1 0x00d0 +#define RK3188_GRF_CPU_CON2 0x00d4 +#define RK3188_GRF_CPU_CON3 0x00d8 +#define RK3188_GRF_CPU_CON4 0x00dc +#define RK3188_GRF_CPU_CON5 0x00e0 + +#define RK3188_GRF_DDRC_CON0 0x00ec +#define RK3188_GRF_DDRC_STAT 0x00f0 +#define RK3188_GRF_IO_CON0 0x00f4 +#define RK3188_GRF_IO_CON1 0x00f8 +#define RK3188_GRF_IO_CON2 0x00fc +#define RK3188_GRF_IO_CON3 0x0100 +#define RK3188_GRF_IO_CON4 0x0104 +#define RK3188_GRF_SOC_STATUS1 0x0108 +#define RK3188_GRF_UOC0_CON0 0x010c +#define RK3188_GRF_UOC0_CON1 0x0110 +#define RK3188_GRF_UOC0_CON2 0x0114 +#define RK3188_GRF_UOC0_CON3 0x0118 +#define RK3188_GRF_UOC1_CON0 0x011c +#define RK3188_GRF_UOC1_CON1 0x0120 +#define RK3188_GRF_UOC1_CON2 0x0124 +#define RK3188_GRF_UOC1_CON3 0x0128 +#define RK3188_GRF_UOC2_CON0 0x012c +#define RK3188_GRF_UOC2_CON1 0x0130 + +#define RK3188_GRF_UOC3_CON0 0x0138 +#define RK3188_GRF_UOC3_CON1 0x013c +#define RK3188_GRF_HSIC_STAT 0x0140 +#define RK3188_GRF_OS_REG0 0x0144 +#define RK3188_GRF_OS_REG1 0x0148 +#define RK3188_GRF_OS_REG2 0x014c +#define RK3188_GRF_OS_REG3 0x0150 +#define RK3188_GRF_OS_REG4 0x0154 +#define RK3188_GRF_OS_REG5 0x0158 +#define RK3188_GRF_OS_REG6 0x015c +#define RK3188_GRF_OS_REG7 0x0160 +#define RK3188_GRF_GPIO0B_PULL 0x0164 +#define RK3188_GRF_GPIO0C_PULL 0x0168 +#define RK3188_GRF_GPIO0D_PULL 0x016c +#define RK3188_GRF_GPIO1A_PULL 0x0170 +#define RK3188_GRF_GPIO1B_PULL 0x0174 +#define RK3188_GRF_GPIO1C_PULL 0x0178 +#define RK3188_GRF_GPIO1D_PULL 0x017c +#define RK3188_GRF_GPIO2A_PULL 0x0180 +#define RK3188_GRF_GPIO2B_PULL 0x0184 +#define RK3188_GRF_GPIO2C_PULL 0x0188 +#define RK3188_GRF_GPIO2D_PULL 0x018c +#define RK3188_GRF_GPIO3A_PULL 0x0190 +#define RK3188_GRF_GPIO3B_PULL 0x0194 +#define RK3188_GRF_GPIO3C_PULL 0x0198 +#define RK3188_GRF_GPIO3D_PULL 0x019c +#define RK3188_GRF_FLASH_DATA_PULL 0x01a0 +#define RK3188_GRF_FLASH_CMD_PULL 0x01a4 + +#define RK3288_GRF_GPIO1D_IOMUX 0x000c +#define RK3288_GRF_GPIO2A_IOMUX 0x0010 +#define RK3288_GRF_GPIO2B_IOMUX 0x0014 +#define RK3288_GRF_GPIO2C_IOMUX 0x0018 + +#define RK3288_GRF_GPIO3A_IOMUX 0x0020 +#define RK3288_GRF_GPIO3B_IOMUX 0x0024 +#define RK3288_GRF_GPIO3C_IOMUX 0x0028 +#define RK3288_GRF_GPIO3DL_IOMUX 0x002c +#define RK3288_GRF_GPIO3DH_IOMUX 0x0030 +#define RK3288_GRF_GPIO4AL_IOMUX 0x0034 +#define RK3288_GRF_GPIO4AH_IOMUX 0x0038 +#define RK3288_GRF_GPIO4BL_IOMUX 0x003c + +#define RK3288_GRF_GPIO4C_IOMUX 0x0044 +#define RK3288_GRF_GPIO4D_IOMUX 0x0048 + +#define RK3288_GRF_GPIO5B_IOMUX 0x0050 +#define RK3288_GRF_GPIO5C_IOMUX 0x0054 + +#define RK3288_GRF_GPIO6A_IOMUX 0x005c +#define RK3288_GRF_GPIO6B_IOMUX 0x0060 +#define RK3288_GRF_GPIO6C_IOMUX 0x0064 + +#define RK3288_GRF_GPIO7A_IOMUX 0x006c +#define RK3288_GRF_GPIO7B_IOMUX 0x0070 +#define RK3288_GRF_GPIO7CL_IOMUX 0x0074 +#define RK3288_GRF_GPIO7CH_IOMUX 0x0078 + +#define RK3288_GRF_GPIO8A_IOMUX 0x0080 +#define RK3288_GRF_GPIO8B_IOMUX 0x0084 + +#define RK3288_GRF_GPIO1H_SR 0x0104 +#define RK3288_GRF_GPIO2L_SR 0x0108 +#define RK3288_GRF_GPIO2H_SR 0x010c +#define RK3288_GRF_GPIO3L_SR 0x0110 +#define RK3288_GRF_GPIO3H_SR 0x0114 +#define RK3288_GRF_GPIO4L_SR 0x0118 +#define RK3288_GRF_GPIO4H_SR 0x011c +#define RK3288_GRF_GPIO5L_SR 0x0120 +#define RK3288_GRF_GPIO5H_SR 0x0124 +#define RK3288_GRF_GPIO6L_SR 0x0128 +#define RK3288_GRF_GPIO6H_SR 0x012c +#define RK3288_GRF_GPIO7L_SR 0x0130 +#define RK3288_GRF_GPIO7H_SR 0x0134 +#define RK3288_GRF_GPIO8L_SR 0x0138 + +#define RK3288_GRF_GPIO1D_P 0x014c +#define RK3288_GRF_GPIO2A_P 0x0150 +#define RK3288_GRF_GPIO2B_P 0x0154 +#define RK3288_GRF_GPIO2C_P 0x0158 + +#define RK3288_GRF_GPIO3A_P 0x0160 +#define RK3288_GRF_GPIO3B_P 0x0164 +#define RK3288_GRF_GPIO3C_P 0x0168 +#define RK3288_GRF_GPIO3D_P 0x016c +#define RK3288_GRF_GPIO4A_P 0x0170 +#define RK3288_GRF_GPIO4B_P 0x0174 +#define RK3288_GRF_GPIO4C_P 0x0178 +#define RK3288_GRF_GPIO4D_P 0x017c + +#define RK3288_GRF_GPIO5B_P 0x0184 +#define RK3288_GRF_GPIO5C_P 0x0188 + +#define RK3288_GRF_GPIO6A_P 0x0190 +#define RK3288_GRF_GPIO6B_P 0x0194 +#define RK3288_GRF_GPIO6C_P 0x0198 + +#define RK3288_GRF_GPIO7A_P 0x01a0 +#define RK3288_GRF_GPIO7B_P 0x01a4 +#define RK3288_GRF_GPIO7C_P 0x01a8 + +#define RK3288_GRF_GPIO8A_P 0x01b0 +#define RK3288_GRF_GPIO8B_P 0x01b4 + +#define RK3288_GRF_GPIO1D_E 0x01cc +#define RK3288_GRF_GPIO2A_E 0x01d0 +#define RK3288_GRF_GPIO2B_E 0x01d4 +#define RK3288_GRF_GPIO2C_E 0x01d8 + +#define RK3288_GRF_GPIO3A_E 0x01e0 +#define RK3288_GRF_GPIO3B_E 0x01e4 +#define RK3288_GRF_GPIO3C_E 0x01e8 +#define RK3288_GRF_GPIO3D_E 0x01ec +#define RK3288_GRF_GPIO4A_E 0x01f0 +#define RK3288_GRF_GPIO4B_E 0x01f4 +#define RK3288_GRF_GPIO4C_E 0x01f8 +#define RK3288_GRF_GPIO4D_E 0x01fc + +#define RK3288_GRF_GPIO5B_E 0x0204 +#define RK3288_GRF_GPIO5C_E 0x0208 + +#define RK3288_GRF_GPIO6A_E 0x0210 +#define RK3288_GRF_GPIO6B_E 0x0214 +#define RK3288_GRF_GPIO6C_E 0x0218 + +#define RK3288_GRF_GPIO7A_E 0x0220 +#define RK3288_GRF_GPIO7B_E 0x0224 +#define RK3288_GRF_GPIO7C_E 0x0228 + +#define RK3288_GRF_GPIO8A_E 0x0230 +#define RK3288_GRF_GPIO8B_E 0x0234 + +#define RK3288_GRF_GPIO_SMT 0x0240 +#define RK3288_GRF_SOC_CON0 0x0244 +#define RK3288_GRF_SOC_CON1 0x0248 +#define RK3288_GRF_SOC_CON2 0x024c +#define RK3288_GRF_SOC_CON3 0x0250 +#define RK3288_GRF_SOC_CON4 0x0254 +#define RK3288_GRF_SOC_CON5 0x0258 +#define RK3288_GRF_SOC_CON6 0x025c +#define RK3288_GRF_SOC_CON7 0x0260 +#define RK3288_GRF_SOC_CON8 0x0264 +#define RK3288_GRF_SOC_CON9 0x0268 +#define RK3288_GRF_SOC_CON10 0x026c +#define RK3288_GRF_SOC_CON11 0x0270 +#define RK3288_GRF_SOC_CON12 0x0274 +#define RK3288_GRF_SOC_CON13 0x0278 +#define RK3288_GRF_SOC_CON14 0x027c +#define RK3288_GRF_SOC_STATUS0 0x0280 +#define RK3288_GRF_SOC_STATUS1 0x0284 +#define RK3288_GRF_SOC_STATUS2 0x0288 +#define RK3288_GRF_SOC_STATUS3 0x028c +#define RK3288_GRF_SOC_STATUS4 0x0290 +#define RK3288_GRF_SOC_STATUS5 0x0294 +#define RK3288_GRF_SOC_STATUS6 0x0298 +#define RK3288_GRF_SOC_STATUS7 0x029c +#define RK3288_GRF_SOC_STATUS8 0x02a0 +#define RK3288_GRF_SOC_STATUS9 0x02a4 +#define RK3288_GRF_SOC_STATUS10 0x02a8 +#define RK3288_GRF_SOC_STATUS11 0x02ac +#define RK3288_GRF_SOC_STATUS12 0x02b0 +#define RK3288_GRF_SOC_STATUS13 0x02b4 +#define RK3288_GRF_SOC_STATUS14 0x02b8 +#define RK3288_GRF_SOC_STATUS15 0x02bc +#define RK3288_GRF_SOC_STATUS16 0x02c0 +#define RK3288_GRF_SOC_STATUS17 0x02c4 +#define RK3288_GRF_SOC_STATUS18 0x02c8 +#define RK3288_GRF_SOC_STATUS19 0x02cc +#define RK3288_GRF_SOC_STATUS20 0x02d0 +#define RK3288_GRF_SOC_STATUS21 0x02d4 + +#define RK3288_GRF_PERIDMAC_CON0 0x02e0 +#define RK3288_GRF_PERIDMAC_CON1 0x02e4 +#define RK3288_GRF_PERIDMAC_CON2 0x02e8 +#define RK3288_GRF_PERIDMAC_CON3 0x02ec +#define RK3288_GRF_DDRC0_CON0 0x02f0 +#define RK3288_GRF_DDRC1_CON0 0x02f4 +#define RK3288_GRF_CPU_CON0 0x02f8 +#define RK3288_GRF_CPU_CON1 0x02fc +#define RK3288_GRF_CPU_CON2 0x0300 +#define RK3288_GRF_CPU_CON3 0x0304 +#define RK3288_GRF_CPU_CON4 0x0308 + +#define RK3288_GRF_CPU_STATUS0 0x0318 + +#define RK3288_GRF_UOC0_CON0 0x0320 +#define RK3288_GRF_UOC0_CON1 0x0324 +#define RK3288_GRF_UOC0_CON2 0x0328 +#define RK3288_GRF_UOC0_CON3 0x032c +#define RK3288_GRF_UOC0_CON4 0x0330 +#define RK3288_GRF_UOC1_CON0 0x0334 +#define RK3288_GRF_UOC1_CON1 0x0338 +#define RK3288_GRF_UOC1_CON2 0x033c +#define RK3288_GRF_UOC1_CON3 0x0340 +#define RK3288_GRF_UOC1_CON4 0x0344 +#define RK3288_GRF_UOC2_CON0 0x0348 +#define RK3288_GRF_UOC2_CON1 0x034c +#define RK3288_GRF_UOC2_CON2 0x0350 +#define RK3288_GRF_UOC2_CON3 0x0354 +#define RK3288_GRF_UOC3_CON0 0x0358 +#define RK3288_GRF_UOC3_CON1 0x035c +#define RK3288_GRF_UOC4_CON0 0x0360 +#define RK3288_GRF_UOC4_CON1 0x0364 +#define RK3288_GRF_PVTM_CON0 0x0368 +#define RK3288_GRF_PVTM_CON1 0x036c +#define RK3288_GRF_PVTM_CON2 0x0370 +#define RK3288_GRF_PVTM_STATUS0 0x0374 +#define RK3288_GRF_PVTM_STATUS1 0x0378 +#define RK3288_GRF_PVTM_STATUS2 0x037c +#define RK3288_GRF_IO_VSEL 0x0380 +#define RK3288_GRF_SARADC_TESTBIT 0x0384 +#define RK3288_GRF_TSADC_TESTBIT_L 0x0388 +#define RK3288_GRF_TSADC_TESTBIT_H 0x038c +#define RK3288_GRF_OS_REG0 0x0390 +#define RK3288_GRF_OS_REG1 0x0394 +#define RK3288_GRF_OS_REG2 0x0398 +#define RK3288_GRF_OS_REG3 0x039c + +#define RK3288_GRF_SOC_CON15 0x03a4 +#define RK3288_GRF_SOC_CON16 0x03a8 + +#define RK3288_SGRF_SOC_CON0 0x0000 +#define RK3288_SGRF_SOC_CON1 0x0004 +#define RK3288_SGRF_SOC_CON2 0x0008 +#define RK3288_SGRF_SOC_CON3 0x000c +#define RK3288_SGRF_SOC_CON4 0x0010 +#define RK3288_SGRF_SOC_CON5 0x0014 + +#define RK3288_SGRF_BUSDMAC_CON0 0x0020 +#define RK3288_SGRF_BUSDMAC_CON1 0x0024 + +#define RK3288_SGRF_CPU_CON0 0x0040 +#define RK3288_SGRF_CPU_CON1 0x0044 +#define RK3288_SGRF_CPU_CON2 0x0048 + +#define RK3288_SGRF_SOC_CON6 0x0050 +#define RK3288_SGRF_SOC_CON7 0x0054 +#define RK3288_SGRF_SOC_CON8 0x0058 +#define RK3288_SGRF_SOC_CON9 0x005c +#define RK3288_SGRF_SOC_CON10 0x0060 +#define RK3288_SGRF_SOC_CON11 0x0064 +#define RK3288_SGRF_SOC_CON12 0x0068 +#define RK3288_SGRF_SOC_CON13 0x006c +#define RK3288_SGRF_SOC_CON14 0x0070 +#define RK3288_SGRF_SOC_CON15 0x0074 +#define RK3288_SGRF_SOC_CON16 0x0078 +#define RK3288_SGRF_SOC_CON17 0x007c +#define RK3288_SGRF_SOC_CON18 0x0080 +#define RK3288_SGRF_SOC_CON19 0x0084 +#define RK3288_SGRF_SOC_CON20 0x0088 +#define RK3288_SGRF_SOC_CON21 0x008c + +#define RK3288_SGRF_SOC_STATUS0 0x0100 +#define RK3288_SGRF_SOC_STATUS1 0x0104 + +#define RK3288_SGRF_FAST_BOOT_ADDR 0x0120 + +#endif diff --git a/include/linux/rockchip/iomap.h b/include/linux/rockchip/iomap.h new file mode 100644 index 000000000000..af834fad8419 --- /dev/null +++ b/include/linux/rockchip/iomap.h @@ -0,0 +1,106 @@ +#ifndef __MACH_ROCKCHIP_IOMAP_H +#define __MACH_ROCKCHIP_IOMAP_H + +#ifndef __ASSEMBLY__ +#include +#endif + +#define RK_IO_ADDRESS(x) IOMEM(0xFED00000 + x) + +#define RK_CRU_VIRT RK_IO_ADDRESS(0x00000000) +#define RK_GRF_VIRT RK_IO_ADDRESS(0x00010000) +#define RK_SGRF_VIRT (RK_GRF_VIRT + 0x1000) +#define RK_PMU_VIRT RK_IO_ADDRESS(0x00020000) +#define RK_ROM_VIRT RK_IO_ADDRESS(0x00030000) +#define RK_EFUSE_VIRT RK_IO_ADDRESS(0x00040000) +#define RK_GPIO_VIRT(n) RK_IO_ADDRESS(0x00050000 + (n) * 0x1000) +#define RK_DEBUG_UART_VIRT RK_IO_ADDRESS(0x00060000) +#define RK_CPU_AXI_BUS_VIRT RK_IO_ADDRESS(0x00070000) +#define RK_TIMER_VIRT RK_IO_ADDRESS(0x00080000) +#define RK_DDR_VIRT RK_IO_ADDRESS(0x000d0000) + +#define RK3188_CRU_PHYS 0x20000000 +#define RK3188_CRU_SIZE SZ_4K +#define RK3188_GRF_PHYS 0x20008000 +#define RK3188_GRF_SIZE SZ_4K +#define RK3188_PMU_PHYS 0x20004000 +#define RK3188_PMU_SIZE SZ_4K +#define RK3188_ROM_PHYS 0x10120000 +#define RK3188_ROM_SIZE SZ_16K +#define RK3188_EFUSE_PHYS 0x20010000 +#define RK3188_EFUSE_SIZE SZ_4K +#define RK3188_GPIO0_PHYS 0x2000a000 +#define RK3188_GPIO1_PHYS 0x2003c000 +#define RK3188_GPIO2_PHYS 0x2003e000 +#define RK3188_GPIO3_PHYS 0x20080000 +#define RK3188_GPIO_SIZE SZ_4K +#define RK3188_CPU_AXI_BUS_PHYS 0x10128000 +#define RK3188_CPU_AXI_BUS_SIZE SZ_32K +#define RK3188_TIMER0_PHYS 0x20038000 +#define RK3188_TIMER3_PHYS 0x2000e000 +#define RK3188_TIMER_SIZE SZ_4K +#define RK3188_DDR_PCTL_PHYS 0x20020000 +#define RK3188_DDR_PCTL_SIZE SZ_4K +#define RK3188_DDR_PUBL_PHYS 0x20040000 +#define RK3188_DDR_PUBL_SIZE SZ_4K +#define RK3188_UART0_PHYS 0x10124000 +#define RK3188_UART1_PHYS 0x10126000 +#define RK3188_UART2_PHYS 0x20064000 +#define RK3188_UART3_PHYS 0x20068000 +#define RK3188_UART_SIZE SZ_4K + +#define RK3288_CRU_PHYS 0xFF760000 +#define RK3288_CRU_SIZE SZ_4K +#define RK3288_GRF_PHYS 0xFF770000 +#define RK3288_GRF_SIZE SZ_4K +#define RK3288_SGRF_PHYS 0xFF740000 +#define RK3288_SGRF_SIZE SZ_4K +#define RK3288_PMU_PHYS 0xFF730000 +#define RK3288_PMU_SIZE SZ_4K +#define RK3288_ROM_PHYS 0xFFFD0000 +#define RK3288_ROM_SIZE (SZ_16K + SZ_4K) +#define RK3288_EFUSE_PHYS 0xFFB40000 +#define RK3288_EFUSE_SIZE SZ_4K +#define RK3288_GPIO0_PHYS 0xFF750000 +#define RK3288_GPIO1_PHYS 0xFF780000 +#define RK3288_GPIO2_PHYS 0xFF790000 +#define RK3288_GPIO3_PHYS 0xFF7A0000 +#define RK3288_GPIO4_PHYS 0xFF7B0000 +#define RK3288_GPIO5_PHYS 0xFF7C0000 +#define RK3288_GPIO6_PHYS 0xFF7D0000 +#define RK3288_GPIO7_PHYS 0xFF7E0000 +#define RK3288_GPIO8_PHYS 0xFF7F0000 +#define RK3288_GPIO_SIZE SZ_4K +#define RK3288_SERVICE_CORE_PHYS 0XFFA80000 +#define RK3288_SERVICE_CORE_SIZE SZ_4K +#define RK3288_SERVICE_DMAC_PHYS 0XFFA90000 +#define RK3288_SERVICE_DMAC_SIZE SZ_4K +#define RK3288_SERVICE_GPU_PHYS 0XFFAA0000 +#define RK3288_SERVICE_GPU_SIZE SZ_4K +#define RK3288_SERVICE_PERI_PHYS 0XFFAB0000 +#define RK3288_SERVICE_PERI_SIZE SZ_4K +#define RK3288_SERVICE_BUS_PHYS 0XFFAC0000 +#define RK3288_SERVICE_BUS_SIZE SZ_16K +#define RK3288_SERVICE_VIO_PHYS 0XFFAD0000 +#define RK3288_SERVICE_VIO_SIZE SZ_4K +#define RK3288_SERVICE_VPU_PHYS 0XFFAE0000 +#define RK3288_SERVICE_VPU_SIZE SZ_4K +#define RK3288_SERVICE_HEVC_PHYS 0XFFAF0000 +#define RK3288_SERVICE_HEVC_SIZE SZ_4K +#define RK3288_TIMER0_PHYS 0xFF6B0000 +#define RK3288_TIMER6_PHYS 0xFF810000 +#define RK3288_TIMER_SIZE SZ_4K +#define RK3288_DDR_PCTL0_PHYS 0xFF610000 +#define RK3288_DDR_PCTL1_PHYS 0xFF630000 +#define RK3288_DDR_PCTL_SIZE SZ_4K +#define RK3288_DDR_PUBL0_PHYS 0xFF620000 +#define RK3288_DDR_PUBL1_PHYS 0xFF640000 +#define RK3288_DDR_PUBL_SIZE SZ_4K +#define RK3288_UART_BT_PHYS 0xFF180000 +#define RK3288_UART_BB_PHYS 0xFF190000 +#define RK3288_UART_DBG_PHYS 0xFF690000 +#define RK3288_UART_GPS_PHYS 0xFF1B0000 +#define RK3288_UART_EXP_PHYS 0xFF1C0000 +#define RK3288_UART_SIZE SZ_4K + +#endif