From: xbw Date: Tue, 29 Apr 2014 09:25:23 +0000 (+0800) Subject: Documentation: devicetree: bindings: mmc: X-Git-Tag: firefly_0821_release~5407 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=ced2d8b49c90e060c1434b0df712ad4e6bfed479;p=firefly-linux-kernel-4.4.55.git Documentation: devicetree: bindings: mmc: More detailed description of the specific content. --- diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt index bb358811f48c..7919b4ca362b 100755 --- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt @@ -10,12 +10,37 @@ extensions to the Synopsys Designware Mobile Storage Host Controller. Required Properties: * compatible: should be - - "rockchip,rk3188-sdmmc": for Rockchip RK3188 and following + - "rockchip,rk_mmc": for controllers compliant with Rockchip sdmmc. + - "rockchip,rk3188-sdmmc": for Rockchip RK3188 and following - "rockchip,rk3288-sdmmc": for Rockchip RK3288 and following +* pinctrl-0: Should specify pin control groups used for this controller. +* pinctrl-names: The corresponding state of the various definitions ,such as "default","idle". +* clocks: Clock IDs array as required by the controller. +* clock-names: names of clock correseponding IDs clock property as requested by the controller driver. * num-slots: - The number of slave devices supported for this single controller, - default 1. + specifies the number of slots supported by the controller. + The number of physical slots actually used could be equal or less than the + value specified by num-slots. If this property is not specified, the value + of num-slot property is assumed to be 1. + +* fifo-depth: The maximum size of the tx/rx fifo's. If this property is not + specified, the default value of the fifo size is determined from the + controller registers. + +* bus-width: as documented in mmc core bindings. + +* wp-gpios: specifies the write protect gpio line. The format of the + gpio specifier depends on the gpio controller. If a GPIO is not used + for write-protect, this property is optional. + +* disable-wp: If the wp-gpios property isn't present then (by default) + we'd assume that the write protect is hooked up directly to the + controller's special purpose write protect line (accessible via + the WRTPRT register). However, it's possible that we simply don't + want write protect. In that case specify 'disable-wp'. + NOTE: This property is not required for slots known to always + connect to eMMC or SDIO cards. * clock-frequency: Stable clk freq for data transfer @@ -47,12 +72,123 @@ Required Properties: * card-detect-delay: For SD/MMC card insert/remove debounce time -Example: - rkdwmmc0@12200000 { - compatible = "rockchip,rk3288-dw-mshc"; - reg = <0x12200000 0x1000>; - interrupts = <0 75 0>; - #address-cells = <1>; - #size-cells = <0>; - }; +* caps2-mmc-hs200-1_8v: Supports mmc HS200 SDR 1.8V mode + +* caps2-mmc-hs200-1_2v: Supports mmc HS200 SDR 1.2V mode + +* broken-cd: as documented in mmc core bindings. + +* vmmc-supply: The phandle to the regulator to use for vmmc. If this is + specified we'll defer probe until we can find this regulator. + + +Example: adding device info in dtsi file + + emmc: rksdmmc@ff0f0000 { + compatible = "rockchip,rk_mmc","rockchip,rk32xx-sdmmc"; + device_type = "emmc"; + reg = <0xff0f0000 0x4000>; + interrupts = ;/*irq=67*/ + #address-cells = <1>; + #size-cells = <0>; + //pinctrl-names = "default",,"suspend"; + //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>; + clocks = <&clk_emmc>, <&clk_gates8 6>; + clock-names = "clk_mmc", "hclk_mmc"; + num-slots = <1>; + fifo-depth = <0x100>; + bus-width = <8>; + }; + + sdmmc: rksdmmc@ff0c0000 { + compatible = "rockchip,rk_mmc","rockchip,rk32xx-sdmmc"; + device_type = "sdmmc"; + reg = <0xff0c0000 0x4000>; + interrupts = ; /*irq=64*/ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default","idle"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + pinctrl-1 = <&sdmmc0_gpio>; + clocks = <&clk_sdmmc>, <&clk_gates8 3>; + clock-names = "clk_mmc", "hclk_mmc"; + num-slots = <1>; + fifo-depth = <0x100>; + bus-width = <4>; + + }; + + sdio: rksdmmc@ff0d0000 { + compatible = "rockchip,rk_mmc","rockchip,rk32xx-sdmmc"; + device_type = "sdio"; + reg = <0xff0d0000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default","idle"; + pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_dectn &sdio0_wrprt &sdio0_pwr &sdio0_bkpwr + &sdio0_intn &sdio0_bus4>; + pinctrl-1 = <&sdio0_gpio>; + clocks = <&clk_sdio0>, <&clk_gates8 4>; + clock-names = "clk_mmc", "hclk_mmc"; + num-slots = <1>; + fifo-depth = <0x100>; + bus-width = <4>; + }; + + sdio1: rksdmmc@ff0e0000 { + compatible = "rockchip,rk_mmc","rockchip,rk32xx-sdmmc"; + device_type = "sdio"; + reg = <0xff0e0000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + //pinctrl-names = "default","suspend"; + //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>; + /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_2 --clk_sdio1_src_gate_en*/ + clocks = <&clk_sdio1>, <&clk_gates8 5>; + clock-names = "clk_mmc", "hclk_mmc"; + num-slots = <1>; + fifo-depth = <0x100>; + bus-width = <4>; + status = "disabled"; + }; + + + + Example: Adding child nodes in dts file + + &emmc { + clock-frequency = <200000000>; + clock-freq-min-max = <400000 200000000>; + supports-highspeed; + supports-emmc; + bootpart-no-access; + ignore-pm-notify; + keep-power-in-suspend; + status = "okay"; + }; + + &sdmmc { + clock-frequency = <50000000>; + lock-freq-min-max = <400000 50000000>; + supports-highspeed; + supports-sd; + broken-cd; + card-detect-delay = <200>; + vmmc-supply = <&rk808_ldo5_reg>; + status = "okay"; + }; + + &sdio { + clock-frequency = <50000000>; + clock-freq-min-max = <200000 50000000>; + supports-highspeed; + supports-sdio; + ignore-pm-notify; + keep-power-in-suspend; + //cap-sdio-irq; + status = "okay"; + }; +