From: Chris Lattner Date: Fri, 27 Jan 2006 01:46:15 +0000 (+0000) Subject: PHI and INLINEASM are now built-in instructions provided by Target.td X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=cedc6f4b30c1fd5f7ad1df0b65b870e6f107e8ff;p=oota-llvm.git PHI and INLINEASM are now built-in instructions provided by Target.td git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25674 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Alpha/Alpha.td b/lib/Target/Alpha/Alpha.td index 7cbb0f181f7..facc767c40b 100644 --- a/lib/Target/Alpha/Alpha.td +++ b/lib/Target/Alpha/Alpha.td @@ -38,8 +38,6 @@ include "AlphaRegisterInfo.td" include "AlphaInstrInfo.td" def AlphaInstrInfo : InstrInfo { - let PHIInst = PHI; - // Define how we want to layout our target-specific information field. // let TSFlagsFields = []; // let TSFlagsShifts = []; diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td index dec058ea9f9..b39c94a7a21 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.td +++ b/lib/Target/Alpha/AlphaInstrInfo.td @@ -113,8 +113,6 @@ def sub8 : PatFrag<(ops node:$op1, node:$op2), //Pseudo ops for selection -def PHI : PseudoInstAlpha<(ops variable_ops), "#phi", []>; - def IDEF_I : PseudoInstAlpha<(ops GPRC:$RA), "#idef $RA", [(set GPRC:$RA, (undef))]>; def IDEF_F32 : PseudoInstAlpha<(ops F4RC:$RA), "#idef $RA", diff --git a/lib/Target/IA64/IA64.td b/lib/Target/IA64/IA64.td index 78cf55e48e0..30337625c58 100644 --- a/lib/Target/IA64/IA64.td +++ b/lib/Target/IA64/IA64.td @@ -28,9 +28,7 @@ include "IA64RegisterInfo.td" include "IA64InstrInfo.td" -def IA64InstrInfo : InstrInfo { - let PHIInst = PHI; -} +def IA64InstrInfo : InstrInfo { } def IA64 : Target { // The following registers are always saved across calls: diff --git a/lib/Target/IA64/IA64InstrInfo.td b/lib/Target/IA64/IA64InstrInfo.td index 67d71e48db6..7dc184c8612 100644 --- a/lib/Target/IA64/IA64InstrInfo.td +++ b/lib/Target/IA64/IA64InstrInfo.td @@ -448,7 +448,6 @@ def : Pat<(i1 0), (CMPNE r0, r0)>; // TODO: any instruction actually *using* // TODO: support postincrement (reg, imm9) loads+stores - this needs more // tablegen support -def PHI : PseudoInstIA64<(ops variable_ops), "PHI">; def IDEF : PseudoInstIA64<(ops variable_ops), "// IDEF">; def IDEF_GR_D : PseudoInstIA64_DAG<(ops GR:$reg), "// $reg = IDEF", diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index 07f0e1ca309..0c7dca0d7b1 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -644,9 +644,8 @@ class VXRForm_1 xo, bit rc, dag OL, string asmstr, } //===----------------------------------------------------------------------===// -def NoItin : InstrItinClass; class Pseudo pattern> - : I<0, OL, asmstr, NoItin> { + : I<0, OL, asmstr, NoItinerary> { let PPC64 = 0; let VMX = 0; let Pattern = pattern; diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 4ccf4c22faf..6312559ce23 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -194,7 +194,6 @@ def FPContractions : Predicate<"!NoExcessFPPrecision">; // PowerPC Instruction Definitions. // Pseudo-instructions: -def PHI : Pseudo<(ops variable_ops), "; PHI", []>; let isLoad = 1, hasCtrlDep = 1 in { def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), @@ -1087,8 +1086,6 @@ def : Pattern<(xor GPRC:$in, imm:$imm), // PowerPCInstrInfo Definition // def PowerPCInstrInfo : InstrInfo { - let PHIInst = PHI; - let TSFlagsFields = [ "VMX", "PPC64" ]; let TSFlagsShifts = [ 0, 1 ]; diff --git a/lib/Target/Skeleton/Skeleton.td b/lib/Target/Skeleton/Skeleton.td index 8a2dc7291f7..47b8a20c276 100644 --- a/lib/Target/Skeleton/Skeleton.td +++ b/lib/Target/Skeleton/Skeleton.td @@ -21,9 +21,7 @@ include "../Target.td" include "SkeletonRegisterInfo.td" include "SkeletonInstrInfo.td" -def SkeletonInstrInfo : InstrInfo { - let PHIInst = PHI; -} +def SkeletonInstrInfo : InstrInfo { } def Skeleton : Target { // Pointers are 32-bits in size. diff --git a/lib/Target/Skeleton/SkeletonInstrInfo.td b/lib/Target/Skeleton/SkeletonInstrInfo.td index c10af8a9ad4..c5a15bbeecb 100644 --- a/lib/Target/Skeleton/SkeletonInstrInfo.td +++ b/lib/Target/Skeleton/SkeletonInstrInfo.td @@ -32,7 +32,6 @@ class SkelInst opcd, dag ops, Format f> : Instruction { } // Pseudo-instructions: -def PHI : SkelInst<"PHI", 0, (ops), Pseudo>; // PHI node... def NOP : SkelInst<"NOP", 0, (ops), Pseudo>; // No-op def ADJCALLSTACKDOWN : SkelInst<"ADJCALLSTACKDOWN", 0, (ops), Pseudo>; def ADJCALLSTACKUP : SkelInst<"ADJCALLSTACKUP", 0, (ops), Pseudo>; diff --git a/lib/Target/Sparc/Sparc.td b/lib/Target/Sparc/Sparc.td index 886edc1c32a..db9b367e88f 100644 --- a/lib/Target/Sparc/Sparc.td +++ b/lib/Target/Sparc/Sparc.td @@ -43,8 +43,6 @@ include "SparcV8RegisterInfo.td" include "SparcV8InstrInfo.td" def SparcV8InstrInfo : InstrInfo { - let PHIInst = PHI; - // Define how we want to layout our target-specific information field. let TSFlagsFields = []; let TSFlagsShifts = []; diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index 9613bc5fd46..db87d4c8500 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -107,7 +107,6 @@ def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag, class Pseudo pattern> : InstV8; -def PHI : Pseudo<(ops variable_ops), "PHI", []>; def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt), "!ADJCALLSTACKDOWN $amt", [(callseq_start imm:$amt)]>; diff --git a/lib/Target/SparcV8/SparcV8.td b/lib/Target/SparcV8/SparcV8.td index 886edc1c32a..db9b367e88f 100644 --- a/lib/Target/SparcV8/SparcV8.td +++ b/lib/Target/SparcV8/SparcV8.td @@ -43,8 +43,6 @@ include "SparcV8RegisterInfo.td" include "SparcV8InstrInfo.td" def SparcV8InstrInfo : InstrInfo { - let PHIInst = PHI; - // Define how we want to layout our target-specific information field. let TSFlagsFields = []; let TSFlagsShifts = []; diff --git a/lib/Target/SparcV8/SparcV8InstrInfo.td b/lib/Target/SparcV8/SparcV8InstrInfo.td index 9613bc5fd46..db87d4c8500 100644 --- a/lib/Target/SparcV8/SparcV8InstrInfo.td +++ b/lib/Target/SparcV8/SparcV8InstrInfo.td @@ -107,7 +107,6 @@ def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag, class Pseudo pattern> : InstV8; -def PHI : Pseudo<(ops variable_ops), "PHI", []>; def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt), "!ADJCALLSTACKDOWN $amt", [(callseq_start imm:$amt)]>; diff --git a/lib/Target/SparcV9/SparcV9.td b/lib/Target/SparcV9/SparcV9.td index a2882483994..87ed94d497f 100644 --- a/lib/Target/SparcV9/SparcV9.td +++ b/lib/Target/SparcV9/SparcV9.td @@ -31,8 +31,6 @@ include "SparcV9RegisterInfo.td" include "SparcV9InstrInfo.td" def SparcV9InstrInfo : InstrInfo { - let PHIInst = PHI; - // Define how we want to layout our TargetSpecific information field. let TSFlagsFields = []; let TSFlagsShifts = []; diff --git a/lib/Target/SparcV9/SparcV9InstrInfo.td b/lib/Target/SparcV9/SparcV9InstrInfo.td index c2df4e46f1e..e813cfaddaf 100644 --- a/lib/Target/SparcV9/SparcV9InstrInfo.td +++ b/lib/Target/SparcV9/SparcV9InstrInfo.td @@ -38,9 +38,6 @@ include "SparcV9_F4.td" // Instruction list //===----------------------------------------------------------------------===// -// Pseudo-instructions -def PHI : Pseudo<"phi">; - // Section A.2: Add - p137 def ADDr : F3_1<2, 0b000000, "add">; // add rs1, rs2, rd def ADDi : F3_2<2, 0b000000, "add">; // add rs1, imm, rd diff --git a/lib/Target/Target.td b/lib/Target/Target.td index b4584244d0f..407ad640594 100644 --- a/lib/Target/Target.td +++ b/lib/Target/Target.td @@ -171,7 +171,7 @@ class Instruction { bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? bit noResults = 0; // Does this instruction produce no results? - InstrItinClass Itinerary; // Execution steps used for scheduling. + InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. } /// Predicates - These are extra conditionals which are turned into instruction @@ -213,8 +213,6 @@ def i64imm : Operand; // which are global to the the target machine. // class InstrInfo { - Instruction PHIInst; - // If the target wants to associate some target-specific information with each // instruction, it should provide these two lists to indicate how to assemble // the target specific information into the 32 bits available. @@ -229,6 +227,16 @@ class InstrInfo { bit isLittleEndianEncoding = 0; } +// Standard Instructions. +def PHI : Instruction { + let OperandList = (ops variable_ops); + let AsmString = "PHINODE"; +} +def INLINEASM : Instruction { + let OperandList = (ops variable_ops); + let AsmString = ""; +} + //===----------------------------------------------------------------------===// // AsmWriter - This class can be implemented by targets that need to customize // the format of the .s file writer. diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td index a93d7822e26..f341949e00b 100644 --- a/lib/Target/X86/X86.td +++ b/lib/Target/X86/X86.td @@ -98,7 +98,6 @@ include "X86RegisterInfo.td" include "X86InstrInfo.td" def X86InstrInfo : InstrInfo { - let PHIInst = PHI; // Define how we want to layout our TargetSpecific information field... This // should be kept up-to-date with the fields in the X86InstrInfo.h file. diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 323b2ab7b20..37e5c957a10 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -378,9 +378,6 @@ class Ii32 o, Format f, dag ops, string asm, list pattern> // Instruction list... // -// Pseudo-instructions: -def PHI : I<0, Pseudo, (ops variable_ops), "PHINODE", []>; // PHI node. - def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN", [(X86callseq_start imm:$amt)]>; def ADJCALLSTACKUP : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2),