From: Rafael Espindola Date: Thu, 30 Jun 2011 21:15:52 +0000 (+0000) Subject: Create a isFullCopy predicate. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=cfe5254cd34d9414d9f6b8aa02dc1239d71a703f;p=oota-llvm.git Create a isFullCopy predicate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134189 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h index 07a14cf0c15..788d149c868 100644 --- a/include/llvm/CodeGen/MachineInstr.h +++ b/include/llvm/CodeGen/MachineInstr.h @@ -278,6 +278,9 @@ public: bool isCopy() const { return getOpcode() == TargetOpcode::COPY; } + bool isFullCopy() const { + return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg(); + } /// isCopyLike - Return true if the instruction behaves like a copy. /// This does not include native copy instructions. diff --git a/lib/CodeGen/InlineSpiller.cpp b/lib/CodeGen/InlineSpiller.cpp index 19ae333115c..0273891d690 100644 --- a/lib/CodeGen/InlineSpiller.cpp +++ b/lib/CodeGen/InlineSpiller.cpp @@ -180,11 +180,7 @@ Spiller *createInlineSpiller(MachineFunctionPass &pass, /// isFullCopyOf - If MI is a COPY to or from Reg, return the other register, /// otherwise return 0. static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) { - if (!MI->isCopy()) - return 0; - if (MI->getOperand(0).getSubReg() != 0) - return 0; - if (MI->getOperand(1).getSubReg() != 0) + if (!MI->isFullCopy()) return 0; if (MI->getOperand(0).getReg() == Reg) return MI->getOperand(1).getReg();