From: Huang, Tao <huangtao@rock-chips.com>
Date: Fri, 5 Dec 2014 13:18:34 +0000 (+0800)
Subject: Merge tag 'lsk-v3.10-android-14.11'
X-Git-Tag: firefly_0821_release~4158^2~566
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=d03390bfcdb71807a537254455a2938322926d57;p=firefly-linux-kernel-4.4.55.git

Merge tag 'lsk-v3.10-android-14.11'

LSK Android 14.11 v3.10

Conflicts:
	arch/arm/include/asm/cputype.h
---

d03390bfcdb71807a537254455a2938322926d57
diff --cc drivers/irqchip/irq-gic.c
index 8cb21def5508,4cb670e61707..c58923eee0c5
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@@ -429,29 -368,9 +399,18 @@@ static void __init gic_dist_init(struc
  	for (i = 32; i < gic_irqs; i += 4)
  		writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
  
- 	/*
- 	 * Set priority on all global interrupts.
- 	 */
- 	for (i = 32; i < gic_irqs; i += 4)
- 		writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
- 
- 	/*
- 	 * Disable all interrupts.  Leave the PPI and SGIs alone
- 	 * as these enables are banked registers.
- 	 */
- 	for (i = 32; i < gic_irqs; i += 32)
- 		writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
+ 	gic_dist_config(base, gic_irqs, NULL);
  
 +#ifdef CONFIG_FIQ_DEBUGGER
 +	// set all the interrupt to non-secure state
 +	for (i = 0; i < gic_irqs; i += 32) {
 +		writel_relaxed(0xffffffff, base + GIC_DIST_IGROUP + i * 4 / 32);
 +	}
 +	dsb();
 +	writel_relaxed(3, base + GIC_DIST_CTRL);
 +#else
  	writel_relaxed(1, base + GIC_DIST_CTRL);
 +#endif
  }
  
  static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
@@@ -476,25 -395,10 +435,14 @@@
  		if (i != cpu)
  			gic_cpu_map[i] &= ~cpu_mask;
  
- 	/*
- 	 * Deal with the banked PPI and SGI interrupts - disable all
- 	 * PPI interrupts, ensure all SGI interrupts are enabled.
- 	 */
- 	writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
- 	writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
- 
- 	/*
- 	 * Set priority on PPI and SGI interrupts
- 	 */
- 	for (i = 0; i < 32; i += 4)
- 		writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
+ 	gic_cpu_config(dist_base, NULL);
  
  	writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
 +#ifdef CONFIG_FIQ_DEBUGGER
 +	writel_relaxed(0x0f, base + GIC_CPU_CTRL);
 +#else
  	writel_relaxed(1, base + GIC_CPU_CTRL);
 +#endif
  }
  
  void gic_cpu_if_down(void)
@@@ -716,17 -612,12 +664,17 @@@ static void gic_raise_softirq(const str
  
  	/*
  	 * Ensure that stores to Normal memory are visible to the
- 	 * other CPUs before issuing the IPI.
+ 	 * other CPUs before they observe us issuing the IPI.
  	 */
- 	dsb();
+ 	dmb(ishst);
  
  	/* this always happens on GIC0 */
 +#ifdef CONFIG_FIQ_DEBUGGER
 +	/* enable non-secure SGI for GIC with security extensions */
 +	writel_relaxed(map << 16 | irq | 0x8000, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
 +#else
  	writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
 +#endif
  
  	raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
  }
diff --cc drivers/usb/core/hcd.c
index 01a518b927ea,f6e5ceb03afb..b62703b89f7d
mode 100755,100644..100755
--- a/drivers/usb/core/hcd.c
+++ b/drivers/usb/core/hcd.c
diff --cc drivers/usb/core/hub.c
index eff3ee6a62e0,c9f56ffdba9a..2260781b50af
mode 100755,100644..100755
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
diff --cc drivers/usb/host/ehci-hcd.c
index 248bd465f1ad,f1c3ad69ca54..32025a9a31a7
mode 100755,100644..100755
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c